Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.36 98.36 93.99 93.90 89.36 97.19 95.45 99.26


Total test records in report: 1122
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1021 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1710888426 Sep 09 10:49:18 AM UTC 24 Sep 09 10:49:21 AM UTC 24 32565829 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2767449155 Sep 09 10:49:17 AM UTC 24 Sep 09 10:49:21 AM UTC 24 51104751 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1517990316 Sep 09 10:49:04 AM UTC 24 Sep 09 10:49:22 AM UTC 24 210553822 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3836498682 Sep 09 10:49:20 AM UTC 24 Sep 09 10:49:22 AM UTC 24 168916648 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1243594256 Sep 09 10:49:11 AM UTC 24 Sep 09 10:49:23 AM UTC 24 431028455 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3379114646 Sep 09 10:49:17 AM UTC 24 Sep 09 10:49:23 AM UTC 24 170849913 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3977243616 Sep 09 10:49:15 AM UTC 24 Sep 09 10:49:24 AM UTC 24 206476259 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2071993229 Sep 09 10:49:21 AM UTC 24 Sep 09 10:49:24 AM UTC 24 104853714 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.498395955 Sep 09 10:49:22 AM UTC 24 Sep 09 10:49:24 AM UTC 24 46320407 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1085405705 Sep 09 10:49:21 AM UTC 24 Sep 09 10:49:24 AM UTC 24 33334743 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1419151806 Sep 09 10:49:22 AM UTC 24 Sep 09 10:49:25 AM UTC 24 134386835 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3863669760 Sep 09 10:49:02 AM UTC 24 Sep 09 10:49:25 AM UTC 24 410578472 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3934154220 Sep 09 10:49:00 AM UTC 24 Sep 09 10:49:26 AM UTC 24 5046445002 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3780854386 Sep 09 10:49:22 AM UTC 24 Sep 09 10:49:26 AM UTC 24 328911708 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3854959683 Sep 09 10:49:22 AM UTC 24 Sep 09 10:49:27 AM UTC 24 44112365 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2536497571 Sep 09 10:49:21 AM UTC 24 Sep 09 10:49:27 AM UTC 24 160307648 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3378216110 Sep 09 10:49:26 AM UTC 24 Sep 09 10:49:28 AM UTC 24 55903860 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1058891924 Sep 09 10:49:25 AM UTC 24 Sep 09 10:49:28 AM UTC 24 38455466 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.1863885744 Sep 09 10:49:23 AM UTC 24 Sep 09 10:49:29 AM UTC 24 112314727 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2744311985 Sep 09 10:49:27 AM UTC 24 Sep 09 10:49:29 AM UTC 24 40539321 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.3046816325 Sep 09 10:49:06 AM UTC 24 Sep 09 10:49:29 AM UTC 24 4559315422 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1037309376 Sep 09 10:49:10 AM UTC 24 Sep 09 10:49:30 AM UTC 24 1848115730 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.1269906582 Sep 09 10:49:26 AM UTC 24 Sep 09 10:49:30 AM UTC 24 101409769 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2941694178 Sep 09 10:49:25 AM UTC 24 Sep 09 10:49:30 AM UTC 24 217941103 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1268042513 Sep 09 10:49:25 AM UTC 24 Sep 09 10:49:30 AM UTC 24 41705298 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2476050950 Sep 09 10:49:28 AM UTC 24 Sep 09 10:49:32 AM UTC 24 98870378 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3251484703 Sep 09 10:49:23 AM UTC 24 Sep 09 10:49:32 AM UTC 24 420164357 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2296423245 Sep 09 10:49:30 AM UTC 24 Sep 09 10:49:32 AM UTC 24 13303884 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.711786696 Sep 09 10:49:28 AM UTC 24 Sep 09 10:49:32 AM UTC 24 107397606 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2458907202 Sep 09 10:49:22 AM UTC 24 Sep 09 10:49:32 AM UTC 24 935528711 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2822154728 Sep 09 10:49:28 AM UTC 24 Sep 09 10:49:32 AM UTC 24 344666367 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.1153980484 Sep 09 10:49:31 AM UTC 24 Sep 09 10:49:33 AM UTC 24 41255538 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1753341257 Sep 09 10:49:30 AM UTC 24 Sep 09 10:49:33 AM UTC 24 180048616 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1876187100 Sep 09 10:49:27 AM UTC 24 Sep 09 10:49:33 AM UTC 24 165651551 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2436265262 Sep 09 10:49:27 AM UTC 24 Sep 09 10:49:34 AM UTC 24 1798595066 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4137751291 Sep 09 10:49:31 AM UTC 24 Sep 09 10:49:34 AM UTC 24 19870486 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.1238610987 Sep 09 10:49:26 AM UTC 24 Sep 09 10:49:35 AM UTC 24 417446409 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.420704991 Sep 09 10:49:29 AM UTC 24 Sep 09 10:49:35 AM UTC 24 72767309 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3817850833 Sep 09 10:49:27 AM UTC 24 Sep 09 10:49:36 AM UTC 24 1117980877 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2323260207 Sep 09 10:49:34 AM UTC 24 Sep 09 10:49:36 AM UTC 24 30491920 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2324702178 Sep 09 10:49:06 AM UTC 24 Sep 09 10:49:36 AM UTC 24 1795449351 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.848065744 Sep 09 10:49:31 AM UTC 24 Sep 09 10:49:36 AM UTC 24 483978166 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3647176373 Sep 09 10:49:30 AM UTC 24 Sep 09 10:49:36 AM UTC 24 179318743 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.325509067 Sep 09 10:49:32 AM UTC 24 Sep 09 10:49:37 AM UTC 24 42680801 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2287529329 Sep 09 10:49:35 AM UTC 24 Sep 09 10:49:37 AM UTC 24 41023153 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.353555974 Sep 09 10:49:34 AM UTC 24 Sep 09 10:49:37 AM UTC 24 68286060 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3885078350 Sep 09 10:49:32 AM UTC 24 Sep 09 10:49:38 AM UTC 24 86860185 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1229105068 Sep 09 10:49:32 AM UTC 24 Sep 09 10:49:38 AM UTC 24 530855865 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1709611616 Sep 09 10:49:34 AM UTC 24 Sep 09 10:49:38 AM UTC 24 123938202 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3346638781 Sep 09 10:49:18 AM UTC 24 Sep 09 10:49:39 AM UTC 24 579164141 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1006453867 Sep 09 10:49:31 AM UTC 24 Sep 09 10:49:39 AM UTC 24 227837870 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3430806169 Sep 09 10:49:35 AM UTC 24 Sep 09 10:49:39 AM UTC 24 274595239 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1608079168 Sep 09 10:49:34 AM UTC 24 Sep 09 10:49:39 AM UTC 24 415484116 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3338918312 Sep 09 10:49:36 AM UTC 24 Sep 09 10:49:40 AM UTC 24 799078068 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.938473424 Sep 09 10:49:37 AM UTC 24 Sep 09 10:49:40 AM UTC 24 19014981 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2179997598 Sep 09 10:49:36 AM UTC 24 Sep 09 10:49:40 AM UTC 24 44028680 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.3681372555 Sep 09 10:49:37 AM UTC 24 Sep 09 10:49:41 AM UTC 24 47987158 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.645411433 Sep 09 10:49:39 AM UTC 24 Sep 09 10:49:42 AM UTC 24 16713386 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2852691614 Sep 09 10:49:35 AM UTC 24 Sep 09 10:49:42 AM UTC 24 139398695 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3821337202 Sep 09 10:49:38 AM UTC 24 Sep 09 10:49:42 AM UTC 24 353621734 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.101925726 Sep 09 10:49:16 AM UTC 24 Sep 09 10:49:42 AM UTC 24 1107381255 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.524419408 Sep 09 10:49:35 AM UTC 24 Sep 09 10:49:43 AM UTC 24 111624895 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.4188897133 Sep 09 10:49:39 AM UTC 24 Sep 09 10:49:43 AM UTC 24 29080710 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3915468419 Sep 09 10:49:32 AM UTC 24 Sep 09 10:49:43 AM UTC 24 341797991 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1289000221 Sep 09 10:49:36 AM UTC 24 Sep 09 10:49:43 AM UTC 24 70893707 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1581735236 Sep 09 10:49:39 AM UTC 24 Sep 09 10:49:43 AM UTC 24 275777022 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1952984330 Sep 09 10:49:38 AM UTC 24 Sep 09 10:49:43 AM UTC 24 117647495 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1616116086 Sep 09 10:49:41 AM UTC 24 Sep 09 10:49:43 AM UTC 24 58941245 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3715997077 Sep 09 10:49:41 AM UTC 24 Sep 09 10:49:44 AM UTC 24 19318306 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.1812811102 Sep 09 10:49:41 AM UTC 24 Sep 09 10:49:44 AM UTC 24 116281546 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2028574995 Sep 09 10:49:40 AM UTC 24 Sep 09 10:49:45 AM UTC 24 105387112 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2897476256 Sep 09 10:49:43 AM UTC 24 Sep 09 10:49:45 AM UTC 24 18490338 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.358528260 Sep 09 10:49:40 AM UTC 24 Sep 09 10:49:45 AM UTC 24 83901108 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1448171255 Sep 09 10:49:31 AM UTC 24 Sep 09 10:49:45 AM UTC 24 1277753147 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4006048979 Sep 09 10:49:41 AM UTC 24 Sep 09 10:49:45 AM UTC 24 40715500 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.2620720498 Sep 09 10:49:40 AM UTC 24 Sep 09 10:49:46 AM UTC 24 1234164812 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3047234616 Sep 09 10:49:49 AM UTC 24 Sep 09 10:49:51 AM UTC 24 28599394 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.672355901 Sep 09 10:49:43 AM UTC 24 Sep 09 10:49:46 AM UTC 24 141751395 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3370201966 Sep 09 10:49:41 AM UTC 24 Sep 09 10:49:46 AM UTC 24 140418290 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1361175668 Sep 09 10:49:44 AM UTC 24 Sep 09 10:49:46 AM UTC 24 123247664 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3528207171 Sep 09 10:49:45 AM UTC 24 Sep 09 10:49:47 AM UTC 24 15263149 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.4045848727 Sep 09 10:49:45 AM UTC 24 Sep 09 10:49:47 AM UTC 24 28195023 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3090363747 Sep 09 10:49:45 AM UTC 24 Sep 09 10:49:47 AM UTC 24 51362683 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2139180722 Sep 09 10:49:44 AM UTC 24 Sep 09 10:49:47 AM UTC 24 77396116 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.169945767 Sep 09 10:49:44 AM UTC 24 Sep 09 10:49:48 AM UTC 24 32488920 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.660620897 Sep 09 10:49:44 AM UTC 24 Sep 09 10:49:48 AM UTC 24 480943313 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.2009790287 Sep 09 10:49:46 AM UTC 24 Sep 09 10:49:49 AM UTC 24 72519482 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3654767215 Sep 09 10:49:47 AM UTC 24 Sep 09 10:49:49 AM UTC 24 46151746 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.930334441 Sep 09 10:49:47 AM UTC 24 Sep 09 10:49:49 AM UTC 24 54564167 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.88001444 Sep 09 10:49:47 AM UTC 24 Sep 09 10:49:49 AM UTC 24 51732695 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3823389474 Sep 09 10:49:47 AM UTC 24 Sep 09 10:49:49 AM UTC 24 34950547 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2898800426 Sep 09 10:49:47 AM UTC 24 Sep 09 10:49:49 AM UTC 24 16046941 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3810469883 Sep 09 10:49:47 AM UTC 24 Sep 09 10:49:49 AM UTC 24 33894308 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.186221895 Sep 09 10:49:44 AM UTC 24 Sep 09 10:49:49 AM UTC 24 175687398 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1451842636 Sep 09 10:49:44 AM UTC 24 Sep 09 10:49:49 AM UTC 24 122320037 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1423656976 Sep 09 10:49:48 AM UTC 24 Sep 09 10:49:50 AM UTC 24 16474362 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.220925835 Sep 09 10:49:44 AM UTC 24 Sep 09 10:49:50 AM UTC 24 52555796 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.3238432374 Sep 09 10:49:48 AM UTC 24 Sep 09 10:49:50 AM UTC 24 20436724 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3142975652 Sep 09 10:49:48 AM UTC 24 Sep 09 10:49:50 AM UTC 24 26393729 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.1856950035 Sep 09 10:49:48 AM UTC 24 Sep 09 10:49:50 AM UTC 24 27384011 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1517527680 Sep 09 10:49:48 AM UTC 24 Sep 09 10:49:50 AM UTC 24 20465205 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2934899180 Sep 09 10:49:49 AM UTC 24 Sep 09 10:49:51 AM UTC 24 13161949 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1660668951 Sep 09 10:49:49 AM UTC 24 Sep 09 10:49:52 AM UTC 24 14792312 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.808865707 Sep 09 10:49:50 AM UTC 24 Sep 09 10:49:52 AM UTC 24 15658491 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.4158231041 Sep 09 10:49:49 AM UTC 24 Sep 09 10:49:52 AM UTC 24 19178118 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.4100928458 Sep 09 10:49:49 AM UTC 24 Sep 09 10:49:52 AM UTC 24 13203943 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2324365353 Sep 09 10:49:50 AM UTC 24 Sep 09 10:49:52 AM UTC 24 12072972 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2632800862 Sep 09 10:49:50 AM UTC 24 Sep 09 10:49:52 AM UTC 24 51658093 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.263928097 Sep 09 10:49:50 AM UTC 24 Sep 09 10:49:52 AM UTC 24 70421577 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1516246986 Sep 09 10:49:30 AM UTC 24 Sep 09 10:49:53 AM UTC 24 5034837049 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3423281809 Sep 09 10:49:51 AM UTC 24 Sep 09 10:49:53 AM UTC 24 118895386 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.697929541 Sep 09 10:49:51 AM UTC 24 Sep 09 10:49:53 AM UTC 24 15374271 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2475351757 Sep 09 10:49:51 AM UTC 24 Sep 09 10:49:53 AM UTC 24 15045334 ps
T1117 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.923732605 Sep 09 10:49:51 AM UTC 24 Sep 09 10:49:53 AM UTC 24 43521056 ps
T1118 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2418882439 Sep 09 10:49:51 AM UTC 24 Sep 09 10:49:53 AM UTC 24 11736339 ps
T1119 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.3911568556 Sep 09 10:49:51 AM UTC 24 Sep 09 10:49:53 AM UTC 24 61157821 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2658854883 Sep 09 10:49:40 AM UTC 24 Sep 09 10:49:54 AM UTC 24 767055828 ps
T1120 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1352856405 Sep 09 10:49:36 AM UTC 24 Sep 09 10:49:54 AM UTC 24 2748434240 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3266121571 Sep 09 10:49:39 AM UTC 24 Sep 09 10:49:56 AM UTC 24 3615177835 ps
T1121 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3290730700 Sep 09 10:49:43 AM UTC 24 Sep 09 10:49:58 AM UTC 24 200228465 ps
T1122 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2926546754 Sep 09 10:49:15 AM UTC 24 Sep 09 10:49:59 AM UTC 24 6270585430 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.319185911 Sep 09 10:49:44 AM UTC 24 Sep 09 10:50:11 AM UTC 24 1092300976 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.4059099079
Short name T10
Test name
Test status
Simulation time 3083013662 ps
CPU time 3.74 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:29:02 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059099079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.4059099079
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.3864060962
Short name T55
Test name
Test status
Simulation time 1895804113 ps
CPU time 31.01 seconds
Started Sep 09 11:29:10 AM UTC 24
Finished Sep 09 11:29:55 AM UTC 24
Peak memory 261748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864060962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.3864060962
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.3761977456
Short name T28
Test name
Test status
Simulation time 1050576421 ps
CPU time 3.74 seconds
Started Sep 09 11:28:55 AM UTC 24
Finished Sep 09 11:29:07 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761977456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3761977456
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.4116763293
Short name T43
Test name
Test status
Simulation time 2166198522 ps
CPU time 22.74 seconds
Started Sep 09 11:29:21 AM UTC 24
Finished Sep 09 11:29:48 AM UTC 24
Peak memory 249432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116763293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4116763293
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2106079936
Short name T254
Test name
Test status
Simulation time 36665104316 ps
CPU time 134.55 seconds
Started Sep 09 11:29:46 AM UTC 24
Finished Sep 09 11:32:06 AM UTC 24
Peak memory 267912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106079936 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.2106079936
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.2152509247
Short name T66
Test name
Test status
Simulation time 4014657478 ps
CPU time 85.51 seconds
Started Sep 09 11:29:27 AM UTC 24
Finished Sep 09 11:30:55 AM UTC 24
Peak memory 267860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152509247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2152509247
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1651078934
Short name T82
Test name
Test status
Simulation time 780327673 ps
CPU time 5.33 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:07 AM UTC 24
Peak memory 227364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1651078934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.spi_device_csr_mem_rw_with_rand_reset.1651078934
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.3844568603
Short name T12
Test name
Test status
Simulation time 3032040700 ps
CPU time 9.56 seconds
Started Sep 09 11:29:26 AM UTC 24
Finished Sep 09 11:29:38 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844568603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3844568603
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1778188655
Short name T69
Test name
Test status
Simulation time 4269244164 ps
CPU time 105.38 seconds
Started Sep 09 11:29:46 AM UTC 24
Finished Sep 09 11:31:36 AM UTC 24
Peak memory 282252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778188655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.1778188655
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.3858783047
Short name T8
Test name
Test status
Simulation time 861367371 ps
CPU time 4.27 seconds
Started Sep 09 11:28:50 AM UTC 24
Finished Sep 09 11:28:59 AM UTC 24
Peak memory 235040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858783047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3858783047
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.4046631267
Short name T206
Test name
Test status
Simulation time 2042208383 ps
CPU time 58.89 seconds
Started Sep 09 11:30:20 AM UTC 24
Finished Sep 09 11:31:21 AM UTC 24
Peak memory 261700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046631267 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.4046631267
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1613463114
Short name T61
Test name
Test status
Simulation time 9404503521 ps
CPU time 56.4 seconds
Started Sep 09 11:29:29 AM UTC 24
Finished Sep 09 11:30:40 AM UTC 24
Peak memory 263880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613463114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1613463114
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4196135825
Short name T14
Test name
Test status
Simulation time 150151967 ps
CPU time 1.07 seconds
Started Sep 09 11:28:58 AM UTC 24
Finished Sep 09 11:29:20 AM UTC 24
Peak memory 258036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196135825 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4196135825
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1127028427
Short name T172
Test name
Test status
Simulation time 9542505698 ps
CPU time 147.52 seconds
Started Sep 09 11:29:34 AM UTC 24
Finished Sep 09 11:32:08 AM UTC 24
Peak memory 276088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127028427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1127028427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3048682986
Short name T209
Test name
Test status
Simulation time 6988027717 ps
CPU time 103.14 seconds
Started Sep 09 11:30:02 AM UTC 24
Finished Sep 09 11:31:48 AM UTC 24
Peak memory 284268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048682986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3048682986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.865552210
Short name T86
Test name
Test status
Simulation time 2506171684 ps
CPU time 50.22 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:30:09 AM UTC 24
Peak memory 278168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865552210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.865552210
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.4019912307
Short name T68
Test name
Test status
Simulation time 51614020008 ps
CPU time 130.2 seconds
Started Sep 09 11:29:21 AM UTC 24
Finished Sep 09 11:31:36 AM UTC 24
Peak memory 267924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019912307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.4019912307
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.655900394
Short name T133
Test name
Test status
Simulation time 231493050 ps
CPU time 3.41 seconds
Started Sep 09 11:29:20 AM UTC 24
Finished Sep 09 11:29:27 AM UTC 24
Peak memory 245280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655900394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.655900394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1161110993
Short name T346
Test name
Test status
Simulation time 74486097279 ps
CPU time 151.32 seconds
Started Sep 09 11:31:44 AM UTC 24
Finished Sep 09 11:34:18 AM UTC 24
Peak memory 263868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161110993 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.1161110993
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2304516320
Short name T130
Test name
Test status
Simulation time 584018562 ps
CPU time 16.77 seconds
Started Sep 09 10:49:08 AM UTC 24
Finished Sep 09 10:49:26 AM UTC 24
Peak memory 225084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304516320 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.2304516320
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.65784237
Short name T342
Test name
Test status
Simulation time 21942836942 ps
CPU time 107.98 seconds
Started Sep 09 11:36:19 AM UTC 24
Finished Sep 09 11:38:10 AM UTC 24
Peak memory 265804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65784237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.65784237
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3519520875
Short name T151
Test name
Test status
Simulation time 120201742 ps
CPU time 3.67 seconds
Started Sep 09 10:49:02 AM UTC 24
Finished Sep 09 10:49:07 AM UTC 24
Peak memory 225000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519520875 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3519520875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2705537181
Short name T258
Test name
Test status
Simulation time 5272448163 ps
CPU time 125.86 seconds
Started Sep 09 11:33:55 AM UTC 24
Finished Sep 09 11:36:04 AM UTC 24
Peak memory 278156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705537181 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2705537181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1608805687
Short name T127
Test name
Test status
Simulation time 315877412 ps
CPU time 6.24 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:08 AM UTC 24
Peak memory 227312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608805687 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1608805687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1377095190
Short name T29
Test name
Test status
Simulation time 1089810312 ps
CPU time 5.56 seconds
Started Sep 09 11:28:55 AM UTC 24
Finished Sep 09 11:29:09 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377095190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1377095190
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.800430575
Short name T199
Test name
Test status
Simulation time 4179836140 ps
CPU time 78.77 seconds
Started Sep 09 11:31:52 AM UTC 24
Finished Sep 09 11:33:13 AM UTC 24
Peak memory 265804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800430575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.800430575
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.974982221
Short name T106
Test name
Test status
Simulation time 9743516240 ps
CPU time 152.96 seconds
Started Sep 09 11:28:58 AM UTC 24
Finished Sep 09 11:31:53 AM UTC 24
Peak memory 267916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974982221 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.974982221
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.468016449
Short name T411
Test name
Test status
Simulation time 10965201795 ps
CPU time 47.16 seconds
Started Sep 09 11:31:02 AM UTC 24
Finished Sep 09 11:31:51 AM UTC 24
Peak memory 235084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468016449 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.468016449
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3991262830
Short name T132
Test name
Test status
Simulation time 2544379064 ps
CPU time 13.29 seconds
Started Sep 09 11:29:16 AM UTC 24
Finished Sep 09 11:29:32 AM UTC 24
Peak memory 261664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991262830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3991262830
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.4185804678
Short name T362
Test name
Test status
Simulation time 22441916290 ps
CPU time 281.34 seconds
Started Sep 09 11:34:23 AM UTC 24
Finished Sep 09 11:39:08 AM UTC 24
Peak memory 280200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185804678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4185804678
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2637835034
Short name T333
Test name
Test status
Simulation time 191734108879 ps
CPU time 443.41 seconds
Started Sep 09 11:31:38 AM UTC 24
Finished Sep 09 11:39:08 AM UTC 24
Peak memory 265896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637835034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.2637835034
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.2375145140
Short name T93
Test name
Test status
Simulation time 634054658897 ps
CPU time 671.81 seconds
Started Sep 09 11:38:06 AM UTC 24
Finished Sep 09 11:49:26 AM UTC 24
Peak memory 296664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375145140 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2375145140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.254191540
Short name T269
Test name
Test status
Simulation time 15318073984 ps
CPU time 167.14 seconds
Started Sep 09 11:30:38 AM UTC 24
Finished Sep 09 11:33:27 AM UTC 24
Peak memory 278124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254191540 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.254191540
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.1507745164
Short name T174
Test name
Test status
Simulation time 33222651373 ps
CPU time 277.09 seconds
Started Sep 09 11:31:29 AM UTC 24
Finished Sep 09 11:36:10 AM UTC 24
Peak memory 267984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507745164 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.1507745164
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.631287636
Short name T11
Test name
Test status
Simulation time 1494243439 ps
CPU time 4.31 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:29:03 AM UTC 24
Peak memory 245160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631287636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.631287636
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2310952575
Short name T988
Test name
Test status
Simulation time 286402632852 ps
CPU time 470.22 seconds
Started Sep 09 11:34:40 AM UTC 24
Finished Sep 09 11:42:36 AM UTC 24
Peak memory 284308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310952575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2310952575
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1793906494
Short name T419
Test name
Test status
Simulation time 19674269 ps
CPU time 0.97 seconds
Started Sep 09 11:28:55 AM UTC 24
Finished Sep 09 11:29:30 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793906494 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1793906494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.1861869238
Short name T240
Test name
Test status
Simulation time 301330859 ps
CPU time 8.61 seconds
Started Sep 09 11:29:59 AM UTC 24
Finished Sep 09 11:30:09 AM UTC 24
Peak memory 245088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861869238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1861869238
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.462143290
Short name T95
Test name
Test status
Simulation time 8460734473 ps
CPU time 107.57 seconds
Started Sep 09 11:33:41 AM UTC 24
Finished Sep 09 11:35:31 AM UTC 24
Peak memory 278112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462143290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.462143290
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3720635501
Short name T216
Test name
Test status
Simulation time 9733523767 ps
CPU time 65.94 seconds
Started Sep 09 11:30:10 AM UTC 24
Finished Sep 09 11:31:18 AM UTC 24
Peak memory 267908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720635501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.3720635501
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1006453867
Short name T1059
Test name
Test status
Simulation time 227837870 ps
CPU time 6.61 seconds
Started Sep 09 10:49:31 AM UTC 24
Finished Sep 09 10:49:39 AM UTC 24
Peak memory 225260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006453867 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.1006453867
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3266121571
Short name T231
Test name
Test status
Simulation time 3615177835 ps
CPU time 15.02 seconds
Started Sep 09 10:49:39 AM UTC 24
Finished Sep 09 10:49:56 AM UTC 24
Peak memory 227232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266121571 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.3266121571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1832741065
Short name T262
Test name
Test status
Simulation time 85739311113 ps
CPU time 584.69 seconds
Started Sep 09 11:30:01 AM UTC 24
Finished Sep 09 11:39:54 AM UTC 24
Peak memory 286312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832741065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1832741065
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.544441975
Short name T122
Test name
Test status
Simulation time 84780261 ps
CPU time 4.43 seconds
Started Sep 09 11:29:58 AM UTC 24
Finished Sep 09 11:30:03 AM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544441975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.544441975
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.716999038
Short name T327
Test name
Test status
Simulation time 83553098 ps
CPU time 2.93 seconds
Started Sep 09 11:30:30 AM UTC 24
Finished Sep 09 11:30:34 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716999038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.716999038
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.2670637672
Short name T124
Test name
Test status
Simulation time 6541241827 ps
CPU time 19 seconds
Started Sep 09 11:29:40 AM UTC 24
Finished Sep 09 11:30:04 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670637672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2670637672
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2141174334
Short name T173
Test name
Test status
Simulation time 22112422715 ps
CPU time 222.13 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:33:03 AM UTC 24
Peak memory 280208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141174334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.2141174334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.759144033
Short name T211
Test name
Test status
Simulation time 2844598542 ps
CPU time 33.19 seconds
Started Sep 09 11:31:00 AM UTC 24
Finished Sep 09 11:31:35 AM UTC 24
Peak memory 261760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759144033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.759144033
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2623801810
Short name T378
Test name
Test status
Simulation time 742306044203 ps
CPU time 578.47 seconds
Started Sep 09 11:37:28 AM UTC 24
Finished Sep 09 11:47:13 AM UTC 24
Peak memory 284388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623801810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2623801810
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3290730700
Short name T1121
Test name
Test status
Simulation time 200228465 ps
CPU time 14.36 seconds
Started Sep 09 10:49:43 AM UTC 24
Finished Sep 09 10:49:58 AM UTC 24
Peak memory 227044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290730700 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.3290730700
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1856406994
Short name T965
Test name
Test status
Simulation time 139551806751 ps
CPU time 284.66 seconds
Started Sep 09 11:35:51 AM UTC 24
Finished Sep 09 11:40:40 AM UTC 24
Peak memory 265940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856406994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1856406994
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3876066725
Short name T2
Test name
Test status
Simulation time 15999388 ps
CPU time 0.69 seconds
Started Sep 09 11:28:43 AM UTC 24
Finished Sep 09 11:28:55 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876066725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3876066725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1327064552
Short name T210
Test name
Test status
Simulation time 7720438898 ps
CPU time 98.68 seconds
Started Sep 09 11:30:18 AM UTC 24
Finished Sep 09 11:31:59 AM UTC 24
Peak memory 278164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327064552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1327064552
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.971922333
Short name T213
Test name
Test status
Simulation time 2789320812 ps
CPU time 28.98 seconds
Started Sep 09 11:31:17 AM UTC 24
Finished Sep 09 11:31:47 AM UTC 24
Peak memory 251648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971922333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.971922333
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1191391248
Short name T387
Test name
Test status
Simulation time 191554314200 ps
CPU time 385.79 seconds
Started Sep 09 11:31:26 AM UTC 24
Finished Sep 09 11:37:57 AM UTC 24
Peak memory 265892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191391248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1191391248
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.605673092
Short name T247
Test name
Test status
Simulation time 14060809233 ps
CPU time 112.77 seconds
Started Sep 09 11:32:01 AM UTC 24
Finished Sep 09 11:33:57 AM UTC 24
Peak memory 278224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605673092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.605673092
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4091731638
Short name T47
Test name
Test status
Simulation time 180821419 ps
CPU time 4.69 seconds
Started Sep 09 11:29:06 AM UTC 24
Finished Sep 09 11:29:13 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091731638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4091731638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.745346208
Short name T203
Test name
Test status
Simulation time 812192158 ps
CPU time 13.38 seconds
Started Sep 09 11:33:02 AM UTC 24
Finished Sep 09 11:33:16 AM UTC 24
Peak memory 249308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745346208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.745346208
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.3911314207
Short name T388
Test name
Test status
Simulation time 975825904 ps
CPU time 10.06 seconds
Started Sep 09 11:33:27 AM UTC 24
Finished Sep 09 11:33:38 AM UTC 24
Peak memory 247260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911314207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3911314207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.236309653
Short name T382
Test name
Test status
Simulation time 106687307464 ps
CPU time 509.44 seconds
Started Sep 09 11:34:07 AM UTC 24
Finished Sep 09 11:42:43 AM UTC 24
Peak memory 274068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236309653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.236309653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3971669236
Short name T374
Test name
Test status
Simulation time 31723295128 ps
CPU time 267.14 seconds
Started Sep 09 11:36:17 AM UTC 24
Finished Sep 09 11:40:48 AM UTC 24
Peak memory 261792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971669236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.3971669236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2514785722
Short name T110
Test name
Test status
Simulation time 42330808 ps
CPU time 2.04 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:04 AM UTC 24
Peak memory 227340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514785722 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.2514785722
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.504089220
Short name T78
Test name
Test status
Simulation time 11436783680 ps
CPU time 19.41 seconds
Started Sep 09 11:28:50 AM UTC 24
Finished Sep 09 11:29:15 AM UTC 24
Peak memory 245328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504089220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.504089220
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.185168736
Short name T81
Test name
Test status
Simulation time 138550558 ps
CPU time 5.08 seconds
Started Sep 09 10:48:58 AM UTC 24
Finished Sep 09 10:49:04 AM UTC 24
Peak memory 227380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185168736 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.185168736
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.4127736412
Short name T159
Test name
Test status
Simulation time 205154160 ps
CPU time 15.98 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:18 AM UTC 24
Peak memory 214884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127736412 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.4127736412
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3934154220
Short name T1027
Test name
Test status
Simulation time 5046445002 ps
CPU time 24.02 seconds
Started Sep 09 10:49:00 AM UTC 24
Finished Sep 09 10:49:26 AM UTC 24
Peak memory 225132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934154220 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.3934154220
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1430992637
Short name T109
Test name
Test status
Simulation time 60842305 ps
CPU time 1.33 seconds
Started Sep 09 10:49:00 AM UTC 24
Finished Sep 09 10:49:03 AM UTC 24
Peak memory 213964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430992637 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.1430992637
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2428826839
Short name T149
Test name
Test status
Simulation time 638556377 ps
CPU time 2.74 seconds
Started Sep 09 10:49:00 AM UTC 24
Finished Sep 09 10:49:04 AM UTC 24
Peak memory 225076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428826839 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2428826839
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2503004719
Short name T1004
Test name
Test status
Simulation time 28722572 ps
CPU time 0.84 seconds
Started Sep 09 10:48:59 AM UTC 24
Finished Sep 09 10:49:00 AM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503004719 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2503004719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1873175476
Short name T148
Test name
Test status
Simulation time 173970929 ps
CPU time 2.02 seconds
Started Sep 09 10:48:59 AM UTC 24
Finished Sep 09 10:49:02 AM UTC 24
Peak memory 225052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873175476 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1873175476
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3739683982
Short name T1005
Test name
Test status
Simulation time 11887512 ps
CPU time 0.99 seconds
Started Sep 09 10:48:59 AM UTC 24
Finished Sep 09 10:49:01 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739683982 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.3739683982
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.292897907
Short name T183
Test name
Test status
Simulation time 484034250 ps
CPU time 3.75 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:05 AM UTC 24
Peak memory 225068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292897907 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.292897907
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3972424436
Short name T83
Test name
Test status
Simulation time 104177020 ps
CPU time 7.49 seconds
Started Sep 09 10:48:58 AM UTC 24
Finished Sep 09 10:49:07 AM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972424436 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.3972424436
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3156500845
Short name T1015
Test name
Test status
Simulation time 487684751 ps
CPU time 10.92 seconds
Started Sep 09 10:49:02 AM UTC 24
Finished Sep 09 10:49:14 AM UTC 24
Peak memory 214816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156500845 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.3156500845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3863669760
Short name T1026
Test name
Test status
Simulation time 410578472 ps
CPU time 22.07 seconds
Started Sep 09 10:49:02 AM UTC 24
Finished Sep 09 10:49:25 AM UTC 24
Peak memory 214740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863669760 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.3863669760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1451159847
Short name T126
Test name
Test status
Simulation time 40011731 ps
CPU time 3.21 seconds
Started Sep 09 10:49:03 AM UTC 24
Finished Sep 09 10:49:08 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1451159847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.spi_device_csr_mem_rw_with_rand_reset.1451159847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1123695883
Short name T1007
Test name
Test status
Simulation time 12808920 ps
CPU time 1.16 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:03 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123695883 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1123695883
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.889748704
Short name T150
Test name
Test status
Simulation time 26742855 ps
CPU time 2.89 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:05 AM UTC 24
Peak memory 225216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889748704 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.889748704
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1937758868
Short name T1006
Test name
Test status
Simulation time 10682692 ps
CPU time 0.99 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:03 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937758868 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.1937758868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3837358267
Short name T1008
Test name
Test status
Simulation time 439197982 ps
CPU time 3.14 seconds
Started Sep 09 10:49:02 AM UTC 24
Finished Sep 09 10:49:06 AM UTC 24
Peak memory 225320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837358267 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand
ing.3837358267
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3772234474
Short name T131
Test name
Test status
Simulation time 2102532083 ps
CPU time 15.34 seconds
Started Sep 09 10:49:01 AM UTC 24
Finished Sep 09 10:49:17 AM UTC 24
Peak memory 227368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772234474 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.3772234474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.711786696
Short name T1040
Test name
Test status
Simulation time 107397606 ps
CPU time 2.54 seconds
Started Sep 09 10:49:28 AM UTC 24
Finished Sep 09 10:49:32 AM UTC 24
Peak memory 225064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=711786696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 10.spi_device_csr_mem_rw_with_rand_reset.711786696
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2822154728
Short name T1041
Test name
Test status
Simulation time 344666367 ps
CPU time 3.03 seconds
Started Sep 09 10:49:28 AM UTC 24
Finished Sep 09 10:49:32 AM UTC 24
Peak memory 224968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822154728 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.2822154728
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2744311985
Short name T1031
Test name
Test status
Simulation time 40539321 ps
CPU time 0.96 seconds
Started Sep 09 10:49:27 AM UTC 24
Finished Sep 09 10:49:29 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744311985 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.2744311985
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2476050950
Short name T1037
Test name
Test status
Simulation time 98870378 ps
CPU time 2.22 seconds
Started Sep 09 10:49:28 AM UTC 24
Finished Sep 09 10:49:32 AM UTC 24
Peak memory 214784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476050950 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstan
ding.2476050950
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1102189312
Short name T129
Test name
Test status
Simulation time 60195958 ps
CPU time 2.91 seconds
Started Sep 09 10:49:27 AM UTC 24
Finished Sep 09 10:49:31 AM UTC 24
Peak memory 225200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102189312 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.1102189312
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3817850833
Short name T1048
Test name
Test status
Simulation time 1117980877 ps
CPU time 7.5 seconds
Started Sep 09 10:49:27 AM UTC 24
Finished Sep 09 10:49:36 AM UTC 24
Peak memory 225040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817850833 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.3817850833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.848065744
Short name T1051
Test name
Test status
Simulation time 483978166 ps
CPU time 4.39 seconds
Started Sep 09 10:49:31 AM UTC 24
Finished Sep 09 10:49:36 AM UTC 24
Peak memory 227396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=848065744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 11.spi_device_csr_mem_rw_with_rand_reset.848065744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1753341257
Short name T1043
Test name
Test status
Simulation time 180048616 ps
CPU time 2.65 seconds
Started Sep 09 10:49:30 AM UTC 24
Finished Sep 09 10:49:33 AM UTC 24
Peak memory 231336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753341257 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.1753341257
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2296423245
Short name T1039
Test name
Test status
Simulation time 13303884 ps
CPU time 1.17 seconds
Started Sep 09 10:49:30 AM UTC 24
Finished Sep 09 10:49:32 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296423245 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.2296423245
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3647176373
Short name T1052
Test name
Test status
Simulation time 179318743 ps
CPU time 5.62 seconds
Started Sep 09 10:49:30 AM UTC 24
Finished Sep 09 10:49:36 AM UTC 24
Peak memory 224996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647176373 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstan
ding.3647176373
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.420704991
Short name T143
Test name
Test status
Simulation time 72767309 ps
CPU time 5.52 seconds
Started Sep 09 10:49:29 AM UTC 24
Finished Sep 09 10:49:35 AM UTC 24
Peak memory 227308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420704991 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.420704991
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1516246986
Short name T229
Test name
Test status
Simulation time 5034837049 ps
CPU time 21.87 seconds
Started Sep 09 10:49:30 AM UTC 24
Finished Sep 09 10:49:53 AM UTC 24
Peak memory 225204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516246986 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.1516246986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3885078350
Short name T1056
Test name
Test status
Simulation time 86860185 ps
CPU time 3.9 seconds
Started Sep 09 10:49:32 AM UTC 24
Finished Sep 09 10:49:38 AM UTC 24
Peak memory 227452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3885078350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.spi_device_csr_mem_rw_with_rand_reset.3885078350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4137751291
Short name T1046
Test name
Test status
Simulation time 19870486 ps
CPU time 1.98 seconds
Started Sep 09 10:49:31 AM UTC 24
Finished Sep 09 10:49:34 AM UTC 24
Peak memory 223908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137751291 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.4137751291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.1153980484
Short name T1042
Test name
Test status
Simulation time 41255538 ps
CPU time 1.06 seconds
Started Sep 09 10:49:31 AM UTC 24
Finished Sep 09 10:49:33 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153980484 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.1153980484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.325509067
Short name T1053
Test name
Test status
Simulation time 42680801 ps
CPU time 3.29 seconds
Started Sep 09 10:49:32 AM UTC 24
Finished Sep 09 10:49:37 AM UTC 24
Peak memory 225080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325509067 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstand
ing.325509067
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1448171255
Short name T228
Test name
Test status
Simulation time 1277753147 ps
CPU time 12.79 seconds
Started Sep 09 10:49:31 AM UTC 24
Finished Sep 09 10:49:45 AM UTC 24
Peak memory 224980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448171255 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.1448171255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1709611616
Short name T1058
Test name
Test status
Simulation time 123938202 ps
CPU time 3.69 seconds
Started Sep 09 10:49:34 AM UTC 24
Finished Sep 09 10:49:38 AM UTC 24
Peak memory 227184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1709611616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.spi_device_csr_mem_rw_with_rand_reset.1709611616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.353555974
Short name T1055
Test name
Test status
Simulation time 68286060 ps
CPU time 2.67 seconds
Started Sep 09 10:49:34 AM UTC 24
Finished Sep 09 10:49:37 AM UTC 24
Peak memory 225084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353555974 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.353555974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2323260207
Short name T1049
Test name
Test status
Simulation time 30491920 ps
CPU time 1.05 seconds
Started Sep 09 10:49:34 AM UTC 24
Finished Sep 09 10:49:36 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323260207 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.2323260207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1608079168
Short name T1061
Test name
Test status
Simulation time 415484116 ps
CPU time 4.58 seconds
Started Sep 09 10:49:34 AM UTC 24
Finished Sep 09 10:49:39 AM UTC 24
Peak memory 225140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608079168 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstan
ding.1608079168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1229105068
Short name T1057
Test name
Test status
Simulation time 530855865 ps
CPU time 3.98 seconds
Started Sep 09 10:49:32 AM UTC 24
Finished Sep 09 10:49:38 AM UTC 24
Peak memory 225288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229105068 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.1229105068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3915468419
Short name T226
Test name
Test status
Simulation time 341797991 ps
CPU time 8.79 seconds
Started Sep 09 10:49:32 AM UTC 24
Finished Sep 09 10:49:43 AM UTC 24
Peak memory 227040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915468419 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.3915468419
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3338918312
Short name T1062
Test name
Test status
Simulation time 799078068 ps
CPU time 2.35 seconds
Started Sep 09 10:49:36 AM UTC 24
Finished Sep 09 10:49:40 AM UTC 24
Peak memory 227444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3338918312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.spi_device_csr_mem_rw_with_rand_reset.3338918312
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3430806169
Short name T1060
Test name
Test status
Simulation time 274595239 ps
CPU time 2.9 seconds
Started Sep 09 10:49:35 AM UTC 24
Finished Sep 09 10:49:39 AM UTC 24
Peak memory 224992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430806169 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.3430806169
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2287529329
Short name T1054
Test name
Test status
Simulation time 41023153 ps
CPU time 1.13 seconds
Started Sep 09 10:49:35 AM UTC 24
Finished Sep 09 10:49:37 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287529329 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.2287529329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2179997598
Short name T1064
Test name
Test status
Simulation time 44028680 ps
CPU time 2.97 seconds
Started Sep 09 10:49:36 AM UTC 24
Finished Sep 09 10:49:40 AM UTC 24
Peak memory 225020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179997598 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstan
ding.2179997598
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2852691614
Short name T1067
Test name
Test status
Simulation time 139398695 ps
CPU time 5.64 seconds
Started Sep 09 10:49:35 AM UTC 24
Finished Sep 09 10:49:42 AM UTC 24
Peak memory 225220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852691614 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.2852691614
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.524419408
Short name T225
Test name
Test status
Simulation time 111624895 ps
CPU time 6.74 seconds
Started Sep 09 10:49:35 AM UTC 24
Finished Sep 09 10:49:43 AM UTC 24
Peak memory 225200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524419408 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.524419408
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3821337202
Short name T1068
Test name
Test status
Simulation time 353621734 ps
CPU time 2.29 seconds
Started Sep 09 10:49:38 AM UTC 24
Finished Sep 09 10:49:42 AM UTC 24
Peak memory 227184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3821337202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.spi_device_csr_mem_rw_with_rand_reset.3821337202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.3681372555
Short name T1065
Test name
Test status
Simulation time 47987158 ps
CPU time 1.68 seconds
Started Sep 09 10:49:37 AM UTC 24
Finished Sep 09 10:49:41 AM UTC 24
Peak memory 213668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681372555 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.3681372555
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.938473424
Short name T1063
Test name
Test status
Simulation time 19014981 ps
CPU time 1.05 seconds
Started Sep 09 10:49:37 AM UTC 24
Finished Sep 09 10:49:40 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938473424 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.938473424
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1952984330
Short name T1072
Test name
Test status
Simulation time 117647495 ps
CPU time 4.27 seconds
Started Sep 09 10:49:38 AM UTC 24
Finished Sep 09 10:49:43 AM UTC 24
Peak memory 225300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952984330 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstan
ding.1952984330
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1289000221
Short name T1070
Test name
Test status
Simulation time 70893707 ps
CPU time 5.65 seconds
Started Sep 09 10:49:36 AM UTC 24
Finished Sep 09 10:49:43 AM UTC 24
Peak memory 225384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289000221 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.1289000221
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1352856405
Short name T1120
Test name
Test status
Simulation time 2748434240 ps
CPU time 16.27 seconds
Started Sep 09 10:49:36 AM UTC 24
Finished Sep 09 10:49:54 AM UTC 24
Peak memory 233388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352856405 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.1352856405
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2028574995
Short name T1076
Test name
Test status
Simulation time 105387112 ps
CPU time 3.61 seconds
Started Sep 09 10:49:40 AM UTC 24
Finished Sep 09 10:49:45 AM UTC 24
Peak memory 229300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2028574995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.spi_device_csr_mem_rw_with_rand_reset.2028574995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.4188897133
Short name T1069
Test name
Test status
Simulation time 29080710 ps
CPU time 2.06 seconds
Started Sep 09 10:49:39 AM UTC 24
Finished Sep 09 10:49:43 AM UTC 24
Peak memory 225236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188897133 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.4188897133
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.645411433
Short name T1066
Test name
Test status
Simulation time 16713386 ps
CPU time 1.01 seconds
Started Sep 09 10:49:39 AM UTC 24
Finished Sep 09 10:49:42 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645411433 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.645411433
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.358528260
Short name T1078
Test name
Test status
Simulation time 83901108 ps
CPU time 3.69 seconds
Started Sep 09 10:49:40 AM UTC 24
Finished Sep 09 10:49:45 AM UTC 24
Peak memory 225120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358528260 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstand
ing.358528260
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1581735236
Short name T1071
Test name
Test status
Simulation time 275777022 ps
CPU time 2.59 seconds
Started Sep 09 10:49:39 AM UTC 24
Finished Sep 09 10:49:43 AM UTC 24
Peak memory 227248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581735236 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.1581735236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4006048979
Short name T1079
Test name
Test status
Simulation time 40715500 ps
CPU time 2.57 seconds
Started Sep 09 10:49:41 AM UTC 24
Finished Sep 09 10:49:45 AM UTC 24
Peak memory 227256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=4006048979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.spi_device_csr_mem_rw_with_rand_reset.4006048979
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3715997077
Short name T1074
Test name
Test status
Simulation time 19318306 ps
CPU time 1.87 seconds
Started Sep 09 10:49:41 AM UTC 24
Finished Sep 09 10:49:44 AM UTC 24
Peak memory 223888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715997077 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.3715997077
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1616116086
Short name T1073
Test name
Test status
Simulation time 58941245 ps
CPU time 0.97 seconds
Started Sep 09 10:49:41 AM UTC 24
Finished Sep 09 10:49:43 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616116086 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.1616116086
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3370201966
Short name T1083
Test name
Test status
Simulation time 140418290 ps
CPU time 3.44 seconds
Started Sep 09 10:49:41 AM UTC 24
Finished Sep 09 10:49:46 AM UTC 24
Peak memory 225260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370201966 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan
ding.3370201966
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.2620720498
Short name T1080
Test name
Test status
Simulation time 1234164812 ps
CPU time 4.47 seconds
Started Sep 09 10:49:40 AM UTC 24
Finished Sep 09 10:49:46 AM UTC 24
Peak memory 224980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620720498 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.2620720498
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2658854883
Short name T235
Test name
Test status
Simulation time 767055828 ps
CPU time 12.61 seconds
Started Sep 09 10:49:40 AM UTC 24
Finished Sep 09 10:49:54 AM UTC 24
Peak memory 227052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658854883 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2658854883
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.186221895
Short name T1098
Test name
Test status
Simulation time 175687398 ps
CPU time 4.11 seconds
Started Sep 09 10:49:44 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 227308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=186221895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.spi_device_csr_mem_rw_with_rand_reset.186221895
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.672355901
Short name T1082
Test name
Test status
Simulation time 141751395 ps
CPU time 2.15 seconds
Started Sep 09 10:49:43 AM UTC 24
Finished Sep 09 10:49:46 AM UTC 24
Peak memory 215076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672355901 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.672355901
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2897476256
Short name T1077
Test name
Test status
Simulation time 18490338 ps
CPU time 1.19 seconds
Started Sep 09 10:49:43 AM UTC 24
Finished Sep 09 10:49:45 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897476256 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.2897476256
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2139180722
Short name T1088
Test name
Test status
Simulation time 77396116 ps
CPU time 2.36 seconds
Started Sep 09 10:49:44 AM UTC 24
Finished Sep 09 10:49:47 AM UTC 24
Peak memory 224996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139180722 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan
ding.2139180722
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.1812811102
Short name T1075
Test name
Test status
Simulation time 116281546 ps
CPU time 1.91 seconds
Started Sep 09 10:49:41 AM UTC 24
Finished Sep 09 10:49:44 AM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812811102 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.1812811102
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.220925835
Short name T1101
Test name
Test status
Simulation time 52555796 ps
CPU time 4.74 seconds
Started Sep 09 10:49:44 AM UTC 24
Finished Sep 09 10:49:50 AM UTC 24
Peak memory 229344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=220925835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 19.spi_device_csr_mem_rw_with_rand_reset.220925835
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.169945767
Short name T1089
Test name
Test status
Simulation time 32488920 ps
CPU time 2.37 seconds
Started Sep 09 10:49:44 AM UTC 24
Finished Sep 09 10:49:48 AM UTC 24
Peak memory 225064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169945767 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.169945767
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1361175668
Short name T1084
Test name
Test status
Simulation time 123247664 ps
CPU time 1.05 seconds
Started Sep 09 10:49:44 AM UTC 24
Finished Sep 09 10:49:46 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361175668 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.1361175668
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1451842636
Short name T1099
Test name
Test status
Simulation time 122320037 ps
CPU time 4 seconds
Started Sep 09 10:49:44 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 225028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451842636 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstan
ding.1451842636
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.660620897
Short name T1090
Test name
Test status
Simulation time 480943313 ps
CPU time 3.25 seconds
Started Sep 09 10:49:44 AM UTC 24
Finished Sep 09 10:49:48 AM UTC 24
Peak memory 225192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660620897 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.660620897
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.319185911
Short name T232
Test name
Test status
Simulation time 1092300976 ps
CPU time 25.11 seconds
Started Sep 09 10:49:44 AM UTC 24
Finished Sep 09 10:50:11 AM UTC 24
Peak memory 227048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319185911 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.319185911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.3046816325
Short name T1032
Test name
Test status
Simulation time 4559315422 ps
CPU time 21.95 seconds
Started Sep 09 10:49:06 AM UTC 24
Finished Sep 09 10:49:29 AM UTC 24
Peak memory 225212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046816325 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.3046816325
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2324702178
Short name T1050
Test name
Test status
Simulation time 1795449351 ps
CPU time 28.75 seconds
Started Sep 09 10:49:06 AM UTC 24
Finished Sep 09 10:49:36 AM UTC 24
Peak memory 214960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324702178 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.2324702178
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2407254719
Short name T111
Test name
Test status
Simulation time 26267006 ps
CPU time 1.44 seconds
Started Sep 09 10:49:05 AM UTC 24
Finished Sep 09 10:49:07 AM UTC 24
Peak memory 213964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407254719 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.2407254719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3160085894
Short name T147
Test name
Test status
Simulation time 104632544 ps
CPU time 5.76 seconds
Started Sep 09 10:49:07 AM UTC 24
Finished Sep 09 10:49:14 AM UTC 24
Peak memory 229248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3160085894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.spi_device_csr_mem_rw_with_rand_reset.3160085894
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2036431908
Short name T153
Test name
Test status
Simulation time 35948757 ps
CPU time 3.11 seconds
Started Sep 09 10:49:06 AM UTC 24
Finished Sep 09 10:49:10 AM UTC 24
Peak memory 225276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036431908 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2036431908
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2450017747
Short name T1010
Test name
Test status
Simulation time 25764491 ps
CPU time 1.14 seconds
Started Sep 09 10:49:05 AM UTC 24
Finished Sep 09 10:49:07 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450017747 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2450017747
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3013986447
Short name T152
Test name
Test status
Simulation time 57888493 ps
CPU time 2.81 seconds
Started Sep 09 10:49:05 AM UTC 24
Finished Sep 09 10:49:09 AM UTC 24
Peak memory 225336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013986447 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.3013986447
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2118864060
Short name T1009
Test name
Test status
Simulation time 11518202 ps
CPU time 1.1 seconds
Started Sep 09 10:49:05 AM UTC 24
Finished Sep 09 10:49:07 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118864060 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.2118864060
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1712502969
Short name T1011
Test name
Test status
Simulation time 93861252 ps
CPU time 2.05 seconds
Started Sep 09 10:49:07 AM UTC 24
Finished Sep 09 10:49:10 AM UTC 24
Peak memory 214976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712502969 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand
ing.1712502969
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2813833144
Short name T128
Test name
Test status
Simulation time 326054201 ps
CPU time 5.13 seconds
Started Sep 09 10:49:03 AM UTC 24
Finished Sep 09 10:49:10 AM UTC 24
Peak memory 225196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813833144 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2813833144
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1517990316
Short name T224
Test name
Test status
Simulation time 210553822 ps
CPU time 17.63 seconds
Started Sep 09 10:49:04 AM UTC 24
Finished Sep 09 10:49:22 AM UTC 24
Peak memory 225140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517990316 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.1517990316
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3090363747
Short name T1087
Test name
Test status
Simulation time 51362683 ps
CPU time 1.2 seconds
Started Sep 09 10:49:45 AM UTC 24
Finished Sep 09 10:49:47 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090363747 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.3090363747
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.4045848727
Short name T1086
Test name
Test status
Simulation time 28195023 ps
CPU time 1.11 seconds
Started Sep 09 10:49:45 AM UTC 24
Finished Sep 09 10:49:47 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045848727 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.4045848727
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3528207171
Short name T1085
Test name
Test status
Simulation time 15263149 ps
CPU time 0.94 seconds
Started Sep 09 10:49:45 AM UTC 24
Finished Sep 09 10:49:47 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528207171 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.3528207171
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.2009790287
Short name T1091
Test name
Test status
Simulation time 72519482 ps
CPU time 1.21 seconds
Started Sep 09 10:49:46 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009790287 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.2009790287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.930334441
Short name T1093
Test name
Test status
Simulation time 54564167 ps
CPU time 1.16 seconds
Started Sep 09 10:49:47 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930334441 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.930334441
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.88001444
Short name T1094
Test name
Test status
Simulation time 51732695 ps
CPU time 1.13 seconds
Started Sep 09 10:49:47 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 211636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88001444 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.88001444
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3823389474
Short name T1095
Test name
Test status
Simulation time 34950547 ps
CPU time 1.14 seconds
Started Sep 09 10:49:47 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823389474 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.3823389474
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3654767215
Short name T1092
Test name
Test status
Simulation time 46151746 ps
CPU time 1 seconds
Started Sep 09 10:49:47 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654767215 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.3654767215
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2898800426
Short name T1096
Test name
Test status
Simulation time 16046941 ps
CPU time 1.19 seconds
Started Sep 09 10:49:47 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898800426 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.2898800426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3810469883
Short name T1097
Test name
Test status
Simulation time 33894308 ps
CPU time 1.03 seconds
Started Sep 09 10:49:47 AM UTC 24
Finished Sep 09 10:49:49 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810469883 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.3810469883
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1243594256
Short name T186
Test name
Test status
Simulation time 431028455 ps
CPU time 11 seconds
Started Sep 09 10:49:11 AM UTC 24
Finished Sep 09 10:49:23 AM UTC 24
Peak memory 225124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243594256 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.1243594256
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1037309376
Short name T1033
Test name
Test status
Simulation time 1848115730 ps
CPU time 18.51 seconds
Started Sep 09 10:49:10 AM UTC 24
Finished Sep 09 10:49:30 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037309376 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.1037309376
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1013908181
Short name T112
Test name
Test status
Simulation time 144976201 ps
CPU time 1.72 seconds
Started Sep 09 10:49:09 AM UTC 24
Finished Sep 09 10:49:11 AM UTC 24
Peak memory 226232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013908181 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.1013908181
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2740075768
Short name T145
Test name
Test status
Simulation time 615053600 ps
CPU time 4.51 seconds
Started Sep 09 10:49:11 AM UTC 24
Finished Sep 09 10:49:17 AM UTC 24
Peak memory 229292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2740075768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.spi_device_csr_mem_rw_with_rand_reset.2740075768
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.285538837
Short name T1014
Test name
Test status
Simulation time 415313439 ps
CPU time 3.63 seconds
Started Sep 09 10:49:09 AM UTC 24
Finished Sep 09 10:49:13 AM UTC 24
Peak memory 225256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285538837 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.285538837
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.674158025
Short name T1012
Test name
Test status
Simulation time 37657819 ps
CPU time 1.02 seconds
Started Sep 09 10:49:08 AM UTC 24
Finished Sep 09 10:49:10 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674158025 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.674158025
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.759641298
Short name T155
Test name
Test status
Simulation time 51808996 ps
CPU time 2.47 seconds
Started Sep 09 10:49:09 AM UTC 24
Finished Sep 09 10:49:12 AM UTC 24
Peak memory 225124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759641298 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.759641298
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2323324915
Short name T1013
Test name
Test status
Simulation time 12804950 ps
CPU time 0.99 seconds
Started Sep 09 10:49:09 AM UTC 24
Finished Sep 09 10:49:11 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323324915 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.2323324915
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1318629083
Short name T184
Test name
Test status
Simulation time 85978611 ps
CPU time 2.34 seconds
Started Sep 09 10:49:11 AM UTC 24
Finished Sep 09 10:49:14 AM UTC 24
Peak memory 214808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318629083 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstand
ing.1318629083
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1622173307
Short name T138
Test name
Test status
Simulation time 331722777 ps
CPU time 3.37 seconds
Started Sep 09 10:49:08 AM UTC 24
Finished Sep 09 10:49:13 AM UTC 24
Peak memory 227324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622173307 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1622173307
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.3238432374
Short name T1102
Test name
Test status
Simulation time 20436724 ps
CPU time 1.09 seconds
Started Sep 09 10:49:48 AM UTC 24
Finished Sep 09 10:49:50 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238432374 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.3238432374
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3142975652
Short name T1103
Test name
Test status
Simulation time 26393729 ps
CPU time 1.14 seconds
Started Sep 09 10:49:48 AM UTC 24
Finished Sep 09 10:49:50 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142975652 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.3142975652
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.1856950035
Short name T1104
Test name
Test status
Simulation time 27384011 ps
CPU time 1.12 seconds
Started Sep 09 10:49:48 AM UTC 24
Finished Sep 09 10:49:50 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856950035 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.1856950035
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1423656976
Short name T1100
Test name
Test status
Simulation time 16474362 ps
CPU time 0.86 seconds
Started Sep 09 10:49:48 AM UTC 24
Finished Sep 09 10:49:50 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423656976 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.1423656976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1517527680
Short name T1105
Test name
Test status
Simulation time 20465205 ps
CPU time 1.11 seconds
Started Sep 09 10:49:48 AM UTC 24
Finished Sep 09 10:49:50 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517527680 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.1517527680
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2934899180
Short name T1106
Test name
Test status
Simulation time 13161949 ps
CPU time 0.88 seconds
Started Sep 09 10:49:49 AM UTC 24
Finished Sep 09 10:49:51 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934899180 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.2934899180
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3047234616
Short name T1081
Test name
Test status
Simulation time 28599394 ps
CPU time 1.05 seconds
Started Sep 09 10:49:49 AM UTC 24
Finished Sep 09 10:49:51 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047234616 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.3047234616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1660668951
Short name T1107
Test name
Test status
Simulation time 14792312 ps
CPU time 1.07 seconds
Started Sep 09 10:49:49 AM UTC 24
Finished Sep 09 10:49:52 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660668951 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.1660668951
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.4158231041
Short name T1109
Test name
Test status
Simulation time 19178118 ps
CPU time 1.09 seconds
Started Sep 09 10:49:49 AM UTC 24
Finished Sep 09 10:49:52 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158231041 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.4158231041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.4100928458
Short name T1110
Test name
Test status
Simulation time 13203943 ps
CPU time 1.12 seconds
Started Sep 09 10:49:49 AM UTC 24
Finished Sep 09 10:49:52 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100928458 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.4100928458
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3977243616
Short name T1023
Test name
Test status
Simulation time 206476259 ps
CPU time 7.96 seconds
Started Sep 09 10:49:15 AM UTC 24
Finished Sep 09 10:49:24 AM UTC 24
Peak memory 225072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977243616 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.3977243616
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2926546754
Short name T1122
Test name
Test status
Simulation time 6270585430 ps
CPU time 42.4 seconds
Started Sep 09 10:49:15 AM UTC 24
Finished Sep 09 10:49:59 AM UTC 24
Peak memory 217132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926546754 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.2926546754
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.161285689
Short name T157
Test name
Test status
Simulation time 23557058 ps
CPU time 1.55 seconds
Started Sep 09 10:49:14 AM UTC 24
Finished Sep 09 10:49:16 AM UTC 24
Peak memory 214020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161285689 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.161285689
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3748928735
Short name T1020
Test name
Test status
Simulation time 74438902 ps
CPU time 4.55 seconds
Started Sep 09 10:49:15 AM UTC 24
Finished Sep 09 10:49:20 AM UTC 24
Peak memory 227240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3748928735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.spi_device_csr_mem_rw_with_rand_reset.3748928735
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2608331263
Short name T158
Test name
Test status
Simulation time 152363469 ps
CPU time 1.58 seconds
Started Sep 09 10:49:14 AM UTC 24
Finished Sep 09 10:49:16 AM UTC 24
Peak memory 223892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608331263 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2608331263
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.300566253
Short name T1017
Test name
Test status
Simulation time 12237734 ps
CPU time 1.07 seconds
Started Sep 09 10:49:12 AM UTC 24
Finished Sep 09 10:49:14 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300566253 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.300566253
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1307958225
Short name T156
Test name
Test status
Simulation time 33722152 ps
CPU time 1.98 seconds
Started Sep 09 10:49:12 AM UTC 24
Finished Sep 09 10:49:15 AM UTC 24
Peak memory 223948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307958225 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.1307958225
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.1030103400
Short name T1016
Test name
Test status
Simulation time 49584240 ps
CPU time 1.03 seconds
Started Sep 09 10:49:12 AM UTC 24
Finished Sep 09 10:49:14 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030103400 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.1030103400
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1057793159
Short name T185
Test name
Test status
Simulation time 900740405 ps
CPU time 4.89 seconds
Started Sep 09 10:49:15 AM UTC 24
Finished Sep 09 10:49:21 AM UTC 24
Peak memory 225084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057793159 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstand
ing.1057793159
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2864249746
Short name T141
Test name
Test status
Simulation time 54977712 ps
CPU time 2.82 seconds
Started Sep 09 10:49:11 AM UTC 24
Finished Sep 09 10:49:15 AM UTC 24
Peak memory 225244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864249746 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2864249746
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.764811426
Short name T233
Test name
Test status
Simulation time 224482723 ps
CPU time 8.38 seconds
Started Sep 09 10:49:11 AM UTC 24
Finished Sep 09 10:49:21 AM UTC 24
Peak memory 225060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764811426 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.764811426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2632800862
Short name T1112
Test name
Test status
Simulation time 51658093 ps
CPU time 1.19 seconds
Started Sep 09 10:49:50 AM UTC 24
Finished Sep 09 10:49:52 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632800862 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.2632800862
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2324365353
Short name T1111
Test name
Test status
Simulation time 12072972 ps
CPU time 1.04 seconds
Started Sep 09 10:49:50 AM UTC 24
Finished Sep 09 10:49:52 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324365353 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.2324365353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.263928097
Short name T1113
Test name
Test status
Simulation time 70421577 ps
CPU time 1.17 seconds
Started Sep 09 10:49:50 AM UTC 24
Finished Sep 09 10:49:52 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263928097 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.263928097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.808865707
Short name T1108
Test name
Test status
Simulation time 15658491 ps
CPU time 0.8 seconds
Started Sep 09 10:49:50 AM UTC 24
Finished Sep 09 10:49:52 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808865707 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.808865707
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.923732605
Short name T1117
Test name
Test status
Simulation time 43521056 ps
CPU time 1.13 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:53 AM UTC 24
Peak memory 211632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923732605 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.923732605
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.697929541
Short name T1115
Test name
Test status
Simulation time 15374271 ps
CPU time 1.03 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:53 AM UTC 24
Peak memory 211652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697929541 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.697929541
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.3911568556
Short name T1119
Test name
Test status
Simulation time 61157821 ps
CPU time 1.14 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:53 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911568556 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.3911568556
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2475351757
Short name T1116
Test name
Test status
Simulation time 15045334 ps
CPU time 1.1 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:53 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475351757 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.2475351757
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2418882439
Short name T1118
Test name
Test status
Simulation time 11736339 ps
CPU time 0.97 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:53 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418882439 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.2418882439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3423281809
Short name T1114
Test name
Test status
Simulation time 118895386 ps
CPU time 0.89 seconds
Started Sep 09 10:49:51 AM UTC 24
Finished Sep 09 10:49:53 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423281809 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.3423281809
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2767449155
Short name T1022
Test name
Test status
Simulation time 51104751 ps
CPU time 2.57 seconds
Started Sep 09 10:49:17 AM UTC 24
Finished Sep 09 10:49:21 AM UTC 24
Peak memory 225148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2767449155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.spi_device_csr_mem_rw_with_rand_reset.2767449155
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.4132521253
Short name T160
Test name
Test status
Simulation time 69493569 ps
CPU time 2.4 seconds
Started Sep 09 10:49:16 AM UTC 24
Finished Sep 09 10:49:20 AM UTC 24
Peak memory 225084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132521253 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4132521253
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3517319734
Short name T1018
Test name
Test status
Simulation time 20028478 ps
CPU time 1.23 seconds
Started Sep 09 10:49:16 AM UTC 24
Finished Sep 09 10:49:18 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517319734 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3517319734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.836283313
Short name T1019
Test name
Test status
Simulation time 96711586 ps
CPU time 2.03 seconds
Started Sep 09 10:49:17 AM UTC 24
Finished Sep 09 10:49:20 AM UTC 24
Peak memory 225248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836283313 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.836283313
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.370191558
Short name T139
Test name
Test status
Simulation time 254487740 ps
CPU time 3.99 seconds
Started Sep 09 10:49:15 AM UTC 24
Finished Sep 09 10:49:20 AM UTC 24
Peak memory 225244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370191558 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.370191558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.101925726
Short name T230
Test name
Test status
Simulation time 1107381255 ps
CPU time 25.11 seconds
Started Sep 09 10:49:16 AM UTC 24
Finished Sep 09 10:49:42 AM UTC 24
Peak memory 227108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101925726 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.101925726
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2536497571
Short name T1029
Test name
Test status
Simulation time 160307648 ps
CPU time 5.04 seconds
Started Sep 09 10:49:21 AM UTC 24
Finished Sep 09 10:49:27 AM UTC 24
Peak memory 229168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2536497571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.spi_device_csr_mem_rw_with_rand_reset.2536497571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3836498682
Short name T161
Test name
Test status
Simulation time 168916648 ps
CPU time 1.9 seconds
Started Sep 09 10:49:20 AM UTC 24
Finished Sep 09 10:49:22 AM UTC 24
Peak memory 213672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836498682 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3836498682
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1710888426
Short name T1021
Test name
Test status
Simulation time 32565829 ps
CPU time 1.15 seconds
Started Sep 09 10:49:18 AM UTC 24
Finished Sep 09 10:49:21 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710888426 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1710888426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2071993229
Short name T1024
Test name
Test status
Simulation time 104853714 ps
CPU time 2.22 seconds
Started Sep 09 10:49:21 AM UTC 24
Finished Sep 09 10:49:24 AM UTC 24
Peak memory 214808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071993229 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstand
ing.2071993229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3379114646
Short name T140
Test name
Test status
Simulation time 170849913 ps
CPU time 4.66 seconds
Started Sep 09 10:49:17 AM UTC 24
Finished Sep 09 10:49:23 AM UTC 24
Peak memory 225184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379114646 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3379114646
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3346638781
Short name T234
Test name
Test status
Simulation time 579164141 ps
CPU time 19.05 seconds
Started Sep 09 10:49:18 AM UTC 24
Finished Sep 09 10:49:39 AM UTC 24
Peak memory 225088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346638781 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.3346638781
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3854959683
Short name T1028
Test name
Test status
Simulation time 44112365 ps
CPU time 3.48 seconds
Started Sep 09 10:49:22 AM UTC 24
Finished Sep 09 10:49:27 AM UTC 24
Peak memory 229176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3854959683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.spi_device_csr_mem_rw_with_rand_reset.3854959683
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3780854386
Short name T188
Test name
Test status
Simulation time 328911708 ps
CPU time 2.94 seconds
Started Sep 09 10:49:22 AM UTC 24
Finished Sep 09 10:49:26 AM UTC 24
Peak memory 225088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780854386 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3780854386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.498395955
Short name T1025
Test name
Test status
Simulation time 46320407 ps
CPU time 1.2 seconds
Started Sep 09 10:49:22 AM UTC 24
Finished Sep 09 10:49:24 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498395955 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.498395955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1419151806
Short name T187
Test name
Test status
Simulation time 134386835 ps
CPU time 2.1 seconds
Started Sep 09 10:49:22 AM UTC 24
Finished Sep 09 10:49:25 AM UTC 24
Peak memory 225048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419151806 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand
ing.1419151806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1085405705
Short name T146
Test name
Test status
Simulation time 33334743 ps
CPU time 2.6 seconds
Started Sep 09 10:49:21 AM UTC 24
Finished Sep 09 10:49:24 AM UTC 24
Peak memory 227292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085405705 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1085405705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2458907202
Short name T227
Test name
Test status
Simulation time 935528711 ps
CPU time 9.23 seconds
Started Sep 09 10:49:22 AM UTC 24
Finished Sep 09 10:49:32 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458907202 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.2458907202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1268042513
Short name T1036
Test name
Test status
Simulation time 41705298 ps
CPU time 4.67 seconds
Started Sep 09 10:49:25 AM UTC 24
Finished Sep 09 10:49:30 AM UTC 24
Peak memory 227176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1268042513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.spi_device_csr_mem_rw_with_rand_reset.1268042513
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2272392304
Short name T154
Test name
Test status
Simulation time 34050371 ps
CPU time 3.79 seconds
Started Sep 09 10:49:24 AM UTC 24
Finished Sep 09 10:49:30 AM UTC 24
Peak memory 225276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272392304 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2272392304
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3335116178
Short name T196
Test name
Test status
Simulation time 124188914 ps
CPU time 1.05 seconds
Started Sep 09 10:49:24 AM UTC 24
Finished Sep 09 10:49:27 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335116178 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3335116178
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2941694178
Short name T1035
Test name
Test status
Simulation time 217941103 ps
CPU time 4.52 seconds
Started Sep 09 10:49:25 AM UTC 24
Finished Sep 09 10:49:30 AM UTC 24
Peak memory 224984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941694178 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand
ing.2941694178
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.1863885744
Short name T144
Test name
Test status
Simulation time 112314727 ps
CPU time 4.39 seconds
Started Sep 09 10:49:23 AM UTC 24
Finished Sep 09 10:49:29 AM UTC 24
Peak memory 227232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863885744 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1863885744
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.3251484703
Short name T1038
Test name
Test status
Simulation time 420164357 ps
CPU time 7.41 seconds
Started Sep 09 10:49:23 AM UTC 24
Finished Sep 09 10:49:32 AM UTC 24
Peak memory 227128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251484703 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.3251484703
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1876187100
Short name T1044
Test name
Test status
Simulation time 165651551 ps
CPU time 5.34 seconds
Started Sep 09 10:49:27 AM UTC 24
Finished Sep 09 10:49:33 AM UTC 24
Peak memory 227308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1876187100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.spi_device_csr_mem_rw_with_rand_reset.1876187100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.1269906582
Short name T1034
Test name
Test status
Simulation time 101409769 ps
CPU time 3.06 seconds
Started Sep 09 10:49:26 AM UTC 24
Finished Sep 09 10:49:30 AM UTC 24
Peak memory 225000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269906582 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1269906582
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3378216110
Short name T1030
Test name
Test status
Simulation time 55903860 ps
CPU time 1.15 seconds
Started Sep 09 10:49:26 AM UTC 24
Finished Sep 09 10:49:28 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378216110 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3378216110
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2436265262
Short name T1045
Test name
Test status
Simulation time 1798595066 ps
CPU time 5.63 seconds
Started Sep 09 10:49:27 AM UTC 24
Finished Sep 09 10:49:34 AM UTC 24
Peak memory 225272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436265262 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand
ing.2436265262
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1058891924
Short name T142
Test name
Test status
Simulation time 38455466 ps
CPU time 2.68 seconds
Started Sep 09 10:49:25 AM UTC 24
Finished Sep 09 10:49:28 AM UTC 24
Peak memory 227308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058891924 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1058891924
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.1238610987
Short name T1047
Test name
Test status
Simulation time 417446409 ps
CPU time 7.59 seconds
Started Sep 09 10:49:26 AM UTC 24
Finished Sep 09 10:49:35 AM UTC 24
Peak memory 225004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238610987 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.1238610987
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.2143825570
Short name T7
Test name
Test status
Simulation time 148764096 ps
CPU time 4.01 seconds
Started Sep 09 11:28:50 AM UTC 24
Finished Sep 09 11:28:59 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143825570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2143825570
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1898926038
Short name T4
Test name
Test status
Simulation time 474719078 ps
CPU time 2.62 seconds
Started Sep 09 11:28:50 AM UTC 24
Finished Sep 09 11:28:57 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898926038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1898926038
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3352649179
Short name T267
Test name
Test status
Simulation time 118375598892 ps
CPU time 238.8 seconds
Started Sep 09 11:28:52 AM UTC 24
Finished Sep 09 11:32:55 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352649179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.3352649179
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1939795601
Short name T85
Test name
Test status
Simulation time 9020644966 ps
CPU time 72.75 seconds
Started Sep 09 11:28:50 AM UTC 24
Finished Sep 09 11:30:08 AM UTC 24
Peak memory 261780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939795601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.1939795601
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.4098513500
Short name T1
Test name
Test status
Simulation time 181283884 ps
CPU time 3.55 seconds
Started Sep 09 11:28:46 AM UTC 24
Finished Sep 09 11:28:52 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098513500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4098513500
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.1267134911
Short name T135
Test name
Test status
Simulation time 12390594490 ps
CPU time 96.02 seconds
Started Sep 09 11:28:46 AM UTC 24
Finished Sep 09 11:30:25 AM UTC 24
Peak memory 261788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267134911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1267134911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1013429223
Short name T13
Test name
Test status
Simulation time 855617882 ps
CPU time 10.28 seconds
Started Sep 09 11:28:50 AM UTC 24
Finished Sep 09 11:29:05 AM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013429223 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.1013429223
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2726717522
Short name T20
Test name
Test status
Simulation time 35406996 ps
CPU time 0.94 seconds
Started Sep 09 11:28:55 AM UTC 24
Finished Sep 09 11:29:30 AM UTC 24
Peak memory 257932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726717522 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2726717522
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2189199317
Short name T15
Test name
Test status
Simulation time 52042350 ps
CPU time 1.03 seconds
Started Sep 09 11:28:55 AM UTC 24
Finished Sep 09 11:29:20 AM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189199317 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.2189199317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.695304127
Short name T3
Test name
Test status
Simulation time 471334372 ps
CPU time 2.79 seconds
Started Sep 09 11:28:49 AM UTC 24
Finished Sep 09 11:28:56 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695304127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.695304127
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.3814033341
Short name T79
Test name
Test status
Simulation time 14515476 ps
CPU time 0.62 seconds
Started Sep 09 11:28:58 AM UTC 24
Finished Sep 09 11:29:19 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814033341 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3814033341
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.716088771
Short name T9
Test name
Test status
Simulation time 1378028660 ps
CPU time 3.62 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:29:02 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716088771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.716088771
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.2333049773
Short name T418
Test name
Test status
Simulation time 30954567 ps
CPU time 0.83 seconds
Started Sep 09 11:28:55 AM UTC 24
Finished Sep 09 11:29:30 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333049773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2333049773
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1855490782
Short name T872
Test name
Test status
Simulation time 125591959525 ps
CPU time 591.54 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:39:16 AM UTC 24
Peak memory 280232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855490782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1855490782
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.1052322468
Short name T422
Test name
Test status
Simulation time 1814816835 ps
CPU time 27.23 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:29:36 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052322468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1052322468
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1517726089
Short name T238
Test name
Test status
Simulation time 47460104894 ps
CPU time 177.76 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:32:08 AM UTC 24
Peak memory 251536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517726089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.1517726089
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.1061500840
Short name T76
Test name
Test status
Simulation time 1822746214 ps
CPU time 10.54 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:29:09 AM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061500840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1061500840
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.4158887082
Short name T63
Test name
Test status
Simulation time 27271539024 ps
CPU time 13.9 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:29:12 AM UTC 24
Peak memory 245280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158887082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4158887082
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.68586
Short name T179
Test name
Test status
Simulation time 5210373580 ps
CPU time 10.74 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:29:29 AM UTC 24
Peak memory 231456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68586 -assert nopostproc +UVM_TESTNAME=spi_device_base
_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.68586
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.543485686
Short name T27
Test name
Test status
Simulation time 23864767 ps
CPU time 0.84 seconds
Started Sep 09 11:28:55 AM UTC 24
Finished Sep 09 11:29:04 AM UTC 24
Peak memory 216448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543485686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.543485686
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3299434303
Short name T26
Test name
Test status
Simulation time 173698752 ps
CPU time 0.76 seconds
Started Sep 09 11:28:55 AM UTC 24
Finished Sep 09 11:29:04 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299434303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3299434303
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.836286860
Short name T24
Test name
Test status
Simulation time 10702966702 ps
CPU time 14.53 seconds
Started Sep 09 11:28:56 AM UTC 24
Finished Sep 09 11:29:23 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836286860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.836286860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.373890328
Short name T438
Test name
Test status
Simulation time 14926505 ps
CPU time 1.07 seconds
Started Sep 09 11:30:22 AM UTC 24
Finished Sep 09 11:30:24 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373890328 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.373890328
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1671860891
Short name T120
Test name
Test status
Simulation time 107116244 ps
CPU time 3.18 seconds
Started Sep 09 11:30:16 AM UTC 24
Finished Sep 09 11:30:20 AM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671860891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1671860891
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.824695170
Short name T453
Test name
Test status
Simulation time 66132423 ps
CPU time 1.06 seconds
Started Sep 09 11:30:11 AM UTC 24
Finished Sep 09 11:30:13 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824695170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.824695170
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.732968736
Short name T288
Test name
Test status
Simulation time 63762471157 ps
CPU time 106.72 seconds
Started Sep 09 11:30:17 AM UTC 24
Finished Sep 09 11:32:06 AM UTC 24
Peak memory 265868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732968736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.732968736
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1590622862
Short name T214
Test name
Test status
Simulation time 3876353063 ps
CPU time 80.39 seconds
Started Sep 09 11:30:19 AM UTC 24
Finished Sep 09 11:31:42 AM UTC 24
Peak memory 267936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590622862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.1590622862
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.3757836168
Short name T287
Test name
Test status
Simulation time 444538881 ps
CPU time 18.05 seconds
Started Sep 09 11:30:17 AM UTC 24
Finished Sep 09 11:30:37 AM UTC 24
Peak memory 244532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757836168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3757836168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1076402194
Short name T248
Test name
Test status
Simulation time 3910643132 ps
CPU time 38.21 seconds
Started Sep 09 11:30:17 AM UTC 24
Finished Sep 09 11:30:57 AM UTC 24
Peak memory 235088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076402194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.1076402194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.2518823842
Short name T134
Test name
Test status
Simulation time 680424902 ps
CPU time 7.62 seconds
Started Sep 09 11:30:15 AM UTC 24
Finished Sep 09 11:30:24 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518823842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2518823842
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.2197156147
Short name T344
Test name
Test status
Simulation time 14088046621 ps
CPU time 19.14 seconds
Started Sep 09 11:30:15 AM UTC 24
Finished Sep 09 11:30:35 AM UTC 24
Peak memory 245280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197156147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2197156147
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3646561156
Short name T339
Test name
Test status
Simulation time 54450246236 ps
CPU time 43.11 seconds
Started Sep 09 11:30:15 AM UTC 24
Finished Sep 09 11:30:59 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646561156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.3646561156
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.97981567
Short name T308
Test name
Test status
Simulation time 1108916766 ps
CPU time 4.98 seconds
Started Sep 09 11:30:14 AM UTC 24
Finished Sep 09 11:30:20 AM UTC 24
Peak memory 245160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97981567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.97981567
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2214023100
Short name T136
Test name
Test status
Simulation time 11069502452 ps
CPU time 18.32 seconds
Started Sep 09 11:30:17 AM UTC 24
Finished Sep 09 11:30:37 AM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214023100 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.2214023100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.451894399
Short name T113
Test name
Test status
Simulation time 1671459521 ps
CPU time 5.31 seconds
Started Sep 09 11:30:12 AM UTC 24
Finished Sep 09 11:30:19 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451894399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.451894399
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2042629336
Short name T75
Test name
Test status
Simulation time 481026077 ps
CPU time 3.95 seconds
Started Sep 09 11:30:12 AM UTC 24
Finished Sep 09 11:30:18 AM UTC 24
Peak memory 217084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042629336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2042629336
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.645942675
Short name T456
Test name
Test status
Simulation time 65273758 ps
CPU time 1.05 seconds
Started Sep 09 11:30:14 AM UTC 24
Finished Sep 09 11:30:16 AM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645942675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.645942675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.3654687444
Short name T457
Test name
Test status
Simulation time 44994184 ps
CPU time 1.23 seconds
Started Sep 09 11:30:14 AM UTC 24
Finished Sep 09 11:30:16 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654687444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3654687444
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.2396132828
Short name T284
Test name
Test status
Simulation time 21314955928 ps
CPU time 19.3 seconds
Started Sep 09 11:30:15 AM UTC 24
Finished Sep 09 11:30:35 AM UTC 24
Peak memory 235084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396132828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2396132828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.16285438
Short name T162
Test name
Test status
Simulation time 11898926 ps
CPU time 1.08 seconds
Started Sep 09 11:30:38 AM UTC 24
Finished Sep 09 11:30:40 AM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16285438 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.16285438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3914019269
Short name T323
Test name
Test status
Simulation time 1756176271 ps
CPU time 12.12 seconds
Started Sep 09 11:30:31 AM UTC 24
Finished Sep 09 11:30:44 AM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914019269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3914019269
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.5309820
Short name T452
Test name
Test status
Simulation time 38910601 ps
CPU time 1.18 seconds
Started Sep 09 11:30:25 AM UTC 24
Finished Sep 09 11:30:27 AM UTC 24
Peak memory 215792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5309820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.5309820
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1898786057
Short name T510
Test name
Test status
Simulation time 35459595259 ps
CPU time 85.77 seconds
Started Sep 09 11:30:36 AM UTC 24
Finished Sep 09 11:32:04 AM UTC 24
Peak memory 249428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898786057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1898786057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3179482526
Short name T408
Test name
Test status
Simulation time 4019466443 ps
CPU time 7.4 seconds
Started Sep 09 11:30:36 AM UTC 24
Finished Sep 09 11:30:45 AM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179482526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3179482526
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1654697047
Short name T107
Test name
Test status
Simulation time 8299717042 ps
CPU time 82.44 seconds
Started Sep 09 11:30:37 AM UTC 24
Finished Sep 09 11:32:02 AM UTC 24
Peak memory 267920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654697047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.1654697047
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.3107524138
Short name T462
Test name
Test status
Simulation time 686072208 ps
CPU time 10.57 seconds
Started Sep 09 11:30:34 AM UTC 24
Finished Sep 09 11:30:46 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107524138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3107524138
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.601593808
Short name T49
Test name
Test status
Simulation time 1898551319 ps
CPU time 15.4 seconds
Started Sep 09 11:30:35 AM UTC 24
Finished Sep 09 11:30:52 AM UTC 24
Peak memory 247312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601593808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.601593808
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.540329488
Short name T166
Test name
Test status
Simulation time 427234275 ps
CPU time 10.76 seconds
Started Sep 09 11:30:29 AM UTC 24
Finished Sep 09 11:30:41 AM UTC 24
Peak memory 241836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540329488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.540329488
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1178387684
Short name T218
Test name
Test status
Simulation time 7109890765 ps
CPU time 34.4 seconds
Started Sep 09 11:30:29 AM UTC 24
Finished Sep 09 11:31:05 AM UTC 24
Peak memory 245284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178387684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1178387684
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3744441871
Short name T65
Test name
Test status
Simulation time 41120478268 ps
CPU time 24.8 seconds
Started Sep 09 11:30:28 AM UTC 24
Finished Sep 09 11:30:54 AM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744441871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.3744441871
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3967087970
Short name T286
Test name
Test status
Simulation time 179246166 ps
CPU time 4.22 seconds
Started Sep 09 11:30:28 AM UTC 24
Finished Sep 09 11:30:33 AM UTC 24
Peak memory 234860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967087970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3967087970
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1323684705
Short name T168
Test name
Test status
Simulation time 103093463 ps
CPU time 5.74 seconds
Started Sep 09 11:30:35 AM UTC 24
Finished Sep 09 11:30:42 AM UTC 24
Peak memory 233568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323684705 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.1323684705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2371695737
Short name T409
Test name
Test status
Simulation time 976796909 ps
CPU time 15.68 seconds
Started Sep 09 11:30:26 AM UTC 24
Finished Sep 09 11:30:43 AM UTC 24
Peak memory 227436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371695737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2371695737
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3511748537
Short name T458
Test name
Test status
Simulation time 721987685 ps
CPU time 1.77 seconds
Started Sep 09 11:30:25 AM UTC 24
Finished Sep 09 11:30:28 AM UTC 24
Peak memory 216452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511748537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3511748537
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.3627234930
Short name T137
Test name
Test status
Simulation time 184863732 ps
CPU time 9.27 seconds
Started Sep 09 11:30:27 AM UTC 24
Finished Sep 09 11:30:37 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627234930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3627234930
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1790117829
Short name T459
Test name
Test status
Simulation time 24190370 ps
CPU time 1.2 seconds
Started Sep 09 11:30:27 AM UTC 24
Finished Sep 09 11:30:29 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790117829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1790117829
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.1694210262
Short name T465
Test name
Test status
Simulation time 44231327 ps
CPU time 1.02 seconds
Started Sep 09 11:30:52 AM UTC 24
Finished Sep 09 11:30:54 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694210262 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.1694210262
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2249169674
Short name T488
Test name
Test status
Simulation time 14999034235 ps
CPU time 43.67 seconds
Started Sep 09 11:30:44 AM UTC 24
Finished Sep 09 11:31:30 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249169674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2249169674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1033779909
Short name T460
Test name
Test status
Simulation time 16379414 ps
CPU time 1.16 seconds
Started Sep 09 11:30:41 AM UTC 24
Finished Sep 09 11:30:43 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033779909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1033779909
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.2426059317
Short name T251
Test name
Test status
Simulation time 26109555134 ps
CPU time 102.39 seconds
Started Sep 09 11:30:46 AM UTC 24
Finished Sep 09 11:32:30 AM UTC 24
Peak memory 261708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426059317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2426059317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2550082482
Short name T410
Test name
Test status
Simulation time 380867516 ps
CPU time 5.25 seconds
Started Sep 09 11:30:47 AM UTC 24
Finished Sep 09 11:30:53 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550082482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2550082482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1476972994
Short name T294
Test name
Test status
Simulation time 72368572958 ps
CPU time 243.96 seconds
Started Sep 09 11:30:47 AM UTC 24
Finished Sep 09 11:34:55 AM UTC 24
Peak memory 263800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476972994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.1476972994
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.22240817
Short name T463
Test name
Test status
Simulation time 36557303 ps
CPU time 3.31 seconds
Started Sep 09 11:30:44 AM UTC 24
Finished Sep 09 11:30:49 AM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22240817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.22240817
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2508269331
Short name T67
Test name
Test status
Simulation time 4218456894 ps
CPU time 48.73 seconds
Started Sep 09 11:30:46 AM UTC 24
Finished Sep 09 11:31:36 AM UTC 24
Peak memory 265820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508269331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.2508269331
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.742925031
Short name T300
Test name
Test status
Simulation time 20205243108 ps
CPU time 21.15 seconds
Started Sep 09 11:30:44 AM UTC 24
Finished Sep 09 11:31:07 AM UTC 24
Peak memory 235100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742925031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.742925031
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.1288416638
Short name T266
Test name
Test status
Simulation time 18205283393 ps
CPU time 76.44 seconds
Started Sep 09 11:30:44 AM UTC 24
Finished Sep 09 11:32:03 AM UTC 24
Peak memory 245276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288416638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1288416638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.1397866557
Short name T331
Test name
Test status
Simulation time 9555912748 ps
CPU time 10.09 seconds
Started Sep 09 11:30:43 AM UTC 24
Finished Sep 09 11:30:54 AM UTC 24
Peak memory 245388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397866557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.1397866557
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3501284729
Short name T307
Test name
Test status
Simulation time 5619414948 ps
CPU time 13.93 seconds
Started Sep 09 11:30:43 AM UTC 24
Finished Sep 09 11:30:58 AM UTC 24
Peak memory 234952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501284729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3501284729
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.976967774
Short name T470
Test name
Test status
Simulation time 1364695380 ps
CPU time 12.45 seconds
Started Sep 09 11:30:46 AM UTC 24
Finished Sep 09 11:30:59 AM UTC 24
Peak memory 233452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976967774 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.976967774
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.1541637071
Short name T245
Test name
Test status
Simulation time 49754078987 ps
CPU time 219.57 seconds
Started Sep 09 11:30:50 AM UTC 24
Finished Sep 09 11:34:33 AM UTC 24
Peak memory 261760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541637071 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.1541637071
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.763120972
Short name T398
Test name
Test status
Simulation time 6054469097 ps
CPU time 9.38 seconds
Started Sep 09 11:30:41 AM UTC 24
Finished Sep 09 11:30:51 AM UTC 24
Peak memory 227624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763120972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.763120972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3446573311
Short name T464
Test name
Test status
Simulation time 6036203099 ps
CPU time 9.17 seconds
Started Sep 09 11:30:41 AM UTC 24
Finished Sep 09 11:30:51 AM UTC 24
Peak memory 227512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446573311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3446573311
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.3377438717
Short name T413
Test name
Test status
Simulation time 24560815 ps
CPU time 1.53 seconds
Started Sep 09 11:30:42 AM UTC 24
Finished Sep 09 11:30:44 AM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377438717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3377438717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.4025091241
Short name T461
Test name
Test status
Simulation time 49116440 ps
CPU time 1.1 seconds
Started Sep 09 11:30:41 AM UTC 24
Finished Sep 09 11:30:43 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025091241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4025091241
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.655140847
Short name T255
Test name
Test status
Simulation time 25391040025 ps
CPU time 38.14 seconds
Started Sep 09 11:30:44 AM UTC 24
Finished Sep 09 11:31:24 AM UTC 24
Peak memory 245408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655140847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.655140847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.248717218
Short name T471
Test name
Test status
Simulation time 44624888 ps
CPU time 1.08 seconds
Started Sep 09 11:31:02 AM UTC 24
Finished Sep 09 11:31:05 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248717218 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.248717218
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1806517271
Short name T309
Test name
Test status
Simulation time 161566989 ps
CPU time 4.57 seconds
Started Sep 09 11:30:58 AM UTC 24
Finished Sep 09 11:31:03 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806517271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1806517271
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.340996460
Short name T466
Test name
Test status
Simulation time 53313362 ps
CPU time 1.15 seconds
Started Sep 09 11:30:52 AM UTC 24
Finished Sep 09 11:30:54 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340996460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.340996460
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.3664207833
Short name T373
Test name
Test status
Simulation time 47828370760 ps
CPU time 350.1 seconds
Started Sep 09 11:30:59 AM UTC 24
Finished Sep 09 11:36:54 AM UTC 24
Peak memory 278152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664207833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3664207833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.642460594
Short name T108
Test name
Test status
Simulation time 23272287429 ps
CPU time 235.47 seconds
Started Sep 09 11:31:00 AM UTC 24
Finished Sep 09 11:34:59 AM UTC 24
Peak memory 261740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642460594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.642460594
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.942924262
Short name T474
Test name
Test status
Simulation time 1465018268 ps
CPU time 8.49 seconds
Started Sep 09 11:30:58 AM UTC 24
Finished Sep 09 11:31:08 AM UTC 24
Peak memory 261660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942924262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.942924262
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.914258532
Short name T597
Test name
Test status
Simulation time 19381688893 ps
CPU time 169.25 seconds
Started Sep 09 11:30:58 AM UTC 24
Finished Sep 09 11:33:50 AM UTC 24
Peak memory 261772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914258532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.914258532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.648636453
Short name T253
Test name
Test status
Simulation time 2727918232 ps
CPU time 7.54 seconds
Started Sep 09 11:30:56 AM UTC 24
Finished Sep 09 11:31:04 AM UTC 24
Peak memory 245388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648636453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.648636453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.384860169
Short name T311
Test name
Test status
Simulation time 523202427 ps
CPU time 5.52 seconds
Started Sep 09 11:30:57 AM UTC 24
Finished Sep 09 11:31:03 AM UTC 24
Peak memory 245156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384860169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.384860169
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.986918680
Short name T338
Test name
Test status
Simulation time 83021465 ps
CPU time 5.14 seconds
Started Sep 09 11:30:56 AM UTC 24
Finished Sep 09 11:31:02 AM UTC 24
Peak memory 245160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986918680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.986918680
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.606691632
Short name T290
Test name
Test status
Simulation time 1967521839 ps
CPU time 18.49 seconds
Started Sep 09 11:30:56 AM UTC 24
Finished Sep 09 11:31:15 AM UTC 24
Peak memory 250876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606691632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.606691632
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1892043185
Short name T472
Test name
Test status
Simulation time 176331911 ps
CPU time 5.61 seconds
Started Sep 09 11:30:59 AM UTC 24
Finished Sep 09 11:31:06 AM UTC 24
Peak memory 231256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892043185 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.1892043185
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.2843029662
Short name T397
Test name
Test status
Simulation time 2531957917 ps
CPU time 16.17 seconds
Started Sep 09 11:30:54 AM UTC 24
Finished Sep 09 11:31:12 AM UTC 24
Peak memory 227468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843029662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2843029662
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1158385439
Short name T468
Test name
Test status
Simulation time 389383339 ps
CPU time 1.87 seconds
Started Sep 09 11:30:54 AM UTC 24
Finished Sep 09 11:30:57 AM UTC 24
Peak memory 215472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158385439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1158385439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.2724207046
Short name T469
Test name
Test status
Simulation time 16473795 ps
CPU time 1.31 seconds
Started Sep 09 11:30:55 AM UTC 24
Finished Sep 09 11:30:58 AM UTC 24
Peak memory 215572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724207046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2724207046
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2671688506
Short name T467
Test name
Test status
Simulation time 98328058 ps
CPU time 1.37 seconds
Started Sep 09 11:30:54 AM UTC 24
Finished Sep 09 11:30:57 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671688506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2671688506
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.2674641103
Short name T322
Test name
Test status
Simulation time 9138625261 ps
CPU time 24.88 seconds
Started Sep 09 11:30:58 AM UTC 24
Finished Sep 09 11:31:24 AM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674641103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2674641103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.1491975523
Short name T481
Test name
Test status
Simulation time 48521364 ps
CPU time 1.11 seconds
Started Sep 09 11:31:19 AM UTC 24
Finished Sep 09 11:31:21 AM UTC 24
Peak memory 215692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491975523 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.1491975523
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.89921548
Short name T320
Test name
Test status
Simulation time 3565891621 ps
CPU time 12.83 seconds
Started Sep 09 11:31:10 AM UTC 24
Finished Sep 09 11:31:24 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89921548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.89921548
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.766741510
Short name T473
Test name
Test status
Simulation time 15463444 ps
CPU time 1.2 seconds
Started Sep 09 11:31:05 AM UTC 24
Finished Sep 09 11:31:07 AM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766741510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.766741510
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.2756233242
Short name T487
Test name
Test status
Simulation time 4265034595 ps
CPU time 12.14 seconds
Started Sep 09 11:31:15 AM UTC 24
Finished Sep 09 11:31:28 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756233242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2756233242
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.258652858
Short name T175
Test name
Test status
Simulation time 92584886558 ps
CPU time 404.46 seconds
Started Sep 09 11:31:16 AM UTC 24
Finished Sep 09 11:38:05 AM UTC 24
Peak memory 284296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258652858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.258652858
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2331501874
Short name T169
Test name
Test status
Simulation time 113710345 ps
CPU time 6.72 seconds
Started Sep 09 11:31:11 AM UTC 24
Finished Sep 09 11:31:19 AM UTC 24
Peak memory 247372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331501874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2331501874
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.944905527
Short name T642
Test name
Test status
Simulation time 408378219368 ps
CPU time 199.85 seconds
Started Sep 09 11:31:13 AM UTC 24
Finished Sep 09 11:34:36 AM UTC 24
Peak memory 265800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944905527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.944905527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.894370419
Short name T314
Test name
Test status
Simulation time 556099011 ps
CPU time 7.89 seconds
Started Sep 09 11:31:08 AM UTC 24
Finished Sep 09 11:31:17 AM UTC 24
Peak memory 245144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894370419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.894370419
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.1420830668
Short name T310
Test name
Test status
Simulation time 811167161 ps
CPU time 14.79 seconds
Started Sep 09 11:31:08 AM UTC 24
Finished Sep 09 11:31:24 AM UTC 24
Peak memory 245132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420830668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1420830668
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.3562195756
Short name T261
Test name
Test status
Simulation time 10790707055 ps
CPU time 19.42 seconds
Started Sep 09 11:31:08 AM UTC 24
Finished Sep 09 11:31:29 AM UTC 24
Peak memory 245460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562195756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.3562195756
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.1522872685
Short name T315
Test name
Test status
Simulation time 92675182 ps
CPU time 3.88 seconds
Started Sep 09 11:31:07 AM UTC 24
Finished Sep 09 11:31:12 AM UTC 24
Peak memory 245272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522872685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1522872685
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.2394311965
Short name T479
Test name
Test status
Simulation time 966269376 ps
CPU time 5.54 seconds
Started Sep 09 11:31:13 AM UTC 24
Finished Sep 09 11:31:19 AM UTC 24
Peak memory 231248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394311965 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.2394311965
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.1804892222
Short name T33
Test name
Test status
Simulation time 36822312 ps
CPU time 1.39 seconds
Started Sep 09 11:31:18 AM UTC 24
Finished Sep 09 11:31:20 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804892222 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.1804892222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.1322990263
Short name T476
Test name
Test status
Simulation time 402623201 ps
CPU time 3.45 seconds
Started Sep 09 11:31:06 AM UTC 24
Finished Sep 09 11:31:10 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322990263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1322990263
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.3443423042
Short name T480
Test name
Test status
Simulation time 2105605364 ps
CPU time 13.88 seconds
Started Sep 09 11:31:06 AM UTC 24
Finished Sep 09 11:31:21 AM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443423042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3443423042
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.1475644168
Short name T478
Test name
Test status
Simulation time 250683383 ps
CPU time 7.91 seconds
Started Sep 09 11:31:07 AM UTC 24
Finished Sep 09 11:31:16 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475644168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1475644168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.4018141972
Short name T475
Test name
Test status
Simulation time 11854564 ps
CPU time 0.94 seconds
Started Sep 09 11:31:06 AM UTC 24
Finished Sep 09 11:31:08 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018141972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4018141972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.2040061353
Short name T282
Test name
Test status
Simulation time 2192702753 ps
CPU time 13.29 seconds
Started Sep 09 11:31:09 AM UTC 24
Finished Sep 09 11:31:24 AM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040061353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2040061353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.3540998468
Short name T490
Test name
Test status
Simulation time 11710497 ps
CPU time 1.08 seconds
Started Sep 09 11:31:29 AM UTC 24
Finished Sep 09 11:31:31 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540998468 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3540998468
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2497444637
Short name T489
Test name
Test status
Simulation time 924407473 ps
CPU time 4.93 seconds
Started Sep 09 11:31:25 AM UTC 24
Finished Sep 09 11:31:31 AM UTC 24
Peak memory 234976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497444637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2497444637
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.3854655587
Short name T482
Test name
Test status
Simulation time 45707335 ps
CPU time 1.12 seconds
Started Sep 09 11:31:19 AM UTC 24
Finished Sep 09 11:31:22 AM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854655587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3854655587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1277359933
Short name T678
Test name
Test status
Simulation time 206692897879 ps
CPU time 258.43 seconds
Started Sep 09 11:31:26 AM UTC 24
Finished Sep 09 11:35:48 AM UTC 24
Peak memory 261788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277359933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1277359933
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.168689575
Short name T297
Test name
Test status
Simulation time 18075240786 ps
CPU time 122.37 seconds
Started Sep 09 11:31:28 AM UTC 24
Finished Sep 09 11:33:33 AM UTC 24
Peak memory 263816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168689575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.168689575
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.2272554128
Short name T296
Test name
Test status
Simulation time 93649076 ps
CPU time 5.04 seconds
Started Sep 09 11:31:25 AM UTC 24
Finished Sep 09 11:31:31 AM UTC 24
Peak memory 247324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272554128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2272554128
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.2734596071
Short name T244
Test name
Test status
Simulation time 1072883163 ps
CPU time 22.41 seconds
Started Sep 09 11:31:25 AM UTC 24
Finished Sep 09 11:31:49 AM UTC 24
Peak memory 247248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734596071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.2734596071
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.597255084
Short name T486
Test name
Test status
Simulation time 58193972 ps
CPU time 3.15 seconds
Started Sep 09 11:31:24 AM UTC 24
Finished Sep 09 11:31:28 AM UTC 24
Peak memory 245004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597255084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.597255084
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.1664772002
Short name T285
Test name
Test status
Simulation time 844860032 ps
CPU time 25.01 seconds
Started Sep 09 11:31:25 AM UTC 24
Finished Sep 09 11:31:51 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664772002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1664772002
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2647403607
Short name T212
Test name
Test status
Simulation time 3582545557 ps
CPU time 18.46 seconds
Started Sep 09 11:31:24 AM UTC 24
Finished Sep 09 11:31:43 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647403607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.2647403607
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.2858947221
Short name T278
Test name
Test status
Simulation time 39946487716 ps
CPU time 29.82 seconds
Started Sep 09 11:31:22 AM UTC 24
Finished Sep 09 11:31:54 AM UTC 24
Peak memory 245412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858947221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2858947221
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3071688808
Short name T492
Test name
Test status
Simulation time 3161228359 ps
CPU time 9.62 seconds
Started Sep 09 11:31:25 AM UTC 24
Finished Sep 09 11:31:36 AM UTC 24
Peak memory 233384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071688808 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.3071688808
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.53864818
Short name T511
Test name
Test status
Simulation time 11620442340 ps
CPU time 42.3 seconds
Started Sep 09 11:31:21 AM UTC 24
Finished Sep 09 11:32:05 AM UTC 24
Peak memory 231700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53864818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.53864818
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.136120510
Short name T484
Test name
Test status
Simulation time 324207682 ps
CPU time 3.12 seconds
Started Sep 09 11:31:20 AM UTC 24
Finished Sep 09 11:31:24 AM UTC 24
Peak memory 227332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136120510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.136120510
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1640151057
Short name T485
Test name
Test status
Simulation time 87535796 ps
CPU time 1.79 seconds
Started Sep 09 11:31:22 AM UTC 24
Finished Sep 09 11:31:25 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640151057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1640151057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.4076317354
Short name T483
Test name
Test status
Simulation time 22960125 ps
CPU time 1.22 seconds
Started Sep 09 11:31:21 AM UTC 24
Finished Sep 09 11:31:24 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076317354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4076317354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2602432354
Short name T277
Test name
Test status
Simulation time 3657365278 ps
CPU time 16.74 seconds
Started Sep 09 11:31:25 AM UTC 24
Finished Sep 09 11:31:43 AM UTC 24
Peak memory 247396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602432354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2602432354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.3805155494
Short name T498
Test name
Test status
Simulation time 29200939 ps
CPU time 1.06 seconds
Started Sep 09 11:31:44 AM UTC 24
Finished Sep 09 11:31:46 AM UTC 24
Peak memory 215612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805155494 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.3805155494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.2201846701
Short name T328
Test name
Test status
Simulation time 158831772 ps
CPU time 3.5 seconds
Started Sep 09 11:31:37 AM UTC 24
Finished Sep 09 11:31:42 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201846701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2201846701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.2620620062
Short name T491
Test name
Test status
Simulation time 14933299 ps
CPU time 1.14 seconds
Started Sep 09 11:31:31 AM UTC 24
Finished Sep 09 11:31:33 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620620062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2620620062
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.3694543882
Short name T312
Test name
Test status
Simulation time 20628537760 ps
CPU time 47.17 seconds
Started Sep 09 11:31:42 AM UTC 24
Finished Sep 09 11:32:31 AM UTC 24
Peak memory 251464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694543882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3694543882
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2179781674
Short name T337
Test name
Test status
Simulation time 344562106073 ps
CPU time 285.01 seconds
Started Sep 09 11:31:43 AM UTC 24
Finished Sep 09 11:36:32 AM UTC 24
Peak memory 278164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179781674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2179781674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2397821793
Short name T415
Test name
Test status
Simulation time 3956094664 ps
CPU time 57.97 seconds
Started Sep 09 11:31:43 AM UTC 24
Finished Sep 09 11:32:42 AM UTC 24
Peak memory 261828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397821793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2397821793
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1299474620
Short name T531
Test name
Test status
Simulation time 18009481690 ps
CPU time 46.27 seconds
Started Sep 09 11:31:37 AM UTC 24
Finished Sep 09 11:32:25 AM UTC 24
Peak memory 261724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299474620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1299474620
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.379693821
Short name T522
Test name
Test status
Simulation time 3198086906 ps
CPU time 33.8 seconds
Started Sep 09 11:31:37 AM UTC 24
Finished Sep 09 11:32:12 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379693821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.379693821
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.1855015790
Short name T496
Test name
Test status
Simulation time 58227900 ps
CPU time 2.9 seconds
Started Sep 09 11:31:37 AM UTC 24
Finished Sep 09 11:31:41 AM UTC 24
Peak memory 244956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855015790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1855015790
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.462321713
Short name T340
Test name
Test status
Simulation time 10417383152 ps
CPU time 20.72 seconds
Started Sep 09 11:31:36 AM UTC 24
Finished Sep 09 11:31:58 AM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462321713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.462321713
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.144394926
Short name T292
Test name
Test status
Simulation time 6399395837 ps
CPU time 14.72 seconds
Started Sep 09 11:31:35 AM UTC 24
Finished Sep 09 11:31:51 AM UTC 24
Peak memory 251404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144394926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.144394926
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2886682230
Short name T501
Test name
Test status
Simulation time 2948088026 ps
CPU time 11 seconds
Started Sep 09 11:31:41 AM UTC 24
Finished Sep 09 11:31:53 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886682230 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.2886682230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.4100732501
Short name T407
Test name
Test status
Simulation time 1733268453 ps
CPU time 10.96 seconds
Started Sep 09 11:31:33 AM UTC 24
Finished Sep 09 11:31:45 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100732501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4100732501
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.795878647
Short name T494
Test name
Test status
Simulation time 347285252 ps
CPU time 3.14 seconds
Started Sep 09 11:31:33 AM UTC 24
Finished Sep 09 11:31:37 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795878647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.795878647
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.2148321033
Short name T495
Test name
Test status
Simulation time 470130826 ps
CPU time 4.72 seconds
Started Sep 09 11:31:34 AM UTC 24
Finished Sep 09 11:31:40 AM UTC 24
Peak memory 227624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148321033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2148321033
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.1050031427
Short name T493
Test name
Test status
Simulation time 35800689 ps
CPU time 1.35 seconds
Started Sep 09 11:31:34 AM UTC 24
Finished Sep 09 11:31:36 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050031427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1050031427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.91978046
Short name T319
Test name
Test status
Simulation time 228291131 ps
CPU time 4.14 seconds
Started Sep 09 11:31:37 AM UTC 24
Finished Sep 09 11:31:42 AM UTC 24
Peak memory 234900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91978046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.91978046
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.3314762572
Short name T505
Test name
Test status
Simulation time 14419312 ps
CPU time 1.06 seconds
Started Sep 09 11:31:56 AM UTC 24
Finished Sep 09 11:31:59 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314762572 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3314762572
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.375736132
Short name T329
Test name
Test status
Simulation time 100870199 ps
CPU time 4.9 seconds
Started Sep 09 11:31:51 AM UTC 24
Finished Sep 09 11:31:57 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375736132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.375736132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.2994996152
Short name T497
Test name
Test status
Simulation time 54681636 ps
CPU time 1.03 seconds
Started Sep 09 11:31:44 AM UTC 24
Finished Sep 09 11:31:46 AM UTC 24
Peak memory 215780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994996152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2994996152
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.454167437
Short name T609
Test name
Test status
Simulation time 12565721092 ps
CPU time 125.75 seconds
Started Sep 09 11:31:54 AM UTC 24
Finished Sep 09 11:34:02 AM UTC 24
Peak memory 261720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454167437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.454167437
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2928318330
Short name T243
Test name
Test status
Simulation time 24527689992 ps
CPU time 122.79 seconds
Started Sep 09 11:31:54 AM UTC 24
Finished Sep 09 11:33:59 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928318330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2928318330
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2677300876
Short name T263
Test name
Test status
Simulation time 228604509622 ps
CPU time 538.52 seconds
Started Sep 09 11:31:54 AM UTC 24
Finished Sep 09 11:40:59 AM UTC 24
Peak memory 269988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677300876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.2677300876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.279588712
Short name T534
Test name
Test status
Simulation time 11760367662 ps
CPU time 39.12 seconds
Started Sep 09 11:31:52 AM UTC 24
Finished Sep 09 11:32:33 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279588712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.279588712
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.826615319
Short name T502
Test name
Test status
Simulation time 142540243 ps
CPU time 4.48 seconds
Started Sep 09 11:31:50 AM UTC 24
Finished Sep 09 11:31:55 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826615319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.826615319
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.574488869
Short name T317
Test name
Test status
Simulation time 152576329 ps
CPU time 4.89 seconds
Started Sep 09 11:31:50 AM UTC 24
Finished Sep 09 11:31:56 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574488869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.574488869
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.3079113340
Short name T299
Test name
Test status
Simulation time 1036394594 ps
CPU time 4.17 seconds
Started Sep 09 11:31:48 AM UTC 24
Finished Sep 09 11:31:54 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079113340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.3079113340
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.600392230
Short name T293
Test name
Test status
Simulation time 280883979 ps
CPU time 7.52 seconds
Started Sep 09 11:31:48 AM UTC 24
Finished Sep 09 11:31:57 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600392230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.600392230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.2295627899
Short name T503
Test name
Test status
Simulation time 969867147 ps
CPU time 3.75 seconds
Started Sep 09 11:31:52 AM UTC 24
Finished Sep 09 11:31:57 AM UTC 24
Peak memory 233584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295627899 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.2295627899
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.4187322512
Short name T272
Test name
Test status
Simulation time 30284847962 ps
CPU time 339.27 seconds
Started Sep 09 11:31:55 AM UTC 24
Finished Sep 09 11:37:39 AM UTC 24
Peak memory 267928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187322512 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.4187322512
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.2374439688
Short name T517
Test name
Test status
Simulation time 1784972589 ps
CPU time 21.08 seconds
Started Sep 09 11:31:47 AM UTC 24
Finished Sep 09 11:32:10 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374439688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2374439688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.259469334
Short name T504
Test name
Test status
Simulation time 11025135416 ps
CPU time 11.5 seconds
Started Sep 09 11:31:45 AM UTC 24
Finished Sep 09 11:31:58 AM UTC 24
Peak memory 227576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259469334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.259469334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.817644368
Short name T500
Test name
Test status
Simulation time 49590089 ps
CPU time 1.35 seconds
Started Sep 09 11:31:47 AM UTC 24
Finished Sep 09 11:31:50 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817644368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.817644368
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.3523960252
Short name T499
Test name
Test status
Simulation time 192499483 ps
CPU time 1.13 seconds
Started Sep 09 11:31:47 AM UTC 24
Finished Sep 09 11:31:50 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523960252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3523960252
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.3025622630
Short name T321
Test name
Test status
Simulation time 493650585 ps
CPU time 5.1 seconds
Started Sep 09 11:31:51 AM UTC 24
Finished Sep 09 11:31:57 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025622630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3025622630
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1401317364
Short name T513
Test name
Test status
Simulation time 62377269 ps
CPU time 1 seconds
Started Sep 09 11:32:07 AM UTC 24
Finished Sep 09 11:32:09 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401317364 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.1401317364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.2780058966
Short name T349
Test name
Test status
Simulation time 4986307346 ps
CPU time 9.77 seconds
Started Sep 09 11:32:00 AM UTC 24
Finished Sep 09 11:32:11 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780058966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2780058966
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.2663260609
Short name T506
Test name
Test status
Simulation time 67877936 ps
CPU time 1.22 seconds
Started Sep 09 11:31:56 AM UTC 24
Finished Sep 09 11:31:59 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663260609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2663260609
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1387651186
Short name T289
Test name
Test status
Simulation time 87664956065 ps
CPU time 88.4 seconds
Started Sep 09 11:32:04 AM UTC 24
Finished Sep 09 11:33:34 AM UTC 24
Peak memory 282268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387651186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1387651186
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.3770605168
Short name T401
Test name
Test status
Simulation time 2433217396 ps
CPU time 38.21 seconds
Started Sep 09 11:32:04 AM UTC 24
Finished Sep 09 11:32:43 AM UTC 24
Peak memory 251556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770605168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3770605168
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.3619218134
Short name T343
Test name
Test status
Simulation time 33216066344 ps
CPU time 367.28 seconds
Started Sep 09 11:32:05 AM UTC 24
Finished Sep 09 11:38:17 AM UTC 24
Peak memory 278216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619218134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.3619218134
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.2048916365
Short name T512
Test name
Test status
Simulation time 78664851 ps
CPU time 3.58 seconds
Started Sep 09 11:32:01 AM UTC 24
Finished Sep 09 11:32:06 AM UTC 24
Peak memory 235020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048916365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2048916365
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.3741653684
Short name T357
Test name
Test status
Simulation time 527892861 ps
CPU time 7.94 seconds
Started Sep 09 11:31:59 AM UTC 24
Finished Sep 09 11:32:08 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741653684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3741653684
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.4267039625
Short name T313
Test name
Test status
Simulation time 8608636826 ps
CPU time 39.39 seconds
Started Sep 09 11:31:59 AM UTC 24
Finished Sep 09 11:32:40 AM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267039625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4267039625
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.4224763703
Short name T509
Test name
Test status
Simulation time 176827220 ps
CPU time 2.82 seconds
Started Sep 09 11:31:59 AM UTC 24
Finished Sep 09 11:32:03 AM UTC 24
Peak memory 244956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224763703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.4224763703
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.3794440196
Short name T250
Test name
Test status
Simulation time 17610579895 ps
CPU time 23.53 seconds
Started Sep 09 11:31:59 AM UTC 24
Finished Sep 09 11:32:24 AM UTC 24
Peak memory 245336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794440196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3794440196
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3372607194
Short name T519
Test name
Test status
Simulation time 6284452528 ps
CPU time 7.95 seconds
Started Sep 09 11:32:02 AM UTC 24
Finished Sep 09 11:32:12 AM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372607194 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.3372607194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.2928371722
Short name T190
Test name
Test status
Simulation time 4756528323 ps
CPU time 63.21 seconds
Started Sep 09 11:32:06 AM UTC 24
Finished Sep 09 11:33:11 AM UTC 24
Peak memory 263880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928371722 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.2928371722
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2139587397
Short name T399
Test name
Test status
Simulation time 3761064764 ps
CPU time 15.11 seconds
Started Sep 09 11:31:58 AM UTC 24
Finished Sep 09 11:32:14 AM UTC 24
Peak memory 229596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139587397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2139587397
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3497634193
Short name T516
Test name
Test status
Simulation time 7305719307 ps
CPU time 10.44 seconds
Started Sep 09 11:31:58 AM UTC 24
Finished Sep 09 11:32:09 AM UTC 24
Peak memory 227648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497634193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3497634193
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.720109981
Short name T508
Test name
Test status
Simulation time 142355499 ps
CPU time 1.6 seconds
Started Sep 09 11:31:58 AM UTC 24
Finished Sep 09 11:32:00 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720109981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.720109981
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.2336849391
Short name T507
Test name
Test status
Simulation time 30342265 ps
CPU time 1.21 seconds
Started Sep 09 11:31:58 AM UTC 24
Finished Sep 09 11:32:00 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336849391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2336849391
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3360941867
Short name T268
Test name
Test status
Simulation time 1471587206 ps
CPU time 5.46 seconds
Started Sep 09 11:32:00 AM UTC 24
Finished Sep 09 11:32:07 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360941867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3360941867
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.3471858167
Short name T526
Test name
Test status
Simulation time 15015601 ps
CPU time 1.12 seconds
Started Sep 09 11:32:19 AM UTC 24
Finished Sep 09 11:32:21 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471858167 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.3471858167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.305109466
Short name T348
Test name
Test status
Simulation time 12036815545 ps
CPU time 25.13 seconds
Started Sep 09 11:32:12 AM UTC 24
Finished Sep 09 11:32:38 AM UTC 24
Peak memory 245336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305109466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.305109466
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.992986073
Short name T514
Test name
Test status
Simulation time 17615829 ps
CPU time 1.15 seconds
Started Sep 09 11:32:07 AM UTC 24
Finished Sep 09 11:32:09 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992986073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.992986073
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.3612965902
Short name T569
Test name
Test status
Simulation time 23848685381 ps
CPU time 73.56 seconds
Started Sep 09 11:32:13 AM UTC 24
Finished Sep 09 11:33:28 AM UTC 24
Peak memory 265880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612965902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3612965902
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2973336029
Short name T539
Test name
Test status
Simulation time 1346445334 ps
CPU time 27.34 seconds
Started Sep 09 11:32:15 AM UTC 24
Finished Sep 09 11:32:44 AM UTC 24
Peak memory 261588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973336029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2973336029
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.3394217530
Short name T546
Test name
Test status
Simulation time 87283016763 ps
CPU time 39.91 seconds
Started Sep 09 11:32:15 AM UTC 24
Finished Sep 09 11:32:56 AM UTC 24
Peak memory 229596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394217530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.3394217530
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1006568112
Short name T529
Test name
Test status
Simulation time 444491541 ps
CPU time 9.67 seconds
Started Sep 09 11:32:13 AM UTC 24
Finished Sep 09 11:32:23 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006568112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1006568112
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1639093430
Short name T236
Test name
Test status
Simulation time 1290847612 ps
CPU time 23.45 seconds
Started Sep 09 11:32:13 AM UTC 24
Finished Sep 09 11:32:37 AM UTC 24
Peak memory 251340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639093430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.1639093430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.1028784218
Short name T524
Test name
Test status
Simulation time 219605368 ps
CPU time 5.19 seconds
Started Sep 09 11:32:11 AM UTC 24
Finished Sep 09 11:32:17 AM UTC 24
Peak memory 235084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028784218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1028784218
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.2635407442
Short name T602
Test name
Test status
Simulation time 138592264181 ps
CPU time 103.46 seconds
Started Sep 09 11:32:11 AM UTC 24
Finished Sep 09 11:33:56 AM UTC 24
Peak memory 245456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635407442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2635407442
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3998794853
Short name T523
Test name
Test status
Simulation time 72690397 ps
CPU time 2.91 seconds
Started Sep 09 11:32:10 AM UTC 24
Finished Sep 09 11:32:14 AM UTC 24
Peak memory 234664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998794853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.3998794853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3665771503
Short name T246
Test name
Test status
Simulation time 943870702 ps
CPU time 7.33 seconds
Started Sep 09 11:32:10 AM UTC 24
Finished Sep 09 11:32:19 AM UTC 24
Peak memory 245284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665771503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3665771503
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1564204840
Short name T525
Test name
Test status
Simulation time 189971159 ps
CPU time 6.18 seconds
Started Sep 09 11:32:13 AM UTC 24
Finished Sep 09 11:32:20 AM UTC 24
Peak memory 233364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564204840 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1564204840
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.3124361096
Short name T191
Test name
Test status
Simulation time 18204441128 ps
CPU time 213.13 seconds
Started Sep 09 11:32:17 AM UTC 24
Finished Sep 09 11:35:53 AM UTC 24
Peak memory 278168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124361096 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.3124361096
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.2854914714
Short name T414
Test name
Test status
Simulation time 9344513217 ps
CPU time 34.79 seconds
Started Sep 09 11:32:09 AM UTC 24
Finished Sep 09 11:32:45 AM UTC 24
Peak memory 227624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854914714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2854914714
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1403235475
Short name T527
Test name
Test status
Simulation time 1108228588 ps
CPU time 12.15 seconds
Started Sep 09 11:32:08 AM UTC 24
Finished Sep 09 11:32:21 AM UTC 24
Peak memory 227540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403235475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1403235475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.1125304133
Short name T520
Test name
Test status
Simulation time 160144796 ps
CPU time 1.83 seconds
Started Sep 09 11:32:09 AM UTC 24
Finished Sep 09 11:32:12 AM UTC 24
Peak memory 226728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125304133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1125304133
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.536315958
Short name T518
Test name
Test status
Simulation time 18143659 ps
CPU time 1.05 seconds
Started Sep 09 11:32:09 AM UTC 24
Finished Sep 09 11:32:11 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536315958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.536315958
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.3228367022
Short name T271
Test name
Test status
Simulation time 3708344708 ps
CPU time 17.49 seconds
Started Sep 09 11:32:11 AM UTC 24
Finished Sep 09 11:32:29 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228367022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3228367022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.2774141279
Short name T80
Test name
Test status
Simulation time 36872109 ps
CPU time 0.77 seconds
Started Sep 09 11:29:11 AM UTC 24
Finished Sep 09 11:29:30 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774141279 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2774141279
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.602905031
Short name T35
Test name
Test status
Simulation time 1280849512 ps
CPU time 11.1 seconds
Started Sep 09 11:29:05 AM UTC 24
Finished Sep 09 11:29:24 AM UTC 24
Peak memory 245156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602905031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.602905031
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.3079035777
Short name T77
Test name
Test status
Simulation time 18354061 ps
CPU time 0.72 seconds
Started Sep 09 11:28:58 AM UTC 24
Finished Sep 09 11:29:20 AM UTC 24
Peak memory 215636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079035777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3079035777
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.1612431097
Short name T305
Test name
Test status
Simulation time 95734135343 ps
CPU time 355.85 seconds
Started Sep 09 11:29:09 AM UTC 24
Finished Sep 09 11:35:23 AM UTC 24
Peak memory 267944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612431097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1612431097
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.3386141909
Short name T171
Test name
Test status
Simulation time 55340714012 ps
CPU time 123.1 seconds
Started Sep 09 11:29:10 AM UTC 24
Finished Sep 09 11:31:18 AM UTC 24
Peak memory 267976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386141909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3386141909
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1714063835
Short name T45
Test name
Test status
Simulation time 16168398435 ps
CPU time 17.46 seconds
Started Sep 09 11:29:07 AM UTC 24
Finished Sep 09 11:29:26 AM UTC 24
Peak memory 244836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714063835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.1714063835
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.447907188
Short name T50
Test name
Test status
Simulation time 127492279 ps
CPU time 2.98 seconds
Started Sep 09 11:29:04 AM UTC 24
Finished Sep 09 11:29:11 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447907188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.447907188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.2186236320
Short name T87
Test name
Test status
Simulation time 7031909341 ps
CPU time 11.39 seconds
Started Sep 09 11:29:04 AM UTC 24
Finished Sep 09 11:29:20 AM UTC 24
Peak memory 235108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186236320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2186236320
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2035159816
Short name T58
Test name
Test status
Simulation time 858772455 ps
CPU time 10 seconds
Started Sep 09 11:29:03 AM UTC 24
Finished Sep 09 11:29:34 AM UTC 24
Peak memory 245140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035159816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.2035159816
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.881174882
Short name T207
Test name
Test status
Simulation time 2486306672 ps
CPU time 8.43 seconds
Started Sep 09 11:29:03 AM UTC 24
Finished Sep 09 11:29:32 AM UTC 24
Peak memory 261712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881174882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.881174882
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1095462893
Short name T46
Test name
Test status
Simulation time 118988784 ps
CPU time 3.55 seconds
Started Sep 09 11:29:07 AM UTC 24
Finished Sep 09 11:29:12 AM UTC 24
Peak memory 233036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095462893 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.1095462893
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.1948322233
Short name T16
Test name
Test status
Simulation time 129564433 ps
CPU time 0.87 seconds
Started Sep 09 11:29:11 AM UTC 24
Finished Sep 09 11:29:20 AM UTC 24
Peak memory 258088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948322233 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1948322233
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.624858998
Short name T90
Test name
Test status
Simulation time 42869884634 ps
CPU time 362.41 seconds
Started Sep 09 11:29:10 AM UTC 24
Finished Sep 09 11:35:30 AM UTC 24
Peak memory 268004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624858998 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.624858998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.4220965204
Short name T404
Test name
Test status
Simulation time 2374863019 ps
CPU time 19.23 seconds
Started Sep 09 11:28:59 AM UTC 24
Finished Sep 09 11:30:09 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220965204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4220965204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2658695453
Short name T32
Test name
Test status
Simulation time 461555286 ps
CPU time 1.82 seconds
Started Sep 09 11:28:59 AM UTC 24
Finished Sep 09 11:29:15 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658695453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2658695453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.583447510
Short name T31
Test name
Test status
Simulation time 5646202632 ps
CPU time 4.15 seconds
Started Sep 09 11:29:00 AM UTC 24
Finished Sep 09 11:29:12 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583447510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.583447510
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.797661143
Short name T30
Test name
Test status
Simulation time 29824755 ps
CPU time 0.69 seconds
Started Sep 09 11:29:00 AM UTC 24
Finished Sep 09 11:29:09 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797661143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.797661143
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3369648568
Short name T37
Test name
Test status
Simulation time 147818723 ps
CPU time 2.12 seconds
Started Sep 09 11:29:05 AM UTC 24
Finished Sep 09 11:29:15 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369648568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3369648568
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.803547211
Short name T537
Test name
Test status
Simulation time 33521192 ps
CPU time 1.06 seconds
Started Sep 09 11:32:39 AM UTC 24
Finished Sep 09 11:32:41 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803547211 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.803547211
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.4239452861
Short name T536
Test name
Test status
Simulation time 907511741 ps
CPU time 6.57 seconds
Started Sep 09 11:32:30 AM UTC 24
Finished Sep 09 11:32:38 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239452861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4239452861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.3008443236
Short name T528
Test name
Test status
Simulation time 14108520 ps
CPU time 1.16 seconds
Started Sep 09 11:32:20 AM UTC 24
Finished Sep 09 11:32:22 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008443236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3008443236
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.2387068497
Short name T574
Test name
Test status
Simulation time 96255252501 ps
CPU time 62.22 seconds
Started Sep 09 11:32:34 AM UTC 24
Finished Sep 09 11:33:38 AM UTC 24
Peak memory 251532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387068497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2387068497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3835549853
Short name T769
Test name
Test status
Simulation time 26146103691 ps
CPU time 298.83 seconds
Started Sep 09 11:32:35 AM UTC 24
Finished Sep 09 11:37:38 AM UTC 24
Peak memory 278164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835549853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3835549853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.4245885608
Short name T625
Test name
Test status
Simulation time 28377039544 ps
CPU time 94.4 seconds
Started Sep 09 11:32:39 AM UTC 24
Finished Sep 09 11:34:15 AM UTC 24
Peak memory 261740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245885608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.4245885608
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.3707486401
Short name T394
Test name
Test status
Simulation time 204853372 ps
CPU time 7.52 seconds
Started Sep 09 11:32:32 AM UTC 24
Finished Sep 09 11:32:40 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707486401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3707486401
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.2080109488
Short name T614
Test name
Test status
Simulation time 7130212114 ps
CPU time 93.32 seconds
Started Sep 09 11:32:32 AM UTC 24
Finished Sep 09 11:34:07 AM UTC 24
Peak memory 263824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080109488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.2080109488
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.896726860
Short name T533
Test name
Test status
Simulation time 78131620 ps
CPU time 4.31 seconds
Started Sep 09 11:32:26 AM UTC 24
Finished Sep 09 11:32:31 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896726860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.896726860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.1958204026
Short name T354
Test name
Test status
Simulation time 1816080281 ps
CPU time 13.48 seconds
Started Sep 09 11:32:26 AM UTC 24
Finished Sep 09 11:32:41 AM UTC 24
Peak memory 245140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958204026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1958204026
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2235836278
Short name T260
Test name
Test status
Simulation time 1486556821 ps
CPU time 11.19 seconds
Started Sep 09 11:32:24 AM UTC 24
Finished Sep 09 11:32:36 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235836278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.2235836278
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.3351522955
Short name T350
Test name
Test status
Simulation time 1223141456 ps
CPU time 16.11 seconds
Started Sep 09 11:32:24 AM UTC 24
Finished Sep 09 11:32:41 AM UTC 24
Peak memory 247268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351522955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3351522955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2254435305
Short name T541
Test name
Test status
Simulation time 1670509199 ps
CPU time 11.1 seconds
Started Sep 09 11:32:33 AM UTC 24
Finished Sep 09 11:32:45 AM UTC 24
Peak memory 233508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254435305 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.2254435305
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2402539065
Short name T993
Test name
Test status
Simulation time 60997362430 ps
CPU time 629.51 seconds
Started Sep 09 11:32:39 AM UTC 24
Finished Sep 09 11:43:16 AM UTC 24
Peak memory 296604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402539065 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.2402539065
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.3149968312
Short name T400
Test name
Test status
Simulation time 7329426870 ps
CPU time 29.28 seconds
Started Sep 09 11:32:22 AM UTC 24
Finished Sep 09 11:32:52 AM UTC 24
Peak memory 231784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149968312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3149968312
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.311480770
Short name T532
Test name
Test status
Simulation time 389326493 ps
CPU time 4.03 seconds
Started Sep 09 11:32:21 AM UTC 24
Finished Sep 09 11:32:26 AM UTC 24
Peak memory 227392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311480770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.311480770
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.819489407
Short name T535
Test name
Test status
Simulation time 356029706 ps
CPU time 10.48 seconds
Started Sep 09 11:32:23 AM UTC 24
Finished Sep 09 11:32:34 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819489407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.819489407
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.2891598001
Short name T530
Test name
Test status
Simulation time 48987717 ps
CPU time 1.11 seconds
Started Sep 09 11:32:23 AM UTC 24
Finished Sep 09 11:32:25 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891598001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2891598001
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.3253194148
Short name T544
Test name
Test status
Simulation time 10728507222 ps
CPU time 22.87 seconds
Started Sep 09 11:32:27 AM UTC 24
Finished Sep 09 11:32:51 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253194148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3253194148
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.249294702
Short name T547
Test name
Test status
Simulation time 32286579 ps
CPU time 1.04 seconds
Started Sep 09 11:32:55 AM UTC 24
Finished Sep 09 11:32:57 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249294702 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.249294702
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.4099853338
Short name T239
Test name
Test status
Simulation time 659255890 ps
CPU time 11.17 seconds
Started Sep 09 11:32:46 AM UTC 24
Finished Sep 09 11:32:58 AM UTC 24
Peak memory 235100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099853338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4099853338
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.4237985801
Short name T538
Test name
Test status
Simulation time 14150253 ps
CPU time 1.15 seconds
Started Sep 09 11:32:39 AM UTC 24
Finished Sep 09 11:32:41 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237985801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4237985801
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.4268585622
Short name T371
Test name
Test status
Simulation time 289401810855 ps
CPU time 396.51 seconds
Started Sep 09 11:32:46 AM UTC 24
Finished Sep 09 11:39:28 AM UTC 24
Peak memory 278152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268585622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4268585622
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.2027806139
Short name T176
Test name
Test status
Simulation time 39139221889 ps
CPU time 355.63 seconds
Started Sep 09 11:32:48 AM UTC 24
Finished Sep 09 11:38:49 AM UTC 24
Peak memory 263844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027806139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2027806139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3998256449
Short name T648
Test name
Test status
Simulation time 10294491259 ps
CPU time 107.35 seconds
Started Sep 09 11:32:52 AM UTC 24
Finished Sep 09 11:34:42 AM UTC 24
Peak memory 267976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998256449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.3998256449
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3976702403
Short name T301
Test name
Test status
Simulation time 934158579 ps
CPU time 9.98 seconds
Started Sep 09 11:32:46 AM UTC 24
Finished Sep 09 11:32:57 AM UTC 24
Peak memory 251332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976702403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3976702403
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.250128331
Short name T237
Test name
Test status
Simulation time 20219990044 ps
CPU time 52.08 seconds
Started Sep 09 11:32:46 AM UTC 24
Finished Sep 09 11:33:40 AM UTC 24
Peak memory 265748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250128331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.250128331
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1293352233
Short name T347
Test name
Test status
Simulation time 956345889 ps
CPU time 6.6 seconds
Started Sep 09 11:32:43 AM UTC 24
Finished Sep 09 11:32:51 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293352233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1293352233
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.2861950482
Short name T521
Test name
Test status
Simulation time 2960093251 ps
CPU time 28.81 seconds
Started Sep 09 11:32:46 AM UTC 24
Finished Sep 09 11:33:16 AM UTC 24
Peak memory 241824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861950482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2861950482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3136911319
Short name T335
Test name
Test status
Simulation time 2819396620 ps
CPU time 10.32 seconds
Started Sep 09 11:32:43 AM UTC 24
Finished Sep 09 11:32:55 AM UTC 24
Peak memory 245260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136911319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3136911319
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.3074715974
Short name T353
Test name
Test status
Simulation time 5581169346 ps
CPU time 17.55 seconds
Started Sep 09 11:32:43 AM UTC 24
Finished Sep 09 11:33:02 AM UTC 24
Peak memory 235080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074715974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3074715974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.2351082467
Short name T197
Test name
Test status
Simulation time 11668101828 ps
CPU time 22.31 seconds
Started Sep 09 11:32:46 AM UTC 24
Finished Sep 09 11:33:10 AM UTC 24
Peak memory 231444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351082467 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.2351082467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.3925850593
Short name T545
Test name
Test status
Simulation time 243676159 ps
CPU time 1.65 seconds
Started Sep 09 11:32:52 AM UTC 24
Finished Sep 09 11:32:55 AM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925850593 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.3925850593
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.725466048
Short name T402
Test name
Test status
Simulation time 20175761126 ps
CPU time 40 seconds
Started Sep 09 11:32:41 AM UTC 24
Finished Sep 09 11:33:22 AM UTC 24
Peak memory 227608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725466048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.725466048
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.988253059
Short name T540
Test name
Test status
Simulation time 127253527 ps
CPU time 2.47 seconds
Started Sep 09 11:32:41 AM UTC 24
Finished Sep 09 11:32:44 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988253059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.988253059
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.3128270017
Short name T543
Test name
Test status
Simulation time 316102065 ps
CPU time 3.16 seconds
Started Sep 09 11:32:43 AM UTC 24
Finished Sep 09 11:32:47 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128270017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3128270017
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.2423431334
Short name T542
Test name
Test status
Simulation time 469535908 ps
CPU time 1.46 seconds
Started Sep 09 11:32:43 AM UTC 24
Finished Sep 09 11:32:45 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423431334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2423431334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.2449795969
Short name T549
Test name
Test status
Simulation time 472758488 ps
CPU time 10.29 seconds
Started Sep 09 11:32:46 AM UTC 24
Finished Sep 09 11:32:57 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449795969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2449795969
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.3239079394
Short name T555
Test name
Test status
Simulation time 33703564 ps
CPU time 1.1 seconds
Started Sep 09 11:33:06 AM UTC 24
Finished Sep 09 11:33:08 AM UTC 24
Peak memory 215664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239079394 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.3239079394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.607067112
Short name T352
Test name
Test status
Simulation time 94119280 ps
CPU time 3.53 seconds
Started Sep 09 11:33:00 AM UTC 24
Finished Sep 09 11:33:04 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607067112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.607067112
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.2263471049
Short name T548
Test name
Test status
Simulation time 15949691 ps
CPU time 1.16 seconds
Started Sep 09 11:32:55 AM UTC 24
Finished Sep 09 11:32:57 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263471049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2263471049
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.990911543
Short name T591
Test name
Test status
Simulation time 4038251781 ps
CPU time 43.12 seconds
Started Sep 09 11:33:04 AM UTC 24
Finished Sep 09 11:33:49 AM UTC 24
Peak memory 261696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990911543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.990911543
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2951752032
Short name T385
Test name
Test status
Simulation time 102252582866 ps
CPU time 597.16 seconds
Started Sep 09 11:33:04 AM UTC 24
Finished Sep 09 11:43:08 AM UTC 24
Peak memory 269912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951752032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2951752032
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1538677707
Short name T681
Test name
Test status
Simulation time 18494068402 ps
CPU time 161.13 seconds
Started Sep 09 11:33:06 AM UTC 24
Finished Sep 09 11:35:50 AM UTC 24
Peak memory 261704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538677707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.1538677707
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2609267758
Short name T579
Test name
Test status
Simulation time 4747824710 ps
CPU time 37.57 seconds
Started Sep 09 11:33:02 AM UTC 24
Finished Sep 09 11:33:41 AM UTC 24
Peak memory 261716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609267758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.2609267758
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2358831240
Short name T318
Test name
Test status
Simulation time 1855790875 ps
CPU time 5.03 seconds
Started Sep 09 11:32:59 AM UTC 24
Finished Sep 09 11:33:05 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358831240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2358831240
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.3088322645
Short name T345
Test name
Test status
Simulation time 8110578385 ps
CPU time 37.46 seconds
Started Sep 09 11:33:00 AM UTC 24
Finished Sep 09 11:33:38 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088322645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3088322645
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3759071434
Short name T554
Test name
Test status
Simulation time 552011508 ps
CPU time 4.63 seconds
Started Sep 09 11:32:59 AM UTC 24
Finished Sep 09 11:33:05 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759071434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.3759071434
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.4012650974
Short name T281
Test name
Test status
Simulation time 13259701707 ps
CPU time 22.23 seconds
Started Sep 09 11:32:59 AM UTC 24
Finished Sep 09 11:33:23 AM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012650974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4012650974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.3601245957
Short name T561
Test name
Test status
Simulation time 19055535930 ps
CPU time 15.93 seconds
Started Sep 09 11:33:04 AM UTC 24
Finished Sep 09 11:33:21 AM UTC 24
Peak memory 231384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601245957 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.3601245957
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.404095833
Short name T189
Test name
Test status
Simulation time 113182509 ps
CPU time 1.49 seconds
Started Sep 09 11:33:06 AM UTC 24
Finished Sep 09 11:33:09 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404095833 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.404095833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.4086101528
Short name T559
Test name
Test status
Simulation time 2932253371 ps
CPU time 22.11 seconds
Started Sep 09 11:32:57 AM UTC 24
Finished Sep 09 11:33:20 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086101528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4086101528
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.4098684526
Short name T551
Test name
Test status
Simulation time 121679857 ps
CPU time 1.53 seconds
Started Sep 09 11:32:57 AM UTC 24
Finished Sep 09 11:32:59 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098684526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4098684526
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.243166540
Short name T552
Test name
Test status
Simulation time 641850752 ps
CPU time 2.86 seconds
Started Sep 09 11:32:59 AM UTC 24
Finished Sep 09 11:33:03 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243166540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.243166540
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3755738825
Short name T550
Test name
Test status
Simulation time 66115698 ps
CPU time 1.37 seconds
Started Sep 09 11:32:57 AM UTC 24
Finished Sep 09 11:32:59 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755738825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3755738825
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.1317087670
Short name T553
Test name
Test status
Simulation time 167726036 ps
CPU time 3.15 seconds
Started Sep 09 11:33:00 AM UTC 24
Finished Sep 09 11:33:04 AM UTC 24
Peak memory 234692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317087670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1317087670
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.1602568165
Short name T563
Test name
Test status
Simulation time 31058499 ps
CPU time 1.1 seconds
Started Sep 09 11:33:22 AM UTC 24
Finished Sep 09 11:33:24 AM UTC 24
Peak memory 215352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602568165 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.1602568165
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.1355416423
Short name T351
Test name
Test status
Simulation time 1890057189 ps
CPU time 6.91 seconds
Started Sep 09 11:33:16 AM UTC 24
Finished Sep 09 11:33:24 AM UTC 24
Peak memory 234952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355416423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1355416423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2965762193
Short name T556
Test name
Test status
Simulation time 25018411 ps
CPU time 1.15 seconds
Started Sep 09 11:33:06 AM UTC 24
Finished Sep 09 11:33:09 AM UTC 24
Peak memory 215604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965762193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2965762193
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.2149930408
Short name T781
Test name
Test status
Simulation time 328955264527 ps
CPU time 269.32 seconds
Started Sep 09 11:33:18 AM UTC 24
Finished Sep 09 11:37:52 AM UTC 24
Peak memory 261720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149930408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2149930408
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.3382301792
Short name T975
Test name
Test status
Simulation time 197821638303 ps
CPU time 449.88 seconds
Started Sep 09 11:33:20 AM UTC 24
Finished Sep 09 11:40:56 AM UTC 24
Peak memory 267876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382301792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3382301792
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.4222327775
Short name T91
Test name
Test status
Simulation time 103623184300 ps
CPU time 192.64 seconds
Started Sep 09 11:33:20 AM UTC 24
Finished Sep 09 11:36:36 AM UTC 24
Peak memory 261704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222327775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.4222327775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.3865037913
Short name T567
Test name
Test status
Simulation time 5428669874 ps
CPU time 9.57 seconds
Started Sep 09 11:33:16 AM UTC 24
Finished Sep 09 11:33:26 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865037913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3865037913
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.598122411
Short name T560
Test name
Test status
Simulation time 11932372 ps
CPU time 1.16 seconds
Started Sep 09 11:33:18 AM UTC 24
Finished Sep 09 11:33:20 AM UTC 24
Peak memory 225736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598122411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.598122411
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.723782852
Short name T204
Test name
Test status
Simulation time 115888315 ps
CPU time 3.72 seconds
Started Sep 09 11:33:13 AM UTC 24
Finished Sep 09 11:33:18 AM UTC 24
Peak memory 229472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723782852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.723782852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.3213731879
Short name T562
Test name
Test status
Simulation time 3805556862 ps
CPU time 7.12 seconds
Started Sep 09 11:33:13 AM UTC 24
Finished Sep 09 11:33:22 AM UTC 24
Peak memory 235088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213731879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3213731879
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.4076198718
Short name T355
Test name
Test status
Simulation time 5449099222 ps
CPU time 6.27 seconds
Started Sep 09 11:33:13 AM UTC 24
Finished Sep 09 11:33:21 AM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076198718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.4076198718
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.87350348
Short name T279
Test name
Test status
Simulation time 4241320334 ps
CPU time 13.07 seconds
Started Sep 09 11:33:11 AM UTC 24
Finished Sep 09 11:33:25 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87350348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.87350348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.1542166672
Short name T565
Test name
Test status
Simulation time 282292220 ps
CPU time 6.13 seconds
Started Sep 09 11:33:18 AM UTC 24
Finished Sep 09 11:33:25 AM UTC 24
Peak memory 231228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542166672 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.1542166672
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.3586975981
Short name T192
Test name
Test status
Simulation time 105276111626 ps
CPU time 222.99 seconds
Started Sep 09 11:33:22 AM UTC 24
Finished Sep 09 11:37:08 AM UTC 24
Peak memory 265568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586975981 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.3586975981
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.1388287385
Short name T557
Test name
Test status
Simulation time 492693827 ps
CPU time 6.9 seconds
Started Sep 09 11:33:11 AM UTC 24
Finished Sep 09 11:33:19 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388287385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1388287385
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.1641835098
Short name T198
Test name
Test status
Simulation time 20381262 ps
CPU time 1.07 seconds
Started Sep 09 11:33:09 AM UTC 24
Finished Sep 09 11:33:11 AM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641835098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1641835098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.1881546952
Short name T515
Test name
Test status
Simulation time 121236744 ps
CPU time 1.04 seconds
Started Sep 09 11:33:11 AM UTC 24
Finished Sep 09 11:33:13 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881546952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1881546952
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3408113596
Short name T202
Test name
Test status
Simulation time 13593174 ps
CPU time 1.07 seconds
Started Sep 09 11:33:11 AM UTC 24
Finished Sep 09 11:33:13 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408113596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3408113596
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.2686262974
Short name T316
Test name
Test status
Simulation time 448429566 ps
CPU time 5.17 seconds
Started Sep 09 11:33:14 AM UTC 24
Finished Sep 09 11:33:20 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686262974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2686262974
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.919144653
Short name T573
Test name
Test status
Simulation time 12135959 ps
CPU time 0.98 seconds
Started Sep 09 11:33:34 AM UTC 24
Finished Sep 09 11:33:37 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919144653 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.919144653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3389961813
Short name T571
Test name
Test status
Simulation time 1452911170 ps
CPU time 7.97 seconds
Started Sep 09 11:33:27 AM UTC 24
Finished Sep 09 11:33:36 AM UTC 24
Peak memory 235020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389961813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3389961813
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.268267503
Short name T564
Test name
Test status
Simulation time 77107037 ps
CPU time 1.17 seconds
Started Sep 09 11:33:22 AM UTC 24
Finished Sep 09 11:33:24 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268267503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.268267503
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.3428678161
Short name T666
Test name
Test status
Simulation time 173741427663 ps
CPU time 102.02 seconds
Started Sep 09 11:33:28 AM UTC 24
Finished Sep 09 11:35:13 AM UTC 24
Peak memory 278088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428678161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3428678161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3326177541
Short name T280
Test name
Test status
Simulation time 4361244085 ps
CPU time 43.76 seconds
Started Sep 09 11:33:29 AM UTC 24
Finished Sep 09 11:34:15 AM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326177541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3326177541
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2627027163
Short name T660
Test name
Test status
Simulation time 20209920419 ps
CPU time 95.35 seconds
Started Sep 09 11:33:29 AM UTC 24
Finished Sep 09 11:35:07 AM UTC 24
Peak memory 261772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627027163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.2627027163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2275200439
Short name T686
Test name
Test status
Simulation time 19225498814 ps
CPU time 145.1 seconds
Started Sep 09 11:33:28 AM UTC 24
Finished Sep 09 11:35:55 AM UTC 24
Peak memory 261856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275200439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2275200439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.977275483
Short name T581
Test name
Test status
Simulation time 11035040867 ps
CPU time 13.95 seconds
Started Sep 09 11:33:26 AM UTC 24
Finished Sep 09 11:33:42 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977275483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.977275483
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.482304368
Short name T586
Test name
Test status
Simulation time 2739959003 ps
CPU time 17.52 seconds
Started Sep 09 11:33:26 AM UTC 24
Finished Sep 09 11:33:45 AM UTC 24
Peak memory 245336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482304368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.482304368
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.519204277
Short name T356
Test name
Test status
Simulation time 21500762711 ps
CPU time 11.14 seconds
Started Sep 09 11:33:24 AM UTC 24
Finished Sep 09 11:33:36 AM UTC 24
Peak memory 235096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519204277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.519204277
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.753947783
Short name T580
Test name
Test status
Simulation time 5043629979 ps
CPU time 15.62 seconds
Started Sep 09 11:33:24 AM UTC 24
Finished Sep 09 11:33:41 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753947783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.753947783
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2308696703
Short name T592
Test name
Test status
Simulation time 1893171240 ps
CPU time 20.47 seconds
Started Sep 09 11:33:28 AM UTC 24
Finished Sep 09 11:33:50 AM UTC 24
Peak memory 233380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308696703 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.2308696703
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.1686879872
Short name T265
Test name
Test status
Simulation time 25844517485 ps
CPU time 242.92 seconds
Started Sep 09 11:33:33 AM UTC 24
Finished Sep 09 11:37:40 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686879872 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.1686879872
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.607123644
Short name T572
Test name
Test status
Simulation time 698133032 ps
CPU time 13.81 seconds
Started Sep 09 11:33:22 AM UTC 24
Finished Sep 09 11:33:37 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607123644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.607123644
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.130306245
Short name T570
Test name
Test status
Simulation time 13535698659 ps
CPU time 9.79 seconds
Started Sep 09 11:33:22 AM UTC 24
Finished Sep 09 11:33:33 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130306245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.130306245
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.3218866081
Short name T568
Test name
Test status
Simulation time 557411246 ps
CPU time 2.06 seconds
Started Sep 09 11:33:24 AM UTC 24
Finished Sep 09 11:33:27 AM UTC 24
Peak memory 227436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218866081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3218866081
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.233914102
Short name T566
Test name
Test status
Simulation time 494987659 ps
CPU time 1.04 seconds
Started Sep 09 11:33:24 AM UTC 24
Finished Sep 09 11:33:26 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233914102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.233914102
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.4189002055
Short name T298
Test name
Test status
Simulation time 415499583 ps
CPU time 9.72 seconds
Started Sep 09 11:33:27 AM UTC 24
Finished Sep 09 11:33:37 AM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189002055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4189002055
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.111291822
Short name T587
Test name
Test status
Simulation time 13789812 ps
CPU time 1.08 seconds
Started Sep 09 11:33:44 AM UTC 24
Finished Sep 09 11:33:46 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111291822 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.111291822
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.892627507
Short name T590
Test name
Test status
Simulation time 1084914850 ps
CPU time 6.05 seconds
Started Sep 09 11:33:40 AM UTC 24
Finished Sep 09 11:33:47 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892627507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.892627507
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.2082229188
Short name T575
Test name
Test status
Simulation time 20893719 ps
CPU time 1.16 seconds
Started Sep 09 11:33:35 AM UTC 24
Finished Sep 09 11:33:38 AM UTC 24
Peak memory 215636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082229188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2082229188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.2376853093
Short name T366
Test name
Test status
Simulation time 208720668685 ps
CPU time 293.41 seconds
Started Sep 09 11:33:41 AM UTC 24
Finished Sep 09 11:38:39 AM UTC 24
Peak memory 263756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376853093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2376853093
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1568990304
Short name T639
Test name
Test status
Simulation time 35954800992 ps
CPU time 50.72 seconds
Started Sep 09 11:33:42 AM UTC 24
Finished Sep 09 11:34:34 AM UTC 24
Peak memory 261760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568990304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1568990304
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1237130307
Short name T635
Test name
Test status
Simulation time 1758546787 ps
CPU time 44.02 seconds
Started Sep 09 11:33:43 AM UTC 24
Finished Sep 09 11:34:28 AM UTC 24
Peak memory 265776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237130307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.1237130307
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.3404145427
Short name T604
Test name
Test status
Simulation time 2750545824 ps
CPU time 15.49 seconds
Started Sep 09 11:33:40 AM UTC 24
Finished Sep 09 11:33:57 AM UTC 24
Peak memory 245276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404145427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3404145427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.2731296075
Short name T583
Test name
Test status
Simulation time 32958525 ps
CPU time 2.79 seconds
Started Sep 09 11:33:39 AM UTC 24
Finished Sep 09 11:33:43 AM UTC 24
Peak memory 244956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731296075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2731296075
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.3407111734
Short name T584
Test name
Test status
Simulation time 176782443 ps
CPU time 3.52 seconds
Started Sep 09 11:33:39 AM UTC 24
Finished Sep 09 11:33:44 AM UTC 24
Peak memory 234868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407111734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3407111734
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3963609985
Short name T582
Test name
Test status
Simulation time 28488072 ps
CPU time 2.17 seconds
Started Sep 09 11:33:39 AM UTC 24
Finished Sep 09 11:33:42 AM UTC 24
Peak memory 245072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963609985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3963609985
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.1911230513
Short name T585
Test name
Test status
Simulation time 488938238 ps
CPU time 3.95 seconds
Started Sep 09 11:33:39 AM UTC 24
Finished Sep 09 11:33:44 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911230513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1911230513
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.1707112360
Short name T596
Test name
Test status
Simulation time 4488508270 ps
CPU time 7.73 seconds
Started Sep 09 11:33:41 AM UTC 24
Finished Sep 09 11:33:50 AM UTC 24
Peak memory 233648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707112360 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.1707112360
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1696940871
Short name T588
Test name
Test status
Simulation time 52015565 ps
CPU time 1.73 seconds
Started Sep 09 11:33:44 AM UTC 24
Finished Sep 09 11:33:47 AM UTC 24
Peak memory 225928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696940871 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1696940871
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.2636844840
Short name T613
Test name
Test status
Simulation time 2159432037 ps
CPU time 26.95 seconds
Started Sep 09 11:33:38 AM UTC 24
Finished Sep 09 11:34:06 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636844840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2636844840
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.2479120662
Short name T576
Test name
Test status
Simulation time 22505824 ps
CPU time 1.08 seconds
Started Sep 09 11:33:36 AM UTC 24
Finished Sep 09 11:33:39 AM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479120662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2479120662
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.2754631787
Short name T578
Test name
Test status
Simulation time 64441735 ps
CPU time 1.63 seconds
Started Sep 09 11:33:38 AM UTC 24
Finished Sep 09 11:33:40 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754631787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2754631787
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2948759539
Short name T577
Test name
Test status
Simulation time 77628078 ps
CPU time 1.49 seconds
Started Sep 09 11:33:38 AM UTC 24
Finished Sep 09 11:33:40 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948759539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2948759539
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.3627480313
Short name T594
Test name
Test status
Simulation time 2381899419 ps
CPU time 9.66 seconds
Started Sep 09 11:33:39 AM UTC 24
Finished Sep 09 11:33:50 AM UTC 24
Peak memory 235080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627480313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3627480313
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.1108706170
Short name T605
Test name
Test status
Simulation time 10758810 ps
CPU time 1.06 seconds
Started Sep 09 11:33:57 AM UTC 24
Finished Sep 09 11:33:59 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108706170 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.1108706170
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.983184668
Short name T324
Test name
Test status
Simulation time 5072639281 ps
CPU time 5.83 seconds
Started Sep 09 11:33:51 AM UTC 24
Finished Sep 09 11:33:58 AM UTC 24
Peak memory 245280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983184668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.983184668
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.181413288
Short name T589
Test name
Test status
Simulation time 60837323 ps
CPU time 1.2 seconds
Started Sep 09 11:33:45 AM UTC 24
Finished Sep 09 11:33:47 AM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181413288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.181413288
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.510983705
Short name T616
Test name
Test status
Simulation time 1785820012 ps
CPU time 14.66 seconds
Started Sep 09 11:33:52 AM UTC 24
Finished Sep 09 11:34:08 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510983705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.510983705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2149499049
Short name T793
Test name
Test status
Simulation time 109398833591 ps
CPU time 245.73 seconds
Started Sep 09 11:33:54 AM UTC 24
Finished Sep 09 11:38:04 AM UTC 24
Peak memory 267924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149499049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2149499049
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.4082563140
Short name T661
Test name
Test status
Simulation time 10686672978 ps
CPU time 71.02 seconds
Started Sep 09 11:33:54 AM UTC 24
Finished Sep 09 11:35:07 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082563140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.4082563140
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.794207449
Short name T200
Test name
Test status
Simulation time 200326401 ps
CPU time 8.02 seconds
Started Sep 09 11:33:51 AM UTC 24
Finished Sep 09 11:34:00 AM UTC 24
Peak memory 235020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794207449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.794207449
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.487330947
Short name T603
Test name
Test status
Simulation time 722960466 ps
CPU time 5.56 seconds
Started Sep 09 11:33:50 AM UTC 24
Finished Sep 09 11:33:56 AM UTC 24
Peak memory 241884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487330947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.487330947
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.2956651392
Short name T662
Test name
Test status
Simulation time 29393389188 ps
CPU time 74.95 seconds
Started Sep 09 11:33:51 AM UTC 24
Finished Sep 09 11:35:08 AM UTC 24
Peak memory 245344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956651392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2956651392
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.3538876375
Short name T273
Test name
Test status
Simulation time 337710956 ps
CPU time 3.79 seconds
Started Sep 09 11:33:48 AM UTC 24
Finished Sep 09 11:33:53 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538876375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.3538876375
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1656894989
Short name T599
Test name
Test status
Simulation time 46969664 ps
CPU time 2.78 seconds
Started Sep 09 11:33:48 AM UTC 24
Finished Sep 09 11:33:53 AM UTC 24
Peak memory 229220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656894989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1656894989
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.4116396608
Short name T610
Test name
Test status
Simulation time 1173994762 ps
CPU time 12.16 seconds
Started Sep 09 11:33:51 AM UTC 24
Finished Sep 09 11:34:04 AM UTC 24
Peak memory 231384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116396608 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.4116396608
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.447828681
Short name T598
Test name
Test status
Simulation time 147945206 ps
CPU time 3.5 seconds
Started Sep 09 11:33:46 AM UTC 24
Finished Sep 09 11:33:51 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447828681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.447828681
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1191872485
Short name T600
Test name
Test status
Simulation time 4104662008 ps
CPU time 8.5 seconds
Started Sep 09 11:33:45 AM UTC 24
Finished Sep 09 11:33:55 AM UTC 24
Peak memory 227572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191872485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1191872485
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.2001953165
Short name T595
Test name
Test status
Simulation time 86195519 ps
CPU time 1.95 seconds
Started Sep 09 11:33:47 AM UTC 24
Finished Sep 09 11:33:50 AM UTC 24
Peak memory 226696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001953165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2001953165
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2196312838
Short name T593
Test name
Test status
Simulation time 220419504 ps
CPU time 1.42 seconds
Started Sep 09 11:33:47 AM UTC 24
Finished Sep 09 11:33:50 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196312838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2196312838
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.3276599405
Short name T601
Test name
Test status
Simulation time 120546392 ps
CPU time 3.33 seconds
Started Sep 09 11:33:51 AM UTC 24
Finished Sep 09 11:33:55 AM UTC 24
Peak memory 234412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276599405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3276599405
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3034519139
Short name T618
Test name
Test status
Simulation time 15311648 ps
CPU time 1.12 seconds
Started Sep 09 11:34:08 AM UTC 24
Finished Sep 09 11:34:10 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034519139 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.3034519139
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3622637493
Short name T612
Test name
Test status
Simulation time 184166156 ps
CPU time 3.03 seconds
Started Sep 09 11:34:01 AM UTC 24
Finished Sep 09 11:34:05 AM UTC 24
Peak memory 234328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622637493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3622637493
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.638858383
Short name T606
Test name
Test status
Simulation time 26035513 ps
CPU time 1.11 seconds
Started Sep 09 11:33:58 AM UTC 24
Finished Sep 09 11:34:00 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638858383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.638858383
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.2584608167
Short name T653
Test name
Test status
Simulation time 10480032278 ps
CPU time 39.42 seconds
Started Sep 09 11:34:06 AM UTC 24
Finished Sep 09 11:34:47 AM UTC 24
Peak memory 261788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584608167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2584608167
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.4205068701
Short name T713
Test name
Test status
Simulation time 11436914924 ps
CPU time 131.87 seconds
Started Sep 09 11:34:07 AM UTC 24
Finished Sep 09 11:36:21 AM UTC 24
Peak memory 263808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205068701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4205068701
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3661198759
Short name T615
Test name
Test status
Simulation time 204593594 ps
CPU time 3.8 seconds
Started Sep 09 11:34:03 AM UTC 24
Finished Sep 09 11:34:07 AM UTC 24
Peak memory 234952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661198759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3661198759
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2995732240
Short name T369
Test name
Test status
Simulation time 122055114074 ps
CPU time 285.17 seconds
Started Sep 09 11:34:03 AM UTC 24
Finished Sep 09 11:38:52 AM UTC 24
Peak memory 263760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995732240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.2995732240
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.3580013743
Short name T617
Test name
Test status
Simulation time 3315140215 ps
CPU time 6.79 seconds
Started Sep 09 11:34:01 AM UTC 24
Finished Sep 09 11:34:09 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580013743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3580013743
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.2927036739
Short name T620
Test name
Test status
Simulation time 1193852347 ps
CPU time 9.28 seconds
Started Sep 09 11:34:01 AM UTC 24
Finished Sep 09 11:34:12 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927036739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2927036739
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1954116806
Short name T622
Test name
Test status
Simulation time 1390636127 ps
CPU time 12.13 seconds
Started Sep 09 11:34:00 AM UTC 24
Finished Sep 09 11:34:13 AM UTC 24
Peak memory 234892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954116806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.1954116806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.1116813777
Short name T611
Test name
Test status
Simulation time 109040556 ps
CPU time 3.56 seconds
Started Sep 09 11:34:00 AM UTC 24
Finished Sep 09 11:34:05 AM UTC 24
Peak memory 245164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116813777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1116813777
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2824016284
Short name T628
Test name
Test status
Simulation time 1342104921 ps
CPU time 13.77 seconds
Started Sep 09 11:34:06 AM UTC 24
Finished Sep 09 11:34:21 AM UTC 24
Peak memory 233608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824016284 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.2824016284
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.3824334999
Short name T92
Test name
Test status
Simulation time 333589167770 ps
CPU time 806.81 seconds
Started Sep 09 11:34:08 AM UTC 24
Finished Sep 09 11:47:45 AM UTC 24
Peak memory 296604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824334999 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.3824334999
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.3698660091
Short name T607
Test name
Test status
Simulation time 77471794 ps
CPU time 1.15 seconds
Started Sep 09 11:33:58 AM UTC 24
Finished Sep 09 11:34:00 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698660091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3698660091
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1237353276
Short name T621
Test name
Test status
Simulation time 16920827467 ps
CPU time 13.08 seconds
Started Sep 09 11:33:58 AM UTC 24
Finished Sep 09 11:34:12 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237353276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1237353276
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.138833009
Short name T608
Test name
Test status
Simulation time 78185144 ps
CPU time 1.17 seconds
Started Sep 09 11:33:59 AM UTC 24
Finished Sep 09 11:34:01 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138833009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.138833009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2055401776
Short name T558
Test name
Test status
Simulation time 90249150 ps
CPU time 1.45 seconds
Started Sep 09 11:33:58 AM UTC 24
Finished Sep 09 11:34:00 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055401776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2055401776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.3883740401
Short name T623
Test name
Test status
Simulation time 1931742753 ps
CPU time 11.05 seconds
Started Sep 09 11:34:01 AM UTC 24
Finished Sep 09 11:34:14 AM UTC 24
Peak memory 247184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883740401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3883740401
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.1209670491
Short name T632
Test name
Test status
Simulation time 22662253 ps
CPU time 1.06 seconds
Started Sep 09 11:34:24 AM UTC 24
Finished Sep 09 11:34:26 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209670491 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.1209670491
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.4114310331
Short name T631
Test name
Test status
Simulation time 690312513 ps
CPU time 5.47 seconds
Started Sep 09 11:34:16 AM UTC 24
Finished Sep 09 11:34:23 AM UTC 24
Peak memory 234888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114310331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4114310331
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.341729285
Short name T619
Test name
Test status
Simulation time 47001356 ps
CPU time 1.16 seconds
Started Sep 09 11:34:09 AM UTC 24
Finished Sep 09 11:34:11 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341729285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.341729285
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.914970102
Short name T679
Test name
Test status
Simulation time 34476059098 ps
CPU time 85.8 seconds
Started Sep 09 11:34:21 AM UTC 24
Finished Sep 09 11:35:49 AM UTC 24
Peak memory 261704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914970102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.914970102
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1989829391
Short name T647
Test name
Test status
Simulation time 4416935872 ps
CPU time 15.9 seconds
Started Sep 09 11:34:24 AM UTC 24
Finished Sep 09 11:34:41 AM UTC 24
Peak memory 231752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989829391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.1989829391
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.3957526320
Short name T395
Test name
Test status
Simulation time 2642661070 ps
CPU time 16.41 seconds
Started Sep 09 11:34:16 AM UTC 24
Finished Sep 09 11:34:34 AM UTC 24
Peak memory 235048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957526320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3957526320
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3146100787
Short name T627
Test name
Test status
Simulation time 152612719 ps
CPU time 1.28 seconds
Started Sep 09 11:34:18 AM UTC 24
Finished Sep 09 11:34:20 AM UTC 24
Peak memory 225736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146100787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.3146100787
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.2342704992
Short name T629
Test name
Test status
Simulation time 200088199 ps
CPU time 5.62 seconds
Started Sep 09 11:34:15 AM UTC 24
Finished Sep 09 11:34:21 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342704992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2342704992
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.1541740386
Short name T657
Test name
Test status
Simulation time 34467347525 ps
CPU time 36.38 seconds
Started Sep 09 11:34:16 AM UTC 24
Finished Sep 09 11:34:54 AM UTC 24
Peak memory 235100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541740386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1541740386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.2934715178
Short name T334
Test name
Test status
Simulation time 791912119 ps
CPU time 8.42 seconds
Started Sep 09 11:34:14 AM UTC 24
Finished Sep 09 11:34:23 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934715178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.2934715178
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1103802995
Short name T644
Test name
Test status
Simulation time 14522426014 ps
CPU time 23.87 seconds
Started Sep 09 11:34:13 AM UTC 24
Finished Sep 09 11:34:38 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103802995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1103802995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.2869212841
Short name T634
Test name
Test status
Simulation time 394455577 ps
CPU time 5.54 seconds
Started Sep 09 11:34:21 AM UTC 24
Finished Sep 09 11:34:28 AM UTC 24
Peak memory 233476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869212841 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.2869212841
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.2083673364
Short name T759
Test name
Test status
Simulation time 8505982970 ps
CPU time 172.51 seconds
Started Sep 09 11:34:24 AM UTC 24
Finished Sep 09 11:37:19 AM UTC 24
Peak memory 278172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083673364 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.2083673364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.4292409796
Short name T630
Test name
Test status
Simulation time 7564555861 ps
CPU time 9.77 seconds
Started Sep 09 11:34:11 AM UTC 24
Finished Sep 09 11:34:22 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292409796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4292409796
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3906190646
Short name T633
Test name
Test status
Simulation time 6240972488 ps
CPU time 16.36 seconds
Started Sep 09 11:34:10 AM UTC 24
Finished Sep 09 11:34:28 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906190646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3906190646
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.1943307142
Short name T626
Test name
Test status
Simulation time 52591248 ps
CPU time 1.87 seconds
Started Sep 09 11:34:13 AM UTC 24
Finished Sep 09 11:34:16 AM UTC 24
Peak memory 226160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943307142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1943307142
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.4152964317
Short name T624
Test name
Test status
Simulation time 42100368 ps
CPU time 1.28 seconds
Started Sep 09 11:34:13 AM UTC 24
Finished Sep 09 11:34:15 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152964317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4152964317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.3551643966
Short name T638
Test name
Test status
Simulation time 14995445456 ps
CPU time 16.5 seconds
Started Sep 09 11:34:16 AM UTC 24
Finished Sep 09 11:34:34 AM UTC 24
Peak memory 235080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551643966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3551643966
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.4173428983
Short name T651
Test name
Test status
Simulation time 150059236 ps
CPU time 1.13 seconds
Started Sep 09 11:34:43 AM UTC 24
Finished Sep 09 11:34:46 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173428983 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.4173428983
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3700954692
Short name T646
Test name
Test status
Simulation time 266795290 ps
CPU time 4.28 seconds
Started Sep 09 11:34:35 AM UTC 24
Finished Sep 09 11:34:40 AM UTC 24
Peak memory 234928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700954692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3700954692
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.3899943347
Short name T636
Test name
Test status
Simulation time 24571358 ps
CPU time 1.16 seconds
Started Sep 09 11:34:27 AM UTC 24
Finished Sep 09 11:34:29 AM UTC 24
Peak memory 215636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899943347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3899943347
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.2687821476
Short name T101
Test name
Test status
Simulation time 30198923573 ps
CPU time 62.09 seconds
Started Sep 09 11:34:39 AM UTC 24
Finished Sep 09 11:35:43 AM UTC 24
Peak memory 263756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687821476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2687821476
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.3150390576
Short name T283
Test name
Test status
Simulation time 102293930713 ps
CPU time 251.52 seconds
Started Sep 09 11:34:41 AM UTC 24
Finished Sep 09 11:38:57 AM UTC 24
Peak memory 284208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150390576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.3150390576
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.3343254576
Short name T391
Test name
Test status
Simulation time 3719372910 ps
CPU time 66.82 seconds
Started Sep 09 11:34:36 AM UTC 24
Finished Sep 09 11:35:44 AM UTC 24
Peak memory 251468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343254576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3343254576
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.2490085612
Short name T859
Test name
Test status
Simulation time 33422856301 ps
CPU time 269.07 seconds
Started Sep 09 11:34:36 AM UTC 24
Finished Sep 09 11:39:09 AM UTC 24
Peak memory 261728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490085612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.2490085612
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.1069221922
Short name T649
Test name
Test status
Simulation time 384533728 ps
CPU time 6.68 seconds
Started Sep 09 11:34:35 AM UTC 24
Finished Sep 09 11:34:42 AM UTC 24
Peak memory 244460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069221922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1069221922
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.821586335
Short name T276
Test name
Test status
Simulation time 2578260218 ps
CPU time 24.55 seconds
Started Sep 09 11:34:35 AM UTC 24
Finished Sep 09 11:35:00 AM UTC 24
Peak memory 249504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821586335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.821586335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3401929451
Short name T645
Test name
Test status
Simulation time 459606760 ps
CPU time 4.46 seconds
Started Sep 09 11:34:33 AM UTC 24
Finished Sep 09 11:34:39 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401929451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.3401929451
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.4197380973
Short name T643
Test name
Test status
Simulation time 369047612 ps
CPU time 4.41 seconds
Started Sep 09 11:34:32 AM UTC 24
Finished Sep 09 11:34:38 AM UTC 24
Peak memory 235028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197380973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4197380973
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.1841983229
Short name T650
Test name
Test status
Simulation time 69700424 ps
CPU time 4.87 seconds
Started Sep 09 11:34:39 AM UTC 24
Finished Sep 09 11:34:45 AM UTC 24
Peak memory 233628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841983229 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.1841983229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.2215425658
Short name T746
Test name
Test status
Simulation time 111069908760 ps
CPU time 140.28 seconds
Started Sep 09 11:34:41 AM UTC 24
Finished Sep 09 11:37:04 AM UTC 24
Peak memory 261760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215425658 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.2215425658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.3729082898
Short name T641
Test name
Test status
Simulation time 141227742 ps
CPU time 4.29 seconds
Started Sep 09 11:34:29 AM UTC 24
Finished Sep 09 11:34:34 AM UTC 24
Peak memory 227392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729082898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3729082898
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3906124120
Short name T654
Test name
Test status
Simulation time 20931866971 ps
CPU time 16.84 seconds
Started Sep 09 11:34:29 AM UTC 24
Finished Sep 09 11:34:47 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906124120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3906124120
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.2869050832
Short name T640
Test name
Test status
Simulation time 82780040 ps
CPU time 2.62 seconds
Started Sep 09 11:34:30 AM UTC 24
Finished Sep 09 11:34:34 AM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869050832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2869050832
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.3783262108
Short name T637
Test name
Test status
Simulation time 80813171 ps
CPU time 1.55 seconds
Started Sep 09 11:34:29 AM UTC 24
Finished Sep 09 11:34:32 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783262108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3783262108
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.721246008
Short name T658
Test name
Test status
Simulation time 14347865265 ps
CPU time 19.67 seconds
Started Sep 09 11:34:35 AM UTC 24
Finished Sep 09 11:34:56 AM UTC 24
Peak memory 245344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721246008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.721246008
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3869299985
Short name T36
Test name
Test status
Simulation time 12863999 ps
CPU time 0.62 seconds
Started Sep 09 11:29:22 AM UTC 24
Finished Sep 09 11:29:25 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869299985 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3869299985
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.4050880870
Short name T118
Test name
Test status
Simulation time 2205119561 ps
CPU time 4.43 seconds
Started Sep 09 11:29:19 AM UTC 24
Finished Sep 09 11:29:28 AM UTC 24
Peak memory 234952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050880870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4050880870
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.3104588136
Short name T420
Test name
Test status
Simulation time 120209305 ps
CPU time 0.92 seconds
Started Sep 09 11:29:11 AM UTC 24
Finished Sep 09 11:29:30 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104588136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3104588136
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3774312531
Short name T165
Test name
Test status
Simulation time 9410520288 ps
CPU time 74.31 seconds
Started Sep 09 11:29:21 AM UTC 24
Finished Sep 09 11:30:40 AM UTC 24
Peak memory 261732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774312531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3774312531
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1858501615
Short name T48
Test name
Test status
Simulation time 21033451765 ps
CPU time 47.96 seconds
Started Sep 09 11:29:21 AM UTC 24
Finished Sep 09 11:30:13 AM UTC 24
Peak memory 261780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858501615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.1858501615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.2192181286
Short name T22
Test name
Test status
Simulation time 348253685 ps
CPU time 1.95 seconds
Started Sep 09 11:29:16 AM UTC 24
Finished Sep 09 11:29:20 AM UTC 24
Peak memory 233876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192181286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2192181286
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.527510028
Short name T59
Test name
Test status
Simulation time 3419124109 ps
CPU time 13.68 seconds
Started Sep 09 11:29:15 AM UTC 24
Finished Sep 09 11:29:43 AM UTC 24
Peak memory 235028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527510028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.527510028
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2485689063
Short name T220
Test name
Test status
Simulation time 163346588 ps
CPU time 1.88 seconds
Started Sep 09 11:29:15 AM UTC 24
Finished Sep 09 11:29:25 AM UTC 24
Peak memory 233960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485689063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2485689063
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3096522243
Short name T105
Test name
Test status
Simulation time 451018714 ps
CPU time 4.07 seconds
Started Sep 09 11:29:21 AM UTC 24
Finished Sep 09 11:29:29 AM UTC 24
Peak memory 231264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096522243 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.3096522243
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2902977439
Short name T17
Test name
Test status
Simulation time 35706324 ps
CPU time 0.86 seconds
Started Sep 09 11:29:22 AM UTC 24
Finished Sep 09 11:29:24 AM UTC 24
Peak memory 257916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902977439 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2902977439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.3514732172
Short name T18
Test name
Test status
Simulation time 146511274 ps
CPU time 1.15 seconds
Started Sep 09 11:29:21 AM UTC 24
Finished Sep 09 11:29:26 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514732172 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.3514732172
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.5756320
Short name T41
Test name
Test status
Simulation time 1942444443 ps
CPU time 4.83 seconds
Started Sep 09 11:29:13 AM UTC 24
Finished Sep 09 11:29:29 AM UTC 24
Peak memory 227476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5756320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.5756320
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.430756344
Short name T115
Test name
Test status
Simulation time 199262935 ps
CPU time 1.49 seconds
Started Sep 09 11:29:13 AM UTC 24
Finished Sep 09 11:29:26 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430756344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.430756344
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.150821038
Short name T23
Test name
Test status
Simulation time 138291929 ps
CPU time 2.12 seconds
Started Sep 09 11:29:14 AM UTC 24
Finished Sep 09 11:29:20 AM UTC 24
Peak memory 227500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150821038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.150821038
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3540334467
Short name T103
Test name
Test status
Simulation time 16031328 ps
CPU time 0.68 seconds
Started Sep 09 11:29:13 AM UTC 24
Finished Sep 09 11:29:25 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540334467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3540334467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.898364968
Short name T62
Test name
Test status
Simulation time 18385973393 ps
CPU time 27.39 seconds
Started Sep 09 11:29:19 AM UTC 24
Finished Sep 09 11:29:51 AM UTC 24
Peak memory 261792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898364968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.898364968
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.789265094
Short name T665
Test name
Test status
Simulation time 10639644 ps
CPU time 1.08 seconds
Started Sep 09 11:35:09 AM UTC 24
Finished Sep 09 11:35:11 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789265094 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.789265094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.4001862494
Short name T659
Test name
Test status
Simulation time 670617399 ps
CPU time 7.71 seconds
Started Sep 09 11:34:56 AM UTC 24
Finished Sep 09 11:35:05 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001862494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4001862494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.2366659648
Short name T652
Test name
Test status
Simulation time 20722592 ps
CPU time 1.18 seconds
Started Sep 09 11:34:44 AM UTC 24
Finished Sep 09 11:34:46 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366659648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2366659648
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.112099810
Short name T757
Test name
Test status
Simulation time 7071353753 ps
CPU time 127.29 seconds
Started Sep 09 11:35:06 AM UTC 24
Finished Sep 09 11:37:16 AM UTC 24
Peak memory 261700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112099810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.112099810
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2863837353
Short name T715
Test name
Test status
Simulation time 8019630200 ps
CPU time 72.07 seconds
Started Sep 09 11:35:08 AM UTC 24
Finished Sep 09 11:36:22 AM UTC 24
Peak memory 249492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863837353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2863837353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2063382618
Short name T987
Test name
Test status
Simulation time 84439087689 ps
CPU time 402.58 seconds
Started Sep 09 11:35:08 AM UTC 24
Finished Sep 09 11:41:56 AM UTC 24
Peak memory 267984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063382618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.2063382618
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.929917103
Short name T390
Test name
Test status
Simulation time 7980342345 ps
CPU time 45.44 seconds
Started Sep 09 11:35:01 AM UTC 24
Finished Sep 09 11:35:48 AM UTC 24
Peak memory 261724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929917103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.929917103
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2235798226
Short name T810
Test name
Test status
Simulation time 98612356519 ps
CPU time 199.35 seconds
Started Sep 09 11:35:02 AM UTC 24
Finished Sep 09 11:38:24 AM UTC 24
Peak memory 261712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235798226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.2235798226
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.2958463995
Short name T264
Test name
Test status
Simulation time 5377988552 ps
CPU time 17.57 seconds
Started Sep 09 11:34:51 AM UTC 24
Finished Sep 09 11:35:10 AM UTC 24
Peak memory 245280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958463995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2958463995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.961535157
Short name T668
Test name
Test status
Simulation time 20351753807 ps
CPU time 18.04 seconds
Started Sep 09 11:34:54 AM UTC 24
Finished Sep 09 11:35:13 AM UTC 24
Peak memory 234976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961535157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.961535157
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1752982000
Short name T330
Test name
Test status
Simulation time 4363959258 ps
CPU time 12.07 seconds
Started Sep 09 11:34:50 AM UTC 24
Finished Sep 09 11:35:03 AM UTC 24
Peak memory 251468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752982000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1752982000
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2265896926
Short name T325
Test name
Test status
Simulation time 9887655661 ps
CPU time 31.58 seconds
Started Sep 09 11:34:48 AM UTC 24
Finished Sep 09 11:35:21 AM UTC 24
Peak memory 245328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265896926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2265896926
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1737600214
Short name T664
Test name
Test status
Simulation time 640821185 ps
CPU time 5.42 seconds
Started Sep 09 11:35:04 AM UTC 24
Finished Sep 09 11:35:10 AM UTC 24
Peak memory 231308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737600214 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.1737600214
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.2801305401
Short name T39
Test name
Test status
Simulation time 35416095017 ps
CPU time 119.17 seconds
Started Sep 09 11:35:09 AM UTC 24
Finished Sep 09 11:37:11 AM UTC 24
Peak memory 284304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801305401 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.2801305401
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3215130622
Short name T669
Test name
Test status
Simulation time 2818020322 ps
CPU time 26 seconds
Started Sep 09 11:34:47 AM UTC 24
Finished Sep 09 11:35:14 AM UTC 24
Peak memory 227532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215130622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3215130622
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3932720334
Short name T672
Test name
Test status
Simulation time 8015902509 ps
CPU time 29.22 seconds
Started Sep 09 11:34:46 AM UTC 24
Finished Sep 09 11:35:16 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932720334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3932720334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.4158336222
Short name T656
Test name
Test status
Simulation time 169695048 ps
CPU time 1.46 seconds
Started Sep 09 11:34:48 AM UTC 24
Finished Sep 09 11:34:50 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158336222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4158336222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1067940495
Short name T655
Test name
Test status
Simulation time 65554027 ps
CPU time 1.12 seconds
Started Sep 09 11:34:47 AM UTC 24
Finished Sep 09 11:34:49 AM UTC 24
Peak memory 215840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067940495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1067940495
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.1669006892
Short name T663
Test name
Test status
Simulation time 2830277414 ps
CPU time 11.42 seconds
Started Sep 09 11:34:55 AM UTC 24
Finished Sep 09 11:35:08 AM UTC 24
Peak memory 245328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669006892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1669006892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.2793134109
Short name T96
Test name
Test status
Simulation time 17257739 ps
CPU time 1.11 seconds
Started Sep 09 11:35:32 AM UTC 24
Finished Sep 09 11:35:34 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793134109 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.2793134109
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1804462056
Short name T680
Test name
Test status
Simulation time 7946191668 ps
CPU time 29.78 seconds
Started Sep 09 11:35:18 AM UTC 24
Finished Sep 09 11:35:50 AM UTC 24
Peak memory 235100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804462056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1804462056
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.815094695
Short name T667
Test name
Test status
Simulation time 77708532 ps
CPU time 1.17 seconds
Started Sep 09 11:35:11 AM UTC 24
Finished Sep 09 11:35:13 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815094695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.815094695
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.662932650
Short name T688
Test name
Test status
Simulation time 25748285682 ps
CPU time 29.76 seconds
Started Sep 09 11:35:25 AM UTC 24
Finished Sep 09 11:35:57 AM UTC 24
Peak memory 251468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662932650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.662932650
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3802389907
Short name T753
Test name
Test status
Simulation time 3633029512 ps
CPU time 103.06 seconds
Started Sep 09 11:35:28 AM UTC 24
Finished Sep 09 11:37:13 AM UTC 24
Peak memory 263788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802389907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3802389907
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.4097777633
Short name T306
Test name
Test status
Simulation time 4260797452 ps
CPU time 31.28 seconds
Started Sep 09 11:35:30 AM UTC 24
Finished Sep 09 11:36:02 AM UTC 24
Peak memory 235168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097777633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.4097777633
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.3972905733
Short name T393
Test name
Test status
Simulation time 4099742362 ps
CPU time 43.93 seconds
Started Sep 09 11:35:20 AM UTC 24
Finished Sep 09 11:36:06 AM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972905733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3972905733
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2453251337
Short name T341
Test name
Test status
Simulation time 87343583044 ps
CPU time 161.81 seconds
Started Sep 09 11:35:21 AM UTC 24
Finished Sep 09 11:38:06 AM UTC 24
Peak memory 265808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453251337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.2453251337
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.4263487223
Short name T94
Test name
Test status
Simulation time 719061434 ps
CPU time 14.49 seconds
Started Sep 09 11:35:15 AM UTC 24
Finished Sep 09 11:35:31 AM UTC 24
Peak memory 234940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263487223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4263487223
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.2019667621
Short name T99
Test name
Test status
Simulation time 4486124239 ps
CPU time 21.15 seconds
Started Sep 09 11:35:17 AM UTC 24
Finished Sep 09 11:35:39 AM UTC 24
Peak memory 249372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019667621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2019667621
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.981262975
Short name T675
Test name
Test status
Simulation time 288696937 ps
CPU time 5.83 seconds
Started Sep 09 11:35:15 AM UTC 24
Finished Sep 09 11:35:22 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981262975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.981262975
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2698482824
Short name T676
Test name
Test status
Simulation time 7033074234 ps
CPU time 11.63 seconds
Started Sep 09 11:35:15 AM UTC 24
Finished Sep 09 11:35:28 AM UTC 24
Peak memory 245336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698482824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2698482824
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.4280445472
Short name T98
Test name
Test status
Simulation time 1616190781 ps
CPU time 11.31 seconds
Started Sep 09 11:35:24 AM UTC 24
Finished Sep 09 11:35:37 AM UTC 24
Peak memory 231380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280445472 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.4280445472
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.784181732
Short name T384
Test name
Test status
Simulation time 114515945418 ps
CPU time 496.62 seconds
Started Sep 09 11:35:32 AM UTC 24
Finished Sep 09 11:43:55 AM UTC 24
Peak memory 298660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784181732 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.784181732
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.4236330216
Short name T674
Test name
Test status
Simulation time 569588158 ps
CPU time 5.67 seconds
Started Sep 09 11:35:12 AM UTC 24
Finished Sep 09 11:35:19 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236330216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4236330216
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.500200130
Short name T670
Test name
Test status
Simulation time 387100713 ps
CPU time 1.69 seconds
Started Sep 09 11:35:11 AM UTC 24
Finished Sep 09 11:35:14 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500200130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.500200130
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.602342914
Short name T673
Test name
Test status
Simulation time 22817246 ps
CPU time 1.41 seconds
Started Sep 09 11:35:15 AM UTC 24
Finished Sep 09 11:35:17 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602342914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.602342914
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.3137129487
Short name T671
Test name
Test status
Simulation time 31904555 ps
CPU time 1.29 seconds
Started Sep 09 11:35:14 AM UTC 24
Finished Sep 09 11:35:16 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137129487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3137129487
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.3604359188
Short name T326
Test name
Test status
Simulation time 999741495 ps
CPU time 8.39 seconds
Started Sep 09 11:35:17 AM UTC 24
Finished Sep 09 11:35:27 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604359188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3604359188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.2190255645
Short name T687
Test name
Test status
Simulation time 17596038 ps
CPU time 1.07 seconds
Started Sep 09 11:35:53 AM UTC 24
Finished Sep 09 11:35:55 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190255645 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.2190255645
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.1088792513
Short name T683
Test name
Test status
Simulation time 297653633 ps
CPU time 3.14 seconds
Started Sep 09 11:35:49 AM UTC 24
Finished Sep 09 11:35:53 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088792513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1088792513
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.1697454555
Short name T97
Test name
Test status
Simulation time 16196659 ps
CPU time 1.13 seconds
Started Sep 09 11:35:32 AM UTC 24
Finished Sep 09 11:35:34 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697454555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1697454555
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.158229076
Short name T866
Test name
Test status
Simulation time 104518484050 ps
CPU time 199.11 seconds
Started Sep 09 11:35:50 AM UTC 24
Finished Sep 09 11:39:12 AM UTC 24
Peak memory 261708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158229076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.158229076
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2524886358
Short name T749
Test name
Test status
Simulation time 89168569113 ps
CPU time 77.81 seconds
Started Sep 09 11:35:51 AM UTC 24
Finished Sep 09 11:37:11 AM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524886358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.2524886358
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.3150367478
Short name T704
Test name
Test status
Simulation time 767863101 ps
CPU time 20.02 seconds
Started Sep 09 11:35:49 AM UTC 24
Finished Sep 09 11:36:10 AM UTC 24
Peak memory 247244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150367478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3150367478
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.3563246536
Short name T997
Test name
Test status
Simulation time 324307057560 ps
CPU time 547.95 seconds
Started Sep 09 11:35:49 AM UTC 24
Finished Sep 09 11:45:03 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563246536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.3563246536
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.1219935423
Short name T685
Test name
Test status
Simulation time 942521897 ps
CPU time 9.27 seconds
Started Sep 09 11:35:45 AM UTC 24
Finished Sep 09 11:35:55 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219935423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1219935423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.40820673
Short name T750
Test name
Test status
Simulation time 21946530760 ps
CPU time 84.56 seconds
Started Sep 09 11:35:45 AM UTC 24
Finished Sep 09 11:37:11 AM UTC 24
Peak memory 235232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40820673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.40820673
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.238911763
Short name T381
Test name
Test status
Simulation time 2100092875 ps
CPU time 7.82 seconds
Started Sep 09 11:35:45 AM UTC 24
Finished Sep 09 11:35:53 AM UTC 24
Peak memory 234948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238911763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.238911763
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.1131948631
Short name T684
Test name
Test status
Simulation time 1164089666 ps
CPU time 9.57 seconds
Started Sep 09 11:35:42 AM UTC 24
Finished Sep 09 11:35:53 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131948631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1131948631
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.4130291919
Short name T695
Test name
Test status
Simulation time 5105305408 ps
CPU time 12.09 seconds
Started Sep 09 11:35:50 AM UTC 24
Finished Sep 09 11:36:03 AM UTC 24
Peak memory 229396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130291919 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.4130291919
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.3548432485
Short name T195
Test name
Test status
Simulation time 218387461955 ps
CPU time 507.04 seconds
Started Sep 09 11:35:53 AM UTC 24
Finished Sep 09 11:44:27 AM UTC 24
Peak memory 278284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548432485 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.3548432485
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.874650879
Short name T705
Test name
Test status
Simulation time 11738239536 ps
CPU time 33.4 seconds
Started Sep 09 11:35:36 AM UTC 24
Finished Sep 09 11:36:11 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874650879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.874650879
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3838660169
Short name T102
Test name
Test status
Simulation time 1127371967 ps
CPU time 5.99 seconds
Started Sep 09 11:35:36 AM UTC 24
Finished Sep 09 11:35:43 AM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838660169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3838660169
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.54643694
Short name T677
Test name
Test status
Simulation time 285559107 ps
CPU time 1.88 seconds
Started Sep 09 11:35:40 AM UTC 24
Finished Sep 09 11:35:43 AM UTC 24
Peak memory 226692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54643694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.54643694
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.3571278704
Short name T100
Test name
Test status
Simulation time 74818672 ps
CPU time 1.03 seconds
Started Sep 09 11:35:38 AM UTC 24
Finished Sep 09 11:35:40 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571278704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3571278704
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.1096001417
Short name T682
Test name
Test status
Simulation time 43234825 ps
CPU time 3.21 seconds
Started Sep 09 11:35:46 AM UTC 24
Finished Sep 09 11:35:50 AM UTC 24
Peak memory 239532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096001417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1096001417
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.1666484119
Short name T701
Test name
Test status
Simulation time 32776239 ps
CPU time 1.07 seconds
Started Sep 09 11:36:06 AM UTC 24
Finished Sep 09 11:36:08 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666484119 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.1666484119
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3504991102
Short name T698
Test name
Test status
Simulation time 96874320 ps
CPU time 2.48 seconds
Started Sep 09 11:36:00 AM UTC 24
Finished Sep 09 11:36:04 AM UTC 24
Peak memory 234604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504991102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3504991102
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.932764885
Short name T689
Test name
Test status
Simulation time 47259869 ps
CPU time 1.14 seconds
Started Sep 09 11:35:55 AM UTC 24
Finished Sep 09 11:35:57 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932764885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.932764885
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.78603598
Short name T732
Test name
Test status
Simulation time 7868299647 ps
CPU time 41.55 seconds
Started Sep 09 11:36:05 AM UTC 24
Finished Sep 09 11:36:48 AM UTC 24
Peak memory 267856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78603598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.78603598
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.3227118492
Short name T825
Test name
Test status
Simulation time 55680265527 ps
CPU time 153.2 seconds
Started Sep 09 11:36:05 AM UTC 24
Finished Sep 09 11:38:41 AM UTC 24
Peak memory 249508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227118492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3227118492
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3761327624
Short name T983
Test name
Test status
Simulation time 156029115903 ps
CPU time 324.31 seconds
Started Sep 09 11:36:05 AM UTC 24
Finished Sep 09 11:41:33 AM UTC 24
Peak memory 276080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761327624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.3761327624
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2607593291
Short name T700
Test name
Test status
Simulation time 113829979 ps
CPU time 3.16 seconds
Started Sep 09 11:36:02 AM UTC 24
Finished Sep 09 11:36:07 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607593291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2607593291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.712782190
Short name T716
Test name
Test status
Simulation time 1588560632 ps
CPU time 17.9 seconds
Started Sep 09 11:36:04 AM UTC 24
Finished Sep 09 11:36:23 AM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712782190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.712782190
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.1249662032
Short name T699
Test name
Test status
Simulation time 653781096 ps
CPU time 5.34 seconds
Started Sep 09 11:35:58 AM UTC 24
Finished Sep 09 11:36:05 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249662032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1249662032
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.2565325688
Short name T697
Test name
Test status
Simulation time 111208170 ps
CPU time 3.21 seconds
Started Sep 09 11:35:59 AM UTC 24
Finished Sep 09 11:36:03 AM UTC 24
Peak memory 234132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565325688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2565325688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.2545315070
Short name T694
Test name
Test status
Simulation time 122989421 ps
CPU time 3.13 seconds
Started Sep 09 11:35:58 AM UTC 24
Finished Sep 09 11:36:02 AM UTC 24
Peak memory 245008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545315070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.2545315070
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.2121815665
Short name T696
Test name
Test status
Simulation time 141910995 ps
CPU time 4.4 seconds
Started Sep 09 11:35:58 AM UTC 24
Finished Sep 09 11:36:03 AM UTC 24
Peak memory 234804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121815665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2121815665
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3681880527
Short name T703
Test name
Test status
Simulation time 80978861 ps
CPU time 5.29 seconds
Started Sep 09 11:36:04 AM UTC 24
Finished Sep 09 11:36:10 AM UTC 24
Peak memory 231400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681880527 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.3681880527
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1681028927
Short name T886
Test name
Test status
Simulation time 140049888328 ps
CPU time 198.65 seconds
Started Sep 09 11:36:05 AM UTC 24
Finished Sep 09 11:39:26 AM UTC 24
Peak memory 261744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681028927 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1681028927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.774984321
Short name T712
Test name
Test status
Simulation time 5057306243 ps
CPU time 23.05 seconds
Started Sep 09 11:35:56 AM UTC 24
Finished Sep 09 11:36:20 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774984321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.774984321
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.535716052
Short name T690
Test name
Test status
Simulation time 11517843 ps
CPU time 1.1 seconds
Started Sep 09 11:35:55 AM UTC 24
Finished Sep 09 11:35:57 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535716052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.535716052
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.3757131458
Short name T693
Test name
Test status
Simulation time 104192399 ps
CPU time 1.76 seconds
Started Sep 09 11:35:57 AM UTC 24
Finished Sep 09 11:36:00 AM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757131458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3757131458
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.1890498553
Short name T692
Test name
Test status
Simulation time 106365706 ps
CPU time 1.4 seconds
Started Sep 09 11:35:56 AM UTC 24
Finished Sep 09 11:35:58 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890498553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1890498553
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.1262509009
Short name T706
Test name
Test status
Simulation time 10060345111 ps
CPU time 11.51 seconds
Started Sep 09 11:35:59 AM UTC 24
Finished Sep 09 11:36:12 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262509009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1262509009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.2254971775
Short name T717
Test name
Test status
Simulation time 11550835 ps
CPU time 1.1 seconds
Started Sep 09 11:36:23 AM UTC 24
Finished Sep 09 11:36:25 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254971775 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2254971775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3403474742
Short name T722
Test name
Test status
Simulation time 745710720 ps
CPU time 15.1 seconds
Started Sep 09 11:36:14 AM UTC 24
Finished Sep 09 11:36:30 AM UTC 24
Peak memory 235020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403474742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3403474742
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.681231262
Short name T702
Test name
Test status
Simulation time 14966122 ps
CPU time 1.14 seconds
Started Sep 09 11:36:07 AM UTC 24
Finished Sep 09 11:36:09 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681231262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.681231262
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3493456939
Short name T358
Test name
Test status
Simulation time 2935701869 ps
CPU time 94.49 seconds
Started Sep 09 11:36:20 AM UTC 24
Finished Sep 09 11:37:57 AM UTC 24
Peak memory 263816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493456939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3493456939
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3789331790
Short name T361
Test name
Test status
Simulation time 21346714136 ps
CPU time 249.46 seconds
Started Sep 09 11:36:23 AM UTC 24
Finished Sep 09 11:40:36 AM UTC 24
Peak memory 263824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789331790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.3789331790
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.419701088
Short name T718
Test name
Test status
Simulation time 1121257711 ps
CPU time 7.98 seconds
Started Sep 09 11:36:16 AM UTC 24
Finished Sep 09 11:36:25 AM UTC 24
Peak memory 251344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419701088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.419701088
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.3795060752
Short name T259
Test name
Test status
Simulation time 207435727 ps
CPU time 4.48 seconds
Started Sep 09 11:36:12 AM UTC 24
Finished Sep 09 11:36:17 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795060752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3795060752
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.2830689982
Short name T739
Test name
Test status
Simulation time 19789937906 ps
CPU time 42.14 seconds
Started Sep 09 11:36:13 AM UTC 24
Finished Sep 09 11:36:56 AM UTC 24
Peak memory 249436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830689982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2830689982
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3306461653
Short name T710
Test name
Test status
Simulation time 37609545 ps
CPU time 3.13 seconds
Started Sep 09 11:36:12 AM UTC 24
Finished Sep 09 11:36:16 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306461653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.3306461653
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.208825260
Short name T709
Test name
Test status
Simulation time 76214617 ps
CPU time 2.61 seconds
Started Sep 09 11:36:12 AM UTC 24
Finished Sep 09 11:36:15 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208825260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.208825260
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2436360276
Short name T721
Test name
Test status
Simulation time 678951943 ps
CPU time 10.47 seconds
Started Sep 09 11:36:18 AM UTC 24
Finished Sep 09 11:36:30 AM UTC 24
Peak memory 233380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436360276 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.2436360276
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.2178297662
Short name T372
Test name
Test status
Simulation time 75525093392 ps
CPU time 875.92 seconds
Started Sep 09 11:36:23 AM UTC 24
Finished Sep 09 11:51:09 AM UTC 24
Peak memory 313064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178297662 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.2178297662
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.1491537261
Short name T725
Test name
Test status
Simulation time 3903320272 ps
CPU time 29.92 seconds
Started Sep 09 11:36:09 AM UTC 24
Finished Sep 09 11:36:41 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491537261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1491537261
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.4278425713
Short name T711
Test name
Test status
Simulation time 2636892245 ps
CPU time 10.49 seconds
Started Sep 09 11:36:07 AM UTC 24
Finished Sep 09 11:36:19 AM UTC 24
Peak memory 227544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278425713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4278425713
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.1322370554
Short name T708
Test name
Test status
Simulation time 44144041 ps
CPU time 2.02 seconds
Started Sep 09 11:36:10 AM UTC 24
Finished Sep 09 11:36:14 AM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322370554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1322370554
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.759973344
Short name T707
Test name
Test status
Simulation time 18104855 ps
CPU time 1.13 seconds
Started Sep 09 11:36:10 AM UTC 24
Finished Sep 09 11:36:13 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759973344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.759973344
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.2424086353
Short name T714
Test name
Test status
Simulation time 3928212811 ps
CPU time 6.36 seconds
Started Sep 09 11:36:14 AM UTC 24
Finished Sep 09 11:36:21 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424086353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2424086353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.3898078636
Short name T735
Test name
Test status
Simulation time 19124029 ps
CPU time 1.1 seconds
Started Sep 09 11:36:48 AM UTC 24
Finished Sep 09 11:36:50 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898078636 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.3898078636
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2798952558
Short name T729
Test name
Test status
Simulation time 116190247 ps
CPU time 4.31 seconds
Started Sep 09 11:36:38 AM UTC 24
Finished Sep 09 11:36:43 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798952558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2798952558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.943538555
Short name T719
Test name
Test status
Simulation time 88867551 ps
CPU time 1.14 seconds
Started Sep 09 11:36:24 AM UTC 24
Finished Sep 09 11:36:26 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943538555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.943538555
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.3956710747
Short name T740
Test name
Test status
Simulation time 2391776216 ps
CPU time 13.21 seconds
Started Sep 09 11:36:43 AM UTC 24
Finished Sep 09 11:36:57 AM UTC 24
Peak memory 235080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956710747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3956710747
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2124781049
Short name T758
Test name
Test status
Simulation time 7002014379 ps
CPU time 32.93 seconds
Started Sep 09 11:36:44 AM UTC 24
Finished Sep 09 11:37:18 AM UTC 24
Peak memory 249508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124781049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2124781049
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1634099458
Short name T992
Test name
Test status
Simulation time 179136339707 ps
CPU time 373.54 seconds
Started Sep 09 11:36:45 AM UTC 24
Finished Sep 09 11:43:04 AM UTC 24
Peak memory 265936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634099458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1634099458
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.3732844755
Short name T761
Test name
Test status
Simulation time 6448874274 ps
CPU time 37.94 seconds
Started Sep 09 11:36:42 AM UTC 24
Finished Sep 09 11:37:21 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732844755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3732844755
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2030888916
Short name T332
Test name
Test status
Simulation time 57363584668 ps
CPU time 95.85 seconds
Started Sep 09 11:36:42 AM UTC 24
Finished Sep 09 11:38:20 AM UTC 24
Peak memory 265872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030888916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.2030888916
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3838133531
Short name T724
Test name
Test status
Simulation time 114448429 ps
CPU time 3.58 seconds
Started Sep 09 11:36:32 AM UTC 24
Finished Sep 09 11:36:37 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838133531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3838133531
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.4164474947
Short name T730
Test name
Test status
Simulation time 148818208 ps
CPU time 6.58 seconds
Started Sep 09 11:36:36 AM UTC 24
Finished Sep 09 11:36:44 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164474947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4164474947
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1719579051
Short name T383
Test name
Test status
Simulation time 12348142644 ps
CPU time 27.28 seconds
Started Sep 09 11:36:31 AM UTC 24
Finished Sep 09 11:37:00 AM UTC 24
Peak memory 261780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719579051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.1719579051
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.713783540
Short name T731
Test name
Test status
Simulation time 1813495424 ps
CPU time 13.71 seconds
Started Sep 09 11:36:31 AM UTC 24
Finished Sep 09 11:36:46 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713783540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.713783540
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3499621410
Short name T733
Test name
Test status
Simulation time 300860955 ps
CPU time 5.42 seconds
Started Sep 09 11:36:42 AM UTC 24
Finished Sep 09 11:36:48 AM UTC 24
Peak memory 233380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499621410 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.3499621410
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.4092820727
Short name T734
Test name
Test status
Simulation time 59485368 ps
CPU time 1.54 seconds
Started Sep 09 11:36:47 AM UTC 24
Finished Sep 09 11:36:50 AM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092820727 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.4092820727
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.2812932386
Short name T743
Test name
Test status
Simulation time 16139421948 ps
CPU time 34.19 seconds
Started Sep 09 11:36:26 AM UTC 24
Finished Sep 09 11:37:02 AM UTC 24
Peak memory 229648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812932386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2812932386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.631987136
Short name T726
Test name
Test status
Simulation time 1202833605 ps
CPU time 13.71 seconds
Started Sep 09 11:36:26 AM UTC 24
Finished Sep 09 11:36:41 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631987136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.631987136
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.369886290
Short name T723
Test name
Test status
Simulation time 55598010 ps
CPU time 3.35 seconds
Started Sep 09 11:36:31 AM UTC 24
Finished Sep 09 11:36:36 AM UTC 24
Peak memory 227492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369886290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.369886290
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3865592439
Short name T720
Test name
Test status
Simulation time 428935737 ps
CPU time 1.56 seconds
Started Sep 09 11:36:27 AM UTC 24
Finished Sep 09 11:36:30 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865592439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3865592439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.3827085409
Short name T728
Test name
Test status
Simulation time 234945798 ps
CPU time 2.98 seconds
Started Sep 09 11:36:38 AM UTC 24
Finished Sep 09 11:36:42 AM UTC 24
Peak memory 234176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827085409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3827085409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.4024483652
Short name T752
Test name
Test status
Simulation time 16079363 ps
CPU time 1.05 seconds
Started Sep 09 11:37:09 AM UTC 24
Finished Sep 09 11:37:11 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024483652 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.4024483652
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.3175094394
Short name T751
Test name
Test status
Simulation time 458023683 ps
CPU time 8.4 seconds
Started Sep 09 11:37:01 AM UTC 24
Finished Sep 09 11:37:11 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175094394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3175094394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.4237590650
Short name T736
Test name
Test status
Simulation time 57237718 ps
CPU time 1.14 seconds
Started Sep 09 11:36:49 AM UTC 24
Finished Sep 09 11:36:52 AM UTC 24
Peak memory 215636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237590650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4237590650
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2426728001
Short name T776
Test name
Test status
Simulation time 5722296092 ps
CPU time 38.53 seconds
Started Sep 09 11:37:05 AM UTC 24
Finished Sep 09 11:37:45 AM UTC 24
Peak memory 261768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426728001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2426728001
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2902282409
Short name T782
Test name
Test status
Simulation time 15843202850 ps
CPU time 45.84 seconds
Started Sep 09 11:37:05 AM UTC 24
Finished Sep 09 11:37:52 AM UTC 24
Peak memory 261796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902282409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2902282409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.485384020
Short name T918
Test name
Test status
Simulation time 25948632774 ps
CPU time 166.8 seconds
Started Sep 09 11:37:07 AM UTC 24
Finished Sep 09 11:39:57 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485384020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.485384020
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.2595668387
Short name T747
Test name
Test status
Simulation time 123818988 ps
CPU time 3.72 seconds
Started Sep 09 11:37:01 AM UTC 24
Finished Sep 09 11:37:06 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595668387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2595668387
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1513194625
Short name T994
Test name
Test status
Simulation time 48500685947 ps
CPU time 372.21 seconds
Started Sep 09 11:37:03 AM UTC 24
Finished Sep 09 11:43:20 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513194625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.1513194625
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.426113802
Short name T744
Test name
Test status
Simulation time 56131830 ps
CPU time 3.48 seconds
Started Sep 09 11:36:57 AM UTC 24
Finished Sep 09 11:37:02 AM UTC 24
Peak memory 245144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426113802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.426113802
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.1807250781
Short name T748
Test name
Test status
Simulation time 585750957 ps
CPU time 8.03 seconds
Started Sep 09 11:36:58 AM UTC 24
Finished Sep 09 11:37:08 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807250781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1807250781
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.293899098
Short name T367
Test name
Test status
Simulation time 23005209252 ps
CPU time 40.01 seconds
Started Sep 09 11:36:56 AM UTC 24
Finished Sep 09 11:37:39 AM UTC 24
Peak memory 261780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293899098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.293899098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.3643886586
Short name T742
Test name
Test status
Simulation time 1469845166 ps
CPU time 4.23 seconds
Started Sep 09 11:36:55 AM UTC 24
Finished Sep 09 11:37:00 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643886586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3643886586
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.806310587
Short name T760
Test name
Test status
Simulation time 18191650337 ps
CPU time 16.69 seconds
Started Sep 09 11:37:03 AM UTC 24
Finished Sep 09 11:37:21 AM UTC 24
Peak memory 231392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806310587 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.806310587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.1605086434
Short name T417
Test name
Test status
Simulation time 235051914957 ps
CPU time 701.93 seconds
Started Sep 09 11:37:09 AM UTC 24
Finished Sep 09 11:48:59 AM UTC 24
Peak memory 294808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605086434 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.1605086434
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.2452506437
Short name T762
Test name
Test status
Simulation time 4253473675 ps
CPU time 33.07 seconds
Started Sep 09 11:36:52 AM UTC 24
Finished Sep 09 11:37:26 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452506437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2452506437
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.4125746851
Short name T737
Test name
Test status
Simulation time 241969151 ps
CPU time 2.05 seconds
Started Sep 09 11:36:51 AM UTC 24
Finished Sep 09 11:36:54 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125746851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4125746851
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.1066623230
Short name T741
Test name
Test status
Simulation time 109029722 ps
CPU time 1.93 seconds
Started Sep 09 11:36:55 AM UTC 24
Finished Sep 09 11:36:58 AM UTC 24
Peak memory 226400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066623230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1066623230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.4213786795
Short name T738
Test name
Test status
Simulation time 25207448 ps
CPU time 1.06 seconds
Started Sep 09 11:36:53 AM UTC 24
Finished Sep 09 11:36:55 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213786795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4213786795
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.15212021
Short name T745
Test name
Test status
Simulation time 163881412 ps
CPU time 2.89 seconds
Started Sep 09 11:36:59 AM UTC 24
Finished Sep 09 11:37:04 AM UTC 24
Peak memory 234964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15212021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.15212021
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.3766230336
Short name T768
Test name
Test status
Simulation time 34319549 ps
CPU time 1.09 seconds
Started Sep 09 11:37:35 AM UTC 24
Finished Sep 09 11:37:37 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766230336 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.3766230336
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3133100132
Short name T763
Test name
Test status
Simulation time 441302389 ps
CPU time 7 seconds
Started Sep 09 11:37:19 AM UTC 24
Finished Sep 09 11:37:27 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133100132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3133100132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.31319227
Short name T754
Test name
Test status
Simulation time 95185001 ps
CPU time 1.16 seconds
Started Sep 09 11:37:11 AM UTC 24
Finished Sep 09 11:37:14 AM UTC 24
Peak memory 215564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31319227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.31319227
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.94817583
Short name T837
Test name
Test status
Simulation time 9530971559 ps
CPU time 79.2 seconds
Started Sep 09 11:37:27 AM UTC 24
Finished Sep 09 11:38:49 AM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94817583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.94817583
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.156808020
Short name T909
Test name
Test status
Simulation time 16065688787 ps
CPU time 138.56 seconds
Started Sep 09 11:37:29 AM UTC 24
Finished Sep 09 11:39:50 AM UTC 24
Peak memory 263792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156808020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.156808020
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.1886251518
Short name T788
Test name
Test status
Simulation time 10183745670 ps
CPU time 37.21 seconds
Started Sep 09 11:37:20 AM UTC 24
Finished Sep 09 11:37:59 AM UTC 24
Peak memory 235148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886251518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1886251518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2103058618
Short name T380
Test name
Test status
Simulation time 83335423163 ps
CPU time 147.09 seconds
Started Sep 09 11:37:21 AM UTC 24
Finished Sep 09 11:39:51 AM UTC 24
Peak memory 263884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103058618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.2103058618
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.2574226539
Short name T764
Test name
Test status
Simulation time 1335675613 ps
CPU time 11.33 seconds
Started Sep 09 11:37:16 AM UTC 24
Finished Sep 09 11:37:28 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574226539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2574226539
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.2446373003
Short name T856
Test name
Test status
Simulation time 33647653141 ps
CPU time 104.45 seconds
Started Sep 09 11:37:17 AM UTC 24
Finished Sep 09 11:39:04 AM UTC 24
Peak memory 235104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446373003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2446373003
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1352878251
Short name T368
Test name
Test status
Simulation time 1006039740 ps
CPU time 10.81 seconds
Started Sep 09 11:37:15 AM UTC 24
Finished Sep 09 11:37:27 AM UTC 24
Peak memory 245220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352878251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.1352878251
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1710549198
Short name T767
Test name
Test status
Simulation time 5731664859 ps
CPU time 21.01 seconds
Started Sep 09 11:37:14 AM UTC 24
Finished Sep 09 11:37:36 AM UTC 24
Peak memory 245300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710549198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1710549198
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1013542749
Short name T766
Test name
Test status
Simulation time 1279129092 ps
CPU time 11.32 seconds
Started Sep 09 11:37:22 AM UTC 24
Finished Sep 09 11:37:35 AM UTC 24
Peak memory 233628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013542749 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1013542749
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.499657808
Short name T193
Test name
Test status
Simulation time 15925236391 ps
CPU time 163.75 seconds
Started Sep 09 11:37:29 AM UTC 24
Finished Sep 09 11:40:15 AM UTC 24
Peak memory 267920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499657808 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.499657808
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.1966425816
Short name T772
Test name
Test status
Simulation time 2860902408 ps
CPU time 25.85 seconds
Started Sep 09 11:37:12 AM UTC 24
Finished Sep 09 11:37:40 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966425816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1966425816
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.1277955548
Short name T765
Test name
Test status
Simulation time 27170204496 ps
CPU time 21.45 seconds
Started Sep 09 11:37:11 AM UTC 24
Finished Sep 09 11:37:34 AM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277955548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1277955548
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.3172967025
Short name T756
Test name
Test status
Simulation time 139668848 ps
CPU time 1.98 seconds
Started Sep 09 11:37:13 AM UTC 24
Finished Sep 09 11:37:16 AM UTC 24
Peak memory 226696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172967025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3172967025
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.179440047
Short name T755
Test name
Test status
Simulation time 71787976 ps
CPU time 1.27 seconds
Started Sep 09 11:37:12 AM UTC 24
Finished Sep 09 11:37:15 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179440047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.179440047
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.1220916788
Short name T252
Test name
Test status
Simulation time 6770049865 ps
CPU time 29.7 seconds
Started Sep 09 11:37:17 AM UTC 24
Finished Sep 09 11:37:48 AM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220916788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1220916788
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.2500397523
Short name T784
Test name
Test status
Simulation time 14086657 ps
CPU time 1.07 seconds
Started Sep 09 11:37:51 AM UTC 24
Finished Sep 09 11:37:54 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500397523 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.2500397523
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2306098906
Short name T778
Test name
Test status
Simulation time 820061566 ps
CPU time 5.28 seconds
Started Sep 09 11:37:42 AM UTC 24
Finished Sep 09 11:37:48 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306098906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2306098906
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.3989920959
Short name T770
Test name
Test status
Simulation time 23091072 ps
CPU time 1.18 seconds
Started Sep 09 11:37:36 AM UTC 24
Finished Sep 09 11:37:38 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989920959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3989920959
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.2410081055
Short name T984
Test name
Test status
Simulation time 109431575796 ps
CPU time 226.05 seconds
Started Sep 09 11:37:48 AM UTC 24
Finished Sep 09 11:41:38 AM UTC 24
Peak memory 263768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410081055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2410081055
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1539835230
Short name T40
Test name
Test status
Simulation time 56391370980 ps
CPU time 124.73 seconds
Started Sep 09 11:37:49 AM UTC 24
Finished Sep 09 11:39:56 AM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539835230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1539835230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3961418717
Short name T908
Test name
Test status
Simulation time 38814894723 ps
CPU time 118.01 seconds
Started Sep 09 11:37:49 AM UTC 24
Finished Sep 09 11:39:50 AM UTC 24
Peak memory 267936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961418717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.3961418717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.2142701413
Short name T392
Test name
Test status
Simulation time 589491420 ps
CPU time 17.02 seconds
Started Sep 09 11:37:42 AM UTC 24
Finished Sep 09 11:38:00 AM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142701413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2142701413
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3271384860
Short name T359
Test name
Test status
Simulation time 4000212316 ps
CPU time 66.53 seconds
Started Sep 09 11:37:43 AM UTC 24
Finished Sep 09 11:38:51 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271384860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.3271384860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.227571832
Short name T779
Test name
Test status
Simulation time 632273443 ps
CPU time 7.69 seconds
Started Sep 09 11:37:41 AM UTC 24
Finished Sep 09 11:37:49 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227571832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.227571832
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.3790409634
Short name T780
Test name
Test status
Simulation time 439801848 ps
CPU time 9.15 seconds
Started Sep 09 11:37:41 AM UTC 24
Finished Sep 09 11:37:51 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790409634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3790409634
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3666459365
Short name T790
Test name
Test status
Simulation time 11779981984 ps
CPU time 20.65 seconds
Started Sep 09 11:37:40 AM UTC 24
Finished Sep 09 11:38:02 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666459365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.3666459365
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3601848403
Short name T789
Test name
Test status
Simulation time 7520838877 ps
CPU time 20.19 seconds
Started Sep 09 11:37:40 AM UTC 24
Finished Sep 09 11:38:02 AM UTC 24
Peak memory 249492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601848403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3601848403
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2406181099
Short name T783
Test name
Test status
Simulation time 2046410771 ps
CPU time 5.98 seconds
Started Sep 09 11:37:46 AM UTC 24
Finished Sep 09 11:37:53 AM UTC 24
Peak memory 233620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406181099 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2406181099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1347014757
Short name T416
Test name
Test status
Simulation time 38849154048 ps
CPU time 380.69 seconds
Started Sep 09 11:37:50 AM UTC 24
Finished Sep 09 11:44:16 AM UTC 24
Peak memory 278272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347014757 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.1347014757
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1269547352
Short name T773
Test name
Test status
Simulation time 34129206 ps
CPU time 1.02 seconds
Started Sep 09 11:37:38 AM UTC 24
Finished Sep 09 11:37:40 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269547352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1269547352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3749678664
Short name T771
Test name
Test status
Simulation time 123937944 ps
CPU time 1.08 seconds
Started Sep 09 11:37:37 AM UTC 24
Finished Sep 09 11:37:39 AM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749678664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3749678664
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.1732794230
Short name T775
Test name
Test status
Simulation time 80430930 ps
CPU time 2.23 seconds
Started Sep 09 11:37:39 AM UTC 24
Finished Sep 09 11:37:43 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732794230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1732794230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.851218433
Short name T774
Test name
Test status
Simulation time 35678275 ps
CPU time 1.05 seconds
Started Sep 09 11:37:39 AM UTC 24
Finished Sep 09 11:37:41 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851218433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.851218433
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.1660499423
Short name T777
Test name
Test status
Simulation time 228388304 ps
CPU time 5.48 seconds
Started Sep 09 11:37:41 AM UTC 24
Finished Sep 09 11:37:47 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660499423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1660499423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.13652481
Short name T795
Test name
Test status
Simulation time 44107756 ps
CPU time 1.1 seconds
Started Sep 09 11:38:07 AM UTC 24
Finished Sep 09 11:38:09 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13652481 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.13652481
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.3946396372
Short name T794
Test name
Test status
Simulation time 649129544 ps
CPU time 4.76 seconds
Started Sep 09 11:38:01 AM UTC 24
Finished Sep 09 11:38:07 AM UTC 24
Peak memory 245280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946396372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3946396372
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.427627892
Short name T785
Test name
Test status
Simulation time 30977961 ps
CPU time 1.16 seconds
Started Sep 09 11:37:53 AM UTC 24
Finished Sep 09 11:37:55 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427627892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.427627892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.2640608161
Short name T824
Test name
Test status
Simulation time 4105002210 ps
CPU time 32.92 seconds
Started Sep 09 11:38:05 AM UTC 24
Finished Sep 09 11:38:39 AM UTC 24
Peak memory 235012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640608161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2640608161
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3415757524
Short name T912
Test name
Test status
Simulation time 196390646315 ps
CPU time 105.33 seconds
Started Sep 09 11:38:05 AM UTC 24
Finished Sep 09 11:39:52 AM UTC 24
Peak memory 263800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415757524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3415757524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1575124521
Short name T386
Test name
Test status
Simulation time 4215097968 ps
CPU time 120.92 seconds
Started Sep 09 11:38:05 AM UTC 24
Finished Sep 09 11:40:08 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575124521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.1575124521
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.734804876
Short name T809
Test name
Test status
Simulation time 1061005259 ps
CPU time 19.59 seconds
Started Sep 09 11:38:02 AM UTC 24
Finished Sep 09 11:38:23 AM UTC 24
Peak memory 245284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734804876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.734804876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.142443761
Short name T826
Test name
Test status
Simulation time 2880972019 ps
CPU time 36.32 seconds
Started Sep 09 11:38:04 AM UTC 24
Finished Sep 09 11:38:41 AM UTC 24
Peak memory 261712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142443761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.142443761
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.898455248
Short name T791
Test name
Test status
Simulation time 461347238 ps
CPU time 3.99 seconds
Started Sep 09 11:37:58 AM UTC 24
Finished Sep 09 11:38:03 AM UTC 24
Peak memory 234888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898455248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.898455248
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.2960540334
Short name T798
Test name
Test status
Simulation time 2997601765 ps
CPU time 13.38 seconds
Started Sep 09 11:37:59 AM UTC 24
Finished Sep 09 11:38:14 AM UTC 24
Peak memory 235168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960540334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2960540334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.1267210194
Short name T336
Test name
Test status
Simulation time 5739676667 ps
CPU time 4.48 seconds
Started Sep 09 11:37:58 AM UTC 24
Finished Sep 09 11:38:04 AM UTC 24
Peak memory 245268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267210194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.1267210194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.2437020094
Short name T797
Test name
Test status
Simulation time 2863259645 ps
CPU time 14.18 seconds
Started Sep 09 11:37:58 AM UTC 24
Finished Sep 09 11:38:13 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437020094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2437020094
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.492113613
Short name T801
Test name
Test status
Simulation time 1879830416 ps
CPU time 11.63 seconds
Started Sep 09 11:38:04 AM UTC 24
Finished Sep 09 11:38:16 AM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492113613 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.492113613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.848862265
Short name T802
Test name
Test status
Simulation time 11146886254 ps
CPU time 22.39 seconds
Started Sep 09 11:37:54 AM UTC 24
Finished Sep 09 11:38:17 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848862265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.848862265
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.554677996
Short name T792
Test name
Test status
Simulation time 741901197 ps
CPU time 8.64 seconds
Started Sep 09 11:37:54 AM UTC 24
Finished Sep 09 11:38:03 AM UTC 24
Peak memory 227476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554677996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.554677996
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.618793831
Short name T787
Test name
Test status
Simulation time 91494002 ps
CPU time 1.62 seconds
Started Sep 09 11:37:56 AM UTC 24
Finished Sep 09 11:37:58 AM UTC 24
Peak memory 215888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618793831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.618793831
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3739427302
Short name T786
Test name
Test status
Simulation time 47428570 ps
CPU time 1.24 seconds
Started Sep 09 11:37:55 AM UTC 24
Finished Sep 09 11:37:57 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739427302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3739427302
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.2681927106
Short name T804
Test name
Test status
Simulation time 6123128262 ps
CPU time 18.19 seconds
Started Sep 09 11:38:00 AM UTC 24
Finished Sep 09 11:38:20 AM UTC 24
Peak memory 247516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681927106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2681927106
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2367807556
Short name T423
Test name
Test status
Simulation time 77589891 ps
CPU time 1.02 seconds
Started Sep 09 11:29:30 AM UTC 24
Finished Sep 09 11:29:45 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367807556 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2367807556
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4132559923
Short name T304
Test name
Test status
Simulation time 1165286122 ps
CPU time 5.34 seconds
Started Sep 09 11:29:26 AM UTC 24
Finished Sep 09 11:29:34 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132559923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4132559923
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.832169300
Short name T25
Test name
Test status
Simulation time 108851817 ps
CPU time 0.67 seconds
Started Sep 09 11:29:22 AM UTC 24
Finished Sep 09 11:29:24 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832169300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.832169300
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.222577657
Short name T104
Test name
Test status
Simulation time 9077076031 ps
CPU time 31.96 seconds
Started Sep 09 11:29:30 AM UTC 24
Finished Sep 09 11:30:16 AM UTC 24
Peak memory 245404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222577657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.222577657
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.354302098
Short name T180
Test name
Test status
Simulation time 127634132 ps
CPU time 3.43 seconds
Started Sep 09 11:29:26 AM UTC 24
Finished Sep 09 11:29:32 AM UTC 24
Peak memory 245156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354302098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.354302098
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2383463218
Short name T125
Test name
Test status
Simulation time 33922614179 ps
CPU time 84.1 seconds
Started Sep 09 11:29:26 AM UTC 24
Finished Sep 09 11:30:53 AM UTC 24
Peak memory 265808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383463218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.2383463218
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2787726822
Short name T70
Test name
Test status
Simulation time 1152075981 ps
CPU time 5.81 seconds
Started Sep 09 11:29:25 AM UTC 24
Finished Sep 09 11:29:55 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787726822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2787726822
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.310308067
Short name T291
Test name
Test status
Simulation time 317272206 ps
CPU time 8.81 seconds
Started Sep 09 11:29:25 AM UTC 24
Finished Sep 09 11:29:52 AM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310308067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.310308067
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.474331496
Short name T56
Test name
Test status
Simulation time 3689996345 ps
CPU time 11.98 seconds
Started Sep 09 11:29:25 AM UTC 24
Finished Sep 09 11:30:01 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474331496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.474331496
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.183353585
Short name T221
Test name
Test status
Simulation time 29688969926 ps
CPU time 27.53 seconds
Started Sep 09 11:29:25 AM UTC 24
Finished Sep 09 11:30:01 AM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183353585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.183353585
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3152988255
Short name T181
Test name
Test status
Simulation time 293310380 ps
CPU time 4.07 seconds
Started Sep 09 11:29:27 AM UTC 24
Finished Sep 09 11:29:33 AM UTC 24
Peak memory 231328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152988255 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.3152988255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.566297497
Short name T21
Test name
Test status
Simulation time 110350723 ps
CPU time 1.68 seconds
Started Sep 09 11:29:30 AM UTC 24
Finished Sep 09 11:29:45 AM UTC 24
Peak memory 258032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566297497 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.566297497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2595765334
Short name T19
Test name
Test status
Simulation time 172557701 ps
CPU time 0.91 seconds
Started Sep 09 11:29:30 AM UTC 24
Finished Sep 09 11:29:45 AM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595765334 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.2595765334
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.350165742
Short name T6
Test name
Test status
Simulation time 912965140 ps
CPU time 11.39 seconds
Started Sep 09 11:29:24 AM UTC 24
Finished Sep 09 11:29:37 AM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350165742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.350165742
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2497387945
Short name T89
Test name
Test status
Simulation time 2920018694 ps
CPU time 10.52 seconds
Started Sep 09 11:29:24 AM UTC 24
Finished Sep 09 11:29:36 AM UTC 24
Peak memory 227620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497387945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2497387945
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.1580072066
Short name T42
Test name
Test status
Simulation time 436832396 ps
CPU time 1.46 seconds
Started Sep 09 11:29:25 AM UTC 24
Finished Sep 09 11:29:41 AM UTC 24
Peak memory 216476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580072066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1580072066
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.467417331
Short name T116
Test name
Test status
Simulation time 128292716 ps
CPU time 0.87 seconds
Started Sep 09 11:29:24 AM UTC 24
Finished Sep 09 11:29:26 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467417331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.467417331
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.1646927845
Short name T812
Test name
Test status
Simulation time 45748121 ps
CPU time 1.08 seconds
Started Sep 09 11:38:25 AM UTC 24
Finished Sep 09 11:38:27 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646927845 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.1646927845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2432233014
Short name T805
Test name
Test status
Simulation time 461891234 ps
CPU time 3.06 seconds
Started Sep 09 11:38:18 AM UTC 24
Finished Sep 09 11:38:22 AM UTC 24
Peak memory 234944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432233014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2432233014
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.2392847009
Short name T796
Test name
Test status
Simulation time 52777139 ps
CPU time 1.08 seconds
Started Sep 09 11:38:08 AM UTC 24
Finished Sep 09 11:38:10 AM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392847009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2392847009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.1558419357
Short name T869
Test name
Test status
Simulation time 5073861970 ps
CPU time 49.51 seconds
Started Sep 09 11:38:22 AM UTC 24
Finished Sep 09 11:39:13 AM UTC 24
Peak memory 251464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558419357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1558419357
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.603111045
Short name T365
Test name
Test status
Simulation time 204000673768 ps
CPU time 1067.82 seconds
Started Sep 09 11:38:23 AM UTC 24
Finished Sep 09 11:56:24 AM UTC 24
Peak memory 286380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603111045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.603111045
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.723687992
Short name T1000
Test name
Test status
Simulation time 318673128129 ps
CPU time 487.7 seconds
Started Sep 09 11:38:24 AM UTC 24
Finished Sep 09 11:46:37 AM UTC 24
Peak memory 267912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723687992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.723687992
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.4084710010
Short name T817
Test name
Test status
Simulation time 2705325620 ps
CPU time 12.05 seconds
Started Sep 09 11:38:19 AM UTC 24
Finished Sep 09 11:38:32 AM UTC 24
Peak memory 251468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084710010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4084710010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.4061367153
Short name T816
Test name
Test status
Simulation time 1202434450 ps
CPU time 8.75 seconds
Started Sep 09 11:38:20 AM UTC 24
Finished Sep 09 11:38:30 AM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061367153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.4061367153
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1494841807
Short name T819
Test name
Test status
Simulation time 2715477601 ps
CPU time 14.52 seconds
Started Sep 09 11:38:17 AM UTC 24
Finished Sep 09 11:38:32 AM UTC 24
Peak memory 235084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494841807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1494841807
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.1542574494
Short name T806
Test name
Test status
Simulation time 108346541 ps
CPU time 4.47 seconds
Started Sep 09 11:38:17 AM UTC 24
Finished Sep 09 11:38:22 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542574494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1542574494
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1393512068
Short name T803
Test name
Test status
Simulation time 284985208 ps
CPU time 2.07 seconds
Started Sep 09 11:38:15 AM UTC 24
Finished Sep 09 11:38:18 AM UTC 24
Peak memory 234604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393512068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.1393512068
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4013092394
Short name T821
Test name
Test status
Simulation time 40090932654 ps
CPU time 18.11 seconds
Started Sep 09 11:38:15 AM UTC 24
Finished Sep 09 11:38:34 AM UTC 24
Peak memory 245328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013092394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4013092394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.1147665046
Short name T811
Test name
Test status
Simulation time 581798599 ps
CPU time 3.6 seconds
Started Sep 09 11:38:20 AM UTC 24
Finished Sep 09 11:38:25 AM UTC 24
Peak memory 231316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147665046 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.1147665046
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3250583967
Short name T999
Test name
Test status
Simulation time 48404587418 ps
CPU time 476.22 seconds
Started Sep 09 11:38:24 AM UTC 24
Finished Sep 09 11:46:26 AM UTC 24
Peak memory 284300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250583967 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.3250583967
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.1189198329
Short name T800
Test name
Test status
Simulation time 1693532487 ps
CPU time 4.61 seconds
Started Sep 09 11:38:10 AM UTC 24
Finished Sep 09 11:38:16 AM UTC 24
Peak memory 227544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189198329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1189198329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1074279121
Short name T807
Test name
Test status
Simulation time 34279420550 ps
CPU time 11.5 seconds
Started Sep 09 11:38:10 AM UTC 24
Finished Sep 09 11:38:23 AM UTC 24
Peak memory 227728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074279121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1074279121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3728700524
Short name T808
Test name
Test status
Simulation time 385663674 ps
CPU time 7.53 seconds
Started Sep 09 11:38:15 AM UTC 24
Finished Sep 09 11:38:23 AM UTC 24
Peak memory 227416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728700524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3728700524
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2329685876
Short name T799
Test name
Test status
Simulation time 51697146 ps
CPU time 1.4 seconds
Started Sep 09 11:38:11 AM UTC 24
Finished Sep 09 11:38:14 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329685876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2329685876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.1939065309
Short name T814
Test name
Test status
Simulation time 497148827 ps
CPU time 10.05 seconds
Started Sep 09 11:38:18 AM UTC 24
Finished Sep 09 11:38:29 AM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939065309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1939065309
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2423353914
Short name T832
Test name
Test status
Simulation time 26076976 ps
CPU time 1.1 seconds
Started Sep 09 11:38:42 AM UTC 24
Finished Sep 09 11:38:45 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423353914 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.2423353914
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.4051129472
Short name T831
Test name
Test status
Simulation time 936046318 ps
CPU time 9.97 seconds
Started Sep 09 11:38:34 AM UTC 24
Finished Sep 09 11:38:45 AM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051129472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4051129472
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1923740205
Short name T813
Test name
Test status
Simulation time 54665368 ps
CPU time 1.11 seconds
Started Sep 09 11:38:26 AM UTC 24
Finished Sep 09 11:38:28 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923740205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1923740205
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.1367126692
Short name T863
Test name
Test status
Simulation time 25015403054 ps
CPU time 32.39 seconds
Started Sep 09 11:38:38 AM UTC 24
Finished Sep 09 11:39:12 AM UTC 24
Peak memory 249420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367126692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1367126692
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1687873379
Short name T896
Test name
Test status
Simulation time 4968472154 ps
CPU time 59.93 seconds
Started Sep 09 11:38:40 AM UTC 24
Finished Sep 09 11:39:42 AM UTC 24
Peak memory 245396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687873379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1687873379
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3914986585
Short name T973
Test name
Test status
Simulation time 14854257567 ps
CPU time 123.87 seconds
Started Sep 09 11:38:40 AM UTC 24
Finished Sep 09 11:40:46 AM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914986585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.3914986585
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.3429927487
Short name T828
Test name
Test status
Simulation time 1050694843 ps
CPU time 5.7 seconds
Started Sep 09 11:38:35 AM UTC 24
Finished Sep 09 11:38:41 AM UTC 24
Peak memory 235012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429927487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3429927487
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2267709012
Short name T989
Test name
Test status
Simulation time 136664206793 ps
CPU time 240.88 seconds
Started Sep 09 11:38:35 AM UTC 24
Finished Sep 09 11:42:39 AM UTC 24
Peak memory 267832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267709012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2267709012
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.4183999141
Short name T823
Test name
Test status
Simulation time 590957000 ps
CPU time 4.69 seconds
Started Sep 09 11:38:31 AM UTC 24
Finished Sep 09 11:38:37 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183999141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4183999141
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.1619244903
Short name T858
Test name
Test status
Simulation time 3295601229 ps
CPU time 33.35 seconds
Started Sep 09 11:38:34 AM UTC 24
Finished Sep 09 11:39:08 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619244903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1619244903
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1863112112
Short name T820
Test name
Test status
Simulation time 88174561 ps
CPU time 2.48 seconds
Started Sep 09 11:38:30 AM UTC 24
Finished Sep 09 11:38:34 AM UTC 24
Peak memory 244948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863112112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.1863112112
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2690657145
Short name T822
Test name
Test status
Simulation time 425040179 ps
CPU time 3.97 seconds
Started Sep 09 11:38:30 AM UTC 24
Finished Sep 09 11:38:35 AM UTC 24
Peak memory 245224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690657145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2690657145
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3276899899
Short name T829
Test name
Test status
Simulation time 176572208 ps
CPU time 6.11 seconds
Started Sep 09 11:38:36 AM UTC 24
Finished Sep 09 11:38:43 AM UTC 24
Peak memory 233428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276899899 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3276899899
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.230034269
Short name T840
Test name
Test status
Simulation time 1329597989 ps
CPU time 10.67 seconds
Started Sep 09 11:38:41 AM UTC 24
Finished Sep 09 11:38:53 AM UTC 24
Peak memory 234892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230034269 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.230034269
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.3421380157
Short name T830
Test name
Test status
Simulation time 7903747019 ps
CPU time 16.19 seconds
Started Sep 09 11:38:26 AM UTC 24
Finished Sep 09 11:38:43 AM UTC 24
Peak memory 227624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421380157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3421380157
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2144767586
Short name T827
Test name
Test status
Simulation time 1804877459 ps
CPU time 14.35 seconds
Started Sep 09 11:38:26 AM UTC 24
Finished Sep 09 11:38:41 AM UTC 24
Peak memory 227500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144767586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2144767586
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.513716357
Short name T818
Test name
Test status
Simulation time 140518954 ps
CPU time 2.27 seconds
Started Sep 09 11:38:29 AM UTC 24
Finished Sep 09 11:38:32 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513716357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.513716357
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3171077754
Short name T815
Test name
Test status
Simulation time 123123826 ps
CPU time 1.28 seconds
Started Sep 09 11:38:27 AM UTC 24
Finished Sep 09 11:38:29 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171077754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3171077754
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.2732572601
Short name T835
Test name
Test status
Simulation time 4007933478 ps
CPU time 13.01 seconds
Started Sep 09 11:38:34 AM UTC 24
Finished Sep 09 11:38:48 AM UTC 24
Peak memory 235088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732572601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2732572601
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.3413425587
Short name T847
Test name
Test status
Simulation time 68913905 ps
CPU time 1.12 seconds
Started Sep 09 11:38:55 AM UTC 24
Finished Sep 09 11:38:57 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413425587 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.3413425587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3541980015
Short name T841
Test name
Test status
Simulation time 37528528 ps
CPU time 2.25 seconds
Started Sep 09 11:38:49 AM UTC 24
Finished Sep 09 11:38:53 AM UTC 24
Peak memory 234304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541980015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3541980015
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2731434228
Short name T833
Test name
Test status
Simulation time 24279012 ps
CPU time 1.2 seconds
Started Sep 09 11:38:42 AM UTC 24
Finished Sep 09 11:38:45 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731434228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2731434228
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2827550232
Short name T894
Test name
Test status
Simulation time 5808903793 ps
CPU time 43.78 seconds
Started Sep 09 11:38:54 AM UTC 24
Finished Sep 09 11:39:39 AM UTC 24
Peak memory 263752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827550232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2827550232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1358703706
Short name T364
Test name
Test status
Simulation time 13571003716 ps
CPU time 94.48 seconds
Started Sep 09 11:38:54 AM UTC 24
Finished Sep 09 11:40:30 AM UTC 24
Peak memory 267920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358703706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1358703706
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2576945175
Short name T920
Test name
Test status
Simulation time 11948358980 ps
CPU time 61.44 seconds
Started Sep 09 11:38:54 AM UTC 24
Finished Sep 09 11:39:57 AM UTC 24
Peak memory 245360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576945175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.2576945175
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1584585892
Short name T867
Test name
Test status
Simulation time 6106616875 ps
CPU time 21.37 seconds
Started Sep 09 11:38:49 AM UTC 24
Finished Sep 09 11:39:13 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584585892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1584585892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.487548739
Short name T901
Test name
Test status
Simulation time 3305751021 ps
CPU time 49.87 seconds
Started Sep 09 11:38:52 AM UTC 24
Finished Sep 09 11:39:45 AM UTC 24
Peak memory 251464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487548739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.487548739
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2246154240
Short name T850
Test name
Test status
Simulation time 1418456531 ps
CPU time 8.42 seconds
Started Sep 09 11:38:48 AM UTC 24
Finished Sep 09 11:38:58 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246154240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2246154240
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.896901309
Short name T843
Test name
Test status
Simulation time 114968568 ps
CPU time 2.96 seconds
Started Sep 09 11:38:49 AM UTC 24
Finished Sep 09 11:38:54 AM UTC 24
Peak memory 244900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896901309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.896901309
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3631129070
Short name T844
Test name
Test status
Simulation time 1113285651 ps
CPU time 7.03 seconds
Started Sep 09 11:38:46 AM UTC 24
Finished Sep 09 11:38:54 AM UTC 24
Peak memory 245144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631129070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.3631129070
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3779697099
Short name T846
Test name
Test status
Simulation time 812934467 ps
CPU time 6.71 seconds
Started Sep 09 11:38:46 AM UTC 24
Finished Sep 09 11:38:54 AM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779697099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3779697099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2564987135
Short name T852
Test name
Test status
Simulation time 475262503 ps
CPU time 6.3 seconds
Started Sep 09 11:38:54 AM UTC 24
Finished Sep 09 11:39:01 AM UTC 24
Peak memory 231256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564987135 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2564987135
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.2837956587
Short name T849
Test name
Test status
Simulation time 87221962 ps
CPU time 1.51 seconds
Started Sep 09 11:38:55 AM UTC 24
Finished Sep 09 11:38:58 AM UTC 24
Peak memory 226544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837956587 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.2837956587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.3287234693
Short name T839
Test name
Test status
Simulation time 599141563 ps
CPU time 6.38 seconds
Started Sep 09 11:38:45 AM UTC 24
Finished Sep 09 11:38:52 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287234693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3287234693
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2113907949
Short name T842
Test name
Test status
Simulation time 2909701644 ps
CPU time 9.66 seconds
Started Sep 09 11:38:43 AM UTC 24
Finished Sep 09 11:38:54 AM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113907949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2113907949
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.548433688
Short name T836
Test name
Test status
Simulation time 24772817 ps
CPU time 1.54 seconds
Started Sep 09 11:38:46 AM UTC 24
Finished Sep 09 11:38:48 AM UTC 24
Peak memory 215624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548433688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.548433688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.4267638058
Short name T834
Test name
Test status
Simulation time 51333085 ps
CPU time 1.22 seconds
Started Sep 09 11:38:45 AM UTC 24
Finished Sep 09 11:38:47 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267638058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4267638058
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2141576302
Short name T845
Test name
Test status
Simulation time 67152827 ps
CPU time 3.17 seconds
Started Sep 09 11:38:49 AM UTC 24
Finished Sep 09 11:38:54 AM UTC 24
Peak memory 234720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141576302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2141576302
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.4001329202
Short name T864
Test name
Test status
Simulation time 20364889 ps
CPU time 1.07 seconds
Started Sep 09 11:39:10 AM UTC 24
Finished Sep 09 11:39:12 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001329202 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.4001329202
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2413935514
Short name T861
Test name
Test status
Simulation time 1865033663 ps
CPU time 6.88 seconds
Started Sep 09 11:39:02 AM UTC 24
Finished Sep 09 11:39:10 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413935514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2413935514
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.3784718340
Short name T848
Test name
Test status
Simulation time 80822130 ps
CPU time 1.17 seconds
Started Sep 09 11:38:55 AM UTC 24
Finished Sep 09 11:38:57 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784718340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3784718340
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.715451751
Short name T941
Test name
Test status
Simulation time 2428740565 ps
CPU time 65.26 seconds
Started Sep 09 11:39:07 AM UTC 24
Finished Sep 09 11:40:15 AM UTC 24
Peak memory 263752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715451751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.715451751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.1293292818
Short name T376
Test name
Test status
Simulation time 50785415916 ps
CPU time 222.68 seconds
Started Sep 09 11:39:08 AM UTC 24
Finished Sep 09 11:42:55 AM UTC 24
Peak memory 267904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293292818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1293292818
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.322886628
Short name T178
Test name
Test status
Simulation time 133474666815 ps
CPU time 294.36 seconds
Started Sep 09 11:39:08 AM UTC 24
Finished Sep 09 11:44:07 AM UTC 24
Peak memory 284424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322886628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.322886628
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2237600506
Short name T862
Test name
Test status
Simulation time 180600991 ps
CPU time 6.8 seconds
Started Sep 09 11:39:03 AM UTC 24
Finished Sep 09 11:39:11 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237600506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2237600506
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1119729848
Short name T890
Test name
Test status
Simulation time 3963631876 ps
CPU time 28.98 seconds
Started Sep 09 11:39:03 AM UTC 24
Finished Sep 09 11:39:33 AM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119729848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1119729848
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1774796409
Short name T870
Test name
Test status
Simulation time 1312997705 ps
CPU time 13.08 seconds
Started Sep 09 11:39:00 AM UTC 24
Finished Sep 09 11:39:14 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774796409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1774796409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1371163229
Short name T875
Test name
Test status
Simulation time 1533986022 ps
CPU time 15.78 seconds
Started Sep 09 11:39:00 AM UTC 24
Finished Sep 09 11:39:17 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371163229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1371163229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1191166680
Short name T868
Test name
Test status
Simulation time 5629654286 ps
CPU time 13.25 seconds
Started Sep 09 11:38:59 AM UTC 24
Finished Sep 09 11:39:13 AM UTC 24
Peak memory 245396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191166680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.1191166680
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2219271290
Short name T855
Test name
Test status
Simulation time 101278471 ps
CPU time 2.76 seconds
Started Sep 09 11:38:59 AM UTC 24
Finished Sep 09 11:39:02 AM UTC 24
Peak memory 233464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219271290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2219271290
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.910575111
Short name T860
Test name
Test status
Simulation time 786300669 ps
CPU time 4.49 seconds
Started Sep 09 11:39:04 AM UTC 24
Finished Sep 09 11:39:10 AM UTC 24
Peak memory 233648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910575111 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.910575111
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.4288778396
Short name T1003
Test name
Test status
Simulation time 248325973699 ps
CPU time 569.77 seconds
Started Sep 09 11:39:09 AM UTC 24
Finished Sep 09 11:48:46 AM UTC 24
Peak memory 294572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288778396 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.4288778396
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.4119731819
Short name T857
Test name
Test status
Simulation time 5388665661 ps
CPU time 10.76 seconds
Started Sep 09 11:38:55 AM UTC 24
Finished Sep 09 11:39:07 AM UTC 24
Peak memory 227608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119731819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4119731819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.744175269
Short name T851
Test name
Test status
Simulation time 499439131 ps
CPU time 2.32 seconds
Started Sep 09 11:38:55 AM UTC 24
Finished Sep 09 11:38:58 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744175269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.744175269
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2018966655
Short name T854
Test name
Test status
Simulation time 394164409 ps
CPU time 2.27 seconds
Started Sep 09 11:38:58 AM UTC 24
Finished Sep 09 11:39:02 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018966655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2018966655
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.820474607
Short name T853
Test name
Test status
Simulation time 116716534 ps
CPU time 1.58 seconds
Started Sep 09 11:38:58 AM UTC 24
Finished Sep 09 11:39:01 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820474607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.820474607
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.1880909639
Short name T838
Test name
Test status
Simulation time 102875007 ps
CPU time 3.13 seconds
Started Sep 09 11:39:02 AM UTC 24
Finished Sep 09 11:39:06 AM UTC 24
Peak memory 234952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880909639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1880909639
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3694375669
Short name T879
Test name
Test status
Simulation time 13342727 ps
CPU time 1.12 seconds
Started Sep 09 11:39:20 AM UTC 24
Finished Sep 09 11:39:22 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694375669 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3694375669
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3319610440
Short name T882
Test name
Test status
Simulation time 873575447 ps
CPU time 9.09 seconds
Started Sep 09 11:39:15 AM UTC 24
Finished Sep 09 11:39:25 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319610440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3319610440
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.1814046683
Short name T865
Test name
Test status
Simulation time 25086121 ps
CPU time 1.13 seconds
Started Sep 09 11:39:10 AM UTC 24
Finished Sep 09 11:39:12 AM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814046683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1814046683
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.530891264
Short name T974
Test name
Test status
Simulation time 8320022771 ps
CPU time 90.73 seconds
Started Sep 09 11:39:17 AM UTC 24
Finished Sep 09 11:40:50 AM UTC 24
Peak memory 261708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530891264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.530891264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2196900818
Short name T880
Test name
Test status
Simulation time 370086366 ps
CPU time 3.54 seconds
Started Sep 09 11:39:17 AM UTC 24
Finished Sep 09 11:39:22 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196900818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2196900818
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4238356892
Short name T976
Test name
Test status
Simulation time 10978935684 ps
CPU time 96.11 seconds
Started Sep 09 11:39:18 AM UTC 24
Finished Sep 09 11:40:56 AM UTC 24
Peak memory 251536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238356892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.4238356892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.450341929
Short name T389
Test name
Test status
Simulation time 5435033018 ps
CPU time 23.63 seconds
Started Sep 09 11:39:15 AM UTC 24
Finished Sep 09 11:39:40 AM UTC 24
Peak memory 235084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450341929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.450341929
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.378230609
Short name T967
Test name
Test status
Simulation time 31924106253 ps
CPU time 84.02 seconds
Started Sep 09 11:39:16 AM UTC 24
Finished Sep 09 11:40:42 AM UTC 24
Peak memory 263760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378230609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.378230609
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.39096716
Short name T889
Test name
Test status
Simulation time 5677533030 ps
CPU time 15.28 seconds
Started Sep 09 11:39:13 AM UTC 24
Finished Sep 09 11:39:30 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39096716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.39096716
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.635871493
Short name T946
Test name
Test status
Simulation time 19818982052 ps
CPU time 63.05 seconds
Started Sep 09 11:39:15 AM UTC 24
Finished Sep 09 11:40:20 AM UTC 24
Peak memory 245408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635871493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.635871493
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.837617445
Short name T874
Test name
Test status
Simulation time 125504531 ps
CPU time 2.09 seconds
Started Sep 09 11:39:13 AM UTC 24
Finished Sep 09 11:39:17 AM UTC 24
Peak memory 244940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837617445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.837617445
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.3298890749
Short name T877
Test name
Test status
Simulation time 422111192 ps
CPU time 4.59 seconds
Started Sep 09 11:39:13 AM UTC 24
Finished Sep 09 11:39:19 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298890749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3298890749
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.4205417926
Short name T884
Test name
Test status
Simulation time 2213293822 ps
CPU time 7.25 seconds
Started Sep 09 11:39:17 AM UTC 24
Finished Sep 09 11:39:26 AM UTC 24
Peak memory 231320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205417926 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.4205417926
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2993561479
Short name T194
Test name
Test status
Simulation time 2757453307 ps
CPU time 69.21 seconds
Started Sep 09 11:39:18 AM UTC 24
Finished Sep 09 11:40:30 AM UTC 24
Peak memory 251668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993561479 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.2993561479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.504760928
Short name T873
Test name
Test status
Simulation time 507285366 ps
CPU time 4.46 seconds
Started Sep 09 11:39:11 AM UTC 24
Finished Sep 09 11:39:16 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504760928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.504760928
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1239486159
Short name T878
Test name
Test status
Simulation time 10295611189 ps
CPU time 8.22 seconds
Started Sep 09 11:39:11 AM UTC 24
Finished Sep 09 11:39:20 AM UTC 24
Peak memory 227644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239486159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1239486159
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.4212782881
Short name T876
Test name
Test status
Simulation time 726144549 ps
CPU time 3.19 seconds
Started Sep 09 11:39:13 AM UTC 24
Finished Sep 09 11:39:17 AM UTC 24
Peak memory 227476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212782881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4212782881
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.40634748
Short name T871
Test name
Test status
Simulation time 51634306 ps
CPU time 1.08 seconds
Started Sep 09 11:39:12 AM UTC 24
Finished Sep 09 11:39:14 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40634748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.40634748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.1917140394
Short name T883
Test name
Test status
Simulation time 1778145897 ps
CPU time 9.39 seconds
Started Sep 09 11:39:15 AM UTC 24
Finished Sep 09 11:39:25 AM UTC 24
Peak memory 245156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917140394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1917140394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.1122280018
Short name T897
Test name
Test status
Simulation time 12631013 ps
CPU time 1.08 seconds
Started Sep 09 11:39:40 AM UTC 24
Finished Sep 09 11:39:42 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122280018 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.1122280018
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3163130678
Short name T900
Test name
Test status
Simulation time 5367969076 ps
CPU time 13.27 seconds
Started Sep 09 11:39:29 AM UTC 24
Finished Sep 09 11:39:44 AM UTC 24
Peak memory 245276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163130678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3163130678
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3381325758
Short name T881
Test name
Test status
Simulation time 38169360 ps
CPU time 1.19 seconds
Started Sep 09 11:39:21 AM UTC 24
Finished Sep 09 11:39:23 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381325758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3381325758
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2673882273
Short name T363
Test name
Test status
Simulation time 29586108533 ps
CPU time 64.45 seconds
Started Sep 09 11:39:36 AM UTC 24
Finished Sep 09 11:40:43 AM UTC 24
Peak memory 261724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673882273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2673882273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3825566951
Short name T910
Test name
Test status
Simulation time 9031730494 ps
CPU time 12.95 seconds
Started Sep 09 11:39:36 AM UTC 24
Finished Sep 09 11:39:51 AM UTC 24
Peak memory 229664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825566951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3825566951
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2371599044
Short name T375
Test name
Test status
Simulation time 8271825250 ps
CPU time 128.64 seconds
Started Sep 09 11:39:38 AM UTC 24
Finished Sep 09 11:41:49 AM UTC 24
Peak memory 251528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371599044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.2371599044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.4044271853
Short name T893
Test name
Test status
Simulation time 183771962 ps
CPU time 4.65 seconds
Started Sep 09 11:39:31 AM UTC 24
Finished Sep 09 11:39:37 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044271853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4044271853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3003815556
Short name T379
Test name
Test status
Simulation time 36425966139 ps
CPU time 280.45 seconds
Started Sep 09 11:39:31 AM UTC 24
Finished Sep 09 11:44:15 AM UTC 24
Peak memory 267920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003815556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.3003815556
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.2198183853
Short name T891
Test name
Test status
Simulation time 463115871 ps
CPU time 7.01 seconds
Started Sep 09 11:39:27 AM UTC 24
Finished Sep 09 11:39:35 AM UTC 24
Peak memory 245116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198183853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2198183853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2426226209
Short name T895
Test name
Test status
Simulation time 3332592723 ps
CPU time 10.15 seconds
Started Sep 09 11:39:28 AM UTC 24
Finished Sep 09 11:39:39 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426226209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2426226209
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.562974896
Short name T892
Test name
Test status
Simulation time 2269178237 ps
CPU time 7.22 seconds
Started Sep 09 11:39:27 AM UTC 24
Finished Sep 09 11:39:35 AM UTC 24
Peak memory 245292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562974896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.562974896
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2585286403
Short name T923
Test name
Test status
Simulation time 9802499495 ps
CPU time 30.41 seconds
Started Sep 09 11:39:27 AM UTC 24
Finished Sep 09 11:39:58 AM UTC 24
Peak memory 245276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585286403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2585286403
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.677430198
Short name T903
Test name
Test status
Simulation time 2013593084 ps
CPU time 10.79 seconds
Started Sep 09 11:39:34 AM UTC 24
Finished Sep 09 11:39:46 AM UTC 24
Peak memory 233388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677430198 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.677430198
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.263428100
Short name T370
Test name
Test status
Simulation time 75323691741 ps
CPU time 891.62 seconds
Started Sep 09 11:39:40 AM UTC 24
Finished Sep 09 11:54:43 AM UTC 24
Peak memory 280204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263428100 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.263428100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.1633563078
Short name T902
Test name
Test status
Simulation time 9497428275 ps
CPU time 21.41 seconds
Started Sep 09 11:39:23 AM UTC 24
Finished Sep 09 11:39:46 AM UTC 24
Peak memory 231644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633563078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1633563078
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2975452706
Short name T888
Test name
Test status
Simulation time 2296559133 ps
CPU time 5.24 seconds
Started Sep 09 11:39:23 AM UTC 24
Finished Sep 09 11:39:30 AM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975452706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2975452706
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.1730815121
Short name T887
Test name
Test status
Simulation time 20992361 ps
CPU time 0.99 seconds
Started Sep 09 11:39:27 AM UTC 24
Finished Sep 09 11:39:29 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730815121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1730815121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.806728813
Short name T885
Test name
Test status
Simulation time 13135710 ps
CPU time 1.08 seconds
Started Sep 09 11:39:24 AM UTC 24
Finished Sep 09 11:39:26 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806728813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.806728813
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.841676077
Short name T899
Test name
Test status
Simulation time 4373185071 ps
CPU time 13.08 seconds
Started Sep 09 11:39:29 AM UTC 24
Finished Sep 09 11:39:44 AM UTC 24
Peak memory 245284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841676077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.841676077
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2457576824
Short name T916
Test name
Test status
Simulation time 78421950 ps
CPU time 1.04 seconds
Started Sep 09 11:39:53 AM UTC 24
Finished Sep 09 11:39:55 AM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457576824 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.2457576824
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.282230195
Short name T915
Test name
Test status
Simulation time 143963058 ps
CPU time 2.77 seconds
Started Sep 09 11:39:49 AM UTC 24
Finished Sep 09 11:39:53 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282230195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.282230195
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.3403870646
Short name T898
Test name
Test status
Simulation time 17315153 ps
CPU time 1.14 seconds
Started Sep 09 11:39:41 AM UTC 24
Finished Sep 09 11:39:43 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403870646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3403870646
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.3564227254
Short name T914
Test name
Test status
Simulation time 48225314 ps
CPU time 1.18 seconds
Started Sep 09 11:39:50 AM UTC 24
Finished Sep 09 11:39:53 AM UTC 24
Peak memory 225728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564227254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3564227254
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3296447324
Short name T377
Test name
Test status
Simulation time 6203100485 ps
CPU time 97.55 seconds
Started Sep 09 11:39:52 AM UTC 24
Finished Sep 09 11:41:31 AM UTC 24
Peak memory 263800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296447324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3296447324
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2780641651
Short name T998
Test name
Test status
Simulation time 184980504102 ps
CPU time 336.07 seconds
Started Sep 09 11:39:52 AM UTC 24
Finished Sep 09 11:45:32 AM UTC 24
Peak memory 267896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780641651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.2780641651
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.3596162483
Short name T924
Test name
Test status
Simulation time 784733989 ps
CPU time 11.93 seconds
Started Sep 09 11:39:49 AM UTC 24
Finished Sep 09 11:40:02 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596162483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3596162483
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.680737464
Short name T955
Test name
Test status
Simulation time 5319913010 ps
CPU time 39.04 seconds
Started Sep 09 11:39:50 AM UTC 24
Finished Sep 09 11:40:31 AM UTC 24
Peak memory 263776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680737464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.680737464
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.401872875
Short name T913
Test name
Test status
Simulation time 115522850 ps
CPU time 5.25 seconds
Started Sep 09 11:39:46 AM UTC 24
Finished Sep 09 11:39:52 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401872875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.401872875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2941383676
Short name T928
Test name
Test status
Simulation time 670733016 ps
CPU time 15.06 seconds
Started Sep 09 11:39:47 AM UTC 24
Finished Sep 09 11:40:04 AM UTC 24
Peak memory 247248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941383676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2941383676
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.403905402
Short name T911
Test name
Test status
Simulation time 322888021 ps
CPU time 4.83 seconds
Started Sep 09 11:39:46 AM UTC 24
Finished Sep 09 11:39:52 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403905402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.403905402
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1277421641
Short name T907
Test name
Test status
Simulation time 111134245 ps
CPU time 3.21 seconds
Started Sep 09 11:39:45 AM UTC 24
Finished Sep 09 11:39:49 AM UTC 24
Peak memory 234372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277421641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1277421641
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2444283251
Short name T929
Test name
Test status
Simulation time 4096207885 ps
CPU time 12.68 seconds
Started Sep 09 11:39:50 AM UTC 24
Finished Sep 09 11:40:04 AM UTC 24
Peak memory 231384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444283251 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.2444283251
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1056070237
Short name T981
Test name
Test status
Simulation time 4513530706 ps
CPU time 87.86 seconds
Started Sep 09 11:39:53 AM UTC 24
Finished Sep 09 11:41:23 AM UTC 24
Peak memory 267864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056070237 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.1056070237
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.3029890301
Short name T969
Test name
Test status
Simulation time 9921481488 ps
CPU time 58.75 seconds
Started Sep 09 11:39:42 AM UTC 24
Finished Sep 09 11:40:43 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029890301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3029890301
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3454585518
Short name T905
Test name
Test status
Simulation time 1338087269 ps
CPU time 4.57 seconds
Started Sep 09 11:39:42 AM UTC 24
Finished Sep 09 11:39:48 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454585518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3454585518
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.4289818215
Short name T906
Test name
Test status
Simulation time 204433058 ps
CPU time 2.12 seconds
Started Sep 09 11:39:45 AM UTC 24
Finished Sep 09 11:39:48 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289818215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4289818215
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1671226608
Short name T904
Test name
Test status
Simulation time 323644894 ps
CPU time 1.49 seconds
Started Sep 09 11:39:45 AM UTC 24
Finished Sep 09 11:39:47 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671226608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1671226608
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.2668051155
Short name T922
Test name
Test status
Simulation time 1023694702 ps
CPU time 8.33 seconds
Started Sep 09 11:39:49 AM UTC 24
Finished Sep 09 11:39:58 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668051155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2668051155
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.4069213432
Short name T931
Test name
Test status
Simulation time 39007261 ps
CPU time 1.09 seconds
Started Sep 09 11:40:06 AM UTC 24
Finished Sep 09 11:40:08 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069213432 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.4069213432
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3127330394
Short name T930
Test name
Test status
Simulation time 803551792 ps
CPU time 5.56 seconds
Started Sep 09 11:39:58 AM UTC 24
Finished Sep 09 11:40:05 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127330394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3127330394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3331519249
Short name T917
Test name
Test status
Simulation time 28355149 ps
CPU time 1.16 seconds
Started Sep 09 11:39:53 AM UTC 24
Finished Sep 09 11:39:55 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331519249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3331519249
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.146426022
Short name T980
Test name
Test status
Simulation time 47476821881 ps
CPU time 74.45 seconds
Started Sep 09 11:40:04 AM UTC 24
Finished Sep 09 11:41:20 AM UTC 24
Peak memory 247372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146426022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.146426022
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.2580485074
Short name T982
Test name
Test status
Simulation time 10081087875 ps
CPU time 78.69 seconds
Started Sep 09 11:40:04 AM UTC 24
Finished Sep 09 11:41:25 AM UTC 24
Peak memory 234988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580485074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2580485074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.9982429
Short name T996
Test name
Test status
Simulation time 105453759737 ps
CPU time 283.7 seconds
Started Sep 09 11:40:04 AM UTC 24
Finished Sep 09 11:44:52 AM UTC 24
Peak memory 272008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9982429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.9982429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.4076410627
Short name T942
Test name
Test status
Simulation time 1296638326 ps
CPU time 14.22 seconds
Started Sep 09 11:40:00 AM UTC 24
Finished Sep 09 11:40:15 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076410627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4076410627
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3095063348
Short name T937
Test name
Test status
Simulation time 265663829 ps
CPU time 11.94 seconds
Started Sep 09 11:40:00 AM UTC 24
Finished Sep 09 11:40:13 AM UTC 24
Peak memory 247312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095063348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.3095063348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3227308758
Short name T925
Test name
Test status
Simulation time 130778290 ps
CPU time 3.18 seconds
Started Sep 09 11:39:58 AM UTC 24
Finished Sep 09 11:40:02 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227308758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3227308758
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.2672431690
Short name T938
Test name
Test status
Simulation time 18606134630 ps
CPU time 14.21 seconds
Started Sep 09 11:39:58 AM UTC 24
Finished Sep 09 11:40:14 AM UTC 24
Peak memory 235232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672431690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2672431690
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3268994682
Short name T963
Test name
Test status
Simulation time 29952417421 ps
CPU time 38.6 seconds
Started Sep 09 11:39:58 AM UTC 24
Finished Sep 09 11:40:38 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268994682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.3268994682
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2108402191
Short name T935
Test name
Test status
Simulation time 11767348720 ps
CPU time 14.53 seconds
Started Sep 09 11:39:56 AM UTC 24
Finished Sep 09 11:40:12 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108402191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2108402191
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2342116842
Short name T943
Test name
Test status
Simulation time 708465944 ps
CPU time 10.54 seconds
Started Sep 09 11:40:04 AM UTC 24
Finished Sep 09 11:40:16 AM UTC 24
Peak memory 231256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342116842 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.2342116842
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1794015730
Short name T933
Test name
Test status
Simulation time 81886959 ps
CPU time 1.42 seconds
Started Sep 09 11:40:06 AM UTC 24
Finished Sep 09 11:40:08 AM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794015730 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.1794015730
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.163557477
Short name T921
Test name
Test status
Simulation time 693310392 ps
CPU time 3.03 seconds
Started Sep 09 11:39:53 AM UTC 24
Finished Sep 09 11:39:57 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163557477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.163557477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.679493992
Short name T934
Test name
Test status
Simulation time 22092440527 ps
CPU time 16.14 seconds
Started Sep 09 11:39:53 AM UTC 24
Finished Sep 09 11:40:11 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679493992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.679493992
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.2536293853
Short name T926
Test name
Test status
Simulation time 149900282 ps
CPU time 5.32 seconds
Started Sep 09 11:39:56 AM UTC 24
Finished Sep 09 11:40:02 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536293853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2536293853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.2134270146
Short name T919
Test name
Test status
Simulation time 30379876 ps
CPU time 1.3 seconds
Started Sep 09 11:39:55 AM UTC 24
Finished Sep 09 11:39:57 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134270146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2134270146
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.2966336073
Short name T927
Test name
Test status
Simulation time 614759920 ps
CPU time 3.12 seconds
Started Sep 09 11:39:58 AM UTC 24
Finished Sep 09 11:40:03 AM UTC 24
Peak memory 234660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966336073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2966336073
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3889108580
Short name T950
Test name
Test status
Simulation time 38348102 ps
CPU time 1.13 seconds
Started Sep 09 11:40:21 AM UTC 24
Finished Sep 09 11:40:23 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889108580 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.3889108580
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2241464937
Short name T954
Test name
Test status
Simulation time 8194937786 ps
CPU time 13.15 seconds
Started Sep 09 11:40:16 AM UTC 24
Finished Sep 09 11:40:30 AM UTC 24
Peak memory 245260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241464937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2241464937
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.3232017235
Short name T932
Test name
Test status
Simulation time 104802247 ps
CPU time 1.16 seconds
Started Sep 09 11:40:06 AM UTC 24
Finished Sep 09 11:40:08 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232017235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3232017235
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.3980908201
Short name T964
Test name
Test status
Simulation time 1317157322 ps
CPU time 20.48 seconds
Started Sep 09 11:40:18 AM UTC 24
Finished Sep 09 11:40:40 AM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980908201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3980908201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.712067566
Short name T1001
Test name
Test status
Simulation time 204287300611 ps
CPU time 413.6 seconds
Started Sep 09 11:40:18 AM UTC 24
Finished Sep 09 11:47:17 AM UTC 24
Peak memory 276104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712067566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.712067566
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3723973380
Short name T1002
Test name
Test status
Simulation time 170433493595 ps
CPU time 493.57 seconds
Started Sep 09 11:40:18 AM UTC 24
Finished Sep 09 11:48:38 AM UTC 24
Peak memory 278200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723973380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.3723973380
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2078184352
Short name T968
Test name
Test status
Simulation time 5864359831 ps
CPU time 25.11 seconds
Started Sep 09 11:40:16 AM UTC 24
Finished Sep 09 11:40:42 AM UTC 24
Peak memory 251468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078184352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2078184352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.636110064
Short name T978
Test name
Test status
Simulation time 10508535584 ps
CPU time 48.58 seconds
Started Sep 09 11:40:16 AM UTC 24
Finished Sep 09 11:41:06 AM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636110064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.636110064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.741067273
Short name T953
Test name
Test status
Simulation time 752970226 ps
CPU time 13.82 seconds
Started Sep 09 11:40:14 AM UTC 24
Finished Sep 09 11:40:29 AM UTC 24
Peak memory 245192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741067273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.741067273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1944591728
Short name T944
Test name
Test status
Simulation time 131793749 ps
CPU time 2.07 seconds
Started Sep 09 11:40:14 AM UTC 24
Finished Sep 09 11:40:17 AM UTC 24
Peak memory 234976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944591728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1944591728
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1725719458
Short name T949
Test name
Test status
Simulation time 2045483396 ps
CPU time 8.66 seconds
Started Sep 09 11:40:13 AM UTC 24
Finished Sep 09 11:40:22 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725719458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.1725719458
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.546169618
Short name T977
Test name
Test status
Simulation time 114703935659 ps
CPU time 47.05 seconds
Started Sep 09 11:40:11 AM UTC 24
Finished Sep 09 11:41:00 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546169618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.546169618
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2587501747
Short name T957
Test name
Test status
Simulation time 12669442242 ps
CPU time 14.3 seconds
Started Sep 09 11:40:18 AM UTC 24
Finished Sep 09 11:40:34 AM UTC 24
Peak memory 231440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587501747 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2587501747
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3251044044
Short name T948
Test name
Test status
Simulation time 211238854 ps
CPU time 1.59 seconds
Started Sep 09 11:40:20 AM UTC 24
Finished Sep 09 11:40:22 AM UTC 24
Peak memory 216412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251044044 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.3251044044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.801717687
Short name T945
Test name
Test status
Simulation time 798714629 ps
CPU time 7.53 seconds
Started Sep 09 11:40:10 AM UTC 24
Finished Sep 09 11:40:19 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801717687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.801717687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3350123564
Short name T940
Test name
Test status
Simulation time 165987438 ps
CPU time 3.01 seconds
Started Sep 09 11:40:10 AM UTC 24
Finished Sep 09 11:40:14 AM UTC 24
Peak memory 227328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350123564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3350123564
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.1057782810
Short name T939
Test name
Test status
Simulation time 154426989 ps
CPU time 2.64 seconds
Started Sep 09 11:40:10 AM UTC 24
Finished Sep 09 11:40:14 AM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057782810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1057782810
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1382489385
Short name T936
Test name
Test status
Simulation time 305578490 ps
CPU time 1.37 seconds
Started Sep 09 11:40:10 AM UTC 24
Finished Sep 09 11:40:12 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382489385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1382489385
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.1613142887
Short name T947
Test name
Test status
Simulation time 79496869 ps
CPU time 2.86 seconds
Started Sep 09 11:40:16 AM UTC 24
Finished Sep 09 11:40:20 AM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613142887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1613142887
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.2874209606
Short name T966
Test name
Test status
Simulation time 37178914 ps
CPU time 1.08 seconds
Started Sep 09 11:40:39 AM UTC 24
Finished Sep 09 11:40:41 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874209606 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.2874209606
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1187034855
Short name T962
Test name
Test status
Simulation time 43894716 ps
CPU time 3.44 seconds
Started Sep 09 11:40:33 AM UTC 24
Finished Sep 09 11:40:38 AM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187034855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1187034855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3529184005
Short name T951
Test name
Test status
Simulation time 15219420 ps
CPU time 1.19 seconds
Started Sep 09 11:40:21 AM UTC 24
Finished Sep 09 11:40:23 AM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529184005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3529184005
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.2636454074
Short name T986
Test name
Test status
Simulation time 6022441987 ps
CPU time 66.49 seconds
Started Sep 09 11:40:36 AM UTC 24
Finished Sep 09 11:41:44 AM UTC 24
Peak memory 261768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636454074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2636454074
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1101142696
Short name T995
Test name
Test status
Simulation time 19814992130 ps
CPU time 201.88 seconds
Started Sep 09 11:40:37 AM UTC 24
Finished Sep 09 11:44:03 AM UTC 24
Peak memory 265868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101142696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1101142696
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.291009380
Short name T991
Test name
Test status
Simulation time 31773490697 ps
CPU time 134.28 seconds
Started Sep 09 11:40:37 AM UTC 24
Finished Sep 09 11:42:54 AM UTC 24
Peak memory 265864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291009380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.291009380
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.2928628502
Short name T985
Test name
Test status
Simulation time 4310034808 ps
CPU time 67.09 seconds
Started Sep 09 11:40:33 AM UTC 24
Finished Sep 09 11:41:42 AM UTC 24
Peak memory 261704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928628502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2928628502
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3607263652
Short name T990
Test name
Test status
Simulation time 161007015469 ps
CPU time 127.32 seconds
Started Sep 09 11:40:35 AM UTC 24
Finished Sep 09 11:42:44 AM UTC 24
Peak memory 267836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607263652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.3607263652
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1202092329
Short name T961
Test name
Test status
Simulation time 282945170 ps
CPU time 4.69 seconds
Started Sep 09 11:40:31 AM UTC 24
Finished Sep 09 11:40:37 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202092329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1202092329
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2925299067
Short name T979
Test name
Test status
Simulation time 3654769362 ps
CPU time 39.06 seconds
Started Sep 09 11:40:32 AM UTC 24
Finished Sep 09 11:41:12 AM UTC 24
Peak memory 245268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925299067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2925299067
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.3902392237
Short name T972
Test name
Test status
Simulation time 4459482514 ps
CPU time 13.46 seconds
Started Sep 09 11:40:30 AM UTC 24
Finished Sep 09 11:40:44 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902392237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.3902392237
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.429525305
Short name T956
Test name
Test status
Simulation time 78232006 ps
CPU time 3.52 seconds
Started Sep 09 11:40:27 AM UTC 24
Finished Sep 09 11:40:32 AM UTC 24
Peak memory 245160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429525305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.429525305
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1283011924
Short name T971
Test name
Test status
Simulation time 2722855217 ps
CPU time 8.17 seconds
Started Sep 09 11:40:35 AM UTC 24
Finished Sep 09 11:40:44 AM UTC 24
Peak memory 233828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283011924 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.1283011924
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1085451163
Short name T177
Test name
Test status
Simulation time 4970492454 ps
CPU time 68.9 seconds
Started Sep 09 11:40:39 AM UTC 24
Finished Sep 09 11:41:50 AM UTC 24
Peak memory 261772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085451163 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.1085451163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2358425669
Short name T958
Test name
Test status
Simulation time 5793066694 ps
CPU time 8.71 seconds
Started Sep 09 11:40:24 AM UTC 24
Finished Sep 09 11:40:34 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358425669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2358425669
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1562327426
Short name T960
Test name
Test status
Simulation time 896460408 ps
CPU time 11.4 seconds
Started Sep 09 11:40:24 AM UTC 24
Finished Sep 09 11:40:37 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562327426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1562327426
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.4276022854
Short name T959
Test name
Test status
Simulation time 540379623 ps
CPU time 9.65 seconds
Started Sep 09 11:40:24 AM UTC 24
Finished Sep 09 11:40:35 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276022854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4276022854
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.260109491
Short name T952
Test name
Test status
Simulation time 81801910 ps
CPU time 1.47 seconds
Started Sep 09 11:40:24 AM UTC 24
Finished Sep 09 11:40:27 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260109491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.260109491
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.46552781
Short name T970
Test name
Test status
Simulation time 1128470761 ps
CPU time 10.13 seconds
Started Sep 09 11:40:32 AM UTC 24
Finished Sep 09 11:40:43 AM UTC 24
Peak memory 235172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46552781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.46552781
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.4023539485
Short name T426
Test name
Test status
Simulation time 33306311 ps
CPU time 0.81 seconds
Started Sep 09 11:29:37 AM UTC 24
Finished Sep 09 11:29:40 AM UTC 24
Peak memory 215444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023539485 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4023539485
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3522254481
Short name T5
Test name
Test status
Simulation time 194629244 ps
CPU time 2.74 seconds
Started Sep 09 11:29:32 AM UTC 24
Finished Sep 09 11:29:36 AM UTC 24
Peak memory 234892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522254481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3522254481
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.3453420768
Short name T424
Test name
Test status
Simulation time 16102057 ps
CPU time 0.8 seconds
Started Sep 09 11:29:30 AM UTC 24
Finished Sep 09 11:29:39 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453420768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3453420768
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.528430230
Short name T270
Test name
Test status
Simulation time 21415100587 ps
CPU time 128.52 seconds
Started Sep 09 11:29:34 AM UTC 24
Finished Sep 09 11:31:48 AM UTC 24
Peak memory 265852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528430230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.528430230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3356269393
Short name T727
Test name
Test status
Simulation time 43881696622 ps
CPU time 413.66 seconds
Started Sep 09 11:29:36 AM UTC 24
Finished Sep 09 11:36:41 AM UTC 24
Peak memory 263748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356269393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.3356269393
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3591740874
Short name T223
Test name
Test status
Simulation time 409594362 ps
CPU time 8.68 seconds
Started Sep 09 11:29:32 AM UTC 24
Finished Sep 09 11:29:52 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591740874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3591740874
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2593126500
Short name T428
Test name
Test status
Simulation time 23164959 ps
CPU time 1.01 seconds
Started Sep 09 11:29:33 AM UTC 24
Finished Sep 09 11:29:46 AM UTC 24
Peak memory 225740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593126500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.2593126500
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.512345150
Short name T51
Test name
Test status
Simulation time 578741409 ps
CPU time 3.79 seconds
Started Sep 09 11:29:31 AM UTC 24
Finished Sep 09 11:29:37 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512345150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.512345150
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2099173669
Short name T421
Test name
Test status
Simulation time 102337121 ps
CPU time 1.97 seconds
Started Sep 09 11:29:31 AM UTC 24
Finished Sep 09 11:29:35 AM UTC 24
Peak memory 243820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099173669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2099173669
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.781716996
Short name T71
Test name
Test status
Simulation time 13101942347 ps
CPU time 22.41 seconds
Started Sep 09 11:29:31 AM UTC 24
Finished Sep 09 11:29:56 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781716996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.781716996
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1668911149
Short name T52
Test name
Test status
Simulation time 1732149671 ps
CPU time 4.87 seconds
Started Sep 09 11:29:31 AM UTC 24
Finished Sep 09 11:29:38 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668911149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1668911149
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2277035806
Short name T121
Test name
Test status
Simulation time 280551596 ps
CPU time 4.74 seconds
Started Sep 09 11:29:33 AM UTC 24
Finished Sep 09 11:29:49 AM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277035806 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.2277035806
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.1537550986
Short name T34
Test name
Test status
Simulation time 11504008523 ps
CPU time 89.94 seconds
Started Sep 09 11:29:37 AM UTC 24
Finished Sep 09 11:31:10 AM UTC 24
Peak memory 249120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537550986 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.1537550986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2670555854
Short name T403
Test name
Test status
Simulation time 15009068524 ps
CPU time 27.42 seconds
Started Sep 09 11:29:30 AM UTC 24
Finished Sep 09 11:30:06 AM UTC 24
Peak memory 227544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670555854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2670555854
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3431486483
Short name T427
Test name
Test status
Simulation time 470290074 ps
CPU time 3.64 seconds
Started Sep 09 11:29:30 AM UTC 24
Finished Sep 09 11:29:42 AM UTC 24
Peak memory 227544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431486483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3431486483
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.1320756691
Short name T44
Test name
Test status
Simulation time 234038632 ps
CPU time 3.06 seconds
Started Sep 09 11:29:31 AM UTC 24
Finished Sep 09 11:29:36 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320756691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1320756691
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2574359176
Short name T117
Test name
Test status
Simulation time 52541255 ps
CPU time 0.76 seconds
Started Sep 09 11:29:30 AM UTC 24
Finished Sep 09 11:29:39 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574359176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2574359176
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.4084830072
Short name T241
Test name
Test status
Simulation time 1302791246 ps
CPU time 6.91 seconds
Started Sep 09 11:29:31 AM UTC 24
Finished Sep 09 11:29:40 AM UTC 24
Peak memory 245220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084830072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4084830072
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.2103503362
Short name T429
Test name
Test status
Simulation time 14141928 ps
CPU time 1.12 seconds
Started Sep 09 11:29:47 AM UTC 24
Finished Sep 09 11:29:49 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103503362 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2103503362
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.448117765
Short name T119
Test name
Test status
Simulation time 218471597 ps
CPU time 3.53 seconds
Started Sep 09 11:29:40 AM UTC 24
Finished Sep 09 11:29:48 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448117765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.448117765
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3384530361
Short name T425
Test name
Test status
Simulation time 42691699 ps
CPU time 0.8 seconds
Started Sep 09 11:29:37 AM UTC 24
Finished Sep 09 11:29:39 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384530361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3384530361
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.2370761995
Short name T53
Test name
Test status
Simulation time 8021296115 ps
CPU time 10.14 seconds
Started Sep 09 11:29:43 AM UTC 24
Finished Sep 09 11:29:54 AM UTC 24
Peak memory 233764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370761995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2370761995
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.4208567753
Short name T691
Test name
Test status
Simulation time 37571913614 ps
CPU time 369.45 seconds
Started Sep 09 11:29:44 AM UTC 24
Finished Sep 09 11:35:58 AM UTC 24
Peak memory 261752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208567753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4208567753
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3855400036
Short name T182
Test name
Test status
Simulation time 178662594 ps
CPU time 5.82 seconds
Started Sep 09 11:29:40 AM UTC 24
Finished Sep 09 11:29:50 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855400036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3855400036
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.4035529638
Short name T64
Test name
Test status
Simulation time 7985579751 ps
CPU time 61.3 seconds
Started Sep 09 11:29:42 AM UTC 24
Finished Sep 09 11:30:46 AM UTC 24
Peak memory 263764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035529638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.4035529638
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.4220159171
Short name T167
Test name
Test status
Simulation time 29294222802 ps
CPU time 57.01 seconds
Started Sep 09 11:29:40 AM UTC 24
Finished Sep 09 11:30:42 AM UTC 24
Peak memory 245124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220159171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4220159171
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1288051972
Short name T60
Test name
Test status
Simulation time 5084501038 ps
CPU time 10.99 seconds
Started Sep 09 11:29:40 AM UTC 24
Finished Sep 09 11:29:56 AM UTC 24
Peak memory 245172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288051972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1288051972
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1940364847
Short name T54
Test name
Test status
Simulation time 2095903623 ps
CPU time 9.52 seconds
Started Sep 09 11:29:40 AM UTC 24
Finished Sep 09 11:29:54 AM UTC 24
Peak memory 251336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940364847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1940364847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3524493725
Short name T123
Test name
Test status
Simulation time 3602276992 ps
CPU time 4.29 seconds
Started Sep 09 11:29:42 AM UTC 24
Finished Sep 09 11:29:48 AM UTC 24
Peak memory 234188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524493725 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.3524493725
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2257746512
Short name T405
Test name
Test status
Simulation time 5123888878 ps
CPU time 23.86 seconds
Started Sep 09 11:29:38 AM UTC 24
Finished Sep 09 11:30:03 AM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257746512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2257746512
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.4052634261
Short name T440
Test name
Test status
Simulation time 7137873569 ps
CPU time 20.77 seconds
Started Sep 09 11:29:38 AM UTC 24
Finished Sep 09 11:30:00 AM UTC 24
Peak memory 227500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052634261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4052634261
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.1556640986
Short name T88
Test name
Test status
Simulation time 171706578 ps
CPU time 2.54 seconds
Started Sep 09 11:29:39 AM UTC 24
Finished Sep 09 11:29:46 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556640986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1556640986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3555481388
Short name T432
Test name
Test status
Simulation time 33143974 ps
CPU time 1.01 seconds
Started Sep 09 11:29:39 AM UTC 24
Finished Sep 09 11:29:51 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555481388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3555481388
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1721518124
Short name T217
Test name
Test status
Simulation time 2305183047 ps
CPU time 8.38 seconds
Started Sep 09 11:29:40 AM UTC 24
Finished Sep 09 11:29:53 AM UTC 24
Peak memory 245284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721518124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1721518124
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.3150200828
Short name T437
Test name
Test status
Simulation time 24656273 ps
CPU time 1.02 seconds
Started Sep 09 11:29:54 AM UTC 24
Finished Sep 09 11:29:56 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150200828 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3150200828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.767572253
Short name T303
Test name
Test status
Simulation time 563977315 ps
CPU time 8.67 seconds
Started Sep 09 11:29:52 AM UTC 24
Finished Sep 09 11:30:01 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767572253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.767572253
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.1266134636
Short name T430
Test name
Test status
Simulation time 21969653 ps
CPU time 1.2 seconds
Started Sep 09 11:29:47 AM UTC 24
Finished Sep 09 11:29:49 AM UTC 24
Peak memory 215580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266134636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1266134636
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.3268672686
Short name T436
Test name
Test status
Simulation time 26396387 ps
CPU time 1.21 seconds
Started Sep 09 11:29:53 AM UTC 24
Finished Sep 09 11:29:55 AM UTC 24
Peak memory 225740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268672686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3268672686
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1824943783
Short name T114
Test name
Test status
Simulation time 2646421269 ps
CPU time 33.22 seconds
Started Sep 09 11:29:53 AM UTC 24
Finished Sep 09 11:30:28 AM UTC 24
Peak memory 261768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824943783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1824943783
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.4186173484
Short name T38
Test name
Test status
Simulation time 2758289245 ps
CPU time 61.83 seconds
Started Sep 09 11:29:53 AM UTC 24
Finished Sep 09 11:30:57 AM UTC 24
Peak memory 261780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186173484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.4186173484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.3783528002
Short name T441
Test name
Test status
Simulation time 2112626859 ps
CPU time 8.01 seconds
Started Sep 09 11:29:52 AM UTC 24
Finished Sep 09 11:30:01 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783528002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3783528002
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.339622387
Short name T201
Test name
Test status
Simulation time 35836179864 ps
CPU time 198.1 seconds
Started Sep 09 11:29:52 AM UTC 24
Finished Sep 09 11:33:13 AM UTC 24
Peak memory 267856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339622387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.339622387
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.465871787
Short name T249
Test name
Test status
Simulation time 2345366113 ps
CPU time 13.9 seconds
Started Sep 09 11:29:50 AM UTC 24
Finished Sep 09 11:30:06 AM UTC 24
Peak memory 245352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465871787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.465871787
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3888003030
Short name T72
Test name
Test status
Simulation time 1777667718 ps
CPU time 4.22 seconds
Started Sep 09 11:29:52 AM UTC 24
Finished Sep 09 11:29:57 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888003030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3888003030
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3385862117
Short name T435
Test name
Test status
Simulation time 106610493 ps
CPU time 2.85 seconds
Started Sep 09 11:29:50 AM UTC 24
Finished Sep 09 11:29:54 AM UTC 24
Peak memory 245016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385862117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3385862117
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2342538688
Short name T73
Test name
Test status
Simulation time 3604069844 ps
CPU time 6.3 seconds
Started Sep 09 11:29:50 AM UTC 24
Finished Sep 09 11:29:58 AM UTC 24
Peak memory 235036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342538688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2342538688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3084603335
Short name T442
Test name
Test status
Simulation time 1551178342 ps
CPU time 9.3 seconds
Started Sep 09 11:29:53 AM UTC 24
Finished Sep 09 11:30:03 AM UTC 24
Peak memory 233372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084603335 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.3084603335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.2010430419
Short name T205
Test name
Test status
Simulation time 22415412683 ps
CPU time 106 seconds
Started Sep 09 11:29:54 AM UTC 24
Finished Sep 09 11:31:42 AM UTC 24
Peak memory 251596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010430419 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.2010430419
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2471524044
Short name T433
Test name
Test status
Simulation time 49860350 ps
CPU time 1.12 seconds
Started Sep 09 11:29:49 AM UTC 24
Finished Sep 09 11:29:51 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471524044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2471524044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1449244177
Short name T431
Test name
Test status
Simulation time 10949332 ps
CPU time 1.04 seconds
Started Sep 09 11:29:48 AM UTC 24
Finished Sep 09 11:29:50 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449244177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1449244177
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2921660364
Short name T406
Test name
Test status
Simulation time 137350694 ps
CPU time 1.41 seconds
Started Sep 09 11:29:50 AM UTC 24
Finished Sep 09 11:29:53 AM UTC 24
Peak memory 216280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921660364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2921660364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2202199490
Short name T434
Test name
Test status
Simulation time 36946772 ps
CPU time 1.15 seconds
Started Sep 09 11:29:49 AM UTC 24
Finished Sep 09 11:29:51 AM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202199490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2202199490
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.2644748935
Short name T57
Test name
Test status
Simulation time 1480073348 ps
CPU time 12.16 seconds
Started Sep 09 11:29:52 AM UTC 24
Finished Sep 09 11:30:05 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644748935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2644748935
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.1372368241
Short name T443
Test name
Test status
Simulation time 15539710 ps
CPU time 1.09 seconds
Started Sep 09 11:30:04 AM UTC 24
Finished Sep 09 11:30:06 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372368241 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1372368241
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3476992429
Short name T439
Test name
Test status
Simulation time 34760582 ps
CPU time 1.21 seconds
Started Sep 09 11:29:55 AM UTC 24
Finished Sep 09 11:29:57 AM UTC 24
Peak memory 215756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476992429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3476992429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2301236991
Short name T274
Test name
Test status
Simulation time 74715257312 ps
CPU time 168.53 seconds
Started Sep 09 11:30:02 AM UTC 24
Finished Sep 09 11:32:54 AM UTC 24
Peak memory 245388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301236991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.2301236991
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.1960864404
Short name T170
Test name
Test status
Simulation time 4763951632 ps
CPU time 42.17 seconds
Started Sep 09 11:29:59 AM UTC 24
Finished Sep 09 11:30:43 AM UTC 24
Peak memory 245184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960864404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.1960864404
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.3865834156
Short name T219
Test name
Test status
Simulation time 184392816 ps
CPU time 5.1 seconds
Started Sep 09 11:29:57 AM UTC 24
Finished Sep 09 11:30:03 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865834156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3865834156
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2650557484
Short name T477
Test name
Test status
Simulation time 40845435235 ps
CPU time 74.52 seconds
Started Sep 09 11:29:58 AM UTC 24
Finished Sep 09 11:31:14 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650557484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2650557484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3340366429
Short name T222
Test name
Test status
Simulation time 22543490699 ps
CPU time 25.71 seconds
Started Sep 09 11:29:57 AM UTC 24
Finished Sep 09 11:30:24 AM UTC 24
Peak memory 245328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340366429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.3340366429
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.4069713291
Short name T256
Test name
Test status
Simulation time 20974120527 ps
CPU time 17.85 seconds
Started Sep 09 11:29:57 AM UTC 24
Finished Sep 09 11:30:16 AM UTC 24
Peak memory 251336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069713291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4069713291
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3318989327
Short name T447
Test name
Test status
Simulation time 3569820840 ps
CPU time 8.5 seconds
Started Sep 09 11:30:00 AM UTC 24
Finished Sep 09 11:30:11 AM UTC 24
Peak memory 231452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318989327 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.3318989327
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.2645931852
Short name T84
Test name
Test status
Simulation time 239534619 ps
CPU time 1.63 seconds
Started Sep 09 11:30:03 AM UTC 24
Finished Sep 09 11:30:05 AM UTC 24
Peak memory 225932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645931852 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.2645931852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.1989546213
Short name T164
Test name
Test status
Simulation time 3110824609 ps
CPU time 41.74 seconds
Started Sep 09 11:29:57 AM UTC 24
Finished Sep 09 11:30:40 AM UTC 24
Peak memory 226740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989546213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1989546213
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.311657896
Short name T449
Test name
Test status
Simulation time 4096345320 ps
CPU time 14.73 seconds
Started Sep 09 11:29:55 AM UTC 24
Finished Sep 09 11:30:11 AM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311657896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.311657896
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.4149078647
Short name T412
Test name
Test status
Simulation time 996302135 ps
CPU time 7.72 seconds
Started Sep 09 11:29:57 AM UTC 24
Finished Sep 09 11:30:05 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149078647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4149078647
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2111372823
Short name T74
Test name
Test status
Simulation time 14691957 ps
CPU time 1.13 seconds
Started Sep 09 11:29:57 AM UTC 24
Finished Sep 09 11:29:59 AM UTC 24
Peak memory 214256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111372823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2111372823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.1274553962
Short name T208
Test name
Test status
Simulation time 445452267 ps
CPU time 4.88 seconds
Started Sep 09 11:29:58 AM UTC 24
Finished Sep 09 11:30:04 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274553962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1274553962
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3082008031
Short name T451
Test name
Test status
Simulation time 34140997 ps
CPU time 1.11 seconds
Started Sep 09 11:30:10 AM UTC 24
Finished Sep 09 11:30:13 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082008031 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3082008031
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1275363642
Short name T302
Test name
Test status
Simulation time 163650159 ps
CPU time 4.2 seconds
Started Sep 09 11:30:07 AM UTC 24
Finished Sep 09 11:30:13 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275363642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1275363642
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.3283995250
Short name T444
Test name
Test status
Simulation time 71044198 ps
CPU time 1.18 seconds
Started Sep 09 11:30:04 AM UTC 24
Finished Sep 09 11:30:06 AM UTC 24
Peak memory 215636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283995250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3283995250
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.2767936188
Short name T360
Test name
Test status
Simulation time 144019425354 ps
CPU time 489.87 seconds
Started Sep 09 11:30:09 AM UTC 24
Finished Sep 09 11:38:25 AM UTC 24
Peak memory 284344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767936188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2767936188
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3438774036
Short name T295
Test name
Test status
Simulation time 12405028788 ps
CPU time 103.54 seconds
Started Sep 09 11:30:09 AM UTC 24
Finished Sep 09 11:31:55 AM UTC 24
Peak memory 251500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438774036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3438774036
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1524024388
Short name T215
Test name
Test status
Simulation time 10666834948 ps
CPU time 20.05 seconds
Started Sep 09 11:30:08 AM UTC 24
Finished Sep 09 11:30:30 AM UTC 24
Peak memory 245344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524024388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.1524024388
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2275706898
Short name T163
Test name
Test status
Simulation time 8137295041 ps
CPU time 30.76 seconds
Started Sep 09 11:30:07 AM UTC 24
Finished Sep 09 11:30:40 AM UTC 24
Peak memory 235108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275706898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2275706898
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2447600614
Short name T275
Test name
Test status
Simulation time 25937900198 ps
CPU time 52.53 seconds
Started Sep 09 11:30:07 AM UTC 24
Finished Sep 09 11:31:01 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447600614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2447600614
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.583109339
Short name T242
Test name
Test status
Simulation time 12715607634 ps
CPU time 17.67 seconds
Started Sep 09 11:30:06 AM UTC 24
Finished Sep 09 11:30:26 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583109339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.583109339
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.656423822
Short name T448
Test name
Test status
Simulation time 158075742 ps
CPU time 2.92 seconds
Started Sep 09 11:30:06 AM UTC 24
Finished Sep 09 11:30:11 AM UTC 24
Peak memory 244896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656423822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.656423822
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1997412206
Short name T454
Test name
Test status
Simulation time 266644128 ps
CPU time 3.45 seconds
Started Sep 09 11:30:09 AM UTC 24
Finished Sep 09 11:30:14 AM UTC 24
Peak memory 231264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997412206 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.1997412206
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.207496028
Short name T257
Test name
Test status
Simulation time 9879645248 ps
CPU time 80.4 seconds
Started Sep 09 11:30:10 AM UTC 24
Finished Sep 09 11:31:33 AM UTC 24
Peak memory 247504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207496028 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.207496028
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.4129763793
Short name T396
Test name
Test status
Simulation time 5655678062 ps
CPU time 27.58 seconds
Started Sep 09 11:30:05 AM UTC 24
Finished Sep 09 11:30:35 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129763793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4129763793
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.4201183533
Short name T455
Test name
Test status
Simulation time 18634997387 ps
CPU time 8.33 seconds
Started Sep 09 11:30:05 AM UTC 24
Finished Sep 09 11:30:15 AM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201183533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4201183533
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2285723304
Short name T446
Test name
Test status
Simulation time 84655815 ps
CPU time 1.23 seconds
Started Sep 09 11:30:05 AM UTC 24
Finished Sep 09 11:30:08 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285723304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2285723304
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1702612812
Short name T445
Test name
Test status
Simulation time 41428986 ps
CPU time 1.1 seconds
Started Sep 09 11:30:05 AM UTC 24
Finished Sep 09 11:30:08 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702612812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1702612812
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2713512305
Short name T450
Test name
Test status
Simulation time 43579785 ps
CPU time 2.91 seconds
Started Sep 09 11:30:07 AM UTC 24
Finished Sep 09 11:30:12 AM UTC 24
Peak memory 244904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713512305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2713512305
Directory /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%