| T841 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3541980015 |
|
|
Sep 09 11:38:49 AM UTC 24 |
Sep 09 11:38:53 AM UTC 24 |
37528528 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2113907949 |
|
|
Sep 09 11:38:43 AM UTC 24 |
Sep 09 11:38:54 AM UTC 24 |
2909701644 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.896901309 |
|
|
Sep 09 11:38:49 AM UTC 24 |
Sep 09 11:38:54 AM UTC 24 |
114968568 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3631129070 |
|
|
Sep 09 11:38:46 AM UTC 24 |
Sep 09 11:38:54 AM UTC 24 |
1113285651 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2141576302 |
|
|
Sep 09 11:38:49 AM UTC 24 |
Sep 09 11:38:54 AM UTC 24 |
67152827 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3779697099 |
|
|
Sep 09 11:38:46 AM UTC 24 |
Sep 09 11:38:54 AM UTC 24 |
812934467 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.3150390576 |
|
|
Sep 09 11:34:41 AM UTC 24 |
Sep 09 11:38:57 AM UTC 24 |
102293930713 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.3413425587 |
|
|
Sep 09 11:38:55 AM UTC 24 |
Sep 09 11:38:57 AM UTC 24 |
68913905 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.3784718340 |
|
|
Sep 09 11:38:55 AM UTC 24 |
Sep 09 11:38:57 AM UTC 24 |
80822130 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.2837956587 |
|
|
Sep 09 11:38:55 AM UTC 24 |
Sep 09 11:38:58 AM UTC 24 |
87221962 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2246154240 |
|
|
Sep 09 11:38:48 AM UTC 24 |
Sep 09 11:38:58 AM UTC 24 |
1418456531 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.744175269 |
|
|
Sep 09 11:38:55 AM UTC 24 |
Sep 09 11:38:58 AM UTC 24 |
499439131 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2564987135 |
|
|
Sep 09 11:38:54 AM UTC 24 |
Sep 09 11:39:01 AM UTC 24 |
475262503 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.820474607 |
|
|
Sep 09 11:38:58 AM UTC 24 |
Sep 09 11:39:01 AM UTC 24 |
116716534 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2018966655 |
|
|
Sep 09 11:38:58 AM UTC 24 |
Sep 09 11:39:02 AM UTC 24 |
394164409 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2219271290 |
|
|
Sep 09 11:38:59 AM UTC 24 |
Sep 09 11:39:02 AM UTC 24 |
101278471 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.2446373003 |
|
|
Sep 09 11:37:17 AM UTC 24 |
Sep 09 11:39:04 AM UTC 24 |
33647653141 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.4119731819 |
|
|
Sep 09 11:38:55 AM UTC 24 |
Sep 09 11:39:07 AM UTC 24 |
5388665661 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2637835034 |
|
|
Sep 09 11:31:38 AM UTC 24 |
Sep 09 11:39:08 AM UTC 24 |
191734108879 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.4185804678 |
|
|
Sep 09 11:34:23 AM UTC 24 |
Sep 09 11:39:08 AM UTC 24 |
22441916290 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.1619244903 |
|
|
Sep 09 11:38:34 AM UTC 24 |
Sep 09 11:39:08 AM UTC 24 |
3295601229 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.2490085612 |
|
|
Sep 09 11:34:36 AM UTC 24 |
Sep 09 11:39:09 AM UTC 24 |
33422856301 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.910575111 |
|
|
Sep 09 11:39:04 AM UTC 24 |
Sep 09 11:39:10 AM UTC 24 |
786300669 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2413935514 |
|
|
Sep 09 11:39:02 AM UTC 24 |
Sep 09 11:39:10 AM UTC 24 |
1865033663 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2237600506 |
|
|
Sep 09 11:39:03 AM UTC 24 |
Sep 09 11:39:11 AM UTC 24 |
180600991 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.1367126692 |
|
|
Sep 09 11:38:38 AM UTC 24 |
Sep 09 11:39:12 AM UTC 24 |
25015403054 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.4001329202 |
|
|
Sep 09 11:39:10 AM UTC 24 |
Sep 09 11:39:12 AM UTC 24 |
20364889 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.1814046683 |
|
|
Sep 09 11:39:10 AM UTC 24 |
Sep 09 11:39:12 AM UTC 24 |
25086121 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.158229076 |
|
|
Sep 09 11:35:50 AM UTC 24 |
Sep 09 11:39:12 AM UTC 24 |
104518484050 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1584585892 |
|
|
Sep 09 11:38:49 AM UTC 24 |
Sep 09 11:39:13 AM UTC 24 |
6106616875 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1191166680 |
|
|
Sep 09 11:38:59 AM UTC 24 |
Sep 09 11:39:13 AM UTC 24 |
5629654286 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.1558419357 |
|
|
Sep 09 11:38:22 AM UTC 24 |
Sep 09 11:39:13 AM UTC 24 |
5073861970 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1774796409 |
|
|
Sep 09 11:39:00 AM UTC 24 |
Sep 09 11:39:14 AM UTC 24 |
1312997705 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.40634748 |
|
|
Sep 09 11:39:12 AM UTC 24 |
Sep 09 11:39:14 AM UTC 24 |
51634306 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1855490782 |
|
|
Sep 09 11:28:56 AM UTC 24 |
Sep 09 11:39:16 AM UTC 24 |
125591959525 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.504760928 |
|
|
Sep 09 11:39:11 AM UTC 24 |
Sep 09 11:39:16 AM UTC 24 |
507285366 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.837617445 |
|
|
Sep 09 11:39:13 AM UTC 24 |
Sep 09 11:39:17 AM UTC 24 |
125504531 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1371163229 |
|
|
Sep 09 11:39:00 AM UTC 24 |
Sep 09 11:39:17 AM UTC 24 |
1533986022 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.4212782881 |
|
|
Sep 09 11:39:13 AM UTC 24 |
Sep 09 11:39:17 AM UTC 24 |
726144549 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.3298890749 |
|
|
Sep 09 11:39:13 AM UTC 24 |
Sep 09 11:39:19 AM UTC 24 |
422111192 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1239486159 |
|
|
Sep 09 11:39:11 AM UTC 24 |
Sep 09 11:39:20 AM UTC 24 |
10295611189 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3694375669 |
|
|
Sep 09 11:39:20 AM UTC 24 |
Sep 09 11:39:22 AM UTC 24 |
13342727 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2196900818 |
|
|
Sep 09 11:39:17 AM UTC 24 |
Sep 09 11:39:22 AM UTC 24 |
370086366 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3381325758 |
|
|
Sep 09 11:39:21 AM UTC 24 |
Sep 09 11:39:23 AM UTC 24 |
38169360 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3319610440 |
|
|
Sep 09 11:39:15 AM UTC 24 |
Sep 09 11:39:25 AM UTC 24 |
873575447 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.1917140394 |
|
|
Sep 09 11:39:15 AM UTC 24 |
Sep 09 11:39:25 AM UTC 24 |
1778145897 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.4205417926 |
|
|
Sep 09 11:39:17 AM UTC 24 |
Sep 09 11:39:26 AM UTC 24 |
2213293822 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.806728813 |
|
|
Sep 09 11:39:24 AM UTC 24 |
Sep 09 11:39:26 AM UTC 24 |
13135710 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1681028927 |
|
|
Sep 09 11:36:05 AM UTC 24 |
Sep 09 11:39:26 AM UTC 24 |
140049888328 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.4268585622 |
|
|
Sep 09 11:32:46 AM UTC 24 |
Sep 09 11:39:28 AM UTC 24 |
289401810855 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.1730815121 |
|
|
Sep 09 11:39:27 AM UTC 24 |
Sep 09 11:39:29 AM UTC 24 |
20992361 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2975452706 |
|
|
Sep 09 11:39:23 AM UTC 24 |
Sep 09 11:39:30 AM UTC 24 |
2296559133 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.39096716 |
|
|
Sep 09 11:39:13 AM UTC 24 |
Sep 09 11:39:30 AM UTC 24 |
5677533030 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1119729848 |
|
|
Sep 09 11:39:03 AM UTC 24 |
Sep 09 11:39:33 AM UTC 24 |
3963631876 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.2198183853 |
|
|
Sep 09 11:39:27 AM UTC 24 |
Sep 09 11:39:35 AM UTC 24 |
463115871 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.562974896 |
|
|
Sep 09 11:39:27 AM UTC 24 |
Sep 09 11:39:35 AM UTC 24 |
2269178237 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.4044271853 |
|
|
Sep 09 11:39:31 AM UTC 24 |
Sep 09 11:39:37 AM UTC 24 |
183771962 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2827550232 |
|
|
Sep 09 11:38:54 AM UTC 24 |
Sep 09 11:39:39 AM UTC 24 |
5808903793 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2426226209 |
|
|
Sep 09 11:39:28 AM UTC 24 |
Sep 09 11:39:39 AM UTC 24 |
3332592723 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.450341929 |
|
|
Sep 09 11:39:15 AM UTC 24 |
Sep 09 11:39:40 AM UTC 24 |
5435033018 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1687873379 |
|
|
Sep 09 11:38:40 AM UTC 24 |
Sep 09 11:39:42 AM UTC 24 |
4968472154 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.1122280018 |
|
|
Sep 09 11:39:40 AM UTC 24 |
Sep 09 11:39:42 AM UTC 24 |
12631013 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.3403870646 |
|
|
Sep 09 11:39:41 AM UTC 24 |
Sep 09 11:39:43 AM UTC 24 |
17315153 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.841676077 |
|
|
Sep 09 11:39:29 AM UTC 24 |
Sep 09 11:39:44 AM UTC 24 |
4373185071 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3163130678 |
|
|
Sep 09 11:39:29 AM UTC 24 |
Sep 09 11:39:44 AM UTC 24 |
5367969076 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.487548739 |
|
|
Sep 09 11:38:52 AM UTC 24 |
Sep 09 11:39:45 AM UTC 24 |
3305751021 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.1633563078 |
|
|
Sep 09 11:39:23 AM UTC 24 |
Sep 09 11:39:46 AM UTC 24 |
9497428275 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.677430198 |
|
|
Sep 09 11:39:34 AM UTC 24 |
Sep 09 11:39:46 AM UTC 24 |
2013593084 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1671226608 |
|
|
Sep 09 11:39:45 AM UTC 24 |
Sep 09 11:39:47 AM UTC 24 |
323644894 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3454585518 |
|
|
Sep 09 11:39:42 AM UTC 24 |
Sep 09 11:39:48 AM UTC 24 |
1338087269 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.4289818215 |
|
|
Sep 09 11:39:45 AM UTC 24 |
Sep 09 11:39:48 AM UTC 24 |
204433058 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1277421641 |
|
|
Sep 09 11:39:45 AM UTC 24 |
Sep 09 11:39:49 AM UTC 24 |
111134245 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3961418717 |
|
|
Sep 09 11:37:49 AM UTC 24 |
Sep 09 11:39:50 AM UTC 24 |
38814894723 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.156808020 |
|
|
Sep 09 11:37:29 AM UTC 24 |
Sep 09 11:39:50 AM UTC 24 |
16065688787 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3825566951 |
|
|
Sep 09 11:39:36 AM UTC 24 |
Sep 09 11:39:51 AM UTC 24 |
9031730494 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2103058618 |
|
|
Sep 09 11:37:21 AM UTC 24 |
Sep 09 11:39:51 AM UTC 24 |
83335423163 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.403905402 |
|
|
Sep 09 11:39:46 AM UTC 24 |
Sep 09 11:39:52 AM UTC 24 |
322888021 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3415757524 |
|
|
Sep 09 11:38:05 AM UTC 24 |
Sep 09 11:39:52 AM UTC 24 |
196390646315 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.401872875 |
|
|
Sep 09 11:39:46 AM UTC 24 |
Sep 09 11:39:52 AM UTC 24 |
115522850 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.3564227254 |
|
|
Sep 09 11:39:50 AM UTC 24 |
Sep 09 11:39:53 AM UTC 24 |
48225314 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.282230195 |
|
|
Sep 09 11:39:49 AM UTC 24 |
Sep 09 11:39:53 AM UTC 24 |
143963058 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1832741065 |
|
|
Sep 09 11:30:01 AM UTC 24 |
Sep 09 11:39:54 AM UTC 24 |
85739311113 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2457576824 |
|
|
Sep 09 11:39:53 AM UTC 24 |
Sep 09 11:39:55 AM UTC 24 |
78421950 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3331519249 |
|
|
Sep 09 11:39:53 AM UTC 24 |
Sep 09 11:39:55 AM UTC 24 |
28355149 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1539835230 |
|
|
Sep 09 11:37:49 AM UTC 24 |
Sep 09 11:39:56 AM UTC 24 |
56391370980 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.485384020 |
|
|
Sep 09 11:37:07 AM UTC 24 |
Sep 09 11:39:57 AM UTC 24 |
25948632774 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.2134270146 |
|
|
Sep 09 11:39:55 AM UTC 24 |
Sep 09 11:39:57 AM UTC 24 |
30379876 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2576945175 |
|
|
Sep 09 11:38:54 AM UTC 24 |
Sep 09 11:39:57 AM UTC 24 |
11948358980 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.163557477 |
|
|
Sep 09 11:39:53 AM UTC 24 |
Sep 09 11:39:57 AM UTC 24 |
693310392 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.2668051155 |
|
|
Sep 09 11:39:49 AM UTC 24 |
Sep 09 11:39:58 AM UTC 24 |
1023694702 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2585286403 |
|
|
Sep 09 11:39:27 AM UTC 24 |
Sep 09 11:39:58 AM UTC 24 |
9802499495 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.3596162483 |
|
|
Sep 09 11:39:49 AM UTC 24 |
Sep 09 11:40:02 AM UTC 24 |
784733989 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3227308758 |
|
|
Sep 09 11:39:58 AM UTC 24 |
Sep 09 11:40:02 AM UTC 24 |
130778290 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.2536293853 |
|
|
Sep 09 11:39:56 AM UTC 24 |
Sep 09 11:40:02 AM UTC 24 |
149900282 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.2966336073 |
|
|
Sep 09 11:39:58 AM UTC 24 |
Sep 09 11:40:03 AM UTC 24 |
614759920 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2941383676 |
|
|
Sep 09 11:39:47 AM UTC 24 |
Sep 09 11:40:04 AM UTC 24 |
670733016 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2444283251 |
|
|
Sep 09 11:39:50 AM UTC 24 |
Sep 09 11:40:04 AM UTC 24 |
4096207885 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3127330394 |
|
|
Sep 09 11:39:58 AM UTC 24 |
Sep 09 11:40:05 AM UTC 24 |
803551792 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.4069213432 |
|
|
Sep 09 11:40:06 AM UTC 24 |
Sep 09 11:40:08 AM UTC 24 |
39007261 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.3232017235 |
|
|
Sep 09 11:40:06 AM UTC 24 |
Sep 09 11:40:08 AM UTC 24 |
104802247 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1575124521 |
|
|
Sep 09 11:38:05 AM UTC 24 |
Sep 09 11:40:08 AM UTC 24 |
4215097968 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1794015730 |
|
|
Sep 09 11:40:06 AM UTC 24 |
Sep 09 11:40:08 AM UTC 24 |
81886959 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.679493992 |
|
|
Sep 09 11:39:53 AM UTC 24 |
Sep 09 11:40:11 AM UTC 24 |
22092440527 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2108402191 |
|
|
Sep 09 11:39:56 AM UTC 24 |
Sep 09 11:40:12 AM UTC 24 |
11767348720 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1382489385 |
|
|
Sep 09 11:40:10 AM UTC 24 |
Sep 09 11:40:12 AM UTC 24 |
305578490 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3095063348 |
|
|
Sep 09 11:40:00 AM UTC 24 |
Sep 09 11:40:13 AM UTC 24 |
265663829 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.2672431690 |
|
|
Sep 09 11:39:58 AM UTC 24 |
Sep 09 11:40:14 AM UTC 24 |
18606134630 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.1057782810 |
|
|
Sep 09 11:40:10 AM UTC 24 |
Sep 09 11:40:14 AM UTC 24 |
154426989 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3350123564 |
|
|
Sep 09 11:40:10 AM UTC 24 |
Sep 09 11:40:14 AM UTC 24 |
165987438 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.715451751 |
|
|
Sep 09 11:39:07 AM UTC 24 |
Sep 09 11:40:15 AM UTC 24 |
2428740565 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.499657808 |
|
|
Sep 09 11:37:29 AM UTC 24 |
Sep 09 11:40:15 AM UTC 24 |
15925236391 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.4076410627 |
|
|
Sep 09 11:40:00 AM UTC 24 |
Sep 09 11:40:15 AM UTC 24 |
1296638326 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2342116842 |
|
|
Sep 09 11:40:04 AM UTC 24 |
Sep 09 11:40:16 AM UTC 24 |
708465944 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1944591728 |
|
|
Sep 09 11:40:14 AM UTC 24 |
Sep 09 11:40:17 AM UTC 24 |
131793749 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.801717687 |
|
|
Sep 09 11:40:10 AM UTC 24 |
Sep 09 11:40:19 AM UTC 24 |
798714629 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.635871493 |
|
|
Sep 09 11:39:15 AM UTC 24 |
Sep 09 11:40:20 AM UTC 24 |
19818982052 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.1613142887 |
|
|
Sep 09 11:40:16 AM UTC 24 |
Sep 09 11:40:20 AM UTC 24 |
79496869 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3251044044 |
|
|
Sep 09 11:40:20 AM UTC 24 |
Sep 09 11:40:22 AM UTC 24 |
211238854 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1725719458 |
|
|
Sep 09 11:40:13 AM UTC 24 |
Sep 09 11:40:22 AM UTC 24 |
2045483396 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3889108580 |
|
|
Sep 09 11:40:21 AM UTC 24 |
Sep 09 11:40:23 AM UTC 24 |
38348102 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3529184005 |
|
|
Sep 09 11:40:21 AM UTC 24 |
Sep 09 11:40:23 AM UTC 24 |
15219420 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.260109491 |
|
|
Sep 09 11:40:24 AM UTC 24 |
Sep 09 11:40:27 AM UTC 24 |
81801910 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.741067273 |
|
|
Sep 09 11:40:14 AM UTC 24 |
Sep 09 11:40:29 AM UTC 24 |
752970226 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2993561479 |
|
|
Sep 09 11:39:18 AM UTC 24 |
Sep 09 11:40:30 AM UTC 24 |
2757453307 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1358703706 |
|
|
Sep 09 11:38:54 AM UTC 24 |
Sep 09 11:40:30 AM UTC 24 |
13571003716 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2241464937 |
|
|
Sep 09 11:40:16 AM UTC 24 |
Sep 09 11:40:30 AM UTC 24 |
8194937786 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.680737464 |
|
|
Sep 09 11:39:50 AM UTC 24 |
Sep 09 11:40:31 AM UTC 24 |
5319913010 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.429525305 |
|
|
Sep 09 11:40:27 AM UTC 24 |
Sep 09 11:40:32 AM UTC 24 |
78232006 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2587501747 |
|
|
Sep 09 11:40:18 AM UTC 24 |
Sep 09 11:40:34 AM UTC 24 |
12669442242 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2358425669 |
|
|
Sep 09 11:40:24 AM UTC 24 |
Sep 09 11:40:34 AM UTC 24 |
5793066694 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.4276022854 |
|
|
Sep 09 11:40:24 AM UTC 24 |
Sep 09 11:40:35 AM UTC 24 |
540379623 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3789331790 |
|
|
Sep 09 11:36:23 AM UTC 24 |
Sep 09 11:40:36 AM UTC 24 |
21346714136 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1562327426 |
|
|
Sep 09 11:40:24 AM UTC 24 |
Sep 09 11:40:37 AM UTC 24 |
896460408 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1202092329 |
|
|
Sep 09 11:40:31 AM UTC 24 |
Sep 09 11:40:37 AM UTC 24 |
282945170 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1187034855 |
|
|
Sep 09 11:40:33 AM UTC 24 |
Sep 09 11:40:38 AM UTC 24 |
43894716 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3268994682 |
|
|
Sep 09 11:39:58 AM UTC 24 |
Sep 09 11:40:38 AM UTC 24 |
29952417421 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.3980908201 |
|
|
Sep 09 11:40:18 AM UTC 24 |
Sep 09 11:40:40 AM UTC 24 |
1317157322 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1856406994 |
|
|
Sep 09 11:35:51 AM UTC 24 |
Sep 09 11:40:40 AM UTC 24 |
139551806751 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.2874209606 |
|
|
Sep 09 11:40:39 AM UTC 24 |
Sep 09 11:40:41 AM UTC 24 |
37178914 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.378230609 |
|
|
Sep 09 11:39:16 AM UTC 24 |
Sep 09 11:40:42 AM UTC 24 |
31924106253 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2078184352 |
|
|
Sep 09 11:40:16 AM UTC 24 |
Sep 09 11:40:42 AM UTC 24 |
5864359831 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2673882273 |
|
|
Sep 09 11:39:36 AM UTC 24 |
Sep 09 11:40:43 AM UTC 24 |
29586108533 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.3029890301 |
|
|
Sep 09 11:39:42 AM UTC 24 |
Sep 09 11:40:43 AM UTC 24 |
9921481488 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.46552781 |
|
|
Sep 09 11:40:32 AM UTC 24 |
Sep 09 11:40:43 AM UTC 24 |
1128470761 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1283011924 |
|
|
Sep 09 11:40:35 AM UTC 24 |
Sep 09 11:40:44 AM UTC 24 |
2722855217 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.3902392237 |
|
|
Sep 09 11:40:30 AM UTC 24 |
Sep 09 11:40:44 AM UTC 24 |
4459482514 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3914986585 |
|
|
Sep 09 11:38:40 AM UTC 24 |
Sep 09 11:40:46 AM UTC 24 |
14854257567 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3971669236 |
|
|
Sep 09 11:36:17 AM UTC 24 |
Sep 09 11:40:48 AM UTC 24 |
31723295128 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.530891264 |
|
|
Sep 09 11:39:17 AM UTC 24 |
Sep 09 11:40:50 AM UTC 24 |
8320022771 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.3382301792 |
|
|
Sep 09 11:33:20 AM UTC 24 |
Sep 09 11:40:56 AM UTC 24 |
197821638303 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4238356892 |
|
|
Sep 09 11:39:18 AM UTC 24 |
Sep 09 11:40:56 AM UTC 24 |
10978935684 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2677300876 |
|
|
Sep 09 11:31:54 AM UTC 24 |
Sep 09 11:40:59 AM UTC 24 |
228604509622 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.546169618 |
|
|
Sep 09 11:40:11 AM UTC 24 |
Sep 09 11:41:00 AM UTC 24 |
114703935659 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.636110064 |
|
|
Sep 09 11:40:16 AM UTC 24 |
Sep 09 11:41:06 AM UTC 24 |
10508535584 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2925299067 |
|
|
Sep 09 11:40:32 AM UTC 24 |
Sep 09 11:41:12 AM UTC 24 |
3654769362 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.146426022 |
|
|
Sep 09 11:40:04 AM UTC 24 |
Sep 09 11:41:20 AM UTC 24 |
47476821881 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1056070237 |
|
|
Sep 09 11:39:53 AM UTC 24 |
Sep 09 11:41:23 AM UTC 24 |
4513530706 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.2580485074 |
|
|
Sep 09 11:40:04 AM UTC 24 |
Sep 09 11:41:25 AM UTC 24 |
10081087875 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3296447324 |
|
|
Sep 09 11:39:52 AM UTC 24 |
Sep 09 11:41:31 AM UTC 24 |
6203100485 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3761327624 |
|
|
Sep 09 11:36:05 AM UTC 24 |
Sep 09 11:41:33 AM UTC 24 |
156029115903 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.2410081055 |
|
|
Sep 09 11:37:48 AM UTC 24 |
Sep 09 11:41:38 AM UTC 24 |
109431575796 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.2928628502 |
|
|
Sep 09 11:40:33 AM UTC 24 |
Sep 09 11:41:42 AM UTC 24 |
4310034808 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.2636454074 |
|
|
Sep 09 11:40:36 AM UTC 24 |
Sep 09 11:41:44 AM UTC 24 |
6022441987 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2371599044 |
|
|
Sep 09 11:39:38 AM UTC 24 |
Sep 09 11:41:49 AM UTC 24 |
8271825250 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1085451163 |
|
|
Sep 09 11:40:39 AM UTC 24 |
Sep 09 11:41:50 AM UTC 24 |
4970492454 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2063382618 |
|
|
Sep 09 11:35:08 AM UTC 24 |
Sep 09 11:41:56 AM UTC 24 |
84439087689 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2310952575 |
|
|
Sep 09 11:34:40 AM UTC 24 |
Sep 09 11:42:36 AM UTC 24 |
286402632852 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2267709012 |
|
|
Sep 09 11:38:35 AM UTC 24 |
Sep 09 11:42:39 AM UTC 24 |
136664206793 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.236309653 |
|
|
Sep 09 11:34:07 AM UTC 24 |
Sep 09 11:42:43 AM UTC 24 |
106687307464 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3607263652 |
|
|
Sep 09 11:40:35 AM UTC 24 |
Sep 09 11:42:44 AM UTC 24 |
161007015469 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.291009380 |
|
|
Sep 09 11:40:37 AM UTC 24 |
Sep 09 11:42:54 AM UTC 24 |
31773490697 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.1293292818 |
|
|
Sep 09 11:39:08 AM UTC 24 |
Sep 09 11:42:55 AM UTC 24 |
50785415916 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1634099458 |
|
|
Sep 09 11:36:45 AM UTC 24 |
Sep 09 11:43:04 AM UTC 24 |
179136339707 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2951752032 |
|
|
Sep 09 11:33:04 AM UTC 24 |
Sep 09 11:43:08 AM UTC 24 |
102252582866 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2402539065 |
|
|
Sep 09 11:32:39 AM UTC 24 |
Sep 09 11:43:16 AM UTC 24 |
60997362430 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1513194625 |
|
|
Sep 09 11:37:03 AM UTC 24 |
Sep 09 11:43:20 AM UTC 24 |
48500685947 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.784181732 |
|
|
Sep 09 11:35:32 AM UTC 24 |
Sep 09 11:43:55 AM UTC 24 |
114515945418 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1101142696 |
|
|
Sep 09 11:40:37 AM UTC 24 |
Sep 09 11:44:03 AM UTC 24 |
19814992130 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.322886628 |
|
|
Sep 09 11:39:08 AM UTC 24 |
Sep 09 11:44:07 AM UTC 24 |
133474666815 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3003815556 |
|
|
Sep 09 11:39:31 AM UTC 24 |
Sep 09 11:44:15 AM UTC 24 |
36425966139 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1347014757 |
|
|
Sep 09 11:37:50 AM UTC 24 |
Sep 09 11:44:16 AM UTC 24 |
38849154048 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.3548432485 |
|
|
Sep 09 11:35:53 AM UTC 24 |
Sep 09 11:44:27 AM UTC 24 |
218387461955 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.9982429 |
|
|
Sep 09 11:40:04 AM UTC 24 |
Sep 09 11:44:52 AM UTC 24 |
105453759737 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.3563246536 |
|
|
Sep 09 11:35:49 AM UTC 24 |
Sep 09 11:45:03 AM UTC 24 |
324307057560 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2780641651 |
|
|
Sep 09 11:39:52 AM UTC 24 |
Sep 09 11:45:32 AM UTC 24 |
184980504102 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3250583967 |
|
|
Sep 09 11:38:24 AM UTC 24 |
Sep 09 11:46:26 AM UTC 24 |
48404587418 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.723687992 |
|
|
Sep 09 11:38:24 AM UTC 24 |
Sep 09 11:46:37 AM UTC 24 |
318673128129 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2623801810 |
|
|
Sep 09 11:37:28 AM UTC 24 |
Sep 09 11:47:13 AM UTC 24 |
742306044203 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.712067566 |
|
|
Sep 09 11:40:18 AM UTC 24 |
Sep 09 11:47:17 AM UTC 24 |
204287300611 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.3824334999 |
|
|
Sep 09 11:34:08 AM UTC 24 |
Sep 09 11:47:45 AM UTC 24 |
333589167770 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3723973380 |
|
|
Sep 09 11:40:18 AM UTC 24 |
Sep 09 11:48:38 AM UTC 24 |
170433493595 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.4288778396 |
|
|
Sep 09 11:39:09 AM UTC 24 |
Sep 09 11:48:46 AM UTC 24 |
248325973699 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.1605086434 |
|
|
Sep 09 11:37:09 AM UTC 24 |
Sep 09 11:48:59 AM UTC 24 |
235051914957 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.2375145140 |
|
|
Sep 09 11:38:06 AM UTC 24 |
Sep 09 11:49:26 AM UTC 24 |
634054658897 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.2178297662 |
|
|
Sep 09 11:36:23 AM UTC 24 |
Sep 09 11:51:09 AM UTC 24 |
75525093392 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.263428100 |
|
|
Sep 09 11:39:40 AM UTC 24 |
Sep 09 11:54:43 AM UTC 24 |
75323691741 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.603111045 |
|
|
Sep 09 11:38:23 AM UTC 24 |
Sep 09 11:56:24 AM UTC 24 |
204000673768 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2503004719 |
|
|
Sep 09 10:48:59 AM UTC 24 |
Sep 09 10:49:00 AM UTC 24 |
28722572 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3739683982 |
|
|
Sep 09 10:48:59 AM UTC 24 |
Sep 09 10:49:01 AM UTC 24 |
11887512 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1873175476 |
|
|
Sep 09 10:48:59 AM UTC 24 |
Sep 09 10:49:02 AM UTC 24 |
173970929 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3335116178 |
|
|
Sep 09 10:49:24 AM UTC 24 |
Sep 09 10:49:27 AM UTC 24 |
124188914 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1430992637 |
|
|
Sep 09 10:49:00 AM UTC 24 |
Sep 09 10:49:03 AM UTC 24 |
60842305 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1937758868 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:03 AM UTC 24 |
10682692 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1123695883 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:03 AM UTC 24 |
12808920 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2514785722 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:04 AM UTC 24 |
42330808 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2428826839 |
|
|
Sep 09 10:49:00 AM UTC 24 |
Sep 09 10:49:04 AM UTC 24 |
638556377 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.185168736 |
|
|
Sep 09 10:48:58 AM UTC 24 |
Sep 09 10:49:04 AM UTC 24 |
138550558 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.889748704 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:05 AM UTC 24 |
26742855 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.292897907 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:05 AM UTC 24 |
484034250 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3837358267 |
|
|
Sep 09 10:49:02 AM UTC 24 |
Sep 09 10:49:06 AM UTC 24 |
439197982 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3519520875 |
|
|
Sep 09 10:49:02 AM UTC 24 |
Sep 09 10:49:07 AM UTC 24 |
120201742 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2118864060 |
|
|
Sep 09 10:49:05 AM UTC 24 |
Sep 09 10:49:07 AM UTC 24 |
11518202 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2450017747 |
|
|
Sep 09 10:49:05 AM UTC 24 |
Sep 09 10:49:07 AM UTC 24 |
25764491 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1651078934 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:07 AM UTC 24 |
780327673 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3972424436 |
|
|
Sep 09 10:48:58 AM UTC 24 |
Sep 09 10:49:07 AM UTC 24 |
104177020 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2407254719 |
|
|
Sep 09 10:49:05 AM UTC 24 |
Sep 09 10:49:07 AM UTC 24 |
26267006 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1451159847 |
|
|
Sep 09 10:49:03 AM UTC 24 |
Sep 09 10:49:08 AM UTC 24 |
40011731 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1608805687 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:08 AM UTC 24 |
315877412 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3013986447 |
|
|
Sep 09 10:49:05 AM UTC 24 |
Sep 09 10:49:09 AM UTC 24 |
57888493 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2813833144 |
|
|
Sep 09 10:49:03 AM UTC 24 |
Sep 09 10:49:10 AM UTC 24 |
326054201 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1102189312 |
|
|
Sep 09 10:49:27 AM UTC 24 |
Sep 09 10:49:31 AM UTC 24 |
60195958 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2036431908 |
|
|
Sep 09 10:49:06 AM UTC 24 |
Sep 09 10:49:10 AM UTC 24 |
35948757 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2304516320 |
|
|
Sep 09 10:49:08 AM UTC 24 |
Sep 09 10:49:26 AM UTC 24 |
584018562 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2272392304 |
|
|
Sep 09 10:49:24 AM UTC 24 |
Sep 09 10:49:30 AM UTC 24 |
34050371 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1712502969 |
|
|
Sep 09 10:49:07 AM UTC 24 |
Sep 09 10:49:10 AM UTC 24 |
93861252 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.674158025 |
|
|
Sep 09 10:49:08 AM UTC 24 |
Sep 09 10:49:10 AM UTC 24 |
37657819 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2323324915 |
|
|
Sep 09 10:49:09 AM UTC 24 |
Sep 09 10:49:11 AM UTC 24 |
12804950 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1013908181 |
|
|
Sep 09 10:49:09 AM UTC 24 |
Sep 09 10:49:11 AM UTC 24 |
144976201 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.759641298 |
|
|
Sep 09 10:49:09 AM UTC 24 |
Sep 09 10:49:12 AM UTC 24 |
51808996 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1622173307 |
|
|
Sep 09 10:49:08 AM UTC 24 |
Sep 09 10:49:13 AM UTC 24 |
331722777 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.285538837 |
|
|
Sep 09 10:49:09 AM UTC 24 |
Sep 09 10:49:13 AM UTC 24 |
415313439 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3160085894 |
|
|
Sep 09 10:49:07 AM UTC 24 |
Sep 09 10:49:14 AM UTC 24 |
104632544 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1318629083 |
|
|
Sep 09 10:49:11 AM UTC 24 |
Sep 09 10:49:14 AM UTC 24 |
85978611 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3156500845 |
|
|
Sep 09 10:49:02 AM UTC 24 |
Sep 09 10:49:14 AM UTC 24 |
487684751 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.1030103400 |
|
|
Sep 09 10:49:12 AM UTC 24 |
Sep 09 10:49:14 AM UTC 24 |
49584240 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.300566253 |
|
|
Sep 09 10:49:12 AM UTC 24 |
Sep 09 10:49:14 AM UTC 24 |
12237734 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2864249746 |
|
|
Sep 09 10:49:11 AM UTC 24 |
Sep 09 10:49:15 AM UTC 24 |
54977712 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1307958225 |
|
|
Sep 09 10:49:12 AM UTC 24 |
Sep 09 10:49:15 AM UTC 24 |
33722152 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.161285689 |
|
|
Sep 09 10:49:14 AM UTC 24 |
Sep 09 10:49:16 AM UTC 24 |
23557058 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2608331263 |
|
|
Sep 09 10:49:14 AM UTC 24 |
Sep 09 10:49:16 AM UTC 24 |
152363469 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2740075768 |
|
|
Sep 09 10:49:11 AM UTC 24 |
Sep 09 10:49:17 AM UTC 24 |
615053600 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3772234474 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:17 AM UTC 24 |
2102532083 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.4127736412 |
|
|
Sep 09 10:49:01 AM UTC 24 |
Sep 09 10:49:18 AM UTC 24 |
205154160 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3517319734 |
|
|
Sep 09 10:49:16 AM UTC 24 |
Sep 09 10:49:18 AM UTC 24 |
20028478 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.4132521253 |
|
|
Sep 09 10:49:16 AM UTC 24 |
Sep 09 10:49:20 AM UTC 24 |
69493569 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.370191558 |
|
|
Sep 09 10:49:15 AM UTC 24 |
Sep 09 10:49:20 AM UTC 24 |
254487740 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.836283313 |
|
|
Sep 09 10:49:17 AM UTC 24 |
Sep 09 10:49:20 AM UTC 24 |
96711586 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3748928735 |
|
|
Sep 09 10:49:15 AM UTC 24 |
Sep 09 10:49:20 AM UTC 24 |
74438902 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.764811426 |
|
|
Sep 09 10:49:11 AM UTC 24 |
Sep 09 10:49:21 AM UTC 24 |
224482723 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1057793159 |
|
|
Sep 09 10:49:15 AM UTC 24 |
Sep 09 10:49:21 AM UTC 24 |
900740405 ps |