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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T828 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.3751552418 Sep 11 12:54:11 PM UTC 24 Sep 11 12:54:16 PM UTC 24 982251646 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.3798902675 Sep 11 12:53:32 PM UTC 24 Sep 11 12:54:16 PM UTC 24 22430175449 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.249632894 Sep 11 12:54:15 PM UTC 24 Sep 11 12:54:17 PM UTC 24 10693285 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1993339117 Sep 11 12:54:13 PM UTC 24 Sep 11 12:54:18 PM UTC 24 1183337162 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2094363111 Sep 11 12:54:15 PM UTC 24 Sep 11 12:54:20 PM UTC 24 773044125 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1450976355 Sep 11 12:54:13 PM UTC 24 Sep 11 12:54:24 PM UTC 24 7062778353 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.957167866 Sep 11 12:54:15 PM UTC 24 Sep 11 12:54:24 PM UTC 24 978822135 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.3222177293 Sep 11 12:54:22 PM UTC 24 Sep 11 12:54:24 PM UTC 24 591421095 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.268473614 Sep 11 12:50:37 PM UTC 24 Sep 11 12:54:25 PM UTC 24 115269601826 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.1387856587 Sep 11 12:54:16 PM UTC 24 Sep 11 12:54:27 PM UTC 24 795493688 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2427383614 Sep 11 12:54:25 PM UTC 24 Sep 11 12:54:28 PM UTC 24 30590461 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2490590793 Sep 11 12:54:26 PM UTC 24 Sep 11 12:54:28 PM UTC 24 45146594 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.1031757122 Sep 11 12:53:42 PM UTC 24 Sep 11 12:54:28 PM UTC 24 69460442721 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.2784251208 Sep 11 12:54:15 PM UTC 24 Sep 11 12:54:29 PM UTC 24 7677669592 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1566692778 Sep 11 12:54:27 PM UTC 24 Sep 11 12:54:30 PM UTC 24 55965381 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2108254064 Sep 11 12:53:58 PM UTC 24 Sep 11 12:54:30 PM UTC 24 2732883372 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.4010246418 Sep 11 12:54:29 PM UTC 24 Sep 11 12:54:31 PM UTC 24 24264120 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.666381941 Sep 11 12:53:46 PM UTC 24 Sep 11 12:54:32 PM UTC 24 4624671425 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3742107016 Sep 11 12:52:41 PM UTC 24 Sep 11 12:54:34 PM UTC 24 7035314123 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.2121567824 Sep 11 12:53:48 PM UTC 24 Sep 11 12:54:34 PM UTC 24 1956107866 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2448119649 Sep 11 12:54:26 PM UTC 24 Sep 11 12:54:34 PM UTC 24 4443251845 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.841199061 Sep 11 12:54:13 PM UTC 24 Sep 11 12:54:34 PM UTC 24 3421765401 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.1821931671 Sep 11 12:54:31 PM UTC 24 Sep 11 12:54:35 PM UTC 24 825437975 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.563573343 Sep 11 12:54:31 PM UTC 24 Sep 11 12:54:35 PM UTC 24 27816350 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2624780703 Sep 11 12:54:31 PM UTC 24 Sep 11 12:54:35 PM UTC 24 313811673 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3108665931 Sep 11 12:54:31 PM UTC 24 Sep 11 12:54:37 PM UTC 24 1093231836 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.905141054 Sep 11 12:54:37 PM UTC 24 Sep 11 12:54:39 PM UTC 24 13876806 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1073895000 Sep 11 12:54:37 PM UTC 24 Sep 11 12:54:39 PM UTC 24 34270452 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2684770383 Sep 11 12:54:33 PM UTC 24 Sep 11 12:54:41 PM UTC 24 177886317 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2725935046 Sep 11 12:54:39 PM UTC 24 Sep 11 12:54:41 PM UTC 24 116876747 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2982630827 Sep 11 12:54:29 PM UTC 24 Sep 11 12:54:42 PM UTC 24 2156061194 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2923821121 Sep 11 12:52:14 PM UTC 24 Sep 11 12:54:42 PM UTC 24 61138623847 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2231376462 Sep 11 12:54:29 PM UTC 24 Sep 11 12:54:47 PM UTC 24 15196790538 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2529913633 Sep 11 12:54:40 PM UTC 24 Sep 11 12:54:47 PM UTC 24 1747069702 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.4013577217 Sep 11 12:54:37 PM UTC 24 Sep 11 12:54:48 PM UTC 24 673678372 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3163606959 Sep 11 12:53:22 PM UTC 24 Sep 11 12:54:48 PM UTC 24 83809318132 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.2141469114 Sep 11 12:54:42 PM UTC 24 Sep 11 12:54:51 PM UTC 24 476638711 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2173124736 Sep 11 12:51:55 PM UTC 24 Sep 11 12:54:51 PM UTC 24 30911097377 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.3380269863 Sep 11 12:54:48 PM UTC 24 Sep 11 12:54:54 PM UTC 24 515976751 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3326748001 Sep 11 12:54:50 PM UTC 24 Sep 11 12:54:55 PM UTC 24 112691356 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.2370087685 Sep 11 12:54:37 PM UTC 24 Sep 11 12:54:57 PM UTC 24 4279610799 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3152195720 Sep 11 12:52:41 PM UTC 24 Sep 11 12:54:57 PM UTC 24 49697488260 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.3910884680 Sep 11 12:54:56 PM UTC 24 Sep 11 12:54:58 PM UTC 24 12942471 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1604450759 Sep 11 12:54:43 PM UTC 24 Sep 11 12:54:59 PM UTC 24 1833558720 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.2136912020 Sep 11 12:54:27 PM UTC 24 Sep 11 12:54:59 PM UTC 24 2994489743 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.1194153401 Sep 11 12:54:57 PM UTC 24 Sep 11 12:55:00 PM UTC 24 46929883 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.4115748946 Sep 11 12:54:59 PM UTC 24 Sep 11 12:55:01 PM UTC 24 40026418 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3403522576 Sep 11 12:54:40 PM UTC 24 Sep 11 12:55:01 PM UTC 24 27286421498 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2640824800 Sep 11 12:54:07 PM UTC 24 Sep 11 12:55:02 PM UTC 24 6312026554 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.2664313403 Sep 11 12:55:01 PM UTC 24 Sep 11 12:55:03 PM UTC 24 34905328 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2457553500 Sep 11 12:54:43 PM UTC 24 Sep 11 12:55:04 PM UTC 24 4019849005 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.318435750 Sep 11 12:55:01 PM UTC 24 Sep 11 12:55:04 PM UTC 24 89326851 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3669540494 Sep 11 12:54:42 PM UTC 24 Sep 11 12:55:05 PM UTC 24 3139329919 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.2877703958 Sep 11 12:55:01 PM UTC 24 Sep 11 12:55:09 PM UTC 24 389082374 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.172871663 Sep 11 12:55:03 PM UTC 24 Sep 11 12:55:11 PM UTC 24 552753859 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.444413826 Sep 11 12:55:03 PM UTC 24 Sep 11 12:55:11 PM UTC 24 1746551177 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2845941132 Sep 11 12:55:04 PM UTC 24 Sep 11 12:55:13 PM UTC 24 384064617 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.4229680639 Sep 11 12:55:06 PM UTC 24 Sep 11 12:55:14 PM UTC 24 591022100 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1406330621 Sep 11 12:54:18 PM UTC 24 Sep 11 12:55:14 PM UTC 24 4129122292 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3948127599 Sep 11 12:54:52 PM UTC 24 Sep 11 12:55:14 PM UTC 24 5206795442 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.4013065745 Sep 11 12:54:37 PM UTC 24 Sep 11 12:55:16 PM UTC 24 2731521167 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.582121714 Sep 11 12:55:07 PM UTC 24 Sep 11 12:55:17 PM UTC 24 2527601643 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3493424603 Sep 11 12:55:15 PM UTC 24 Sep 11 12:55:18 PM UTC 24 11200277 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3086325120 Sep 11 12:55:15 PM UTC 24 Sep 11 12:55:18 PM UTC 24 44390023 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2118120268 Sep 11 12:55:17 PM UTC 24 Sep 11 12:55:19 PM UTC 24 62399448 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1670172646 Sep 11 12:55:15 PM UTC 24 Sep 11 12:55:20 PM UTC 24 296249162 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3097287928 Sep 11 12:54:31 PM UTC 24 Sep 11 12:55:20 PM UTC 24 23601012860 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.2465918822 Sep 11 12:55:19 PM UTC 24 Sep 11 12:55:22 PM UTC 24 144253205 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.1339762120 Sep 11 12:54:48 PM UTC 24 Sep 11 12:55:23 PM UTC 24 2185765516 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.232152614 Sep 11 12:55:06 PM UTC 24 Sep 11 12:55:23 PM UTC 24 3611267630 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.480574474 Sep 11 12:49:28 PM UTC 24 Sep 11 12:55:25 PM UTC 24 286196619109 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3705970188 Sep 11 12:55:21 PM UTC 24 Sep 11 12:55:25 PM UTC 24 489087355 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1699674714 Sep 11 12:55:19 PM UTC 24 Sep 11 12:55:27 PM UTC 24 860552890 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.4147219742 Sep 11 12:54:56 PM UTC 24 Sep 11 12:55:30 PM UTC 24 1316988575 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.38816043 Sep 11 12:55:22 PM UTC 24 Sep 11 12:55:31 PM UTC 24 1912956113 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.918239067 Sep 11 12:53:02 PM UTC 24 Sep 11 12:55:31 PM UTC 24 34095464932 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2410203781 Sep 11 12:53:17 PM UTC 24 Sep 11 12:55:32 PM UTC 24 39572137156 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.669850644 Sep 11 12:55:30 PM UTC 24 Sep 11 12:55:33 PM UTC 24 23261127 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.583574910 Sep 11 12:54:59 PM UTC 24 Sep 11 12:55:33 PM UTC 24 4491908675 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.4019902252 Sep 11 12:55:32 PM UTC 24 Sep 11 12:55:34 PM UTC 24 54089081 ps
T901 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1035897518 Sep 11 12:55:07 PM UTC 24 Sep 11 12:55:35 PM UTC 24 3627396879 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1116104215 Sep 11 12:55:23 PM UTC 24 Sep 11 12:55:36 PM UTC 24 313043725 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1502688466 Sep 11 12:55:34 PM UTC 24 Sep 11 12:55:36 PM UTC 24 12509578 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.2918665311 Sep 11 12:45:48 PM UTC 24 Sep 11 12:55:37 PM UTC 24 184181584640 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.959905608 Sep 11 12:54:55 PM UTC 24 Sep 11 12:55:38 PM UTC 24 4649781686 ps
T905 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.124273709 Sep 11 12:55:36 PM UTC 24 Sep 11 12:55:38 PM UTC 24 21147865 ps
T906 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.2653885180 Sep 11 12:55:34 PM UTC 24 Sep 11 12:55:38 PM UTC 24 488819761 ps
T907 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.3094642432 Sep 11 12:55:11 PM UTC 24 Sep 11 12:55:39 PM UTC 24 12829875320 ps
T908 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.3437405003 Sep 11 12:55:04 PM UTC 24 Sep 11 12:55:39 PM UTC 24 5771307180 ps
T909 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1510941714 Sep 11 12:55:25 PM UTC 24 Sep 11 12:55:39 PM UTC 24 1225858626 ps
T910 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3103784296 Sep 11 12:55:36 PM UTC 24 Sep 11 12:55:40 PM UTC 24 57508096 ps
T911 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3238786713 Sep 11 12:55:34 PM UTC 24 Sep 11 12:55:41 PM UTC 24 6665598478 ps
T912 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3957336155 Sep 11 12:55:17 PM UTC 24 Sep 11 12:55:41 PM UTC 24 26804297164 ps
T913 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3028496848 Sep 11 12:55:36 PM UTC 24 Sep 11 12:55:43 PM UTC 24 353928665 ps
T914 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1029196856 Sep 11 12:55:25 PM UTC 24 Sep 11 12:55:43 PM UTC 24 426105034 ps
T915 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3480611874 Sep 11 12:55:40 PM UTC 24 Sep 11 12:55:43 PM UTC 24 106957650 ps
T916 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.4286238330 Sep 11 12:55:42 PM UTC 24 Sep 11 12:55:44 PM UTC 24 51965847 ps
T917 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3534045190 Sep 11 12:54:18 PM UTC 24 Sep 11 12:55:44 PM UTC 24 9229318451 ps
T918 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.3116841485 Sep 11 12:55:38 PM UTC 24 Sep 11 12:55:45 PM UTC 24 2990678673 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.748959177 Sep 11 12:55:19 PM UTC 24 Sep 11 12:55:45 PM UTC 24 9578333922 ps
T919 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.310507526 Sep 11 12:55:40 PM UTC 24 Sep 11 12:55:45 PM UTC 24 862614477 ps
T920 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3060696009 Sep 11 12:55:44 PM UTC 24 Sep 11 12:55:47 PM UTC 24 57464287 ps
T921 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3833974825 Sep 11 12:55:44 PM UTC 24 Sep 11 12:55:47 PM UTC 24 27917217 ps
T922 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.3777203795 Sep 11 12:55:44 PM UTC 24 Sep 11 12:55:47 PM UTC 24 193898069 ps
T923 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3490389704 Sep 11 12:54:33 PM UTC 24 Sep 11 12:55:49 PM UTC 24 12037658165 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3846936449 Sep 11 12:53:44 PM UTC 24 Sep 11 12:55:49 PM UTC 24 58882278107 ps
T924 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.2619168841 Sep 11 12:55:38 PM UTC 24 Sep 11 12:55:50 PM UTC 24 1167900584 ps
T925 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.3397546759 Sep 11 12:55:46 PM UTC 24 Sep 11 12:55:51 PM UTC 24 221605191 ps
T926 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.881070001 Sep 11 12:49:39 PM UTC 24 Sep 11 12:56:34 PM UTC 24 69103181387 ps
T927 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.1923548363 Sep 11 12:55:21 PM UTC 24 Sep 11 12:55:53 PM UTC 24 8425737557 ps
T928 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3136690441 Sep 11 12:55:40 PM UTC 24 Sep 11 12:55:55 PM UTC 24 8050727642 ps
T929 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.967067864 Sep 11 12:55:48 PM UTC 24 Sep 11 12:55:55 PM UTC 24 1376505505 ps
T930 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.1910759411 Sep 11 12:55:46 PM UTC 24 Sep 11 12:55:56 PM UTC 24 2062720244 ps
T931 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1945980577 Sep 11 12:55:12 PM UTC 24 Sep 11 12:55:56 PM UTC 24 21361011035 ps
T932 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.2649221399 Sep 11 12:55:53 PM UTC 24 Sep 11 12:55:56 PM UTC 24 193565901 ps
T933 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.3223587303 Sep 11 12:55:51 PM UTC 24 Sep 11 12:55:57 PM UTC 24 389728168 ps
T934 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3579071687 Sep 11 12:55:27 PM UTC 24 Sep 11 12:55:57 PM UTC 24 1344516644 ps
T935 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1597528611 Sep 11 12:54:50 PM UTC 24 Sep 11 12:55:57 PM UTC 24 3940449774 ps
T936 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3846750081 Sep 11 12:55:46 PM UTC 24 Sep 11 12:55:58 PM UTC 24 4829284866 ps
T937 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.3609584306 Sep 11 12:55:56 PM UTC 24 Sep 11 12:55:58 PM UTC 24 30412095 ps
T938 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.223517257 Sep 11 12:55:56 PM UTC 24 Sep 11 12:55:58 PM UTC 24 105057750 ps
T939 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.3366328313 Sep 11 12:55:38 PM UTC 24 Sep 11 12:56:00 PM UTC 24 4984302747 ps
T940 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3168102249 Sep 11 12:55:59 PM UTC 24 Sep 11 12:56:01 PM UTC 24 41031562 ps
T941 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.213587351 Sep 11 12:55:59 PM UTC 24 Sep 11 12:56:01 PM UTC 24 49131630 ps
T942 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.2908944235 Sep 11 12:55:59 PM UTC 24 Sep 11 12:56:02 PM UTC 24 58823021 ps
T943 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.805078675 Sep 11 12:55:46 PM UTC 24 Sep 11 12:56:02 PM UTC 24 1504423151 ps
T944 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1118190535 Sep 11 12:52:15 PM UTC 24 Sep 11 12:56:02 PM UTC 24 52676362512 ps
T945 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2599713736 Sep 11 12:55:59 PM UTC 24 Sep 11 12:56:02 PM UTC 24 71356019 ps
T946 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1818710024 Sep 11 12:56:01 PM UTC 24 Sep 11 12:56:05 PM UTC 24 56659920 ps
T947 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3466971383 Sep 11 12:55:59 PM UTC 24 Sep 11 12:56:05 PM UTC 24 2814687747 ps
T948 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1988708303 Sep 11 12:56:13 PM UTC 24 Sep 11 12:56:31 PM UTC 24 12028800180 ps
T949 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.1680022683 Sep 11 12:55:21 PM UTC 24 Sep 11 12:56:06 PM UTC 24 17551232576 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.66897696 Sep 11 12:48:01 PM UTC 24 Sep 11 12:56:07 PM UTC 24 109423172596 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2694073675 Sep 11 12:53:25 PM UTC 24 Sep 11 12:56:07 PM UTC 24 19610184064 ps
T950 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.4052160337 Sep 11 12:56:06 PM UTC 24 Sep 11 12:56:08 PM UTC 24 13383449 ps
T951 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.4003976143 Sep 11 12:56:06 PM UTC 24 Sep 11 12:56:08 PM UTC 24 365857206 ps
T952 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2689794255 Sep 11 12:56:03 PM UTC 24 Sep 11 12:56:08 PM UTC 24 142684800 ps
T953 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.1718691355 Sep 11 12:55:46 PM UTC 24 Sep 11 12:56:09 PM UTC 24 1721398070 ps
T954 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.1383710852 Sep 11 12:56:07 PM UTC 24 Sep 11 12:56:10 PM UTC 24 26539037 ps
T955 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.3711694923 Sep 11 12:51:52 PM UTC 24 Sep 11 12:56:10 PM UTC 24 27243958205 ps
T956 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1960043014 Sep 11 12:53:58 PM UTC 24 Sep 11 12:56:10 PM UTC 24 88103974790 ps
T957 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2034818270 Sep 11 12:55:59 PM UTC 24 Sep 11 12:56:10 PM UTC 24 910683020 ps
T958 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.4088868522 Sep 11 12:56:01 PM UTC 24 Sep 11 12:56:11 PM UTC 24 320731071 ps
T959 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2495875631 Sep 11 12:55:44 PM UTC 24 Sep 11 12:56:12 PM UTC 24 9604967590 ps
T960 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2912212296 Sep 11 12:56:03 PM UTC 24 Sep 11 12:56:12 PM UTC 24 1529871680 ps
T961 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.171895742 Sep 11 12:54:15 PM UTC 24 Sep 11 12:56:12 PM UTC 24 10579093086 ps
T962 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.4150039490 Sep 11 12:56:10 PM UTC 24 Sep 11 12:56:13 PM UTC 24 111055815 ps
T963 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2406879214 Sep 11 12:56:10 PM UTC 24 Sep 11 12:56:14 PM UTC 24 349649413 ps
T964 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2616294343 Sep 11 12:56:11 PM UTC 24 Sep 11 12:56:14 PM UTC 24 59430209 ps
T965 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.510877368 Sep 11 12:55:59 PM UTC 24 Sep 11 12:56:16 PM UTC 24 19466566841 ps
T966 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.2346283704 Sep 11 12:56:10 PM UTC 24 Sep 11 12:56:17 PM UTC 24 808756510 ps
T967 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.791696918 Sep 11 12:55:28 PM UTC 24 Sep 11 12:56:17 PM UTC 24 2496563402 ps
T968 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.787535660 Sep 11 12:56:13 PM UTC 24 Sep 11 12:56:18 PM UTC 24 749902785 ps
T969 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.792254359 Sep 11 12:55:48 PM UTC 24 Sep 11 12:56:18 PM UTC 24 6422676334 ps
T970 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.1053395923 Sep 11 12:56:14 PM UTC 24 Sep 11 12:56:18 PM UTC 24 119236333 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2408100871 Sep 11 12:47:55 PM UTC 24 Sep 11 12:56:18 PM UTC 24 62037258428 ps
T971 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.17145749 Sep 11 12:56:17 PM UTC 24 Sep 11 12:56:19 PM UTC 24 19539528 ps
T972 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1012474959 Sep 11 12:56:14 PM UTC 24 Sep 11 12:56:20 PM UTC 24 498998140 ps
T973 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.137054700 Sep 11 12:56:11 PM UTC 24 Sep 11 12:56:20 PM UTC 24 223181724 ps
T974 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3709456341 Sep 11 12:55:51 PM UTC 24 Sep 11 12:56:21 PM UTC 24 4736513574 ps
T975 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.778528636 Sep 11 12:56:13 PM UTC 24 Sep 11 12:56:23 PM UTC 24 608151814 ps
T976 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.3945715654 Sep 11 12:55:44 PM UTC 24 Sep 11 12:56:25 PM UTC 24 14567730025 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.1262661981 Sep 11 12:54:37 PM UTC 24 Sep 11 12:56:25 PM UTC 24 7855346950 ps
T977 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1004264071 Sep 11 12:56:10 PM UTC 24 Sep 11 12:56:26 PM UTC 24 2059563901 ps
T978 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.1414970991 Sep 11 12:56:01 PM UTC 24 Sep 11 12:56:27 PM UTC 24 24676743216 ps
T979 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.289023428 Sep 11 12:56:03 PM UTC 24 Sep 11 12:56:27 PM UTC 24 1640419089 ps
T980 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2486301367 Sep 11 12:56:15 PM UTC 24 Sep 11 12:56:34 PM UTC 24 3467401654 ps
T981 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2809238709 Sep 11 12:55:42 PM UTC 24 Sep 11 12:56:37 PM UTC 24 38357555301 ps
T982 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1247229806 Sep 11 12:56:10 PM UTC 24 Sep 11 12:56:41 PM UTC 24 5145882371 ps
T983 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.1141297142 Sep 11 12:54:37 PM UTC 24 Sep 11 12:56:48 PM UTC 24 28843665679 ps
T984 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2660821191 Sep 11 12:54:37 PM UTC 24 Sep 11 12:57:11 PM UTC 24 31432688508 ps
T985 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2924385488 Sep 11 12:56:03 PM UTC 24 Sep 11 12:57:13 PM UTC 24 6459200078 ps
T986 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.747144129 Sep 11 12:54:02 PM UTC 24 Sep 11 12:57:15 PM UTC 24 393542304587 ps
T987 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1845295571 Sep 11 12:54:52 PM UTC 24 Sep 11 12:57:17 PM UTC 24 65029431955 ps
T988 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1821611316 Sep 11 12:55:12 PM UTC 24 Sep 11 12:57:21 PM UTC 24 10671629650 ps
T989 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.270591492 Sep 11 12:51:23 PM UTC 24 Sep 11 12:57:22 PM UTC 24 83729031171 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.2773771597 Sep 11 12:50:11 PM UTC 24 Sep 11 12:57:28 PM UTC 24 169797180837 ps
T990 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.2262379584 Sep 11 12:53:41 PM UTC 24 Sep 11 12:57:31 PM UTC 24 55116709312 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.38586018 Sep 11 12:53:02 PM UTC 24 Sep 11 12:57:33 PM UTC 24 121707926209 ps
T991 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.173572388 Sep 11 12:55:42 PM UTC 24 Sep 11 12:57:36 PM UTC 24 11160680302 ps
T992 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.110855794 Sep 11 12:54:19 PM UTC 24 Sep 11 12:57:44 PM UTC 24 14518209747 ps
T993 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.3291545433 Sep 11 12:56:16 PM UTC 24 Sep 11 12:57:49 PM UTC 24 5856128396 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1482028617 Sep 11 12:48:57 PM UTC 24 Sep 11 12:57:56 PM UTC 24 105376102871 ps
T994 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3675238376 Sep 11 12:45:41 PM UTC 24 Sep 11 12:57:59 PM UTC 24 133905799781 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.4037919230 Sep 11 12:55:15 PM UTC 24 Sep 11 12:58:10 PM UTC 24 12076961472 ps
T995 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.4080649226 Sep 11 12:55:48 PM UTC 24 Sep 11 12:58:17 PM UTC 24 18536893890 ps
T996 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.888226829 Sep 11 12:52:41 PM UTC 24 Sep 11 12:58:34 PM UTC 24 78247911276 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3182461701 Sep 11 12:56:14 PM UTC 24 Sep 11 12:58:36 PM UTC 24 41217888445 ps
T997 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.3319868933 Sep 11 12:53:59 PM UTC 24 Sep 11 12:58:45 PM UTC 24 727952471818 ps
T998 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2906289373 Sep 11 12:55:27 PM UTC 24 Sep 11 12:58:48 PM UTC 24 36502316480 ps
T999 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.597714586 Sep 11 12:50:37 PM UTC 24 Sep 11 12:58:50 PM UTC 24 67827132968 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.2442726568 Sep 11 12:56:03 PM UTC 24 Sep 11 12:58:59 PM UTC 24 85296448093 ps
T1000 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2876491413 Sep 11 12:55:29 PM UTC 24 Sep 11 12:59:05 PM UTC 24 13500378625 ps
T1001 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.98758072 Sep 11 12:51:57 PM UTC 24 Sep 11 12:59:08 PM UTC 24 177969308936 ps
T1002 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.3000804723 Sep 11 12:56:14 PM UTC 24 Sep 11 12:59:08 PM UTC 24 27882274168 ps
T1003 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.476819740 Sep 11 12:55:42 PM UTC 24 Sep 11 12:59:09 PM UTC 24 44155911101 ps
T1004 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3495314897 Sep 11 12:55:40 PM UTC 24 Sep 11 12:59:13 PM UTC 24 18711883721 ps
T1005 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.129893303 Sep 11 12:53:00 PM UTC 24 Sep 11 12:59:14 PM UTC 24 221063109649 ps
T1006 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1398541352 Sep 11 12:53:26 PM UTC 24 Sep 11 12:59:16 PM UTC 24 230130724540 ps
T1007 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.1703088793 Sep 11 12:51:04 PM UTC 24 Sep 11 12:59:53 PM UTC 24 88369939936 ps
T1008 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1765752244 Sep 11 12:56:16 PM UTC 24 Sep 11 12:59:55 PM UTC 24 19273842645 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.4285364805 Sep 11 12:55:51 PM UTC 24 Sep 11 01:00:37 PM UTC 24 219364960102 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1286717911 Sep 11 12:53:04 PM UTC 24 Sep 11 01:02:08 PM UTC 24 56778440754 ps
T1011 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.853473733 Sep 11 12:55:42 PM UTC 24 Sep 11 01:02:58 PM UTC 24 42289959912 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3111106323 Sep 11 12:56:04 PM UTC 24 Sep 11 01:03:24 PM UTC 24 43340824038 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2653859079 Sep 11 12:55:52 PM UTC 24 Sep 11 01:04:30 PM UTC 24 235835069309 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3504597745 Sep 11 08:39:47 AM UTC 24 Sep 11 08:39:49 AM UTC 24 76418780 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.172067631 Sep 11 08:39:56 AM UTC 24 Sep 11 08:40:16 AM UTC 24 15535290 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.979467159 Sep 11 08:39:47 AM UTC 24 Sep 11 08:39:49 AM UTC 24 11890536 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3965673327 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:50 AM UTC 24 44052242 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1781288605 Sep 11 08:40:09 AM UTC 24 Sep 11 08:40:16 AM UTC 24 109633137 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3653020749 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:50 AM UTC 24 21119867 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1785265879 Sep 11 08:39:47 AM UTC 24 Sep 11 08:39:50 AM UTC 24 31403274 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.914606802 Sep 11 08:39:47 AM UTC 24 Sep 11 08:39:50 AM UTC 24 23164427 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4181098131 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:50 AM UTC 24 16516461 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1574910219 Sep 11 08:39:47 AM UTC 24 Sep 11 08:39:50 AM UTC 24 77540979 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.331472883 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:51 AM UTC 24 23225749 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3684844447 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:51 AM UTC 24 159051834 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2575136823 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:51 AM UTC 24 52258502 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1767554549 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:52 AM UTC 24 555232679 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3285093722 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:52 AM UTC 24 514907961 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.1330080414 Sep 11 08:39:56 AM UTC 24 Sep 11 08:40:16 AM UTC 24 207869486 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1974683734 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:52 AM UTC 24 18382175 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1247396873 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:52 AM UTC 24 48433204 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2552323828 Sep 11 08:40:14 AM UTC 24 Sep 11 08:40:16 AM UTC 24 41012509 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.186766184 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:52 AM UTC 24 45371067 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.4238937032 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:52 AM UTC 24 87483917 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2839730933 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:53 AM UTC 24 17953099 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.431521837 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:53 AM UTC 24 148755549 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.900457605 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:53 AM UTC 24 12123961 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3846793171 Sep 11 08:39:47 AM UTC 24 Sep 11 08:39:53 AM UTC 24 2013131570 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.545384624 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:53 AM UTC 24 171160992 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.308051710 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:53 AM UTC 24 29418056 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.1541369527 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:53 AM UTC 24 68361221 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1438632428 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:53 AM UTC 24 63081390 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3188414216 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:53 AM UTC 24 140995957 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1789134980 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:53 AM UTC 24 306614329 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2377579817 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:54 AM UTC 24 111646642 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2334780960 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:54 AM UTC 24 152417671 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1105216003 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:54 AM UTC 24 265727518 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2960110534 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:54 AM UTC 24 203136402 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.421826038 Sep 11 08:39:50 AM UTC 24 Sep 11 08:39:54 AM UTC 24 215911440 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1570267519 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:54 AM UTC 24 175274233 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.136761348 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:54 AM UTC 24 194629605 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.3266898330 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:54 AM UTC 24 20154254 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1522708701 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:55 AM UTC 24 435857024 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.904859504 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:55 AM UTC 24 57341961 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.3441579919 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:55 AM UTC 24 27198994 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2177956206 Sep 11 08:39:51 AM UTC 24 Sep 11 08:39:55 AM UTC 24 244601966 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2749140307 Sep 11 08:39:48 AM UTC 24 Sep 11 08:39:56 AM UTC 24 368434956 ps
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