| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.04 | 98.38 | 93.99 | 98.62 | 89.36 | 97.19 | 95.45 | 99.26 |
| T105 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2342005238 | Sep 11 08:39:48 AM UTC 24 | Sep 11 08:39:56 AM UTC 24 | 543530951 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1308996309 | Sep 11 08:39:50 AM UTC 24 | Sep 11 08:39:57 AM UTC 24 | 108880850 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2094042889 | Sep 11 08:39:51 AM UTC 24 | Sep 11 08:39:59 AM UTC 24 | 345124062 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.4110933413 | Sep 11 08:39:50 AM UTC 24 | Sep 11 08:39:59 AM UTC 24 | 995435962 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2210594601 | Sep 11 08:39:51 AM UTC 24 | Sep 11 08:40:04 AM UTC 24 | 3748238807 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2695573709 | Sep 11 08:39:47 AM UTC 24 | Sep 11 08:40:05 AM UTC 24 | 1247705455 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.553663733 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:05 AM UTC 24 | 38973825 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1485361468 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:05 AM UTC 24 | 191115887 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.511634613 | Sep 11 08:39:51 AM UTC 24 | Sep 11 08:40:06 AM UTC 24 | 420349770 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2413340245 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:06 AM UTC 24 | 52501074 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2767303561 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:06 AM UTC 24 | 246792158 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1271268174 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:06 AM UTC 24 | 134125310 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2946837280 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:07 AM UTC 24 | 151584341 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4218121146 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:07 AM UTC 24 | 121547097 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4118388428 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:08 AM UTC 24 | 2772845307 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1860022766 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:08 AM UTC 24 | 63225318 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.523417680 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:08 AM UTC 24 | 61571210 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3371688075 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:09 AM UTC 24 | 56061369 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1866803136 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:09 AM UTC 24 | 23991391 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2943258008 | Sep 11 08:39:57 AM UTC 24 | Sep 11 08:40:09 AM UTC 24 | 18785551 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3574508393 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:09 AM UTC 24 | 53021408 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3505758738 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:10 AM UTC 24 | 236430542 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1911613463 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:10 AM UTC 24 | 285208915 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2298522067 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:10 AM UTC 24 | 306532855 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.510172775 | Sep 11 08:39:50 AM UTC 24 | Sep 11 08:40:11 AM UTC 24 | 3758172621 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.277774648 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:11 AM UTC 24 | 63866141 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3065047385 | Sep 11 08:39:48 AM UTC 24 | Sep 11 08:40:12 AM UTC 24 | 1246226237 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.598142184 | Sep 11 08:39:57 AM UTC 24 | Sep 11 08:40:12 AM UTC 24 | 688137386 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3115071376 | Sep 11 08:39:51 AM UTC 24 | Sep 11 08:40:12 AM UTC 24 | 910639721 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1661224789 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:13 AM UTC 24 | 455679078 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3559535389 | Sep 11 08:39:57 AM UTC 24 | Sep 11 08:40:14 AM UTC 24 | 579461545 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3999570944 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:14 AM UTC 24 | 318621181 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3897802147 | Sep 11 08:40:09 AM UTC 24 | Sep 11 08:40:15 AM UTC 24 | 27004967 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.4056400219 | Sep 11 08:40:11 AM UTC 24 | Sep 11 08:40:15 AM UTC 24 | 19730629 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2687701163 | Sep 11 08:40:09 AM UTC 24 | Sep 11 08:40:15 AM UTC 24 | 94197440 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3645976305 | Sep 11 08:40:09 AM UTC 24 | Sep 11 08:40:16 AM UTC 24 | 357812441 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2810246562 | Sep 11 08:40:09 AM UTC 24 | Sep 11 08:40:16 AM UTC 24 | 157632754 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1671751062 | Sep 11 08:40:11 AM UTC 24 | Sep 11 08:40:16 AM UTC 24 | 326178031 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3330943100 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:16 AM UTC 24 | 15554850 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3255759243 | Sep 11 08:39:57 AM UTC 24 | Sep 11 08:40:16 AM UTC 24 | 37723053 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2077632431 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:16 AM UTC 24 | 18032811 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2484353135 | Sep 11 08:40:13 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 135038832 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2347178368 | Sep 11 08:39:48 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 2276034320 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3251152163 | Sep 11 08:40:14 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 25787017 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.224790978 | Sep 11 08:40:07 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 49413536 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3647711677 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 221934667 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3159906115 | Sep 11 08:40:05 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 29880563 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3229281125 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 374513827 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3852980888 | Sep 11 08:40:07 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 49268235 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.803507098 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 54060018 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.887936537 | Sep 11 08:40:09 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 84791199 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1426224809 | Sep 11 08:40:07 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 90476346 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.16199847 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 45872442 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3153769667 | Sep 11 08:40:15 AM UTC 24 | Sep 11 08:40:17 AM UTC 24 | 109022782 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1983807808 | Sep 11 08:40:01 AM UTC 24 | Sep 11 08:40:18 AM UTC 24 | 169246196 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.909377061 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:18 AM UTC 24 | 112061950 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.2651771916 | Sep 11 08:40:07 AM UTC 24 | Sep 11 08:40:18 AM UTC 24 | 103006000 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.798812312 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:18 AM UTC 24 | 126151137 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.4278256951 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:18 AM UTC 24 | 337476740 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1428899768 | Sep 11 08:39:59 AM UTC 24 | Sep 11 08:40:18 AM UTC 24 | 72946882 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1891304961 | Sep 11 08:40:11 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 219916431 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2117268862 | Sep 11 08:40:09 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 149462676 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.7287157 | Sep 11 08:40:07 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 42361707 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.718271665 | Sep 11 08:39:53 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 1395450092 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.246503739 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 634443879 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2586732079 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 23108508 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2082579020 | Sep 11 08:40:14 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 602258126 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3317351688 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 256965602 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.4169786968 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 57990831 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.306612058 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 29713103 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1504376555 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 40014852 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1344715853 | Sep 11 08:39:57 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 179121177 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3041065480 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:19 AM UTC 24 | 13296437 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2974085180 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 744132579 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3350781568 | Sep 11 08:40:15 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 54410840 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.120737595 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 89040033 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.932660771 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 170914142 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3741886631 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 261891259 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3686898 | Sep 11 08:40:15 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 117983310 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4235589541 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 72999539 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3889266614 | Sep 11 08:39:50 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 7467157551 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3190973252 | Sep 11 08:40:07 AM UTC 24 | Sep 11 08:40:20 AM UTC 24 | 823481456 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.765219120 | Sep 11 08:40:11 AM UTC 24 | Sep 11 08:40:21 AM UTC 24 | 287507759 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3334616161 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:21 AM UTC 24 | 555314574 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3819589313 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:21 AM UTC 24 | 289998291 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3628161212 | Sep 11 08:40:15 AM UTC 24 | Sep 11 08:40:21 AM UTC 24 | 242643149 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.1126495512 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:21 AM UTC 24 | 18352157 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1480775535 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:21 AM UTC 24 | 72043156 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.474835896 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:21 AM UTC 24 | 247411394 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1038871173 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 24851803 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3333081029 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 66160404 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3880082670 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:21 AM UTC 24 | 21555348 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.814505780 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 28466173 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.489090722 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 11314683 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.2902233493 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 49714826 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1599890173 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 489495677 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3449301341 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 12470836 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2050578230 | Sep 11 08:39:54 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 609440529 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.124808196 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 12300437 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1751714528 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 20109354 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.605997661 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 26333590 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3546049232 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 13518850 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3350805209 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 13644065 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1200007720 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 56454508 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3116447935 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 53227666 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.1093453919 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 37939678 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3458745456 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 12809244 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3458756975 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 15528382 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3654017659 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 30273677 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.153290660 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 20451948 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.2990009513 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 15162733 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.34236593 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 228096661 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.895980286 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 13136561 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2982314693 | Sep 11 08:40:07 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 105749576 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1249853154 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 32274415 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.955237373 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 18686520 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2062349746 | Sep 11 08:40:20 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 30001778 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4282241477 | Sep 11 08:39:48 AM UTC 24 | Sep 11 08:40:22 AM UTC 24 | 11765880086 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.183712470 | Sep 11 08:39:51 AM UTC 24 | Sep 11 08:40:23 AM UTC 24 | 1409812857 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1548664793 | Sep 11 08:40:23 AM UTC 24 | Sep 11 08:40:24 AM UTC 24 | 32484677 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2148196302 | Sep 11 08:40:23 AM UTC 24 | Sep 11 08:40:24 AM UTC 24 | 11871569 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.816883205 | Sep 11 08:40:23 AM UTC 24 | Sep 11 08:40:24 AM UTC 24 | 35832969 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.4014135572 | Sep 11 08:40:23 AM UTC 24 | Sep 11 08:40:24 AM UTC 24 | 14360136 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2583100421 | Sep 11 08:40:23 AM UTC 24 | Sep 11 08:40:24 AM UTC 24 | 35529111 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.2872051226 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:25 AM UTC 24 | 1980314983 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.3766848579 | Sep 11 08:40:01 AM UTC 24 | Sep 11 08:40:27 AM UTC 24 | 213324180 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1679755073 | Sep 11 08:40:14 AM UTC 24 | Sep 11 08:40:28 AM UTC 24 | 692357080 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.4159454486 | Sep 11 08:39:56 AM UTC 24 | Sep 11 08:40:29 AM UTC 24 | 2963243719 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.468900998 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:31 AM UTC 24 | 6156793449 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.656438545 | Sep 11 08:40:17 AM UTC 24 | Sep 11 08:40:34 AM UTC 24 | 1314252138 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.4021224495 | Sep 11 08:40:09 AM UTC 24 | Sep 11 08:40:34 AM UTC 24 | 2200864222 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.265983733 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 447999835 ps |
| CPU time | 12.82 seconds |
| Started | Sep 11 12:28:06 PM UTC 24 |
| Finished | Sep 11 12:28:20 PM UTC 24 |
| Peak memory | 245280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265983733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.265983733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.3261862406 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11559500242 ps |
| CPU time | 72.32 seconds |
| Started | Sep 11 12:30:41 PM UTC 24 |
| Finished | Sep 11 12:31:55 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261862406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.3261862406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.860013610 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5393133165 ps |
| CPU time | 42.74 seconds |
| Started | Sep 11 12:27:49 PM UTC 24 |
| Finished | Sep 11 12:28:34 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860013610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.860013610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3387491874 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8064966575 ps |
| CPU time | 121.78 seconds |
| Started | Sep 11 12:30:42 PM UTC 24 |
| Finished | Sep 11 12:32:46 PM UTC 24 |
| Peak memory | 265864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387491874 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.3387491874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.4109894598 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 159034427832 ps |
| CPU time | 334.44 seconds |
| Started | Sep 11 12:29:15 PM UTC 24 |
| Finished | Sep 11 12:34:54 PM UTC 24 |
| Peak memory | 278248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109894598 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.4109894598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2377579817 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 111646642 ps |
| CPU time | 2.36 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:54 AM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2377579817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.spi_device_csr_mem_rw_with_rand_reset.2377579817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.1703677810 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2295045093 ps |
| CPU time | 12.4 seconds |
| Started | Sep 11 12:30:17 PM UTC 24 |
| Finished | Sep 11 12:30:30 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703677810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1703677810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1496063403 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 17648180175 ps |
| CPU time | 108.65 seconds |
| Started | Sep 11 12:32:44 PM UTC 24 |
| Finished | Sep 11 12:34:35 PM UTC 24 |
| Peak memory | 265860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496063403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.1496063403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1517390170 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15661171 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:27:46 PM UTC 24 |
| Finished | Sep 11 12:27:49 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517390170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1517390170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.98676996 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 40663887507 ps |
| CPU time | 479.7 seconds |
| Started | Sep 11 12:35:49 PM UTC 24 |
| Finished | Sep 11 12:43:54 PM UTC 24 |
| Peak memory | 294528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98676996 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.98676996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1390012560 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 140896365481 ps |
| CPU time | 492.84 seconds |
| Started | Sep 11 12:42:25 PM UTC 24 |
| Finished | Sep 11 12:50:44 PM UTC 24 |
| Peak memory | 294540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390012560 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.1390012560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1267117875 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 350540873 ps |
| CPU time | 1.85 seconds |
| Started | Sep 11 12:29:43 PM UTC 24 |
| Finished | Sep 11 12:29:46 PM UTC 24 |
| Peak memory | 257904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267117875 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1267117875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2140952616 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 9669075946 ps |
| CPU time | 149.48 seconds |
| Started | Sep 11 12:36:13 PM UTC 24 |
| Finished | Sep 11 12:38:46 PM UTC 24 |
| Peak memory | 265800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140952616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.2140952616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.645404168 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8894513783 ps |
| CPU time | 153.21 seconds |
| Started | Sep 11 12:34:12 PM UTC 24 |
| Finished | Sep 11 12:36:48 PM UTC 24 |
| Peak memory | 265856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645404168 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.645404168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.1670987307 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 474650670 ps |
| CPU time | 16.18 seconds |
| Started | Sep 11 12:31:35 PM UTC 24 |
| Finished | Sep 11 12:31:52 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670987307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1670987307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.409825172 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 120240196112 ps |
| CPU time | 348.73 seconds |
| Started | Sep 11 12:31:56 PM UTC 24 |
| Finished | Sep 11 12:37:50 PM UTC 24 |
| Peak memory | 276140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409825172 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.409825172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.951262528 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 933866971211 ps |
| CPU time | 649.26 seconds |
| Started | Sep 11 12:34:08 PM UTC 24 |
| Finished | Sep 11 12:45:05 PM UTC 24 |
| Peak memory | 267880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951262528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.951262528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2695573709 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1247705455 ps |
| CPU time | 15.86 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:40:05 AM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695573709 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.2695573709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3846793171 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2013131570 ps |
| CPU time | 3.99 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 225128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846793171 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3846793171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3334419631 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 18738690854 ps |
| CPU time | 106.84 seconds |
| Started | Sep 11 12:35:31 PM UTC 24 |
| Finished | Sep 11 12:37:20 PM UTC 24 |
| Peak memory | 278104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334419631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.3334419631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.431521837 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 148755549 ps |
| CPU time | 1.33 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431521837 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.431521837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3501520388 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 198990204529 ps |
| CPU time | 554.96 seconds |
| Started | Sep 11 12:29:06 PM UTC 24 |
| Finished | Sep 11 12:38:29 PM UTC 24 |
| Peak memory | 278224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501520388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.3501520388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3615844427 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2949507751 ps |
| CPU time | 26.93 seconds |
| Started | Sep 11 12:31:00 PM UTC 24 |
| Finished | Sep 11 12:31:28 PM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615844427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3615844427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.2918665311 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 184181584640 ps |
| CPU time | 581.37 seconds |
| Started | Sep 11 12:45:48 PM UTC 24 |
| Finished | Sep 11 12:55:37 PM UTC 24 |
| Peak memory | 300732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918665311 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.2918665311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2130026230 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5347089035 ps |
| CPU time | 109.13 seconds |
| Started | Sep 11 12:43:36 PM UTC 24 |
| Finished | Sep 11 12:45:27 PM UTC 24 |
| Peak memory | 263896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130026230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.2130026230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1960012084 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 39362813788 ps |
| CPU time | 394.24 seconds |
| Started | Sep 11 12:47:25 PM UTC 24 |
| Finished | Sep 11 12:54:05 PM UTC 24 |
| Peak memory | 265892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960012084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.1960012084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1496124044 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6708014599 ps |
| CPU time | 36.09 seconds |
| Started | Sep 11 12:29:56 PM UTC 24 |
| Finished | Sep 11 12:30:34 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496124044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1496124044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2990649995 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 23019029697 ps |
| CPU time | 101.33 seconds |
| Started | Sep 11 12:34:05 PM UTC 24 |
| Finished | Sep 11 12:35:49 PM UTC 24 |
| Peak memory | 263768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990649995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2990649995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2223853726 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 37590800 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:29:47 PM UTC 24 |
| Finished | Sep 11 12:29:49 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223853726 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2223853726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.916641616 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 5108573088 ps |
| CPU time | 126.09 seconds |
| Started | Sep 11 12:42:21 PM UTC 24 |
| Finished | Sep 11 12:44:30 PM UTC 24 |
| Peak memory | 267976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916641616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.916641616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.1582101536 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 22959841039 ps |
| CPU time | 92.01 seconds |
| Started | Sep 11 12:48:25 PM UTC 24 |
| Finished | Sep 11 12:49:58 PM UTC 24 |
| Peak memory | 267848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582101536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.1582101536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3097287928 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 23601012860 ps |
| CPU time | 46.64 seconds |
| Started | Sep 11 12:54:31 PM UTC 24 |
| Finished | Sep 11 12:55:20 PM UTC 24 |
| Peak memory | 245460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097287928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3097287928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3555346730 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 97964098348 ps |
| CPU time | 123.29 seconds |
| Started | Sep 11 12:34:07 PM UTC 24 |
| Finished | Sep 11 12:36:12 PM UTC 24 |
| Peak memory | 265884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555346730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3555346730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1679755073 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 692357080 ps |
| CPU time | 12.95 seconds |
| Started | Sep 11 08:40:14 AM UTC 24 |
| Finished | Sep 11 08:40:28 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679755073 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.1679755073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.66897696 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 109423172596 ps |
| CPU time | 479.33 seconds |
| Started | Sep 11 12:48:01 PM UTC 24 |
| Finished | Sep 11 12:56:07 PM UTC 24 |
| Peak memory | 300748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66897696 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.66897696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3080278467 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 19376728767 ps |
| CPU time | 184.85 seconds |
| Started | Sep 11 12:48:52 PM UTC 24 |
| Finished | Sep 11 12:52:00 PM UTC 24 |
| Peak memory | 265812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080278467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.3080278467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.38586018 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 121707926209 ps |
| CPU time | 266.97 seconds |
| Started | Sep 11 12:53:02 PM UTC 24 |
| Finished | Sep 11 12:57:33 PM UTC 24 |
| Peak memory | 267848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38586018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.38586018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.4037919230 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 12076961472 ps |
| CPU time | 171.31 seconds |
| Started | Sep 11 12:55:15 PM UTC 24 |
| Finished | Sep 11 12:58:10 PM UTC 24 |
| Peak memory | 281804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037919230 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.4037919230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1406766546 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 200569444333 ps |
| CPU time | 562.63 seconds |
| Started | Sep 11 12:35:47 PM UTC 24 |
| Finished | Sep 11 12:45:17 PM UTC 24 |
| Peak memory | 278148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406766546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.1406766546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.195297096 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 14532679751 ps |
| CPU time | 114.4 seconds |
| Started | Sep 11 12:39:01 PM UTC 24 |
| Finished | Sep 11 12:40:58 PM UTC 24 |
| Peak memory | 245380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195297096 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.195297096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1482028617 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 105376102871 ps |
| CPU time | 531.76 seconds |
| Started | Sep 11 12:48:57 PM UTC 24 |
| Finished | Sep 11 12:57:56 PM UTC 24 |
| Peak memory | 274104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482028617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.1482028617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.4169786968 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 57990831 ps |
| CPU time | 3.56 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 227312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169786968 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4169786968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.4159454486 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2963243719 ps |
| CPU time | 14.27 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:29 AM UTC 24 |
| Peak memory | 227116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159454486 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.4159454486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3559535389 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 579461545 ps |
| CPU time | 5.82 seconds |
| Started | Sep 11 08:39:57 AM UTC 24 |
| Finished | Sep 11 08:40:14 AM UTC 24 |
| Peak memory | 225252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559535389 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.3559535389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2604577781 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 25326977493 ps |
| CPU time | 95.79 seconds |
| Started | Sep 11 12:28:33 PM UTC 24 |
| Finished | Sep 11 12:30:11 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604577781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2604577781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2078018396 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 24923843647 ps |
| CPU time | 260.57 seconds |
| Started | Sep 11 12:38:50 PM UTC 24 |
| Finished | Sep 11 12:43:14 PM UTC 24 |
| Peak memory | 284232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078018396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.2078018396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1004488235 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 342638151 ps |
| CPU time | 5.1 seconds |
| Started | Sep 11 12:39:40 PM UTC 24 |
| Finished | Sep 11 12:39:46 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004488235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1004488235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.224168168 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 40529861565 ps |
| CPU time | 490.92 seconds |
| Started | Sep 11 12:39:54 PM UTC 24 |
| Finished | Sep 11 12:48:11 PM UTC 24 |
| Peak memory | 267928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224168168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.224168168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.434247032 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 96796600497 ps |
| CPU time | 266.43 seconds |
| Started | Sep 11 12:41:33 PM UTC 24 |
| Finished | Sep 11 12:46:04 PM UTC 24 |
| Peak memory | 280180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434247032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.434247032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.274606571 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3024974517 ps |
| CPU time | 76 seconds |
| Started | Sep 11 12:44:00 PM UTC 24 |
| Finished | Sep 11 12:45:18 PM UTC 24 |
| Peak memory | 276088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274606571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.274606571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.511821310 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 83372611471 ps |
| CPU time | 65.19 seconds |
| Started | Sep 11 12:44:58 PM UTC 24 |
| Finished | Sep 11 12:46:05 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511821310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.511821310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3319186080 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 328061268 ps |
| CPU time | 5.42 seconds |
| Started | Sep 11 12:48:23 PM UTC 24 |
| Finished | Sep 11 12:48:30 PM UTC 24 |
| Peak memory | 247316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319186080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3319186080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.3239608342 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 10398629106 ps |
| CPU time | 40.42 seconds |
| Started | Sep 11 12:48:59 PM UTC 24 |
| Finished | Sep 11 12:49:40 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239608342 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.3239608342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3190973252 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 823481456 ps |
| CPU time | 4.61 seconds |
| Started | Sep 11 08:40:07 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190973252 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.3190973252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1570267519 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 175274233 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:54 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570267519 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.1570267519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2749140307 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 368434956 ps |
| CPU time | 6.8 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:56 AM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749140307 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.2749140307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4282241477 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 11765880086 ps |
| CPU time | 33.29 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 214972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282241477 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.4282241477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1785265879 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 31403274 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:50 AM UTC 24 |
| Peak memory | 212488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785265879 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.1785265879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3285093722 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 514907961 ps |
| CPU time | 2.95 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:52 AM UTC 24 |
| Peak memory | 229428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3285093722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.spi_device_csr_mem_rw_with_rand_reset.3285093722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.914606802 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 23164427 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:50 AM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914606802 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.914606802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3504597745 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 76418780 ps |
| CPU time | 0.68 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 211992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504597745 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3504597745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1574910219 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 77540979 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:50 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574910219 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1574910219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.979467159 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 11890536 ps |
| CPU time | 0.64 seconds |
| Started | Sep 11 08:39:47 AM UTC 24 |
| Finished | Sep 11 08:39:49 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979467159 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.979467159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1767554549 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 555232679 ps |
| CPU time | 2.74 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:52 AM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767554549 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstand ing.1767554549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3065047385 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1246226237 ps |
| CPU time | 21.69 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:40:12 AM UTC 24 |
| Peak memory | 225064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065047385 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.3065047385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2347178368 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2276034320 ps |
| CPU time | 27.3 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 215160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347178368 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.2347178368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4181098131 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 16516461 ps |
| CPU time | 0.9 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:50 AM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181098131 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.4181098131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2334780960 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 152417671 ps |
| CPU time | 2.74 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:54 AM UTC 24 |
| Peak memory | 226592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2334780960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.spi_device_csr_mem_rw_with_rand_reset.2334780960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2575136823 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 52258502 ps |
| CPU time | 1.64 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:51 AM UTC 24 |
| Peak memory | 223044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575136823 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2575136823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3965673327 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 44052242 ps |
| CPU time | 0.69 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:50 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965673327 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3965673327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.331472883 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 23225749 ps |
| CPU time | 1.57 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:51 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331472883 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.331472883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3653020749 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 21119867 ps |
| CPU time | 0.62 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:50 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653020749 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.3653020749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1438632428 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 63081390 ps |
| CPU time | 3.37 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 225116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438632428 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand ing.1438632428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3684844447 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 159051834 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:51 AM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684844447 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3684844447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2342005238 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 543530951 ps |
| CPU time | 6.87 seconds |
| Started | Sep 11 08:39:48 AM UTC 24 |
| Finished | Sep 11 08:39:56 AM UTC 24 |
| Peak memory | 227116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342005238 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.2342005238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2298522067 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 306532855 ps |
| CPU time | 2.34 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:10 AM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2298522067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.spi_device_csr_mem_rw_with_rand_reset.2298522067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1911613463 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 285208915 ps |
| CPU time | 1.82 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:10 AM UTC 24 |
| Peak memory | 223900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911613463 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.1911613463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.172067631 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 15535290 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172067631 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.172067631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.909377061 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 112061950 ps |
| CPU time | 2.7 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:18 AM UTC 24 |
| Peak memory | 225088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909377061 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstand ing.909377061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.798812312 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 126151137 ps |
| CPU time | 3.27 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:18 AM UTC 24 |
| Peak memory | 225192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798812312 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.798812312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1428899768 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 72946882 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 08:39:59 AM UTC 24 |
| Finished | Sep 11 08:40:18 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1428899768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.spi_device_csr_mem_rw_with_rand_reset.1428899768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3255759243 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 37723053 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 08:39:57 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255759243 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.3255759243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2943258008 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 18785551 ps |
| CPU time | 0.74 seconds |
| Started | Sep 11 08:39:57 AM UTC 24 |
| Finished | Sep 11 08:40:09 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943258008 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.2943258008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1344715853 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 179121177 ps |
| CPU time | 3.99 seconds |
| Started | Sep 11 08:39:57 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 225072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344715853 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstan ding.1344715853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.598142184 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 688137386 ps |
| CPU time | 3.79 seconds |
| Started | Sep 11 08:39:57 AM UTC 24 |
| Finished | Sep 11 08:40:12 AM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598142184 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.598142184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.7287157 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 42361707 ps |
| CPU time | 2.99 seconds |
| Started | Sep 11 08:40:07 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 227116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=7287157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.spi_device_csr_mem_rw_with_rand_reset.7287157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3852980888 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 49268235 ps |
| CPU time | 1.4 seconds |
| Started | Sep 11 08:40:07 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852980888 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.3852980888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3159906115 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 29880563 ps |
| CPU time | 0.63 seconds |
| Started | Sep 11 08:40:05 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159906115 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3159906115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1426224809 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 90476346 ps |
| CPU time | 1.66 seconds |
| Started | Sep 11 08:40:07 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 224416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426224809 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan ding.1426224809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1983807808 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 169246196 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 08:40:01 AM UTC 24 |
| Finished | Sep 11 08:40:18 AM UTC 24 |
| Peak memory | 227236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983807808 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.1983807808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.3766848579 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 213324180 ps |
| CPU time | 11.16 seconds |
| Started | Sep 11 08:40:01 AM UTC 24 |
| Finished | Sep 11 08:40:27 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766848579 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.3766848579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2810246562 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 157632754 ps |
| CPU time | 2.39 seconds |
| Started | Sep 11 08:40:09 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 227196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2810246562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.spi_device_csr_mem_rw_with_rand_reset.2810246562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.2651771916 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 103006000 ps |
| CPU time | 2.05 seconds |
| Started | Sep 11 08:40:07 AM UTC 24 |
| Finished | Sep 11 08:40:18 AM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651771916 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.2651771916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.224790978 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 49413536 ps |
| CPU time | 0.78 seconds |
| Started | Sep 11 08:40:07 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224790978 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.224790978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.887936537 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 84791199 ps |
| CPU time | 3.35 seconds |
| Started | Sep 11 08:40:09 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 225072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887936537 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstand ing.887936537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2982314693 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 105749576 ps |
| CPU time | 6.53 seconds |
| Started | Sep 11 08:40:07 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982314693 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.2982314693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3645976305 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 357812441 ps |
| CPU time | 2.25 seconds |
| Started | Sep 11 08:40:09 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 227256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3645976305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.spi_device_csr_mem_rw_with_rand_reset.3645976305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1781288605 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 109633137 ps |
| CPU time | 1.66 seconds |
| Started | Sep 11 08:40:09 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781288605 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.1781288605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3897802147 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 27004967 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:40:09 AM UTC 24 |
| Finished | Sep 11 08:40:15 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897802147 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.3897802147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2687701163 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 94197440 ps |
| CPU time | 1.57 seconds |
| Started | Sep 11 08:40:09 AM UTC 24 |
| Finished | Sep 11 08:40:15 AM UTC 24 |
| Peak memory | 214200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687701163 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstan ding.2687701163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2117268862 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 149462676 ps |
| CPU time | 4.79 seconds |
| Started | Sep 11 08:40:09 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117268862 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.2117268862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.4021224495 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2200864222 ps |
| CPU time | 20.15 seconds |
| Started | Sep 11 08:40:09 AM UTC 24 |
| Finished | Sep 11 08:40:34 AM UTC 24 |
| Peak memory | 227184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021224495 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.4021224495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2082579020 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 602258126 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 08:40:14 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 227172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2082579020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.spi_device_csr_mem_rw_with_rand_reset.2082579020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1671751062 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 326178031 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 08:40:11 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671751062 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.1671751062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.4056400219 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 19730629 ps |
| CPU time | 0.7 seconds |
| Started | Sep 11 08:40:11 AM UTC 24 |
| Finished | Sep 11 08:40:15 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056400219 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.4056400219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2484353135 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 135038832 ps |
| CPU time | 2.61 seconds |
| Started | Sep 11 08:40:13 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484353135 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstan ding.2484353135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1891304961 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 219916431 ps |
| CPU time | 4.48 seconds |
| Started | Sep 11 08:40:11 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 227112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891304961 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.1891304961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.765219120 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 287507759 ps |
| CPU time | 6.57 seconds |
| Started | Sep 11 08:40:11 AM UTC 24 |
| Finished | Sep 11 08:40:21 AM UTC 24 |
| Peak memory | 225140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765219120 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.765219120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3350781568 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 54410840 ps |
| CPU time | 3.27 seconds |
| Started | Sep 11 08:40:15 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 229172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3350781568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.spi_device_csr_mem_rw_with_rand_reset.3350781568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3153769667 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 109022782 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 08:40:15 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153769667 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.3153769667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2552323828 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 41012509 ps |
| CPU time | 0.66 seconds |
| Started | Sep 11 08:40:14 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552323828 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.2552323828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3686898 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 117983310 ps |
| CPU time | 3.51 seconds |
| Started | Sep 11 08:40:15 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 225044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686898 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.3686898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3251152163 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 25787017 ps |
| CPU time | 1.41 seconds |
| Started | Sep 11 08:40:14 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251152163 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.3251152163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.474835896 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 247411394 ps |
| CPU time | 3.11 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:21 AM UTC 24 |
| Peak memory | 229160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=474835896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.spi_device_csr_mem_rw_with_rand_reset.474835896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3741886631 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 261891259 ps |
| CPU time | 1.83 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741886631 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.3741886631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2586732079 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 23108508 ps |
| CPU time | 0.76 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586732079 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.2586732079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1599890173 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 489495677 ps |
| CPU time | 3.34 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 225012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599890173 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan ding.1599890173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3628161212 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 242643149 ps |
| CPU time | 4.59 seconds |
| Started | Sep 11 08:40:15 AM UTC 24 |
| Finished | Sep 11 08:40:21 AM UTC 24 |
| Peak memory | 227240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628161212 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.3628161212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.656438545 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1314252138 ps |
| CPU time | 15.3 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:34 AM UTC 24 |
| Peak memory | 226804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656438545 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.656438545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3819589313 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 289998291 ps |
| CPU time | 2.49 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:21 AM UTC 24 |
| Peak memory | 227432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3819589313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.spi_device_csr_mem_rw_with_rand_reset.3819589313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.932660771 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 170914142 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932660771 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.932660771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.306612058 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 29713103 ps |
| CPU time | 0.74 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306612058 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.306612058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4235589541 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 72999539 ps |
| CPU time | 1.7 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 214288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235589541 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan ding.4235589541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3334616161 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 555314574 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:21 AM UTC 24 |
| Peak memory | 225336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334616161 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3334616161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.468900998 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 6156793449 ps |
| CPU time | 12.48 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:31 AM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468900998 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.468900998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.34236593 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 228096661 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=34236593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 19.spi_device_csr_mem_rw_with_rand_reset.34236593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.120737595 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 89040033 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 223912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120737595 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.120737595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3041065480 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 13296437 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041065480 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.3041065480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2062349746 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 30001778 ps |
| CPU time | 1.74 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 224212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062349746 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstan ding.2062349746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3116447935 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 53227666 ps |
| CPU time | 3.27 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 229236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116447935 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.3116447935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.2872051226 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1980314983 ps |
| CPU time | 5.89 seconds |
| Started | Sep 11 08:40:17 AM UTC 24 |
| Finished | Sep 11 08:40:25 AM UTC 24 |
| Peak memory | 227216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872051226 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.2872051226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.510172775 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3758172621 ps |
| CPU time | 19.79 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:40:11 AM UTC 24 |
| Peak memory | 225148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510172775 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.510172775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3889266614 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 7467157551 ps |
| CPU time | 28.58 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 224848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889266614 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.3889266614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.421826038 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 215911440 ps |
| CPU time | 2.6 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:54 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421826038 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.421826038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1247396873 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 48433204 ps |
| CPU time | 0.67 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:52 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247396873 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1247396873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.4238937032 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 87483917 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:52 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238937032 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.4238937032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1974683734 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 18382175 ps |
| CPU time | 0.6 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:52 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974683734 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.1974683734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1789134980 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 306614329 ps |
| CPU time | 1.89 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 224216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789134980 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand ing.1789134980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3188414216 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 140995957 ps |
| CPU time | 1.98 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188414216 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3188414216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.4110933413 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 995435962 ps |
| CPU time | 7.91 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:59 AM UTC 24 |
| Peak memory | 227168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110933413 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.4110933413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.1126495512 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 18352157 ps |
| CPU time | 0.75 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:21 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126495512 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.1126495512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1480775535 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 72043156 ps |
| CPU time | 0.7 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:21 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480775535 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.1480775535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3880082670 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 21555348 ps |
| CPU time | 0.67 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:21 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880082670 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.3880082670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1751714528 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 20109354 ps |
| CPU time | 0.88 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751714528 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1751714528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.814505780 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 28466173 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814505780 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.814505780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.489090722 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 11314683 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489090722 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.489090722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.2902233493 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 49714826 ps |
| CPU time | 0.67 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902233493 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.2902233493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3449301341 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 12470836 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449301341 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.3449301341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.124808196 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 12300437 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124808196 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.124808196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.3350805209 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 13644065 ps |
| CPU time | 0.7 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350805209 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.3350805209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3115071376 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 910639721 ps |
| CPU time | 19.71 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:40:12 AM UTC 24 |
| Peak memory | 224948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115071376 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.3115071376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2210594601 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3748238807 ps |
| CPU time | 11.87 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:40:04 AM UTC 24 |
| Peak memory | 215064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210594601 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.2210594601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.308051710 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 29418056 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308051710 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.308051710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2177956206 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 244601966 ps |
| CPU time | 3.09 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:55 AM UTC 24 |
| Peak memory | 229208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2177956206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.spi_device_csr_mem_rw_with_rand_reset.2177956206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.1541369527 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 68361221 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541369527 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1541369527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.186766184 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 45371067 ps |
| CPU time | 0.7 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:52 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186766184 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.186766184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1105216003 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 265727518 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:54 AM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105216003 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.1105216003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2839730933 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 17953099 ps |
| CPU time | 0.85 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839730933 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.2839730933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1522708701 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 435857024 ps |
| CPU time | 2.72 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:55 AM UTC 24 |
| Peak memory | 225116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522708701 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstand ing.1522708701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2960110534 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 203136402 ps |
| CPU time | 2.38 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:54 AM UTC 24 |
| Peak memory | 229372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960110534 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2960110534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1308996309 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 108880850 ps |
| CPU time | 5.68 seconds |
| Started | Sep 11 08:39:50 AM UTC 24 |
| Finished | Sep 11 08:39:57 AM UTC 24 |
| Peak memory | 224996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308996309 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1308996309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1200007720 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 56454508 ps |
| CPU time | 0.74 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200007720 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.1200007720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.1093453919 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 37939678 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093453919 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.1093453919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3458745456 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 12809244 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458745456 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3458745456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3546049232 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 13518850 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546049232 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.3546049232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1038871173 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 24851803 ps |
| CPU time | 0.75 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038871173 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.1038871173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.153290660 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 20451948 ps |
| CPU time | 0.77 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153290660 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.153290660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3458756975 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 15528382 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458756975 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.3458756975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.2990009513 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 15162733 ps |
| CPU time | 0.66 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990009513 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.2990009513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1504376555 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 40014852 ps |
| CPU time | 0.72 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504376555 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.1504376555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1249853154 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 32274415 ps |
| CPU time | 0.78 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249853154 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.1249853154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.511634613 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 420349770 ps |
| CPU time | 12.24 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:40:06 AM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511634613 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.511634613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.183712470 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 1409812857 ps |
| CPU time | 29.45 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:40:23 AM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183712470 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.183712470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2413340245 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 52501074 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:06 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2413340245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.spi_device_csr_mem_rw_with_rand_reset.2413340245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.3266898330 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 20154254 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:54 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266898330 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3266898330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.545384624 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 171160992 ps |
| CPU time | 0.7 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545384624 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.545384624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.3441579919 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 27198994 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:55 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441579919 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.3441579919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.900457605 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 12123961 ps |
| CPU time | 0.67 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:53 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900457605 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.900457605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.904859504 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 57341961 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:55 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904859504 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.904859504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.136761348 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 194629605 ps |
| CPU time | 2.32 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:54 AM UTC 24 |
| Peak memory | 227272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136761348 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.136761348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2094042889 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 345124062 ps |
| CPU time | 6.96 seconds |
| Started | Sep 11 08:39:51 AM UTC 24 |
| Finished | Sep 11 08:39:59 AM UTC 24 |
| Peak memory | 227200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094042889 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.2094042889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3654017659 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 30273677 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654017659 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.3654017659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.895980286 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 13136561 ps |
| CPU time | 0.76 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895980286 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.895980286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3333081029 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 66160404 ps |
| CPU time | 0.65 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333081029 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3333081029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.955237373 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 18686520 ps |
| CPU time | 0.69 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955237373 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.955237373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.605997661 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 26333590 ps |
| CPU time | 0.61 seconds |
| Started | Sep 11 08:40:20 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605997661 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.605997661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.816883205 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 35832969 ps |
| CPU time | 0.66 seconds |
| Started | Sep 11 08:40:23 AM UTC 24 |
| Finished | Sep 11 08:40:24 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816883205 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.816883205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1548664793 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 32484677 ps |
| CPU time | 0.63 seconds |
| Started | Sep 11 08:40:23 AM UTC 24 |
| Finished | Sep 11 08:40:24 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548664793 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.1548664793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.4014135572 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 14360136 ps |
| CPU time | 0.71 seconds |
| Started | Sep 11 08:40:23 AM UTC 24 |
| Finished | Sep 11 08:40:24 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014135572 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.4014135572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2148196302 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 11871569 ps |
| CPU time | 0.67 seconds |
| Started | Sep 11 08:40:23 AM UTC 24 |
| Finished | Sep 11 08:40:24 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148196302 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.2148196302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2583100421 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 35529111 ps |
| CPU time | 0.65 seconds |
| Started | Sep 11 08:40:23 AM UTC 24 |
| Finished | Sep 11 08:40:24 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583100421 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2583100421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4118388428 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 2772845307 ps |
| CPU time | 3.06 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:08 AM UTC 24 |
| Peak memory | 229312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4118388428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.spi_device_csr_mem_rw_with_rand_reset.4118388428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2946837280 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 151584341 ps |
| CPU time | 2.31 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:07 AM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946837280 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2946837280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1485361468 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 191115887 ps |
| CPU time | 0.67 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:05 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485361468 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1485361468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.523417680 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 61571210 ps |
| CPU time | 3.52 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:08 AM UTC 24 |
| Peak memory | 225064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523417680 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.523417680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1860022766 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 63225318 ps |
| CPU time | 3.45 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:08 AM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860022766 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1860022766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.718271665 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 1395450092 ps |
| CPU time | 13.98 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 227324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718271665 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.718271665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3647711677 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 221934667 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3647711677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.spi_device_csr_mem_rw_with_rand_reset.3647711677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3505758738 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 236430542 ps |
| CPU time | 1.69 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:10 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505758738 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3505758738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3371688075 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 56061369 ps |
| CPU time | 0.73 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:09 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371688075 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3371688075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3574508393 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 53021408 ps |
| CPU time | 1.63 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:09 AM UTC 24 |
| Peak memory | 224448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574508393 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstand ing.3574508393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3229281125 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 374513827 ps |
| CPU time | 2.19 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 227236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229281125 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3229281125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3999570944 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 318621181 ps |
| CPU time | 6.52 seconds |
| Started | Sep 11 08:39:53 AM UTC 24 |
| Finished | Sep 11 08:40:14 AM UTC 24 |
| Peak memory | 227136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999570944 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.3999570944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.246503739 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 634443879 ps |
| CPU time | 3.41 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 229360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=246503739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.spi_device_csr_mem_rw_with_rand_reset.246503739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2077632431 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 18032811 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077632431 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2077632431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1866803136 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 23991391 ps |
| CPU time | 0.68 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:09 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866803136 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1866803136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3317351688 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 256965602 ps |
| CPU time | 3.65 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:19 AM UTC 24 |
| Peak memory | 225064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317351688 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand ing.3317351688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.277774648 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 63866141 ps |
| CPU time | 3.47 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:11 AM UTC 24 |
| Peak memory | 225396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277774648 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.277774648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1661224789 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 455679078 ps |
| CPU time | 5.25 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:13 AM UTC 24 |
| Peak memory | 227116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661224789 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.1661224789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.803507098 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 54060018 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=803507098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.spi_device_csr_mem_rw_with_rand_reset.803507098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.16199847 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 45872442 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:17 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16199847 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.16199847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3330943100 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 15554850 ps |
| CPU time | 0.8 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330943100 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3330943100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2974085180 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 744132579 ps |
| CPU time | 3.93 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:20 AM UTC 24 |
| Peak memory | 225248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974085180 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand ing.2974085180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2050578230 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 609440529 ps |
| CPU time | 6.06 seconds |
| Started | Sep 11 08:39:54 AM UTC 24 |
| Finished | Sep 11 08:40:22 AM UTC 24 |
| Peak memory | 227108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050578230 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.2050578230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2767303561 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 246792158 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:06 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2767303561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.spi_device_csr_mem_rw_with_rand_reset.2767303561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.4278256951 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 337476740 ps |
| CPU time | 2.23 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:18 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278256951 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4278256951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.553663733 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 38973825 ps |
| CPU time | 0.65 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:05 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553663733 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.553663733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4218121146 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 121547097 ps |
| CPU time | 2.57 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:07 AM UTC 24 |
| Peak memory | 224952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218121146 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand ing.4218121146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1271268174 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 134125310 ps |
| CPU time | 1.97 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:06 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271268174 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1271268174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.1330080414 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 207869486 ps |
| CPU time | 10.98 seconds |
| Started | Sep 11 08:39:56 AM UTC 24 |
| Finished | Sep 11 08:40:16 AM UTC 24 |
| Peak memory | 224812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330080414 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.1330080414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3198854590 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 46775206 ps |
| CPU time | 3.8 seconds |
| Started | Sep 11 12:28:35 PM UTC 24 |
| Finished | Sep 11 12:28:40 PM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198854590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3198854590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.2296564959 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 44532377 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 12:27:43 PM UTC 24 |
| Finished | Sep 11 12:27:45 PM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296564959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2296564959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3098398596 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 73521890 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 12:29:03 PM UTC 24 |
| Finished | Sep 11 12:29:05 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098398596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3098398596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.62550282 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 40236611163 ps |
| CPU time | 189.11 seconds |
| Started | Sep 11 12:29:04 PM UTC 24 |
| Finished | Sep 11 12:32:16 PM UTC 24 |
| Peak memory | 261760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62550282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.62550282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.1376448196 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 126297492 ps |
| CPU time | 4.89 seconds |
| Started | Sep 11 12:28:41 PM UTC 24 |
| Finished | Sep 11 12:28:47 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376448196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1376448196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.4220465844 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 78763571471 ps |
| CPU time | 191.35 seconds |
| Started | Sep 11 12:28:48 PM UTC 24 |
| Finished | Sep 11 12:32:02 PM UTC 24 |
| Peak memory | 265804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220465844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.4220465844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2082455327 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 72895797 ps |
| CPU time | 4.88 seconds |
| Started | Sep 11 12:28:27 PM UTC 24 |
| Finished | Sep 11 12:28:33 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082455327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2082455327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.27717331 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7120964205 ps |
| CPU time | 8.8 seconds |
| Started | Sep 11 12:28:21 PM UTC 24 |
| Finished | Sep 11 12:28:31 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27717331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.27717331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.725077693 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2142656631 ps |
| CPU time | 10.99 seconds |
| Started | Sep 11 12:28:50 PM UTC 24 |
| Finished | Sep 11 12:29:02 PM UTC 24 |
| Peak memory | 233372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725077693 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.725077693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1371427281 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1164228209 ps |
| CPU time | 9.34 seconds |
| Started | Sep 11 12:27:48 PM UTC 24 |
| Finished | Sep 11 12:27:59 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371427281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1371427281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.4123764923 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 173237350 ps |
| CPU time | 1.76 seconds |
| Started | Sep 11 12:28:02 PM UTC 24 |
| Finished | Sep 11 12:28:05 PM UTC 24 |
| Peak memory | 216520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123764923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4123764923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1382442643 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 17103710 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 12:27:59 PM UTC 24 |
| Finished | Sep 11 12:28:01 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382442643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1382442643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.1406654776 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3461106194 ps |
| CPU time | 14.1 seconds |
| Started | Sep 11 12:28:34 PM UTC 24 |
| Finished | Sep 11 12:28:49 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406654776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1406654776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.982671639 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 10734939 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 12:30:49 PM UTC 24 |
| Finished | Sep 11 12:30:51 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982671639 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.982671639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1565130592 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10910562304 ps |
| CPU time | 13.44 seconds |
| Started | Sep 11 12:30:30 PM UTC 24 |
| Finished | Sep 11 12:30:45 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565130592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1565130592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1373381356 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 36182131 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 12:29:50 PM UTC 24 |
| Finished | Sep 11 12:29:53 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373381356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1373381356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.750029928 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4885505221 ps |
| CPU time | 96 seconds |
| Started | Sep 11 12:30:35 PM UTC 24 |
| Finished | Sep 11 12:32:13 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750029928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.750029928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1222574443 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 215416869913 ps |
| CPU time | 306.9 seconds |
| Started | Sep 11 12:30:38 PM UTC 24 |
| Finished | Sep 11 12:35:49 PM UTC 24 |
| Peak memory | 267908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222574443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1222574443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2617362662 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 300203279 ps |
| CPU time | 7.73 seconds |
| Started | Sep 11 12:30:31 PM UTC 24 |
| Finished | Sep 11 12:30:40 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617362662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2617362662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2873379 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 48782277550 ps |
| CPU time | 195.72 seconds |
| Started | Sep 11 12:30:35 PM UTC 24 |
| Finished | Sep 11 12:33:54 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.2873379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3279694661 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 144278628810 ps |
| CPU time | 118.17 seconds |
| Started | Sep 11 12:30:22 PM UTC 24 |
| Finished | Sep 11 12:32:22 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279694661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3279694661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.653273191 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6919276504 ps |
| CPU time | 8.42 seconds |
| Started | Sep 11 12:30:16 PM UTC 24 |
| Finished | Sep 11 12:30:25 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653273191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.653273191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3604750883 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13877133153 ps |
| CPU time | 19.59 seconds |
| Started | Sep 11 12:30:13 PM UTC 24 |
| Finished | Sep 11 12:30:33 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604750883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3604750883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2328784859 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 181209719 ps |
| CPU time | 5.31 seconds |
| Started | Sep 11 12:30:35 PM UTC 24 |
| Finished | Sep 11 12:30:41 PM UTC 24 |
| Peak memory | 231320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328784859 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.2328784859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.474744509 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 80114093 ps |
| CPU time | 1.56 seconds |
| Started | Sep 11 12:30:46 PM UTC 24 |
| Finished | Sep 11 12:30:49 PM UTC 24 |
| Peak memory | 257904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474744509 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.474744509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.4096513815 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 58666237 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 12:30:06 PM UTC 24 |
| Finished | Sep 11 12:30:09 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096513815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4096513815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3434006689 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 158256331 ps |
| CPU time | 2.37 seconds |
| Started | Sep 11 12:30:11 PM UTC 24 |
| Finished | Sep 11 12:30:15 PM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434006689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3434006689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2133521277 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 61380383 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 12:30:09 PM UTC 24 |
| Finished | Sep 11 12:30:12 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133521277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2133521277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.1680257878 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 16321221974 ps |
| CPU time | 57.04 seconds |
| Started | Sep 11 12:30:26 PM UTC 24 |
| Finished | Sep 11 12:31:25 PM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680257878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1680257878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.4137853124 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 73185821 ps |
| CPU time | 0.92 seconds |
| Started | Sep 11 12:37:39 PM UTC 24 |
| Finished | Sep 11 12:37:41 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137853124 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.4137853124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2340134671 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 406191741 ps |
| CPU time | 3.36 seconds |
| Started | Sep 11 12:37:18 PM UTC 24 |
| Finished | Sep 11 12:37:23 PM UTC 24 |
| Peak memory | 234016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340134671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2340134671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.1222064591 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 19573097 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 12:36:58 PM UTC 24 |
| Finished | Sep 11 12:37:00 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222064591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1222064591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1647340699 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 46560051283 ps |
| CPU time | 70.64 seconds |
| Started | Sep 11 12:37:26 PM UTC 24 |
| Finished | Sep 11 12:38:39 PM UTC 24 |
| Peak memory | 263836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647340699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1647340699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3535586076 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 14984422476 ps |
| CPU time | 93.75 seconds |
| Started | Sep 11 12:37:26 PM UTC 24 |
| Finished | Sep 11 12:39:02 PM UTC 24 |
| Peak memory | 267984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535586076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3535586076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.2082049147 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 30024603713 ps |
| CPU time | 322.21 seconds |
| Started | Sep 11 12:37:26 PM UTC 24 |
| Finished | Sep 11 12:42:53 PM UTC 24 |
| Peak memory | 267984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082049147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.2082049147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.556464751 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 754613582 ps |
| CPU time | 15.5 seconds |
| Started | Sep 11 12:37:21 PM UTC 24 |
| Finished | Sep 11 12:37:37 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556464751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.556464751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.521688442 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 11984725 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 12:37:23 PM UTC 24 |
| Finished | Sep 11 12:37:25 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521688442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.521688442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.742483718 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 97102476 ps |
| CPU time | 4.53 seconds |
| Started | Sep 11 12:37:11 PM UTC 24 |
| Finished | Sep 11 12:37:17 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742483718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.742483718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.237554589 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 6424553431 ps |
| CPU time | 30.95 seconds |
| Started | Sep 11 12:37:14 PM UTC 24 |
| Finished | Sep 11 12:37:47 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237554589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.237554589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.393217186 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1066644972 ps |
| CPU time | 12.28 seconds |
| Started | Sep 11 12:37:11 PM UTC 24 |
| Finished | Sep 11 12:37:25 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393217186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.393217186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1638587503 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 16573738481 ps |
| CPU time | 29.61 seconds |
| Started | Sep 11 12:37:07 PM UTC 24 |
| Finished | Sep 11 12:37:38 PM UTC 24 |
| Peak memory | 245372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638587503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1638587503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3668932449 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 8665404568 ps |
| CPU time | 24.99 seconds |
| Started | Sep 11 12:37:24 PM UTC 24 |
| Finished | Sep 11 12:37:50 PM UTC 24 |
| Peak memory | 231436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668932449 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.3668932449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.3008015449 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 64694259885 ps |
| CPU time | 357.33 seconds |
| Started | Sep 11 12:37:38 PM UTC 24 |
| Finished | Sep 11 12:43:40 PM UTC 24 |
| Peak memory | 278112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008015449 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.3008015449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.3950850514 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 19970098 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 12:37:01 PM UTC 24 |
| Finished | Sep 11 12:37:03 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950850514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3950850514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.107720419 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4905745572 ps |
| CPU time | 8.99 seconds |
| Started | Sep 11 12:37:01 PM UTC 24 |
| Finished | Sep 11 12:37:11 PM UTC 24 |
| Peak memory | 229668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107720419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.107720419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2765948913 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 370923190 ps |
| CPU time | 5.03 seconds |
| Started | Sep 11 12:37:07 PM UTC 24 |
| Finished | Sep 11 12:37:13 PM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765948913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2765948913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.3317745240 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 59974357 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 12:37:04 PM UTC 24 |
| Finished | Sep 11 12:37:06 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317745240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3317745240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.2156661984 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 37840710 ps |
| CPU time | 3.14 seconds |
| Started | Sep 11 12:37:17 PM UTC 24 |
| Finished | Sep 11 12:37:21 PM UTC 24 |
| Peak memory | 244892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156661984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2156661984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.4175591510 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 11556905 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:38:30 PM UTC 24 |
| Finished | Sep 11 12:38:32 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175591510 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.4175591510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2554219063 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 135626699 ps |
| CPU time | 3.31 seconds |
| Started | Sep 11 12:38:13 PM UTC 24 |
| Finished | Sep 11 12:38:17 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554219063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2554219063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.3478834108 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 68085857 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:37:42 PM UTC 24 |
| Finished | Sep 11 12:37:45 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478834108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3478834108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1818671077 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 15104070 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 12:38:19 PM UTC 24 |
| Finished | Sep 11 12:38:22 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818671077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1818671077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1895657862 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 50781878639 ps |
| CPU time | 233.39 seconds |
| Started | Sep 11 12:38:23 PM UTC 24 |
| Finished | Sep 11 12:42:19 PM UTC 24 |
| Peak memory | 267960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895657862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1895657862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1444115237 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 265673888550 ps |
| CPU time | 662.31 seconds |
| Started | Sep 11 12:38:25 PM UTC 24 |
| Finished | Sep 11 12:49:35 PM UTC 24 |
| Peak memory | 276120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444115237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.1444115237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.2755117724 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2144801645 ps |
| CPU time | 37.99 seconds |
| Started | Sep 11 12:38:15 PM UTC 24 |
| Finished | Sep 11 12:38:55 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755117724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2755117724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2567435889 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 25391906 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:38:16 PM UTC 24 |
| Finished | Sep 11 12:38:18 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567435889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.2567435889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3099643602 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 160395474 ps |
| CPU time | 5.1 seconds |
| Started | Sep 11 12:37:55 PM UTC 24 |
| Finished | Sep 11 12:38:01 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099643602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3099643602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1040447626 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1047579273 ps |
| CPU time | 12.84 seconds |
| Started | Sep 11 12:38:02 PM UTC 24 |
| Finished | Sep 11 12:38:16 PM UTC 24 |
| Peak memory | 235012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040447626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1040447626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.964608566 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 6200979148 ps |
| CPU time | 30.85 seconds |
| Started | Sep 11 12:37:54 PM UTC 24 |
| Finished | Sep 11 12:38:26 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964608566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.964608566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.736412945 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 5312248934 ps |
| CPU time | 13.96 seconds |
| Started | Sep 11 12:37:51 PM UTC 24 |
| Finished | Sep 11 12:38:06 PM UTC 24 |
| Peak memory | 245384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736412945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.736412945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1101885274 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1021385675 ps |
| CPU time | 14.09 seconds |
| Started | Sep 11 12:38:18 PM UTC 24 |
| Finished | Sep 11 12:38:34 PM UTC 24 |
| Peak memory | 231248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101885274 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.1101885274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1167408917 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 24484431016 ps |
| CPU time | 117.84 seconds |
| Started | Sep 11 12:38:27 PM UTC 24 |
| Finished | Sep 11 12:40:27 PM UTC 24 |
| Peak memory | 263716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167408917 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.1167408917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.3217246784 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 8616616834 ps |
| CPU time | 65.62 seconds |
| Started | Sep 11 12:37:48 PM UTC 24 |
| Finished | Sep 11 12:38:56 PM UTC 24 |
| Peak memory | 227512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217246784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3217246784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2020939091 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 12299347 ps |
| CPU time | 1.06 seconds |
| Started | Sep 11 12:37:47 PM UTC 24 |
| Finished | Sep 11 12:37:50 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020939091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2020939091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.1847775005 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 516692358 ps |
| CPU time | 2.06 seconds |
| Started | Sep 11 12:37:51 PM UTC 24 |
| Finished | Sep 11 12:37:54 PM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847775005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1847775005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2574082116 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 44063410 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 12:37:50 PM UTC 24 |
| Finished | Sep 11 12:37:53 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574082116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2574082116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1448175893 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 7875220435 ps |
| CPU time | 22.35 seconds |
| Started | Sep 11 12:38:07 PM UTC 24 |
| Finished | Sep 11 12:38:30 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448175893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1448175893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.274906185 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 13024329 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:39:01 PM UTC 24 |
| Finished | Sep 11 12:39:03 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274906185 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.274906185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.291775613 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 148359887 ps |
| CPU time | 5.86 seconds |
| Started | Sep 11 12:38:46 PM UTC 24 |
| Finished | Sep 11 12:38:53 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291775613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.291775613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.304255496 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 72194787 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 12:38:31 PM UTC 24 |
| Finished | Sep 11 12:38:33 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304255496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.304255496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.754281770 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 35843880954 ps |
| CPU time | 331.56 seconds |
| Started | Sep 11 12:38:56 PM UTC 24 |
| Finished | Sep 11 12:44:33 PM UTC 24 |
| Peak memory | 263748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754281770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.754281770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2455670717 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1248396952 ps |
| CPU time | 38.48 seconds |
| Started | Sep 11 12:38:57 PM UTC 24 |
| Finished | Sep 11 12:39:38 PM UTC 24 |
| Peak memory | 247424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455670717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2455670717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.948541017 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 19515141400 ps |
| CPU time | 36.8 seconds |
| Started | Sep 11 12:39:01 PM UTC 24 |
| Finished | Sep 11 12:39:39 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948541017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.948541017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.3626356854 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 8661368521 ps |
| CPU time | 44.2 seconds |
| Started | Sep 11 12:38:50 PM UTC 24 |
| Finished | Sep 11 12:39:35 PM UTC 24 |
| Peak memory | 261700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626356854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3626356854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.775653305 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 489548201 ps |
| CPU time | 5.77 seconds |
| Started | Sep 11 12:38:42 PM UTC 24 |
| Finished | Sep 11 12:38:49 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775653305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.775653305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.2190970400 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4776070728 ps |
| CPU time | 16.72 seconds |
| Started | Sep 11 12:38:42 PM UTC 24 |
| Finished | Sep 11 12:39:00 PM UTC 24 |
| Peak memory | 244980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190970400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2190970400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.4001699473 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 931600636 ps |
| CPU time | 8.19 seconds |
| Started | Sep 11 12:38:40 PM UTC 24 |
| Finished | Sep 11 12:38:49 PM UTC 24 |
| Peak memory | 234992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001699473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.4001699473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2646065285 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 134679953 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 12:38:40 PM UTC 24 |
| Finished | Sep 11 12:38:44 PM UTC 24 |
| Peak memory | 244852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646065285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2646065285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3348811269 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 79123958 ps |
| CPU time | 5.05 seconds |
| Started | Sep 11 12:38:54 PM UTC 24 |
| Finished | Sep 11 12:39:00 PM UTC 24 |
| Peak memory | 233728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348811269 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.3348811269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1791966111 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2824022172 ps |
| CPU time | 25.22 seconds |
| Started | Sep 11 12:38:34 PM UTC 24 |
| Finished | Sep 11 12:39:01 PM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791966111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1791966111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2051240945 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 17350981 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:38:34 PM UTC 24 |
| Finished | Sep 11 12:38:36 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051240945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2051240945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.1489008070 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 383994274 ps |
| CPU time | 2.15 seconds |
| Started | Sep 11 12:38:38 PM UTC 24 |
| Finished | Sep 11 12:38:41 PM UTC 24 |
| Peak memory | 227468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489008070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1489008070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1467271973 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 26095599 ps |
| CPU time | 1.03 seconds |
| Started | Sep 11 12:38:36 PM UTC 24 |
| Finished | Sep 11 12:38:39 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467271973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1467271973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3098163660 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 960211347 ps |
| CPU time | 15.3 seconds |
| Started | Sep 11 12:38:45 PM UTC 24 |
| Finished | Sep 11 12:39:02 PM UTC 24 |
| Peak memory | 247320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098163660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3098163660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.2092635299 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 16128194 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:40:08 PM UTC 24 |
| Finished | Sep 11 12:40:10 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092635299 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.2092635299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.2955246239 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 270267834 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 12:39:03 PM UTC 24 |
| Finished | Sep 11 12:39:05 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955246239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2955246239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.2219649304 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 36693636720 ps |
| CPU time | 380.67 seconds |
| Started | Sep 11 12:39:47 PM UTC 24 |
| Finished | Sep 11 12:46:13 PM UTC 24 |
| Peak memory | 277920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219649304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2219649304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.2859874448 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 54329329844 ps |
| CPU time | 589.78 seconds |
| Started | Sep 11 12:39:52 PM UTC 24 |
| Finished | Sep 11 12:49:49 PM UTC 24 |
| Peak memory | 280192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859874448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2859874448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3408802035 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 5507146828 ps |
| CPU time | 19.75 seconds |
| Started | Sep 11 12:39:42 PM UTC 24 |
| Finished | Sep 11 12:40:03 PM UTC 24 |
| Peak memory | 249428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408802035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3408802035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.953642618 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2563056030 ps |
| CPU time | 32.85 seconds |
| Started | Sep 11 12:39:44 PM UTC 24 |
| Finished | Sep 11 12:40:19 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953642618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.953642618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.1384802564 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 233510217 ps |
| CPU time | 5.77 seconds |
| Started | Sep 11 12:39:37 PM UTC 24 |
| Finished | Sep 11 12:39:43 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384802564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1384802564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.4179761103 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4093842876 ps |
| CPU time | 48.6 seconds |
| Started | Sep 11 12:39:39 PM UTC 24 |
| Finished | Sep 11 12:40:29 PM UTC 24 |
| Peak memory | 249496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179761103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4179761103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.40036166 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 9773331424 ps |
| CPU time | 18.18 seconds |
| Started | Sep 11 12:39:27 PM UTC 24 |
| Finished | Sep 11 12:39:47 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40036166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.40036166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.3178517471 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 19287227269 ps |
| CPU time | 29.65 seconds |
| Started | Sep 11 12:39:19 PM UTC 24 |
| Finished | Sep 11 12:39:50 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178517471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3178517471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.988070898 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 187823048 ps |
| CPU time | 4.16 seconds |
| Started | Sep 11 12:39:47 PM UTC 24 |
| Finished | Sep 11 12:39:53 PM UTC 24 |
| Peak memory | 231064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988070898 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.988070898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.239701928 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 917916357 ps |
| CPU time | 1.86 seconds |
| Started | Sep 11 12:40:04 PM UTC 24 |
| Finished | Sep 11 12:40:07 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239701928 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.239701928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.2393531448 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 16321072590 ps |
| CPU time | 29.93 seconds |
| Started | Sep 11 12:39:06 PM UTC 24 |
| Finished | Sep 11 12:39:37 PM UTC 24 |
| Peak memory | 227728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393531448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2393531448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3227076214 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 18556283609 ps |
| CPU time | 20.69 seconds |
| Started | Sep 11 12:39:05 PM UTC 24 |
| Finished | Sep 11 12:39:27 PM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227076214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3227076214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.774244812 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 113957582 ps |
| CPU time | 6.6 seconds |
| Started | Sep 11 12:39:11 PM UTC 24 |
| Finished | Sep 11 12:39:19 PM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774244812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.774244812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2570817842 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 168372679 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 12:39:07 PM UTC 24 |
| Finished | Sep 11 12:39:10 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570817842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2570817842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.2123127267 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 16202139096 ps |
| CPU time | 28.82 seconds |
| Started | Sep 11 12:39:39 PM UTC 24 |
| Finished | Sep 11 12:40:09 PM UTC 24 |
| Peak memory | 261656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123127267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2123127267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.1496671075 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 14219612 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:40:56 PM UTC 24 |
| Finished | Sep 11 12:40:58 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496671075 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.1496671075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.1302385352 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1410237228 ps |
| CPU time | 3.38 seconds |
| Started | Sep 11 12:40:35 PM UTC 24 |
| Finished | Sep 11 12:40:39 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302385352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1302385352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.3483744966 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 13266758 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 12:40:10 PM UTC 24 |
| Finished | Sep 11 12:40:12 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483744966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3483744966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.305216997 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 7455967956 ps |
| CPU time | 72.43 seconds |
| Started | Sep 11 12:40:41 PM UTC 24 |
| Finished | Sep 11 12:41:56 PM UTC 24 |
| Peak memory | 261832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305216997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.305216997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.1479324875 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 17251918187 ps |
| CPU time | 95.01 seconds |
| Started | Sep 11 12:40:50 PM UTC 24 |
| Finished | Sep 11 12:42:27 PM UTC 24 |
| Peak memory | 261760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479324875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1479324875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1223439522 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 14354878066 ps |
| CPU time | 69.12 seconds |
| Started | Sep 11 12:40:51 PM UTC 24 |
| Finished | Sep 11 12:42:01 PM UTC 24 |
| Peak memory | 261768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223439522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.1223439522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2788255125 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2644679322 ps |
| CPU time | 14.01 seconds |
| Started | Sep 11 12:40:40 PM UTC 24 |
| Finished | Sep 11 12:40:55 PM UTC 24 |
| Peak memory | 261696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788255125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2788255125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1884426743 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 19838722623 ps |
| CPU time | 38.61 seconds |
| Started | Sep 11 12:40:40 PM UTC 24 |
| Finished | Sep 11 12:41:20 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884426743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.1884426743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.281298566 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1425725023 ps |
| CPU time | 11.08 seconds |
| Started | Sep 11 12:40:27 PM UTC 24 |
| Finished | Sep 11 12:40:40 PM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281298566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.281298566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.2164851129 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 27938451545 ps |
| CPU time | 63.07 seconds |
| Started | Sep 11 12:40:27 PM UTC 24 |
| Finished | Sep 11 12:41:32 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164851129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2164851129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.324990517 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4610786556 ps |
| CPU time | 23.92 seconds |
| Started | Sep 11 12:40:24 PM UTC 24 |
| Finished | Sep 11 12:40:49 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324990517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.324990517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.4044346311 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3520502011 ps |
| CPU time | 16.04 seconds |
| Started | Sep 11 12:40:23 PM UTC 24 |
| Finished | Sep 11 12:40:40 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044346311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4044346311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.810011711 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1178992445 ps |
| CPU time | 8.37 seconds |
| Started | Sep 11 12:40:41 PM UTC 24 |
| Finished | Sep 11 12:40:51 PM UTC 24 |
| Peak memory | 231444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810011711 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.810011711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.3470568534 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 684375275 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 12:40:52 PM UTC 24 |
| Finished | Sep 11 12:40:55 PM UTC 24 |
| Peak memory | 215724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470568534 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.3470568534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.3581819882 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2782623765 ps |
| CPU time | 5.28 seconds |
| Started | Sep 11 12:40:15 PM UTC 24 |
| Finished | Sep 11 12:40:21 PM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581819882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3581819882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2418555214 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 5574675983 ps |
| CPU time | 8.5 seconds |
| Started | Sep 11 12:40:13 PM UTC 24 |
| Finished | Sep 11 12:40:23 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418555214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2418555214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.4110377662 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 214049503 ps |
| CPU time | 3.66 seconds |
| Started | Sep 11 12:40:22 PM UTC 24 |
| Finished | Sep 11 12:40:26 PM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110377662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4110377662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.781802501 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 28171712 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 12:40:20 PM UTC 24 |
| Finished | Sep 11 12:40:22 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781802501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.781802501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.3038740973 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 680177447 ps |
| CPU time | 8.68 seconds |
| Started | Sep 11 12:40:30 PM UTC 24 |
| Finished | Sep 11 12:40:39 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038740973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3038740973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.2626890166 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 18636255 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 12:41:36 PM UTC 24 |
| Finished | Sep 11 12:41:39 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626890166 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.2626890166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2404257536 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 4140029734 ps |
| CPU time | 8.99 seconds |
| Started | Sep 11 12:41:22 PM UTC 24 |
| Finished | Sep 11 12:41:32 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404257536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2404257536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.933949424 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 56915622 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 12:40:56 PM UTC 24 |
| Finished | Sep 11 12:40:58 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933949424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.933949424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.4199372486 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5630326451 ps |
| CPU time | 93.17 seconds |
| Started | Sep 11 12:41:32 PM UTC 24 |
| Finished | Sep 11 12:43:07 PM UTC 24 |
| Peak memory | 265796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199372486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4199372486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.78591865 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 10105103918 ps |
| CPU time | 50.68 seconds |
| Started | Sep 11 12:41:33 PM UTC 24 |
| Finished | Sep 11 12:42:25 PM UTC 24 |
| Peak memory | 263788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78591865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.78591865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.4232700290 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 641087786 ps |
| CPU time | 11.12 seconds |
| Started | Sep 11 12:41:22 PM UTC 24 |
| Finished | Sep 11 12:41:34 PM UTC 24 |
| Peak memory | 249300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232700290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4232700290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1055053777 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 9123851189 ps |
| CPU time | 44.77 seconds |
| Started | Sep 11 12:41:28 PM UTC 24 |
| Finished | Sep 11 12:42:14 PM UTC 24 |
| Peak memory | 261724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055053777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.1055053777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3846037998 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1819667840 ps |
| CPU time | 17.45 seconds |
| Started | Sep 11 12:41:17 PM UTC 24 |
| Finished | Sep 11 12:41:36 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846037998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3846037998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.1112631134 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 767275404 ps |
| CPU time | 9.9 seconds |
| Started | Sep 11 12:41:21 PM UTC 24 |
| Finished | Sep 11 12:41:32 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112631134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1112631134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2740097291 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1911487483 ps |
| CPU time | 7.91 seconds |
| Started | Sep 11 12:41:12 PM UTC 24 |
| Finished | Sep 11 12:41:21 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740097291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.2740097291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1606579717 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1392659350 ps |
| CPU time | 5.62 seconds |
| Started | Sep 11 12:41:10 PM UTC 24 |
| Finished | Sep 11 12:41:17 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606579717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1606579717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.4176537929 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6821061774 ps |
| CPU time | 20.74 seconds |
| Started | Sep 11 12:41:29 PM UTC 24 |
| Finished | Sep 11 12:41:51 PM UTC 24 |
| Peak memory | 231440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176537929 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.4176537929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.3675844898 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 99150305 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 12:41:34 PM UTC 24 |
| Finished | Sep 11 12:41:37 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675844898 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.3675844898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.456819005 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3635876863 ps |
| CPU time | 27.03 seconds |
| Started | Sep 11 12:40:59 PM UTC 24 |
| Finished | Sep 11 12:41:28 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456819005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.456819005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2719050300 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 6514184479 ps |
| CPU time | 10.37 seconds |
| Started | Sep 11 12:40:59 PM UTC 24 |
| Finished | Sep 11 12:41:11 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719050300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2719050300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.2996595720 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 318571287 ps |
| CPU time | 2.34 seconds |
| Started | Sep 11 12:41:06 PM UTC 24 |
| Finished | Sep 11 12:41:09 PM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996595720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2996595720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.2797247742 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 61622010 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 12:41:03 PM UTC 24 |
| Finished | Sep 11 12:41:05 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797247742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2797247742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2145966737 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2589361838 ps |
| CPU time | 4.6 seconds |
| Started | Sep 11 12:41:21 PM UTC 24 |
| Finished | Sep 11 12:41:27 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145966737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2145966737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.356390996 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 14861165 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 12:42:26 PM UTC 24 |
| Finished | Sep 11 12:42:29 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356390996 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.356390996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3985623397 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2252138285 ps |
| CPU time | 10.01 seconds |
| Started | Sep 11 12:42:06 PM UTC 24 |
| Finished | Sep 11 12:42:17 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985623397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3985623397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.609855571 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 22201866 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 12:41:38 PM UTC 24 |
| Finished | Sep 11 12:41:40 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609855571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.609855571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.376669390 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2942799722 ps |
| CPU time | 55.88 seconds |
| Started | Sep 11 12:42:18 PM UTC 24 |
| Finished | Sep 11 12:43:15 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376669390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.376669390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3207242839 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 51830915503 ps |
| CPU time | 251.04 seconds |
| Started | Sep 11 12:42:21 PM UTC 24 |
| Finished | Sep 11 12:46:36 PM UTC 24 |
| Peak memory | 261812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207242839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3207242839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.4048749355 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1582564520 ps |
| CPU time | 36.19 seconds |
| Started | Sep 11 12:42:09 PM UTC 24 |
| Finished | Sep 11 12:42:47 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048749355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4048749355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.1232276917 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 12306821084 ps |
| CPU time | 106.25 seconds |
| Started | Sep 11 12:42:10 PM UTC 24 |
| Finished | Sep 11 12:43:59 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232276917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.1232276917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.1796733175 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 103733027 ps |
| CPU time | 6.35 seconds |
| Started | Sep 11 12:42:01 PM UTC 24 |
| Finished | Sep 11 12:42:08 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796733175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1796733175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.3790515329 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 5659593905 ps |
| CPU time | 16.11 seconds |
| Started | Sep 11 12:42:03 PM UTC 24 |
| Finished | Sep 11 12:42:20 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790515329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3790515329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.352258150 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 15616916303 ps |
| CPU time | 8.45 seconds |
| Started | Sep 11 12:42:00 PM UTC 24 |
| Finished | Sep 11 12:42:09 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352258150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.352258150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1629373716 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 454813446 ps |
| CPU time | 6.02 seconds |
| Started | Sep 11 12:41:56 PM UTC 24 |
| Finished | Sep 11 12:42:03 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629373716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1629373716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1771313767 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2408757592 ps |
| CPU time | 10.2 seconds |
| Started | Sep 11 12:42:15 PM UTC 24 |
| Finished | Sep 11 12:42:27 PM UTC 24 |
| Peak memory | 231376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771313767 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.1771313767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.1789188695 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2003864576 ps |
| CPU time | 20.61 seconds |
| Started | Sep 11 12:41:43 PM UTC 24 |
| Finished | Sep 11 12:42:05 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789188695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1789188695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.1232941615 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 32104564383 ps |
| CPU time | 17.46 seconds |
| Started | Sep 11 12:41:41 PM UTC 24 |
| Finished | Sep 11 12:41:59 PM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232941615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1232941615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.2274742969 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 217693695 ps |
| CPU time | 2.47 seconds |
| Started | Sep 11 12:41:55 PM UTC 24 |
| Finished | Sep 11 12:41:59 PM UTC 24 |
| Peak memory | 227468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274742969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2274742969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2201018185 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 28085306 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 12:41:52 PM UTC 24 |
| Finished | Sep 11 12:41:54 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201018185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2201018185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.1226375724 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1666684709 ps |
| CPU time | 18.61 seconds |
| Started | Sep 11 12:42:04 PM UTC 24 |
| Finished | Sep 11 12:42:24 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226375724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1226375724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.3805571992 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 18498101 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 12:43:08 PM UTC 24 |
| Finished | Sep 11 12:43:11 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805571992 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3805571992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.332707080 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 4207028742 ps |
| CPU time | 23.17 seconds |
| Started | Sep 11 12:42:46 PM UTC 24 |
| Finished | Sep 11 12:43:11 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332707080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.332707080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.873786719 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 14193877 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:42:27 PM UTC 24 |
| Finished | Sep 11 12:42:30 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873786719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.873786719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.33029038 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 61855872688 ps |
| CPU time | 148.13 seconds |
| Started | Sep 11 12:42:54 PM UTC 24 |
| Finished | Sep 11 12:45:25 PM UTC 24 |
| Peak memory | 261692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33029038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.33029038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.572201702 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5865628519 ps |
| CPU time | 28.07 seconds |
| Started | Sep 11 12:42:58 PM UTC 24 |
| Finished | Sep 11 12:43:27 PM UTC 24 |
| Peak memory | 235140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572201702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.572201702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.856230068 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 29978063335 ps |
| CPU time | 40.23 seconds |
| Started | Sep 11 12:43:02 PM UTC 24 |
| Finished | Sep 11 12:43:44 PM UTC 24 |
| Peak memory | 229656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856230068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.856230068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.746002077 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3442664724 ps |
| CPU time | 22.97 seconds |
| Started | Sep 11 12:42:48 PM UTC 24 |
| Finished | Sep 11 12:43:12 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746002077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.746002077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.4150476404 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1209223362 ps |
| CPU time | 8.49 seconds |
| Started | Sep 11 12:42:48 PM UTC 24 |
| Finished | Sep 11 12:42:57 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150476404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.4150476404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.2831768037 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1211970031 ps |
| CPU time | 8.66 seconds |
| Started | Sep 11 12:42:35 PM UTC 24 |
| Finished | Sep 11 12:42:45 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831768037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2831768037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.1890690241 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 79431097803 ps |
| CPU time | 44.42 seconds |
| Started | Sep 11 12:42:40 PM UTC 24 |
| Finished | Sep 11 12:43:26 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890690241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1890690241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.4278787201 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 5885297549 ps |
| CPU time | 10.91 seconds |
| Started | Sep 11 12:42:35 PM UTC 24 |
| Finished | Sep 11 12:42:47 PM UTC 24 |
| Peak memory | 235016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278787201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.4278787201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.2156553044 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5403246580 ps |
| CPU time | 9.9 seconds |
| Started | Sep 11 12:42:32 PM UTC 24 |
| Finished | Sep 11 12:42:43 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156553044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2156553044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.640305057 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 234256971 ps |
| CPU time | 6.65 seconds |
| Started | Sep 11 12:42:54 PM UTC 24 |
| Finished | Sep 11 12:43:02 PM UTC 24 |
| Peak memory | 231316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640305057 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.640305057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2882593861 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 12081097621 ps |
| CPU time | 84.74 seconds |
| Started | Sep 11 12:43:08 PM UTC 24 |
| Finished | Sep 11 12:44:35 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882593861 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.2882593861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.324324863 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2325305146 ps |
| CPU time | 36.14 seconds |
| Started | Sep 11 12:42:29 PM UTC 24 |
| Finished | Sep 11 12:43:07 PM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324324863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.324324863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.738869623 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3797150877 ps |
| CPU time | 10.4 seconds |
| Started | Sep 11 12:42:27 PM UTC 24 |
| Finished | Sep 11 12:42:39 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738869623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.738869623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.1644543903 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 24367057 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 12:42:31 PM UTC 24 |
| Finished | Sep 11 12:42:34 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644543903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1644543903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1817282224 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 96854109 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 12:42:31 PM UTC 24 |
| Finished | Sep 11 12:42:34 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817282224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1817282224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.468539033 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6225236128 ps |
| CPU time | 7.31 seconds |
| Started | Sep 11 12:42:44 PM UTC 24 |
| Finished | Sep 11 12:42:53 PM UTC 24 |
| Peak memory | 249376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468539033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.468539033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.590141512 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 65827535 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 12:43:41 PM UTC 24 |
| Finished | Sep 11 12:43:43 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590141512 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.590141512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.852721132 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 168651576 ps |
| CPU time | 2.61 seconds |
| Started | Sep 11 12:43:27 PM UTC 24 |
| Finished | Sep 11 12:43:31 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852721132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.852721132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.1927140909 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 21342907 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 12:43:12 PM UTC 24 |
| Finished | Sep 11 12:43:14 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927140909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1927140909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.3256910296 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1803704426 ps |
| CPU time | 28.62 seconds |
| Started | Sep 11 12:43:31 PM UTC 24 |
| Finished | Sep 11 12:44:01 PM UTC 24 |
| Peak memory | 267724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256910296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3256910296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2223154087 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 53773188392 ps |
| CPU time | 96.77 seconds |
| Started | Sep 11 12:43:32 PM UTC 24 |
| Finished | Sep 11 12:45:11 PM UTC 24 |
| Peak memory | 261696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223154087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2223154087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.261110086 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 4722740363 ps |
| CPU time | 18.75 seconds |
| Started | Sep 11 12:43:27 PM UTC 24 |
| Finished | Sep 11 12:43:47 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261110086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.261110086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3772407897 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 4615376360 ps |
| CPU time | 22.69 seconds |
| Started | Sep 11 12:43:28 PM UTC 24 |
| Finished | Sep 11 12:43:52 PM UTC 24 |
| Peak memory | 263884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772407897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.3772407897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.2540554231 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2926211949 ps |
| CPU time | 11.07 seconds |
| Started | Sep 11 12:43:18 PM UTC 24 |
| Finished | Sep 11 12:43:30 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540554231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2540554231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.53002533 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1183803868 ps |
| CPU time | 9.63 seconds |
| Started | Sep 11 12:43:19 PM UTC 24 |
| Finished | Sep 11 12:43:30 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53002533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.53002533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1163461430 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 21779303817 ps |
| CPU time | 36.93 seconds |
| Started | Sep 11 12:43:16 PM UTC 24 |
| Finished | Sep 11 12:43:54 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163461430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.1163461430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.81599852 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 27988448346 ps |
| CPU time | 26.96 seconds |
| Started | Sep 11 12:43:15 PM UTC 24 |
| Finished | Sep 11 12:43:44 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81599852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.81599852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.4235105234 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 73011375 ps |
| CPU time | 3.17 seconds |
| Started | Sep 11 12:43:31 PM UTC 24 |
| Finished | Sep 11 12:43:35 PM UTC 24 |
| Peak memory | 231240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235105234 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.4235105234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.2704539794 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 31632682777 ps |
| CPU time | 212.53 seconds |
| Started | Sep 11 12:43:39 PM UTC 24 |
| Finished | Sep 11 12:47:15 PM UTC 24 |
| Peak memory | 267944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704539794 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.2704539794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.442955169 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1068355948 ps |
| CPU time | 10.78 seconds |
| Started | Sep 11 12:43:14 PM UTC 24 |
| Finished | Sep 11 12:43:26 PM UTC 24 |
| Peak memory | 231512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442955169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.442955169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2438819549 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1616381135 ps |
| CPU time | 8.41 seconds |
| Started | Sep 11 12:43:13 PM UTC 24 |
| Finished | Sep 11 12:43:22 PM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438819549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2438819549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.4265023450 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 79453788 ps |
| CPU time | 1.82 seconds |
| Started | Sep 11 12:43:15 PM UTC 24 |
| Finished | Sep 11 12:43:18 PM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265023450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4265023450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.969567389 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 99025416 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 12:43:14 PM UTC 24 |
| Finished | Sep 11 12:43:17 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969567389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.969567389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.4039207756 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 12091915934 ps |
| CPU time | 17.37 seconds |
| Started | Sep 11 12:43:23 PM UTC 24 |
| Finished | Sep 11 12:43:42 PM UTC 24 |
| Peak memory | 247368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039207756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4039207756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.3890448779 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 97012496 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 12:44:02 PM UTC 24 |
| Finished | Sep 11 12:44:04 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890448779 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.3890448779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2154389925 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 34220699 ps |
| CPU time | 2.75 seconds |
| Started | Sep 11 12:43:54 PM UTC 24 |
| Finished | Sep 11 12:43:57 PM UTC 24 |
| Peak memory | 244888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154389925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2154389925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.992378803 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 28849833 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 12:43:42 PM UTC 24 |
| Finished | Sep 11 12:43:44 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992378803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.992378803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.2447852749 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 33791258094 ps |
| CPU time | 124.04 seconds |
| Started | Sep 11 12:43:59 PM UTC 24 |
| Finished | Sep 11 12:46:05 PM UTC 24 |
| Peak memory | 276040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447852749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2447852749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.1719490703 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 237094329399 ps |
| CPU time | 216.7 seconds |
| Started | Sep 11 12:43:59 PM UTC 24 |
| Finished | Sep 11 12:47:39 PM UTC 24 |
| Peak memory | 263804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719490703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1719490703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.324878462 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3851142175 ps |
| CPU time | 24.8 seconds |
| Started | Sep 11 12:43:55 PM UTC 24 |
| Finished | Sep 11 12:44:21 PM UTC 24 |
| Peak memory | 251588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324878462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.324878462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3190359695 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 4636799310 ps |
| CPU time | 26.68 seconds |
| Started | Sep 11 12:43:56 PM UTC 24 |
| Finished | Sep 11 12:44:24 PM UTC 24 |
| Peak memory | 261724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190359695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.3190359695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.1797270700 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 3883173113 ps |
| CPU time | 9.45 seconds |
| Started | Sep 11 12:43:49 PM UTC 24 |
| Finished | Sep 11 12:44:00 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797270700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1797270700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.1845739146 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1390379939 ps |
| CPU time | 10.93 seconds |
| Started | Sep 11 12:43:52 PM UTC 24 |
| Finished | Sep 11 12:44:04 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845739146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1845739146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3403036925 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4234923045 ps |
| CPU time | 29.83 seconds |
| Started | Sep 11 12:43:49 PM UTC 24 |
| Finished | Sep 11 12:44:20 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403036925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.3403036925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.4099075869 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 960803527 ps |
| CPU time | 8.99 seconds |
| Started | Sep 11 12:43:48 PM UTC 24 |
| Finished | Sep 11 12:43:58 PM UTC 24 |
| Peak memory | 234944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099075869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4099075869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1810844446 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1019386247 ps |
| CPU time | 13.74 seconds |
| Started | Sep 11 12:43:58 PM UTC 24 |
| Finished | Sep 11 12:44:13 PM UTC 24 |
| Peak memory | 233312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810844446 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1810844446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.3692451952 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 33227394081 ps |
| CPU time | 93.02 seconds |
| Started | Sep 11 12:44:02 PM UTC 24 |
| Finished | Sep 11 12:45:37 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692451952 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.3692451952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3684751765 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 13808256743 ps |
| CPU time | 34.41 seconds |
| Started | Sep 11 12:43:45 PM UTC 24 |
| Finished | Sep 11 12:44:20 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684751765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3684751765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.71817556 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 418555991 ps |
| CPU time | 2.58 seconds |
| Started | Sep 11 12:43:45 PM UTC 24 |
| Finished | Sep 11 12:43:48 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71817556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.71817556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.542345485 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 160584272 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 12:43:48 PM UTC 24 |
| Finished | Sep 11 12:43:51 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542345485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.542345485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.195205646 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 124938497 ps |
| CPU time | 1.51 seconds |
| Started | Sep 11 12:43:46 PM UTC 24 |
| Finished | Sep 11 12:43:48 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195205646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.195205646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.2962566195 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2192499195 ps |
| CPU time | 12.33 seconds |
| Started | Sep 11 12:43:52 PM UTC 24 |
| Finished | Sep 11 12:44:05 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962566195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2962566195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.3086618308 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 13552308 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 12:32:07 PM UTC 24 |
| Finished | Sep 11 12:32:09 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086618308 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3086618308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.429398459 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 877607375 ps |
| CPU time | 8.41 seconds |
| Started | Sep 11 12:31:31 PM UTC 24 |
| Finished | Sep 11 12:31:40 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429398459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.429398459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.3109298375 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 20007933 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:30:52 PM UTC 24 |
| Finished | Sep 11 12:30:55 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109298375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3109298375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.651928005 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 11908325414 ps |
| CPU time | 167.69 seconds |
| Started | Sep 11 12:31:52 PM UTC 24 |
| Finished | Sep 11 12:34:43 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651928005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.651928005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.3725903214 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9028612333 ps |
| CPU time | 38.35 seconds |
| Started | Sep 11 12:31:52 PM UTC 24 |
| Finished | Sep 11 12:32:32 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725903214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3725903214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1246112644 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 10778654146 ps |
| CPU time | 134.45 seconds |
| Started | Sep 11 12:31:53 PM UTC 24 |
| Finished | Sep 11 12:34:10 PM UTC 24 |
| Peak memory | 235112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246112644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.1246112644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.242519297 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 8235043252 ps |
| CPU time | 43.33 seconds |
| Started | Sep 11 12:31:41 PM UTC 24 |
| Finished | Sep 11 12:32:26 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242519297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.242519297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.36071934 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 612940525 ps |
| CPU time | 7.68 seconds |
| Started | Sep 11 12:31:20 PM UTC 24 |
| Finished | Sep 11 12:31:29 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36071934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.36071934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3346341327 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 764965001 ps |
| CPU time | 24.1 seconds |
| Started | Sep 11 12:31:25 PM UTC 24 |
| Finished | Sep 11 12:31:51 PM UTC 24 |
| Peak memory | 261596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346341327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3346341327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.1598986479 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 33728595 ps |
| CPU time | 3.35 seconds |
| Started | Sep 11 12:31:15 PM UTC 24 |
| Finished | Sep 11 12:31:20 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598986479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.1598986479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3089108024 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3513275099 ps |
| CPU time | 19.72 seconds |
| Started | Sep 11 12:31:12 PM UTC 24 |
| Finished | Sep 11 12:31:33 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089108024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3089108024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2831108285 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3249256050 ps |
| CPU time | 22.61 seconds |
| Started | Sep 11 12:31:47 PM UTC 24 |
| Finished | Sep 11 12:32:11 PM UTC 24 |
| Peak memory | 233508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831108285 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.2831108285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3965333051 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 84446433 ps |
| CPU time | 1.94 seconds |
| Started | Sep 11 12:32:03 PM UTC 24 |
| Finished | Sep 11 12:32:06 PM UTC 24 |
| Peak memory | 259948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965333051 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3965333051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2598096710 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 245700970 ps |
| CPU time | 4.47 seconds |
| Started | Sep 11 12:30:59 PM UTC 24 |
| Finished | Sep 11 12:31:04 PM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598096710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2598096710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3255153100 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 29912655 ps |
| CPU time | 1.82 seconds |
| Started | Sep 11 12:31:08 PM UTC 24 |
| Finished | Sep 11 12:31:11 PM UTC 24 |
| Peak memory | 226388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255153100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3255153100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1355904028 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 64960894 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 12:31:05 PM UTC 24 |
| Finished | Sep 11 12:31:07 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355904028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1355904028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.2929603432 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3646143682 ps |
| CPU time | 16.66 seconds |
| Started | Sep 11 12:31:28 PM UTC 24 |
| Finished | Sep 11 12:31:46 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929603432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2929603432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.682392808 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 47916142 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:44:31 PM UTC 24 |
| Finished | Sep 11 12:44:33 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682392808 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.682392808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.4141077874 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 34755270 ps |
| CPU time | 3.27 seconds |
| Started | Sep 11 12:44:20 PM UTC 24 |
| Finished | Sep 11 12:44:24 PM UTC 24 |
| Peak memory | 244888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141077874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4141077874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2628743331 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 16066755 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:44:05 PM UTC 24 |
| Finished | Sep 11 12:44:07 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628743331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2628743331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.3414194697 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 120282012555 ps |
| CPU time | 426.69 seconds |
| Started | Sep 11 12:44:22 PM UTC 24 |
| Finished | Sep 11 12:51:34 PM UTC 24 |
| Peak memory | 265800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414194697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3414194697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2680455780 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 39131080187 ps |
| CPU time | 130.81 seconds |
| Started | Sep 11 12:44:25 PM UTC 24 |
| Finished | Sep 11 12:46:38 PM UTC 24 |
| Peak memory | 261760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680455780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2680455780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3313501848 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 72673563791 ps |
| CPU time | 154.48 seconds |
| Started | Sep 11 12:44:25 PM UTC 24 |
| Finished | Sep 11 12:47:02 PM UTC 24 |
| Peak memory | 265880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313501848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.3313501848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.1387169019 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 13501258188 ps |
| CPU time | 21.95 seconds |
| Started | Sep 11 12:44:22 PM UTC 24 |
| Finished | Sep 11 12:44:45 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387169019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1387169019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.2986425058 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 233338575359 ps |
| CPU time | 298.14 seconds |
| Started | Sep 11 12:44:22 PM UTC 24 |
| Finished | Sep 11 12:49:24 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986425058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.2986425058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.3456982953 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 237217927 ps |
| CPU time | 3.36 seconds |
| Started | Sep 11 12:44:16 PM UTC 24 |
| Finished | Sep 11 12:44:20 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456982953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3456982953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.557793444 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 66095066869 ps |
| CPU time | 144.86 seconds |
| Started | Sep 11 12:44:18 PM UTC 24 |
| Finished | Sep 11 12:46:45 PM UTC 24 |
| Peak memory | 247312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557793444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.557793444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.3221631588 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 410323839 ps |
| CPU time | 4.18 seconds |
| Started | Sep 11 12:44:14 PM UTC 24 |
| Finished | Sep 11 12:44:19 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221631588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.3221631588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.2140273621 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3793417792 ps |
| CPU time | 4.1 seconds |
| Started | Sep 11 12:44:12 PM UTC 24 |
| Finished | Sep 11 12:44:18 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140273621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2140273621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2586292952 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 612061778 ps |
| CPU time | 7.44 seconds |
| Started | Sep 11 12:44:22 PM UTC 24 |
| Finished | Sep 11 12:44:30 PM UTC 24 |
| Peak memory | 233628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586292952 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.2586292952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.3078410186 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 48688887112 ps |
| CPU time | 526.41 seconds |
| Started | Sep 11 12:44:31 PM UTC 24 |
| Finished | Sep 11 12:53:24 PM UTC 24 |
| Peak memory | 278196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078410186 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.3078410186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.405972851 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1010540427 ps |
| CPU time | 7.77 seconds |
| Started | Sep 11 12:44:06 PM UTC 24 |
| Finished | Sep 11 12:44:15 PM UTC 24 |
| Peak memory | 229656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405972851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.405972851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.274340811 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1093989087 ps |
| CPU time | 3.61 seconds |
| Started | Sep 11 12:44:05 PM UTC 24 |
| Finished | Sep 11 12:44:10 PM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274340811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.274340811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.3092075816 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 533928198 ps |
| CPU time | 5.14 seconds |
| Started | Sep 11 12:44:10 PM UTC 24 |
| Finished | Sep 11 12:44:17 PM UTC 24 |
| Peak memory | 227468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092075816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3092075816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1421529244 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 27727698 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 12:44:08 PM UTC 24 |
| Finished | Sep 11 12:44:11 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421529244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1421529244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.3113353544 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 24039167700 ps |
| CPU time | 35.37 seconds |
| Started | Sep 11 12:44:19 PM UTC 24 |
| Finished | Sep 11 12:44:56 PM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113353544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3113353544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.1367272066 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 91140637 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 12:45:14 PM UTC 24 |
| Finished | Sep 11 12:45:16 PM UTC 24 |
| Peak memory | 215728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367272066 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1367272066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.4059142054 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 297898318 ps |
| CPU time | 6.63 seconds |
| Started | Sep 11 12:44:51 PM UTC 24 |
| Finished | Sep 11 12:44:59 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059142054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4059142054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2321497565 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 19995853 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 12:44:32 PM UTC 24 |
| Finished | Sep 11 12:44:35 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321497565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2321497565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.2374037470 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 10747760421 ps |
| CPU time | 109.27 seconds |
| Started | Sep 11 12:45:06 PM UTC 24 |
| Finished | Sep 11 12:46:57 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374037470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2374037470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3073575255 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 12981351061 ps |
| CPU time | 144.55 seconds |
| Started | Sep 11 12:45:08 PM UTC 24 |
| Finished | Sep 11 12:47:35 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073575255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3073575255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3354040767 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 39979810665 ps |
| CPU time | 223.21 seconds |
| Started | Sep 11 12:45:12 PM UTC 24 |
| Finished | Sep 11 12:48:59 PM UTC 24 |
| Peak memory | 265944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354040767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.3354040767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3873256570 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1615113155 ps |
| CPU time | 31.12 seconds |
| Started | Sep 11 12:44:57 PM UTC 24 |
| Finished | Sep 11 12:45:30 PM UTC 24 |
| Peak memory | 245924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873256570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3873256570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.283993663 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 4793026269 ps |
| CPU time | 24.62 seconds |
| Started | Sep 11 12:44:40 PM UTC 24 |
| Finished | Sep 11 12:45:06 PM UTC 24 |
| Peak memory | 235140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283993663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.283993663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.679679288 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3710309629 ps |
| CPU time | 36.5 seconds |
| Started | Sep 11 12:44:46 PM UTC 24 |
| Finished | Sep 11 12:45:24 PM UTC 24 |
| Peak memory | 261664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679679288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.679679288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3465822158 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 683732924 ps |
| CPU time | 8.28 seconds |
| Started | Sep 11 12:44:40 PM UTC 24 |
| Finished | Sep 11 12:44:50 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465822158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3465822158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.2160063992 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 124000564 ps |
| CPU time | 5.31 seconds |
| Started | Sep 11 12:44:39 PM UTC 24 |
| Finished | Sep 11 12:44:45 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160063992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2160063992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1192145078 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 4445378134 ps |
| CPU time | 13.23 seconds |
| Started | Sep 11 12:44:59 PM UTC 24 |
| Finished | Sep 11 12:45:14 PM UTC 24 |
| Peak memory | 231376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192145078 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.1192145078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1213498091 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 14400781576 ps |
| CPU time | 108.04 seconds |
| Started | Sep 11 12:45:12 PM UTC 24 |
| Finished | Sep 11 12:47:02 PM UTC 24 |
| Peak memory | 265868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213498091 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.1213498091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2303567228 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 6332927173 ps |
| CPU time | 34.75 seconds |
| Started | Sep 11 12:44:35 PM UTC 24 |
| Finished | Sep 11 12:45:11 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303567228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2303567228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.4196752038 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1530046314 ps |
| CPU time | 4.09 seconds |
| Started | Sep 11 12:44:35 PM UTC 24 |
| Finished | Sep 11 12:44:40 PM UTC 24 |
| Peak memory | 227324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196752038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4196752038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.3045993113 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 166643994 ps |
| CPU time | 1.99 seconds |
| Started | Sep 11 12:44:36 PM UTC 24 |
| Finished | Sep 11 12:44:39 PM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045993113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3045993113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.367003741 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 202556323 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 12:44:36 PM UTC 24 |
| Finished | Sep 11 12:44:38 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367003741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.367003741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.4254012966 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 3918745153 ps |
| CPU time | 8.84 seconds |
| Started | Sep 11 12:44:47 PM UTC 24 |
| Finished | Sep 11 12:44:57 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254012966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4254012966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.2793419240 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 40052623 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:45:49 PM UTC 24 |
| Finished | Sep 11 12:45:52 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793419240 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.2793419240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2373905269 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1237336318 ps |
| CPU time | 16.14 seconds |
| Started | Sep 11 12:45:30 PM UTC 24 |
| Finished | Sep 11 12:45:47 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373905269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2373905269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.3269047711 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 31802096 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 12:45:17 PM UTC 24 |
| Finished | Sep 11 12:45:19 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269047711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3269047711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.641530277 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 7992772531 ps |
| CPU time | 50.47 seconds |
| Started | Sep 11 12:45:41 PM UTC 24 |
| Finished | Sep 11 12:46:33 PM UTC 24 |
| Peak memory | 265796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641530277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.641530277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3675238376 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 133905799781 ps |
| CPU time | 728.11 seconds |
| Started | Sep 11 12:45:41 PM UTC 24 |
| Finished | Sep 11 12:57:59 PM UTC 24 |
| Peak memory | 282100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675238376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3675238376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1029765957 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 4509448777 ps |
| CPU time | 21 seconds |
| Started | Sep 11 12:45:45 PM UTC 24 |
| Finished | Sep 11 12:46:08 PM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029765957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.1029765957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.1869027047 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 801914495 ps |
| CPU time | 11.76 seconds |
| Started | Sep 11 12:45:31 PM UTC 24 |
| Finished | Sep 11 12:45:44 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869027047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1869027047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.1606208878 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 17700282 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 12:45:38 PM UTC 24 |
| Finished | Sep 11 12:45:40 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606208878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.1606208878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.1848990645 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1799255669 ps |
| CPU time | 9.49 seconds |
| Started | Sep 11 12:45:26 PM UTC 24 |
| Finished | Sep 11 12:45:36 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848990645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1848990645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.3793758559 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2729840962 ps |
| CPU time | 35.79 seconds |
| Started | Sep 11 12:45:28 PM UTC 24 |
| Finished | Sep 11 12:46:05 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793758559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3793758559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3819020886 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 3715746783 ps |
| CPU time | 14.14 seconds |
| Started | Sep 11 12:45:24 PM UTC 24 |
| Finished | Sep 11 12:45:40 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819020886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.3819020886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.2155490443 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2727643915 ps |
| CPU time | 6.1 seconds |
| Started | Sep 11 12:45:23 PM UTC 24 |
| Finished | Sep 11 12:45:30 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155490443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2155490443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1944104769 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 6969904636 ps |
| CPU time | 14.25 seconds |
| Started | Sep 11 12:45:38 PM UTC 24 |
| Finished | Sep 11 12:45:53 PM UTC 24 |
| Peak memory | 233764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944104769 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.1944104769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.513910024 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 33029792652 ps |
| CPU time | 28.02 seconds |
| Started | Sep 11 12:45:19 PM UTC 24 |
| Finished | Sep 11 12:45:48 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513910024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.513910024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2035034350 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 315910805 ps |
| CPU time | 2.11 seconds |
| Started | Sep 11 12:45:19 PM UTC 24 |
| Finished | Sep 11 12:45:22 PM UTC 24 |
| Peak memory | 216448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035034350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2035034350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.3756923189 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 130820743 ps |
| CPU time | 3.06 seconds |
| Started | Sep 11 12:45:23 PM UTC 24 |
| Finished | Sep 11 12:45:27 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756923189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3756923189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.240041694 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 124820312 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 12:45:20 PM UTC 24 |
| Finished | Sep 11 12:45:22 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240041694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.240041694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.969934850 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4656909815 ps |
| CPU time | 34.57 seconds |
| Started | Sep 11 12:45:28 PM UTC 24 |
| Finished | Sep 11 12:46:04 PM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969934850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.969934850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.2875132789 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 27621014 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:46:26 PM UTC 24 |
| Finished | Sep 11 12:46:28 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875132789 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.2875132789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.1134341676 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 133358983 ps |
| CPU time | 2.98 seconds |
| Started | Sep 11 12:46:07 PM UTC 24 |
| Finished | Sep 11 12:46:11 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134341676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1134341676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.1630790185 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 14399822 ps |
| CPU time | 1 seconds |
| Started | Sep 11 12:45:53 PM UTC 24 |
| Finished | Sep 11 12:45:55 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630790185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1630790185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.3999475494 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 6038902189 ps |
| CPU time | 100.33 seconds |
| Started | Sep 11 12:46:15 PM UTC 24 |
| Finished | Sep 11 12:47:57 PM UTC 24 |
| Peak memory | 265820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999475494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3999475494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.786499730 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 97680365297 ps |
| CPU time | 230.73 seconds |
| Started | Sep 11 12:46:15 PM UTC 24 |
| Finished | Sep 11 12:50:09 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786499730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.786499730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1668062785 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 4884717655 ps |
| CPU time | 36.24 seconds |
| Started | Sep 11 12:46:17 PM UTC 24 |
| Finished | Sep 11 12:46:55 PM UTC 24 |
| Peak memory | 245384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668062785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.1668062785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1599957835 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 425858319 ps |
| CPU time | 4.1 seconds |
| Started | Sep 11 12:46:09 PM UTC 24 |
| Finished | Sep 11 12:46:15 PM UTC 24 |
| Peak memory | 235012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599957835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1599957835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1694615730 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 39792369982 ps |
| CPU time | 169.78 seconds |
| Started | Sep 11 12:46:13 PM UTC 24 |
| Finished | Sep 11 12:49:05 PM UTC 24 |
| Peak memory | 261768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694615730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.1694615730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.455130379 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 9740787836 ps |
| CPU time | 22.21 seconds |
| Started | Sep 11 12:46:06 PM UTC 24 |
| Finished | Sep 11 12:46:29 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455130379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.455130379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.4078911953 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 29305796026 ps |
| CPU time | 69.54 seconds |
| Started | Sep 11 12:46:06 PM UTC 24 |
| Finished | Sep 11 12:47:17 PM UTC 24 |
| Peak memory | 245460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078911953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4078911953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.3340307777 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2531313299 ps |
| CPU time | 6.96 seconds |
| Started | Sep 11 12:46:05 PM UTC 24 |
| Finished | Sep 11 12:46:13 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340307777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.3340307777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.4074446346 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3264805514 ps |
| CPU time | 10.91 seconds |
| Started | Sep 11 12:46:05 PM UTC 24 |
| Finished | Sep 11 12:46:17 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074446346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4074446346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.251048985 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 916282539 ps |
| CPU time | 9.69 seconds |
| Started | Sep 11 12:46:14 PM UTC 24 |
| Finished | Sep 11 12:46:25 PM UTC 24 |
| Peak memory | 231320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251048985 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.251048985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.3796892536 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 11332209097 ps |
| CPU time | 144.82 seconds |
| Started | Sep 11 12:46:17 PM UTC 24 |
| Finished | Sep 11 12:48:45 PM UTC 24 |
| Peak memory | 263884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796892536 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.3796892536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.90410156 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 4257735380 ps |
| CPU time | 19.42 seconds |
| Started | Sep 11 12:45:56 PM UTC 24 |
| Finished | Sep 11 12:46:17 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90410156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.90410156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.4257636376 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1396725082 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 12:45:54 PM UTC 24 |
| Finished | Sep 11 12:45:59 PM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257636376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4257636376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.646526043 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 277438590 ps |
| CPU time | 2.14 seconds |
| Started | Sep 11 12:46:03 PM UTC 24 |
| Finished | Sep 11 12:46:07 PM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646526043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.646526043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.663702903 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 36558755 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 12:46:00 PM UTC 24 |
| Finished | Sep 11 12:46:03 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663702903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.663702903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.751705375 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 7024125923 ps |
| CPU time | 36.05 seconds |
| Started | Sep 11 12:46:07 PM UTC 24 |
| Finished | Sep 11 12:46:45 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751705375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.751705375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.268821436 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 12668904 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 12:47:01 PM UTC 24 |
| Finished | Sep 11 12:47:03 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268821436 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.268821436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1981454626 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2811076251 ps |
| CPU time | 29.58 seconds |
| Started | Sep 11 12:46:50 PM UTC 24 |
| Finished | Sep 11 12:47:21 PM UTC 24 |
| Peak memory | 235016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981454626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1981454626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.3323744761 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 47795750 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 12:46:29 PM UTC 24 |
| Finished | Sep 11 12:46:31 PM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323744761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3323744761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.477941275 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 650309734 ps |
| CPU time | 16.84 seconds |
| Started | Sep 11 12:46:54 PM UTC 24 |
| Finished | Sep 11 12:47:12 PM UTC 24 |
| Peak memory | 247432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477941275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.477941275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.2976091972 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 30152943884 ps |
| CPU time | 76.97 seconds |
| Started | Sep 11 12:46:55 PM UTC 24 |
| Finished | Sep 11 12:48:14 PM UTC 24 |
| Peak memory | 263808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976091972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2976091972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1912302509 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 41759028350 ps |
| CPU time | 162.67 seconds |
| Started | Sep 11 12:46:56 PM UTC 24 |
| Finished | Sep 11 12:49:42 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912302509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.1912302509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.1977461691 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 384381786 ps |
| CPU time | 7.59 seconds |
| Started | Sep 11 12:46:52 PM UTC 24 |
| Finished | Sep 11 12:47:00 PM UTC 24 |
| Peak memory | 247236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977461691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1977461691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1419910926 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 71920775918 ps |
| CPU time | 406.03 seconds |
| Started | Sep 11 12:46:53 PM UTC 24 |
| Finished | Sep 11 12:53:44 PM UTC 24 |
| Peak memory | 278084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419910926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.1419910926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3127546015 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1976730372 ps |
| CPU time | 9.84 seconds |
| Started | Sep 11 12:46:41 PM UTC 24 |
| Finished | Sep 11 12:46:52 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127546015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3127546015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1591373749 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 714531103 ps |
| CPU time | 6.79 seconds |
| Started | Sep 11 12:46:45 PM UTC 24 |
| Finished | Sep 11 12:46:53 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591373749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1591373749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.395860985 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 4224316777 ps |
| CPU time | 22.65 seconds |
| Started | Sep 11 12:46:40 PM UTC 24 |
| Finished | Sep 11 12:47:04 PM UTC 24 |
| Peak memory | 261636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395860985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.395860985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1162035039 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 9034603038 ps |
| CPU time | 10.6 seconds |
| Started | Sep 11 12:46:38 PM UTC 24 |
| Finished | Sep 11 12:46:49 PM UTC 24 |
| Peak memory | 245248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162035039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1162035039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2470076829 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 5712109869 ps |
| CPU time | 16.94 seconds |
| Started | Sep 11 12:46:54 PM UTC 24 |
| Finished | Sep 11 12:47:12 PM UTC 24 |
| Peak memory | 231504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470076829 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.2470076829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.1387501607 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 3215348421 ps |
| CPU time | 29.22 seconds |
| Started | Sep 11 12:46:58 PM UTC 24 |
| Finished | Sep 11 12:47:28 PM UTC 24 |
| Peak memory | 235072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387501607 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.1387501607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.1761798534 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1761408747 ps |
| CPU time | 16.91 seconds |
| Started | Sep 11 12:46:32 PM UTC 24 |
| Finished | Sep 11 12:46:50 PM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761798534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1761798534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.2081343123 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 13483294267 ps |
| CPU time | 22.33 seconds |
| Started | Sep 11 12:46:30 PM UTC 24 |
| Finished | Sep 11 12:46:54 PM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081343123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2081343123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.3287021191 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 860777957 ps |
| CPU time | 2.66 seconds |
| Started | Sep 11 12:46:36 PM UTC 24 |
| Finished | Sep 11 12:46:40 PM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287021191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3287021191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.10617737 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 53937058 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 12:46:34 PM UTC 24 |
| Finished | Sep 11 12:46:36 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10617737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.10617737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.425464527 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 342840996 ps |
| CPU time | 5.49 seconds |
| Started | Sep 11 12:46:46 PM UTC 24 |
| Finished | Sep 11 12:46:53 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425464527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.425464527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.3402742767 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 181277016 ps |
| CPU time | 0.93 seconds |
| Started | Sep 11 12:47:25 PM UTC 24 |
| Finished | Sep 11 12:47:27 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402742767 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.3402742767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.4125612135 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 508513778 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 12:47:16 PM UTC 24 |
| Finished | Sep 11 12:47:21 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125612135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4125612135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1304416754 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 67968800 ps |
| CPU time | 1.03 seconds |
| Started | Sep 11 12:47:03 PM UTC 24 |
| Finished | Sep 11 12:47:05 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304416754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1304416754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.148046722 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 49776875997 ps |
| CPU time | 91.92 seconds |
| Started | Sep 11 12:47:22 PM UTC 24 |
| Finished | Sep 11 12:48:56 PM UTC 24 |
| Peak memory | 261696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148046722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.148046722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3878000099 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 13198511366 ps |
| CPU time | 46.04 seconds |
| Started | Sep 11 12:47:24 PM UTC 24 |
| Finished | Sep 11 12:48:11 PM UTC 24 |
| Peak memory | 267904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878000099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3878000099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.1642818798 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 119677148 ps |
| CPU time | 3.38 seconds |
| Started | Sep 11 12:47:18 PM UTC 24 |
| Finished | Sep 11 12:47:22 PM UTC 24 |
| Peak memory | 234944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642818798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1642818798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2706948768 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 8715141645 ps |
| CPU time | 63.77 seconds |
| Started | Sep 11 12:47:20 PM UTC 24 |
| Finished | Sep 11 12:48:25 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706948768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.2706948768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.3423243414 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2189624087 ps |
| CPU time | 9.49 seconds |
| Started | Sep 11 12:47:13 PM UTC 24 |
| Finished | Sep 11 12:47:24 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423243414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3423243414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.454977697 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 629997826 ps |
| CPU time | 17.09 seconds |
| Started | Sep 11 12:47:13 PM UTC 24 |
| Finished | Sep 11 12:47:32 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454977697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.454977697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3001544303 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3219062215 ps |
| CPU time | 12.27 seconds |
| Started | Sep 11 12:47:10 PM UTC 24 |
| Finished | Sep 11 12:47:24 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001544303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3001544303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2966144354 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 901475994 ps |
| CPU time | 5.26 seconds |
| Started | Sep 11 12:47:08 PM UTC 24 |
| Finished | Sep 11 12:47:14 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966144354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2966144354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.928563106 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 918336453 ps |
| CPU time | 6.98 seconds |
| Started | Sep 11 12:47:21 PM UTC 24 |
| Finished | Sep 11 12:47:29 PM UTC 24 |
| Peak memory | 233596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928563106 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.928563106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.613670801 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2863417955 ps |
| CPU time | 63.66 seconds |
| Started | Sep 11 12:47:25 PM UTC 24 |
| Finished | Sep 11 12:48:31 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613670801 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.613670801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.2606565976 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 13153841783 ps |
| CPU time | 30 seconds |
| Started | Sep 11 12:47:04 PM UTC 24 |
| Finished | Sep 11 12:47:36 PM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606565976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2606565976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.160945447 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 4815982956 ps |
| CPU time | 28.2 seconds |
| Started | Sep 11 12:47:03 PM UTC 24 |
| Finished | Sep 11 12:47:33 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160945447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.160945447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.838224225 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 77645060 ps |
| CPU time | 1.97 seconds |
| Started | Sep 11 12:47:06 PM UTC 24 |
| Finished | Sep 11 12:47:09 PM UTC 24 |
| Peak memory | 226368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838224225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.838224225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1116761260 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 62034552 ps |
| CPU time | 1.51 seconds |
| Started | Sep 11 12:47:04 PM UTC 24 |
| Finished | Sep 11 12:47:07 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116761260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1116761260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.4278141743 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1126702928 ps |
| CPU time | 7.3 seconds |
| Started | Sep 11 12:47:16 PM UTC 24 |
| Finished | Sep 11 12:47:24 PM UTC 24 |
| Peak memory | 234884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278141743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4278141743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.1154650657 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 12172648 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:48:03 PM UTC 24 |
| Finished | Sep 11 12:48:05 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154650657 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.1154650657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1089782426 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1753590258 ps |
| CPU time | 8.4 seconds |
| Started | Sep 11 12:47:40 PM UTC 24 |
| Finished | Sep 11 12:47:49 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089782426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1089782426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.2492510510 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 16419764 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:47:28 PM UTC 24 |
| Finished | Sep 11 12:47:31 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492510510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2492510510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2408100871 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 62037258428 ps |
| CPU time | 497.33 seconds |
| Started | Sep 11 12:47:55 PM UTC 24 |
| Finished | Sep 11 12:56:18 PM UTC 24 |
| Peak memory | 278084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408100871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2408100871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2673142657 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 544015123 ps |
| CPU time | 15.97 seconds |
| Started | Sep 11 12:47:59 PM UTC 24 |
| Finished | Sep 11 12:48:16 PM UTC 24 |
| Peak memory | 249332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673142657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2673142657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2712187766 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1772269799 ps |
| CPU time | 48.41 seconds |
| Started | Sep 11 12:48:00 PM UTC 24 |
| Finished | Sep 11 12:48:50 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712187766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.2712187766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1612502703 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 23547311150 ps |
| CPU time | 41.05 seconds |
| Started | Sep 11 12:47:41 PM UTC 24 |
| Finished | Sep 11 12:48:24 PM UTC 24 |
| Peak memory | 235204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612502703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1612502703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.729171870 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 56620303786 ps |
| CPU time | 140.12 seconds |
| Started | Sep 11 12:47:47 PM UTC 24 |
| Finished | Sep 11 12:50:10 PM UTC 24 |
| Peak memory | 267868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729171870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.729171870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.965421890 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2355340316 ps |
| CPU time | 15.5 seconds |
| Started | Sep 11 12:47:37 PM UTC 24 |
| Finished | Sep 11 12:47:53 PM UTC 24 |
| Peak memory | 245304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965421890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.965421890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.3220167235 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 10294032592 ps |
| CPU time | 79.74 seconds |
| Started | Sep 11 12:47:37 PM UTC 24 |
| Finished | Sep 11 12:48:58 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220167235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3220167235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.4103061758 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 89043454 ps |
| CPU time | 3.84 seconds |
| Started | Sep 11 12:47:35 PM UTC 24 |
| Finished | Sep 11 12:47:40 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103061758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.4103061758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.2639070950 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 6650115610 ps |
| CPU time | 27.09 seconds |
| Started | Sep 11 12:47:34 PM UTC 24 |
| Finished | Sep 11 12:48:02 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639070950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2639070950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2168501078 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1310385058 ps |
| CPU time | 7.58 seconds |
| Started | Sep 11 12:47:50 PM UTC 24 |
| Finished | Sep 11 12:47:59 PM UTC 24 |
| Peak memory | 233476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168501078 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2168501078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.3611710146 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 8060862655 ps |
| CPU time | 34.1 seconds |
| Started | Sep 11 12:47:31 PM UTC 24 |
| Finished | Sep 11 12:48:06 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611710146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3611710146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.2800059788 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1547655421 ps |
| CPU time | 15.47 seconds |
| Started | Sep 11 12:47:29 PM UTC 24 |
| Finished | Sep 11 12:47:46 PM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800059788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2800059788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.2204869970 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 20464612 ps |
| CPU time | 1.08 seconds |
| Started | Sep 11 12:47:33 PM UTC 24 |
| Finished | Sep 11 12:47:35 PM UTC 24 |
| Peak memory | 215728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204869970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2204869970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3854416652 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 109931511 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 12:47:32 PM UTC 24 |
| Finished | Sep 11 12:47:34 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854416652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3854416652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.2665084326 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 33720996086 ps |
| CPU time | 21.64 seconds |
| Started | Sep 11 12:47:37 PM UTC 24 |
| Finished | Sep 11 12:48:00 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665084326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2665084326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.545503807 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 22453511 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:48:32 PM UTC 24 |
| Finished | Sep 11 12:48:34 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545503807 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.545503807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.2070518252 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 180832600 ps |
| CPU time | 4.83 seconds |
| Started | Sep 11 12:48:21 PM UTC 24 |
| Finished | Sep 11 12:48:27 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070518252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2070518252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.1113039571 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 249285097 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 12:48:06 PM UTC 24 |
| Finished | Sep 11 12:48:09 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113039571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1113039571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.1588133559 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 20118951265 ps |
| CPU time | 170.55 seconds |
| Started | Sep 11 12:48:27 PM UTC 24 |
| Finished | Sep 11 12:51:20 PM UTC 24 |
| Peak memory | 261768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588133559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1588133559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1498875496 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 129699168736 ps |
| CPU time | 221.12 seconds |
| Started | Sep 11 12:48:28 PM UTC 24 |
| Finished | Sep 11 12:52:13 PM UTC 24 |
| Peak memory | 282304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498875496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1498875496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.839272417 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 40615843104 ps |
| CPU time | 100.01 seconds |
| Started | Sep 11 12:48:29 PM UTC 24 |
| Finished | Sep 11 12:50:11 PM UTC 24 |
| Peak memory | 267820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839272417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.839272417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.4150176337 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 872238347 ps |
| CPU time | 14.9 seconds |
| Started | Sep 11 12:48:16 PM UTC 24 |
| Finished | Sep 11 12:48:32 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150176337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4150176337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.2801983489 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1650394709 ps |
| CPU time | 12.36 seconds |
| Started | Sep 11 12:48:17 PM UTC 24 |
| Finished | Sep 11 12:48:30 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801983489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2801983489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.2660079643 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1531593258 ps |
| CPU time | 3.53 seconds |
| Started | Sep 11 12:48:16 PM UTC 24 |
| Finished | Sep 11 12:48:20 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660079643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.2660079643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.2655305739 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 604133346 ps |
| CPU time | 7.54 seconds |
| Started | Sep 11 12:48:14 PM UTC 24 |
| Finished | Sep 11 12:48:23 PM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655305739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2655305739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3398159409 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 899214720 ps |
| CPU time | 7.61 seconds |
| Started | Sep 11 12:48:25 PM UTC 24 |
| Finished | Sep 11 12:48:33 PM UTC 24 |
| Peak memory | 233296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398159409 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.3398159409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.3455005436 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 92355019 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 12:48:30 PM UTC 24 |
| Finished | Sep 11 12:48:33 PM UTC 24 |
| Peak memory | 216012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455005436 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.3455005436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.2623851408 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 3153468287 ps |
| CPU time | 12.62 seconds |
| Started | Sep 11 12:48:10 PM UTC 24 |
| Finished | Sep 11 12:48:24 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623851408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2623851408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1175238255 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2023650091 ps |
| CPU time | 4.44 seconds |
| Started | Sep 11 12:48:08 PM UTC 24 |
| Finished | Sep 11 12:48:13 PM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175238255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1175238255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1157304197 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 324163246 ps |
| CPU time | 2.39 seconds |
| Started | Sep 11 12:48:12 PM UTC 24 |
| Finished | Sep 11 12:48:16 PM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157304197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1157304197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2806260139 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 25504290 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 12:48:12 PM UTC 24 |
| Finished | Sep 11 12:48:14 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806260139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2806260139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.2848305616 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 466207951 ps |
| CPU time | 10.24 seconds |
| Started | Sep 11 12:48:17 PM UTC 24 |
| Finished | Sep 11 12:48:28 PM UTC 24 |
| Peak memory | 234884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848305616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2848305616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.1309816884 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 13919594 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:49:00 PM UTC 24 |
| Finished | Sep 11 12:49:02 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309816884 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.1309816884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.426702522 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 166974065 ps |
| CPU time | 3.07 seconds |
| Started | Sep 11 12:48:49 PM UTC 24 |
| Finished | Sep 11 12:48:54 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426702522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.426702522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.1273160313 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 23792593 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 12:48:32 PM UTC 24 |
| Finished | Sep 11 12:48:34 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273160313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1273160313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.2584381574 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 12075390118 ps |
| CPU time | 74.14 seconds |
| Started | Sep 11 12:48:57 PM UTC 24 |
| Finished | Sep 11 12:50:14 PM UTC 24 |
| Peak memory | 274056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584381574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2584381574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1499494208 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 56770133387 ps |
| CPU time | 270.87 seconds |
| Started | Sep 11 12:48:57 PM UTC 24 |
| Finished | Sep 11 12:53:33 PM UTC 24 |
| Peak memory | 278160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499494208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1499494208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.3757371101 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 115237541 ps |
| CPU time | 5.06 seconds |
| Started | Sep 11 12:48:51 PM UTC 24 |
| Finished | Sep 11 12:48:57 PM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757371101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3757371101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.1963995404 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 5814988668 ps |
| CPU time | 16.37 seconds |
| Started | Sep 11 12:48:39 PM UTC 24 |
| Finished | Sep 11 12:48:57 PM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963995404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1963995404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.2253583127 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 901493171 ps |
| CPU time | 9.71 seconds |
| Started | Sep 11 12:48:39 PM UTC 24 |
| Finished | Sep 11 12:48:50 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253583127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2253583127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.280172896 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 883006470 ps |
| CPU time | 9.71 seconds |
| Started | Sep 11 12:48:38 PM UTC 24 |
| Finished | Sep 11 12:48:49 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280172896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.280172896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.154126413 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3792163343 ps |
| CPU time | 22.72 seconds |
| Started | Sep 11 12:48:35 PM UTC 24 |
| Finished | Sep 11 12:48:59 PM UTC 24 |
| Peak memory | 251400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154126413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.154126413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.2235528197 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 174313164 ps |
| CPU time | 6.6 seconds |
| Started | Sep 11 12:48:55 PM UTC 24 |
| Finished | Sep 11 12:49:03 PM UTC 24 |
| Peak memory | 233620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235528197 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.2235528197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.4052717283 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2680028574 ps |
| CPU time | 43.26 seconds |
| Started | Sep 11 12:48:34 PM UTC 24 |
| Finished | Sep 11 12:49:19 PM UTC 24 |
| Peak memory | 231632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052717283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4052717283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.2914228497 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 414448586 ps |
| CPU time | 3.24 seconds |
| Started | Sep 11 12:48:33 PM UTC 24 |
| Finished | Sep 11 12:48:37 PM UTC 24 |
| Peak memory | 217144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914228497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2914228497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.927584050 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 104062215 ps |
| CPU time | 1.85 seconds |
| Started | Sep 11 12:48:35 PM UTC 24 |
| Finished | Sep 11 12:48:38 PM UTC 24 |
| Peak memory | 226392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927584050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.927584050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.112988476 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 220956686 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 12:48:34 PM UTC 24 |
| Finished | Sep 11 12:48:36 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112988476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.112988476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.3996098389 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 4120786047 ps |
| CPU time | 9.06 seconds |
| Started | Sep 11 12:48:45 PM UTC 24 |
| Finished | Sep 11 12:48:56 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996098389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3996098389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.2426009666 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 13693945 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:49:41 PM UTC 24 |
| Finished | Sep 11 12:49:43 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426009666 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.2426009666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3195275794 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 182456904 ps |
| CPU time | 3.3 seconds |
| Started | Sep 11 12:49:20 PM UTC 24 |
| Finished | Sep 11 12:49:24 PM UTC 24 |
| Peak memory | 245128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195275794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3195275794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.1870729526 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 39294980 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 12:49:00 PM UTC 24 |
| Finished | Sep 11 12:49:02 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870729526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1870729526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.1227632456 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1981731778 ps |
| CPU time | 9.95 seconds |
| Started | Sep 11 12:49:28 PM UTC 24 |
| Finished | Sep 11 12:49:39 PM UTC 24 |
| Peak memory | 234932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227632456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1227632456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.480574474 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 286196619109 ps |
| CPU time | 351.72 seconds |
| Started | Sep 11 12:49:28 PM UTC 24 |
| Finished | Sep 11 12:55:25 PM UTC 24 |
| Peak memory | 265816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480574474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.480574474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.2589056365 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 3343509630 ps |
| CPU time | 93.67 seconds |
| Started | Sep 11 12:49:36 PM UTC 24 |
| Finished | Sep 11 12:51:11 PM UTC 24 |
| Peak memory | 267904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589056365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.2589056365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.724916225 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1280263882 ps |
| CPU time | 29.19 seconds |
| Started | Sep 11 12:49:20 PM UTC 24 |
| Finished | Sep 11 12:49:50 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724916225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.724916225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.2510335247 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5071089476 ps |
| CPU time | 51.67 seconds |
| Started | Sep 11 12:49:25 PM UTC 24 |
| Finished | Sep 11 12:50:18 PM UTC 24 |
| Peak memory | 265804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510335247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.2510335247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.3688113210 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 309500134 ps |
| CPU time | 6.78 seconds |
| Started | Sep 11 12:49:07 PM UTC 24 |
| Finished | Sep 11 12:49:15 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688113210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3688113210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.3184189080 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 8688398166 ps |
| CPU time | 81.36 seconds |
| Started | Sep 11 12:49:08 PM UTC 24 |
| Finished | Sep 11 12:50:31 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184189080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3184189080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3193489683 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 890001964 ps |
| CPU time | 10.47 seconds |
| Started | Sep 11 12:49:07 PM UTC 24 |
| Finished | Sep 11 12:49:19 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193489683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.3193489683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.1120549486 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 6831582802 ps |
| CPU time | 18.68 seconds |
| Started | Sep 11 12:49:07 PM UTC 24 |
| Finished | Sep 11 12:49:27 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120549486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1120549486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.453675600 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2652969942 ps |
| CPU time | 11.75 seconds |
| Started | Sep 11 12:49:25 PM UTC 24 |
| Finished | Sep 11 12:49:38 PM UTC 24 |
| Peak memory | 233620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453675600 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.453675600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.881070001 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 69103181387 ps |
| CPU time | 410 seconds |
| Started | Sep 11 12:49:39 PM UTC 24 |
| Finished | Sep 11 12:56:34 PM UTC 24 |
| Peak memory | 276100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881070001 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.881070001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.1094293872 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 6240036041 ps |
| CPU time | 56.15 seconds |
| Started | Sep 11 12:49:03 PM UTC 24 |
| Finished | Sep 11 12:50:01 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094293872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1094293872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3309811597 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 637103030 ps |
| CPU time | 3.7 seconds |
| Started | Sep 11 12:49:01 PM UTC 24 |
| Finished | Sep 11 12:49:06 PM UTC 24 |
| Peak memory | 227316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309811597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3309811597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.4269129612 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 520201398 ps |
| CPU time | 2.6 seconds |
| Started | Sep 11 12:49:03 PM UTC 24 |
| Finished | Sep 11 12:49:07 PM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269129612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4269129612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2857940538 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 55012685 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 12:49:03 PM UTC 24 |
| Finished | Sep 11 12:49:06 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857940538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2857940538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.565343038 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2211548856 ps |
| CPU time | 11.3 seconds |
| Started | Sep 11 12:49:15 PM UTC 24 |
| Finished | Sep 11 12:49:28 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565343038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.565343038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.4081938442 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 58455731 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:32:47 PM UTC 24 |
| Finished | Sep 11 12:32:49 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081938442 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4081938442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1878921482 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 108702126 ps |
| CPU time | 2.89 seconds |
| Started | Sep 11 12:32:32 PM UTC 24 |
| Finished | Sep 11 12:32:36 PM UTC 24 |
| Peak memory | 234632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878921482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1878921482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1675704128 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 29839096 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:32:10 PM UTC 24 |
| Finished | Sep 11 12:32:13 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675704128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1675704128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.1699673416 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 39126607 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 12:32:43 PM UTC 24 |
| Finished | Sep 11 12:32:45 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699673416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1699673416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2658025796 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2746802912 ps |
| CPU time | 9.46 seconds |
| Started | Sep 11 12:32:43 PM UTC 24 |
| Finished | Sep 11 12:32:53 PM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658025796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2658025796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.2364216471 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 945573062 ps |
| CPU time | 15.52 seconds |
| Started | Sep 11 12:32:33 PM UTC 24 |
| Finished | Sep 11 12:32:50 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364216471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2364216471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3180736515 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1247233582 ps |
| CPU time | 27.86 seconds |
| Started | Sep 11 12:32:38 PM UTC 24 |
| Finished | Sep 11 12:33:07 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180736515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.3180736515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.2188360611 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2355130545 ps |
| CPU time | 18.01 seconds |
| Started | Sep 11 12:32:23 PM UTC 24 |
| Finished | Sep 11 12:32:42 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188360611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2188360611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3293523195 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 374311934 ps |
| CPU time | 8.57 seconds |
| Started | Sep 11 12:32:23 PM UTC 24 |
| Finished | Sep 11 12:32:33 PM UTC 24 |
| Peak memory | 251336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293523195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3293523195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3221415612 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 17089535140 ps |
| CPU time | 18.39 seconds |
| Started | Sep 11 12:32:18 PM UTC 24 |
| Finished | Sep 11 12:32:38 PM UTC 24 |
| Peak memory | 245280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221415612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.3221415612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.778660562 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2131145259 ps |
| CPU time | 25.44 seconds |
| Started | Sep 11 12:32:17 PM UTC 24 |
| Finished | Sep 11 12:32:44 PM UTC 24 |
| Peak memory | 261576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778660562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.778660562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2506822839 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 819268957 ps |
| CPU time | 11.57 seconds |
| Started | Sep 11 12:32:39 PM UTC 24 |
| Finished | Sep 11 12:32:51 PM UTC 24 |
| Peak memory | 233372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506822839 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.2506822839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.3449690736 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 342645095 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 12:32:46 PM UTC 24 |
| Finished | Sep 11 12:32:49 PM UTC 24 |
| Peak memory | 257908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449690736 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3449690736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.4070490842 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11377160439 ps |
| CPU time | 84.99 seconds |
| Started | Sep 11 12:32:45 PM UTC 24 |
| Finished | Sep 11 12:34:12 PM UTC 24 |
| Peak memory | 247428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070490842 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.4070490842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2835438466 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 33014531 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:32:14 PM UTC 24 |
| Finished | Sep 11 12:32:16 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835438466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2835438466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2694986556 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4279335568 ps |
| CPU time | 28.04 seconds |
| Started | Sep 11 12:32:14 PM UTC 24 |
| Finished | Sep 11 12:32:43 PM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694986556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2694986556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3065965443 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 890377417 ps |
| CPU time | 4.2 seconds |
| Started | Sep 11 12:32:17 PM UTC 24 |
| Finished | Sep 11 12:32:22 PM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065965443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3065965443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1994958603 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 27683326 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:32:15 PM UTC 24 |
| Finished | Sep 11 12:32:17 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994958603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1994958603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1780239950 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1899355232 ps |
| CPU time | 14.29 seconds |
| Started | Sep 11 12:32:26 PM UTC 24 |
| Finished | Sep 11 12:32:42 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780239950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1780239950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.2189248150 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 10971043 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:50:13 PM UTC 24 |
| Finished | Sep 11 12:50:15 PM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189248150 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.2189248150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3231310998 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 819519789 ps |
| CPU time | 13.05 seconds |
| Started | Sep 11 12:49:58 PM UTC 24 |
| Finished | Sep 11 12:50:12 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231310998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3231310998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.840968897 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 20306629 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 12:49:42 PM UTC 24 |
| Finished | Sep 11 12:49:44 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840968897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.840968897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.1739295398 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 7109351170 ps |
| CPU time | 117.58 seconds |
| Started | Sep 11 12:50:02 PM UTC 24 |
| Finished | Sep 11 12:52:02 PM UTC 24 |
| Peak memory | 278152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739295398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1739295398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.289997157 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 12580718412 ps |
| CPU time | 83.24 seconds |
| Started | Sep 11 12:50:08 PM UTC 24 |
| Finished | Sep 11 12:51:33 PM UTC 24 |
| Peak memory | 265896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289997157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.289997157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.416592710 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 12329071856 ps |
| CPU time | 118.13 seconds |
| Started | Sep 11 12:50:10 PM UTC 24 |
| Finished | Sep 11 12:52:10 PM UTC 24 |
| Peak memory | 278124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416592710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.416592710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.3169232987 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4006846401 ps |
| CPU time | 21.12 seconds |
| Started | Sep 11 12:49:59 PM UTC 24 |
| Finished | Sep 11 12:50:21 PM UTC 24 |
| Peak memory | 249428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169232987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3169232987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3259169150 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 2332838374 ps |
| CPU time | 61.19 seconds |
| Started | Sep 11 12:50:00 PM UTC 24 |
| Finished | Sep 11 12:51:03 PM UTC 24 |
| Peak memory | 267908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259169150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.3259169150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.3277756325 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 222858750 ps |
| CPU time | 3.94 seconds |
| Started | Sep 11 12:49:51 PM UTC 24 |
| Finished | Sep 11 12:49:56 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277756325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3277756325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.1977533141 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 16628286738 ps |
| CPU time | 41.41 seconds |
| Started | Sep 11 12:49:52 PM UTC 24 |
| Finished | Sep 11 12:50:35 PM UTC 24 |
| Peak memory | 245316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977533141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1977533141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.555462836 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 269167027 ps |
| CPU time | 5.32 seconds |
| Started | Sep 11 12:49:50 PM UTC 24 |
| Finished | Sep 11 12:49:56 PM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555462836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.555462836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2849719464 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1766825818 ps |
| CPU time | 8.99 seconds |
| Started | Sep 11 12:49:50 PM UTC 24 |
| Finished | Sep 11 12:50:00 PM UTC 24 |
| Peak memory | 245104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849719464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2849719464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.95176683 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 5657182231 ps |
| CPU time | 20.2 seconds |
| Started | Sep 11 12:50:01 PM UTC 24 |
| Finished | Sep 11 12:50:23 PM UTC 24 |
| Peak memory | 231380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95176683 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.95176683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.2773771597 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 169797180837 ps |
| CPU time | 431.48 seconds |
| Started | Sep 11 12:50:11 PM UTC 24 |
| Finished | Sep 11 12:57:28 PM UTC 24 |
| Peak memory | 300740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773771597 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.2773771597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.805960393 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 20712724085 ps |
| CPU time | 41.29 seconds |
| Started | Sep 11 12:49:44 PM UTC 24 |
| Finished | Sep 11 12:50:27 PM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805960393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.805960393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3029161194 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 398977831 ps |
| CPU time | 5.28 seconds |
| Started | Sep 11 12:49:43 PM UTC 24 |
| Finished | Sep 11 12:49:50 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029161194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3029161194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.3469716179 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 191130810 ps |
| CPU time | 1.98 seconds |
| Started | Sep 11 12:49:49 PM UTC 24 |
| Finished | Sep 11 12:49:52 PM UTC 24 |
| Peak memory | 216152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469716179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3469716179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.839155932 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 254244607 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 12:49:46 PM UTC 24 |
| Finished | Sep 11 12:49:48 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839155932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.839155932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.857463 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2883121570 ps |
| CPU time | 27.3 seconds |
| Started | Sep 11 12:49:58 PM UTC 24 |
| Finished | Sep 11 12:50:26 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_devi ce_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.857463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.344994833 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 19857017 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:50:38 PM UTC 24 |
| Finished | Sep 11 12:50:40 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344994833 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.344994833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4077010527 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 648740059 ps |
| CPU time | 10.32 seconds |
| Started | Sep 11 12:50:26 PM UTC 24 |
| Finished | Sep 11 12:50:38 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077010527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4077010527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.1437224763 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 12722346 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:50:13 PM UTC 24 |
| Finished | Sep 11 12:50:15 PM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437224763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1437224763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.2976888973 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3791006709 ps |
| CPU time | 70.6 seconds |
| Started | Sep 11 12:50:30 PM UTC 24 |
| Finished | Sep 11 12:51:43 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976888973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2976888973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3797015307 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 20360126218 ps |
| CPU time | 64.99 seconds |
| Started | Sep 11 12:50:32 PM UTC 24 |
| Finished | Sep 11 12:51:39 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797015307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3797015307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.597714586 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 67827132968 ps |
| CPU time | 486.34 seconds |
| Started | Sep 11 12:50:37 PM UTC 24 |
| Finished | Sep 11 12:58:50 PM UTC 24 |
| Peak memory | 278152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597714586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.597714586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.2983438136 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 200537007 ps |
| CPU time | 7.23 seconds |
| Started | Sep 11 12:50:27 PM UTC 24 |
| Finished | Sep 11 12:50:36 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983438136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2983438136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.1383646881 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2736135806 ps |
| CPU time | 49.25 seconds |
| Started | Sep 11 12:50:29 PM UTC 24 |
| Finished | Sep 11 12:51:20 PM UTC 24 |
| Peak memory | 263756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383646881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.1383646881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.747483755 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 5991781589 ps |
| CPU time | 14.47 seconds |
| Started | Sep 11 12:50:22 PM UTC 24 |
| Finished | Sep 11 12:50:38 PM UTC 24 |
| Peak memory | 234992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747483755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.747483755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.1775480648 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 536349866 ps |
| CPU time | 4.02 seconds |
| Started | Sep 11 12:50:24 PM UTC 24 |
| Finished | Sep 11 12:50:29 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775480648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1775480648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1792550182 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 206107912 ps |
| CPU time | 5.7 seconds |
| Started | Sep 11 12:50:22 PM UTC 24 |
| Finished | Sep 11 12:50:29 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792550182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1792550182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.93184221 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 408465129 ps |
| CPU time | 4.44 seconds |
| Started | Sep 11 12:50:20 PM UTC 24 |
| Finished | Sep 11 12:50:25 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93184221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.93184221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1605023110 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 528602510 ps |
| CPU time | 6.09 seconds |
| Started | Sep 11 12:50:30 PM UTC 24 |
| Finished | Sep 11 12:50:38 PM UTC 24 |
| Peak memory | 231248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605023110 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.1605023110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.268473614 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 115269601826 ps |
| CPU time | 224.92 seconds |
| Started | Sep 11 12:50:37 PM UTC 24 |
| Finished | Sep 11 12:54:25 PM UTC 24 |
| Peak memory | 278128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268473614 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.268473614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.2614474906 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 12330777377 ps |
| CPU time | 34.14 seconds |
| Started | Sep 11 12:50:16 PM UTC 24 |
| Finished | Sep 11 12:50:52 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614474906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2614474906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.603850339 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 420646903 ps |
| CPU time | 5.31 seconds |
| Started | Sep 11 12:50:15 PM UTC 24 |
| Finished | Sep 11 12:50:21 PM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603850339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.603850339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.532809995 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 36772407 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 12:50:20 PM UTC 24 |
| Finished | Sep 11 12:50:22 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532809995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.532809995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.3451933909 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 66152146 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 12:50:16 PM UTC 24 |
| Finished | Sep 11 12:50:18 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451933909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3451933909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.531867377 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 20340106510 ps |
| CPU time | 31.06 seconds |
| Started | Sep 11 12:50:24 PM UTC 24 |
| Finished | Sep 11 12:50:56 PM UTC 24 |
| Peak memory | 245384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531867377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.531867377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.1585581165 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 36622646 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 12:51:07 PM UTC 24 |
| Finished | Sep 11 12:51:09 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585581165 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.1585581165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.1585779992 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 136222459 ps |
| CPU time | 3.18 seconds |
| Started | Sep 11 12:50:55 PM UTC 24 |
| Finished | Sep 11 12:51:00 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585779992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1585779992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.2772906775 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 15176584 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 12:50:38 PM UTC 24 |
| Finished | Sep 11 12:50:40 PM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772906775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2772906775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.1077979057 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 37220251566 ps |
| CPU time | 74.88 seconds |
| Started | Sep 11 12:51:01 PM UTC 24 |
| Finished | Sep 11 12:52:18 PM UTC 24 |
| Peak memory | 263836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077979057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1077979057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3296696218 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 21329263916 ps |
| CPU time | 153.44 seconds |
| Started | Sep 11 12:51:03 PM UTC 24 |
| Finished | Sep 11 12:53:39 PM UTC 24 |
| Peak memory | 282256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296696218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3296696218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.590076542 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 42223176859 ps |
| CPU time | 90.23 seconds |
| Started | Sep 11 12:51:03 PM UTC 24 |
| Finished | Sep 11 12:52:35 PM UTC 24 |
| Peak memory | 235056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590076542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.590076542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.3846817888 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3573456954 ps |
| CPU time | 9.32 seconds |
| Started | Sep 11 12:50:55 PM UTC 24 |
| Finished | Sep 11 12:51:06 PM UTC 24 |
| Peak memory | 247360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846817888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3846817888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1466044739 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 7373604509 ps |
| CPU time | 85.02 seconds |
| Started | Sep 11 12:50:58 PM UTC 24 |
| Finished | Sep 11 12:52:25 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466044739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.1466044739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.2519368422 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 438157691 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 12:50:50 PM UTC 24 |
| Finished | Sep 11 12:50:55 PM UTC 24 |
| Peak memory | 233500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519368422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2519368422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.2051077176 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1163651751 ps |
| CPU time | 12.7 seconds |
| Started | Sep 11 12:50:52 PM UTC 24 |
| Finished | Sep 11 12:51:05 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051077176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2051077176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1356797252 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 8497692733 ps |
| CPU time | 19.64 seconds |
| Started | Sep 11 12:50:49 PM UTC 24 |
| Finished | Sep 11 12:51:10 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356797252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.1356797252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2248737171 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3659475553 ps |
| CPU time | 7.01 seconds |
| Started | Sep 11 12:50:46 PM UTC 24 |
| Finished | Sep 11 12:50:54 PM UTC 24 |
| Peak memory | 235072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248737171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2248737171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.155624353 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3786989259 ps |
| CPU time | 18.1 seconds |
| Started | Sep 11 12:51:01 PM UTC 24 |
| Finished | Sep 11 12:51:21 PM UTC 24 |
| Peak memory | 231384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155624353 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.155624353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.1703088793 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 88369939936 ps |
| CPU time | 521.72 seconds |
| Started | Sep 11 12:51:04 PM UTC 24 |
| Finished | Sep 11 12:59:53 PM UTC 24 |
| Peak memory | 298608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703088793 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.1703088793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.2220506669 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3053463753 ps |
| CPU time | 17.69 seconds |
| Started | Sep 11 12:50:42 PM UTC 24 |
| Finished | Sep 11 12:51:01 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220506669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2220506669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3448542301 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 654698605 ps |
| CPU time | 8.27 seconds |
| Started | Sep 11 12:50:40 PM UTC 24 |
| Finished | Sep 11 12:50:49 PM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448542301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3448542301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.1607830571 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 10895653 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 12:50:46 PM UTC 24 |
| Finished | Sep 11 12:50:48 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607830571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1607830571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2337070256 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 68367344 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 12:50:42 PM UTC 24 |
| Finished | Sep 11 12:50:44 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337070256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2337070256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.2340896255 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 597906861 ps |
| CPU time | 6.06 seconds |
| Started | Sep 11 12:50:53 PM UTC 24 |
| Finished | Sep 11 12:51:00 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340896255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2340896255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.1857807808 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 13440235 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:51:33 PM UTC 24 |
| Finished | Sep 11 12:51:35 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857807808 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.1857807808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.475741130 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 228123384 ps |
| CPU time | 7.16 seconds |
| Started | Sep 11 12:51:22 PM UTC 24 |
| Finished | Sep 11 12:51:30 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475741130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.475741130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.2134654941 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 186427238 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:51:07 PM UTC 24 |
| Finished | Sep 11 12:51:09 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134654941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2134654941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.4083945585 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 9074361571 ps |
| CPU time | 77.14 seconds |
| Started | Sep 11 12:51:25 PM UTC 24 |
| Finished | Sep 11 12:52:43 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083945585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4083945585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1865586656 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5008148210 ps |
| CPU time | 93.56 seconds |
| Started | Sep 11 12:51:27 PM UTC 24 |
| Finished | Sep 11 12:53:03 PM UTC 24 |
| Peak memory | 276156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865586656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1865586656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3443307507 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 16305403776 ps |
| CPU time | 130.22 seconds |
| Started | Sep 11 12:51:29 PM UTC 24 |
| Finished | Sep 11 12:53:42 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443307507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.3443307507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.1070963014 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 318001566 ps |
| CPU time | 8.84 seconds |
| Started | Sep 11 12:51:22 PM UTC 24 |
| Finished | Sep 11 12:51:32 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070963014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1070963014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.270591492 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 83729031171 ps |
| CPU time | 354.33 seconds |
| Started | Sep 11 12:51:23 PM UTC 24 |
| Finished | Sep 11 12:57:22 PM UTC 24 |
| Peak memory | 284372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270591492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.270591492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.664031367 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 787150316 ps |
| CPU time | 5.96 seconds |
| Started | Sep 11 12:51:19 PM UTC 24 |
| Finished | Sep 11 12:51:26 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664031367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.664031367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3410651513 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 591063648 ps |
| CPU time | 3.71 seconds |
| Started | Sep 11 12:51:19 PM UTC 24 |
| Finished | Sep 11 12:51:24 PM UTC 24 |
| Peak memory | 234916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410651513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3410651513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.235372446 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 326035302 ps |
| CPU time | 6.89 seconds |
| Started | Sep 11 12:51:15 PM UTC 24 |
| Finished | Sep 11 12:51:23 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235372446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.235372446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.2560866680 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 104445559 ps |
| CPU time | 3.23 seconds |
| Started | Sep 11 12:51:13 PM UTC 24 |
| Finished | Sep 11 12:51:17 PM UTC 24 |
| Peak memory | 234144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560866680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2560866680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.993835626 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1707659478 ps |
| CPU time | 19.93 seconds |
| Started | Sep 11 12:51:25 PM UTC 24 |
| Finished | Sep 11 12:51:46 PM UTC 24 |
| Peak memory | 233320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993835626 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.993835626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.156486740 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 7276356406 ps |
| CPU time | 155.19 seconds |
| Started | Sep 11 12:51:31 PM UTC 24 |
| Finished | Sep 11 12:54:10 PM UTC 24 |
| Peak memory | 278108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156486740 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.156486740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.372659146 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2000238745 ps |
| CPU time | 33.57 seconds |
| Started | Sep 11 12:51:10 PM UTC 24 |
| Finished | Sep 11 12:51:45 PM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372659146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.372659146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.946327587 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1512538652 ps |
| CPU time | 10.37 seconds |
| Started | Sep 11 12:51:10 PM UTC 24 |
| Finished | Sep 11 12:51:22 PM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946327587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.946327587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.2735615245 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2989719250 ps |
| CPU time | 4.94 seconds |
| Started | Sep 11 12:51:12 PM UTC 24 |
| Finished | Sep 11 12:51:18 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735615245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2735615245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.2765199492 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 252420427 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 12:51:12 PM UTC 24 |
| Finished | Sep 11 12:51:14 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765199492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2765199492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.2769245572 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 5284156441 ps |
| CPU time | 18.09 seconds |
| Started | Sep 11 12:51:22 PM UTC 24 |
| Finished | Sep 11 12:51:41 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769245572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2769245572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.1667341885 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 14384644 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 12:51:58 PM UTC 24 |
| Finished | Sep 11 12:52:01 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667341885 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.1667341885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.1875667546 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 44930862 ps |
| CPU time | 3.26 seconds |
| Started | Sep 11 12:51:45 PM UTC 24 |
| Finished | Sep 11 12:51:49 PM UTC 24 |
| Peak memory | 244888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875667546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1875667546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.2993809002 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 126389186 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:51:34 PM UTC 24 |
| Finished | Sep 11 12:51:36 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993809002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2993809002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.3711694923 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 27243958205 ps |
| CPU time | 253.9 seconds |
| Started | Sep 11 12:51:52 PM UTC 24 |
| Finished | Sep 11 12:56:10 PM UTC 24 |
| Peak memory | 276052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711694923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3711694923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1933354703 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 26806670776 ps |
| CPU time | 66.33 seconds |
| Started | Sep 11 12:51:53 PM UTC 24 |
| Finished | Sep 11 12:53:01 PM UTC 24 |
| Peak memory | 265960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933354703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1933354703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2173124736 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 30911097377 ps |
| CPU time | 173.23 seconds |
| Started | Sep 11 12:51:55 PM UTC 24 |
| Finished | Sep 11 12:54:51 PM UTC 24 |
| Peak memory | 263816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173124736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.2173124736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.3852253628 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 157898279 ps |
| CPU time | 4.71 seconds |
| Started | Sep 11 12:51:46 PM UTC 24 |
| Finished | Sep 11 12:51:52 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852253628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3852253628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.1267735983 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 6903079110 ps |
| CPU time | 117.93 seconds |
| Started | Sep 11 12:51:46 PM UTC 24 |
| Finished | Sep 11 12:53:47 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267735983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.1267735983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.2651044079 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1197451150 ps |
| CPU time | 7.41 seconds |
| Started | Sep 11 12:51:42 PM UTC 24 |
| Finished | Sep 11 12:51:51 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651044079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2651044079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.4273469491 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4186746249 ps |
| CPU time | 12.76 seconds |
| Started | Sep 11 12:51:43 PM UTC 24 |
| Finished | Sep 11 12:51:57 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273469491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4273469491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1086407702 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 104071891349 ps |
| CPU time | 35.54 seconds |
| Started | Sep 11 12:51:41 PM UTC 24 |
| Finished | Sep 11 12:52:18 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086407702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.1086407702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.3085305499 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3355659055 ps |
| CPU time | 22.27 seconds |
| Started | Sep 11 12:51:41 PM UTC 24 |
| Finished | Sep 11 12:52:04 PM UTC 24 |
| Peak memory | 245292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085305499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3085305499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2491783102 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 864488595 ps |
| CPU time | 9.59 seconds |
| Started | Sep 11 12:51:51 PM UTC 24 |
| Finished | Sep 11 12:52:01 PM UTC 24 |
| Peak memory | 231248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491783102 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.2491783102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.98758072 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 177969308936 ps |
| CPU time | 425.2 seconds |
| Started | Sep 11 12:51:57 PM UTC 24 |
| Finished | Sep 11 12:59:08 PM UTC 24 |
| Peak memory | 263820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98758072 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.98758072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.2268320307 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 11910515030 ps |
| CPU time | 21.45 seconds |
| Started | Sep 11 12:51:36 PM UTC 24 |
| Finished | Sep 11 12:51:58 PM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268320307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2268320307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3212622710 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 281446239 ps |
| CPU time | 2.33 seconds |
| Started | Sep 11 12:51:36 PM UTC 24 |
| Finished | Sep 11 12:51:39 PM UTC 24 |
| Peak memory | 217140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212622710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3212622710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.29275124 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 430379406 ps |
| CPU time | 1.51 seconds |
| Started | Sep 11 12:51:41 PM UTC 24 |
| Finished | Sep 11 12:51:43 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29275124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.29275124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.1042871887 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 49424455 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 12:51:37 PM UTC 24 |
| Finished | Sep 11 12:51:39 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042871887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1042871887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.3328829892 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 444263264 ps |
| CPU time | 7.63 seconds |
| Started | Sep 11 12:51:45 PM UTC 24 |
| Finished | Sep 11 12:51:54 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328829892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3328829892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2506290336 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 11733456 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:52:22 PM UTC 24 |
| Finished | Sep 11 12:52:24 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506290336 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.2506290336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.649848748 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2193525748 ps |
| CPU time | 6.62 seconds |
| Started | Sep 11 12:52:07 PM UTC 24 |
| Finished | Sep 11 12:52:15 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649848748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.649848748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.82370012 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 14183494 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 12:51:59 PM UTC 24 |
| Finished | Sep 11 12:52:02 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82370012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.82370012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2923821121 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 61138623847 ps |
| CPU time | 145.69 seconds |
| Started | Sep 11 12:52:14 PM UTC 24 |
| Finished | Sep 11 12:54:42 PM UTC 24 |
| Peak memory | 267848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923821121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2923821121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1118190535 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 52676362512 ps |
| CPU time | 223.66 seconds |
| Started | Sep 11 12:52:15 PM UTC 24 |
| Finished | Sep 11 12:56:02 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118190535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1118190535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.3690849324 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 32959016981 ps |
| CPU time | 71.55 seconds |
| Started | Sep 11 12:52:19 PM UTC 24 |
| Finished | Sep 11 12:53:32 PM UTC 24 |
| Peak memory | 263816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690849324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.3690849324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.1095275821 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 15560855058 ps |
| CPU time | 46.24 seconds |
| Started | Sep 11 12:52:11 PM UTC 24 |
| Finished | Sep 11 12:53:00 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095275821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1095275821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.1913703132 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 12041504677 ps |
| CPU time | 92.06 seconds |
| Started | Sep 11 12:52:11 PM UTC 24 |
| Finished | Sep 11 12:53:46 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913703132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.1913703132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.2661180039 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2430256998 ps |
| CPU time | 8.02 seconds |
| Started | Sep 11 12:52:04 PM UTC 24 |
| Finished | Sep 11 12:52:13 PM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661180039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2661180039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.1339170128 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 420621615 ps |
| CPU time | 16.43 seconds |
| Started | Sep 11 12:52:06 PM UTC 24 |
| Finished | Sep 11 12:52:23 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339170128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1339170128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.256247217 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 27185846918 ps |
| CPU time | 27.52 seconds |
| Started | Sep 11 12:52:04 PM UTC 24 |
| Finished | Sep 11 12:52:33 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256247217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.256247217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2017531253 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 54072142869 ps |
| CPU time | 40.42 seconds |
| Started | Sep 11 12:52:04 PM UTC 24 |
| Finished | Sep 11 12:52:46 PM UTC 24 |
| Peak memory | 245376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017531253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2017531253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.4289579201 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1538425441 ps |
| CPU time | 14.01 seconds |
| Started | Sep 11 12:52:14 PM UTC 24 |
| Finished | Sep 11 12:52:29 PM UTC 24 |
| Peak memory | 233356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289579201 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.4289579201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2412487346 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 78912006 ps |
| CPU time | 1.51 seconds |
| Started | Sep 11 12:52:19 PM UTC 24 |
| Finished | Sep 11 12:52:22 PM UTC 24 |
| Peak memory | 215692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412487346 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2412487346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.1916025661 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 23083425596 ps |
| CPU time | 32.81 seconds |
| Started | Sep 11 12:52:02 PM UTC 24 |
| Finished | Sep 11 12:52:37 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916025661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1916025661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.296267851 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 36956391 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 12:52:01 PM UTC 24 |
| Finished | Sep 11 12:52:03 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296267851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.296267851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.2576969513 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 873354253 ps |
| CPU time | 2.7 seconds |
| Started | Sep 11 12:52:02 PM UTC 24 |
| Finished | Sep 11 12:52:06 PM UTC 24 |
| Peak memory | 227252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576969513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2576969513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.700614861 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 22882532 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:52:02 PM UTC 24 |
| Finished | Sep 11 12:52:05 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700614861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.700614861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.1325254322 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 322871838 ps |
| CPU time | 2.98 seconds |
| Started | Sep 11 12:52:06 PM UTC 24 |
| Finished | Sep 11 12:52:10 PM UTC 24 |
| Peak memory | 234708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325254322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1325254322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.4115052679 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 21571428 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:52:45 PM UTC 24 |
| Finished | Sep 11 12:52:47 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115052679 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.4115052679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.3489538417 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 121179481 ps |
| CPU time | 3.64 seconds |
| Started | Sep 11 12:52:35 PM UTC 24 |
| Finished | Sep 11 12:52:40 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489538417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3489538417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.2014900588 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 39281699 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 12:52:25 PM UTC 24 |
| Finished | Sep 11 12:52:27 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014900588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2014900588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.1396580798 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 6942096604 ps |
| CPU time | 52.2 seconds |
| Started | Sep 11 12:52:41 PM UTC 24 |
| Finished | Sep 11 12:53:35 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396580798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1396580798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3152195720 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 49697488260 ps |
| CPU time | 133.47 seconds |
| Started | Sep 11 12:52:41 PM UTC 24 |
| Finished | Sep 11 12:54:57 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152195720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3152195720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3742107016 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 7035314123 ps |
| CPU time | 110.59 seconds |
| Started | Sep 11 12:52:41 PM UTC 24 |
| Finished | Sep 11 12:54:34 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742107016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.3742107016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.1824819590 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3520274832 ps |
| CPU time | 26.43 seconds |
| Started | Sep 11 12:52:36 PM UTC 24 |
| Finished | Sep 11 12:53:04 PM UTC 24 |
| Peak memory | 261700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824819590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1824819590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.372659078 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 25576026 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 12:52:38 PM UTC 24 |
| Finished | Sep 11 12:52:40 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372659078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.372659078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.1327422135 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2336793632 ps |
| CPU time | 26.84 seconds |
| Started | Sep 11 12:52:32 PM UTC 24 |
| Finished | Sep 11 12:53:01 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327422135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1327422135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.3182695347 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1375706701 ps |
| CPU time | 11.62 seconds |
| Started | Sep 11 12:52:34 PM UTC 24 |
| Finished | Sep 11 12:52:47 PM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182695347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3182695347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.3426785575 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 688771357 ps |
| CPU time | 5.73 seconds |
| Started | Sep 11 12:52:32 PM UTC 24 |
| Finished | Sep 11 12:52:39 PM UTC 24 |
| Peak memory | 241828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426785575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.3426785575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2352295732 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1722021437 ps |
| CPU time | 7.03 seconds |
| Started | Sep 11 12:52:31 PM UTC 24 |
| Finished | Sep 11 12:52:39 PM UTC 24 |
| Peak memory | 234916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352295732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2352295732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.668873542 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 544729158 ps |
| CPU time | 6.22 seconds |
| Started | Sep 11 12:52:38 PM UTC 24 |
| Finished | Sep 11 12:52:45 PM UTC 24 |
| Peak memory | 231316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668873542 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.668873542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.888226829 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 78247911276 ps |
| CPU time | 348.67 seconds |
| Started | Sep 11 12:52:41 PM UTC 24 |
| Finished | Sep 11 12:58:34 PM UTC 24 |
| Peak memory | 267876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888226829 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.888226829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.557857715 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4447754148 ps |
| CPU time | 6.84 seconds |
| Started | Sep 11 12:52:26 PM UTC 24 |
| Finished | Sep 11 12:52:34 PM UTC 24 |
| Peak memory | 231632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557857715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.557857715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.324451276 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3313120486 ps |
| CPU time | 11.2 seconds |
| Started | Sep 11 12:52:25 PM UTC 24 |
| Finished | Sep 11 12:52:37 PM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324451276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.324451276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.2799533214 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 24257482 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 12:52:29 PM UTC 24 |
| Finished | Sep 11 12:52:31 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799533214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2799533214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.1017018127 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 63552240 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 12:52:29 PM UTC 24 |
| Finished | Sep 11 12:52:31 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017018127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1017018127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.867708175 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1624976485 ps |
| CPU time | 8.52 seconds |
| Started | Sep 11 12:52:34 PM UTC 24 |
| Finished | Sep 11 12:52:43 PM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867708175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.867708175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.2697773188 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 14344064 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:53:04 PM UTC 24 |
| Finished | Sep 11 12:53:06 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697773188 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.2697773188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3307121987 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 77033957 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 12:52:58 PM UTC 24 |
| Finished | Sep 11 12:53:02 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307121987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3307121987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.2100758021 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 166119203 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 12:52:45 PM UTC 24 |
| Finished | Sep 11 12:52:47 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100758021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2100758021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.508764282 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 6291178938 ps |
| CPU time | 61.04 seconds |
| Started | Sep 11 12:53:02 PM UTC 24 |
| Finished | Sep 11 12:54:04 PM UTC 24 |
| Peak memory | 265844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508764282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.508764282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.918239067 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 34095464932 ps |
| CPU time | 147.12 seconds |
| Started | Sep 11 12:53:02 PM UTC 24 |
| Finished | Sep 11 12:55:31 PM UTC 24 |
| Peak memory | 267976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918239067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.918239067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.18639214 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 152397437 ps |
| CPU time | 4.23 seconds |
| Started | Sep 11 12:53:00 PM UTC 24 |
| Finished | Sep 11 12:53:05 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18639214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.18639214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.129893303 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 221063109649 ps |
| CPU time | 368.93 seconds |
| Started | Sep 11 12:53:00 PM UTC 24 |
| Finished | Sep 11 12:59:14 PM UTC 24 |
| Peak memory | 267932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129893303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.129893303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.2223678701 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2142063809 ps |
| CPU time | 12.5 seconds |
| Started | Sep 11 12:52:49 PM UTC 24 |
| Finished | Sep 11 12:53:02 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223678701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2223678701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1339588503 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 281592906 ps |
| CPU time | 8.66 seconds |
| Started | Sep 11 12:52:52 PM UTC 24 |
| Finished | Sep 11 12:53:02 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339588503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1339588503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.309812843 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1182076832 ps |
| CPU time | 9.39 seconds |
| Started | Sep 11 12:52:49 PM UTC 24 |
| Finished | Sep 11 12:52:59 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309812843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.309812843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.867715670 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 153418286745 ps |
| CPU time | 37.45 seconds |
| Started | Sep 11 12:52:49 PM UTC 24 |
| Finished | Sep 11 12:53:27 PM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867715670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.867715670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.2058728384 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 111154285 ps |
| CPU time | 4.39 seconds |
| Started | Sep 11 12:53:02 PM UTC 24 |
| Finished | Sep 11 12:53:07 PM UTC 24 |
| Peak memory | 233348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058728384 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.2058728384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1286717911 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 56778440754 ps |
| CPU time | 536.94 seconds |
| Started | Sep 11 12:53:04 PM UTC 24 |
| Finished | Sep 11 01:02:08 PM UTC 24 |
| Peak memory | 284300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286717911 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.1286717911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.4189808108 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 10297040390 ps |
| CPU time | 31.88 seconds |
| Started | Sep 11 12:52:46 PM UTC 24 |
| Finished | Sep 11 12:53:20 PM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189808108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4189808108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3381070556 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5639787139 ps |
| CPU time | 8.76 seconds |
| Started | Sep 11 12:52:46 PM UTC 24 |
| Finished | Sep 11 12:52:56 PM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381070556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3381070556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.2282777498 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 456630264 ps |
| CPU time | 1.7 seconds |
| Started | Sep 11 12:52:49 PM UTC 24 |
| Finished | Sep 11 12:52:51 PM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282777498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2282777498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.4253799669 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 158556396 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 12:52:48 PM UTC 24 |
| Finished | Sep 11 12:52:51 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253799669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4253799669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.3057950581 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 298803180 ps |
| CPU time | 7.5 seconds |
| Started | Sep 11 12:52:52 PM UTC 24 |
| Finished | Sep 11 12:53:01 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057950581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3057950581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.2249398851 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 15957474 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:53:29 PM UTC 24 |
| Finished | Sep 11 12:53:31 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249398851 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.2249398851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1713876675 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1093408662 ps |
| CPU time | 5.85 seconds |
| Started | Sep 11 12:53:13 PM UTC 24 |
| Finished | Sep 11 12:53:19 PM UTC 24 |
| Peak memory | 234920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713876675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1713876675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.2665226751 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 23615693 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 12:53:04 PM UTC 24 |
| Finished | Sep 11 12:53:06 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665226751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2665226751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.1884469311 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4564579553 ps |
| CPU time | 50.9 seconds |
| Started | Sep 11 12:53:21 PM UTC 24 |
| Finished | Sep 11 12:54:13 PM UTC 24 |
| Peak memory | 267360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884469311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1884469311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3163606959 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 83809318132 ps |
| CPU time | 84.41 seconds |
| Started | Sep 11 12:53:22 PM UTC 24 |
| Finished | Sep 11 12:54:48 PM UTC 24 |
| Peak memory | 261760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163606959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3163606959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2694073675 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 19610184064 ps |
| CPU time | 159.47 seconds |
| Started | Sep 11 12:53:25 PM UTC 24 |
| Finished | Sep 11 12:56:07 PM UTC 24 |
| Peak memory | 267948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694073675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.2694073675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.1075711740 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 143607714 ps |
| CPU time | 3.49 seconds |
| Started | Sep 11 12:53:16 PM UTC 24 |
| Finished | Sep 11 12:53:20 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075711740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1075711740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2410203781 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 39572137156 ps |
| CPU time | 132.87 seconds |
| Started | Sep 11 12:53:17 PM UTC 24 |
| Finished | Sep 11 12:55:32 PM UTC 24 |
| Peak memory | 274060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410203781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.2410203781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.737000860 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1448355046 ps |
| CPU time | 7.38 seconds |
| Started | Sep 11 12:53:08 PM UTC 24 |
| Finished | Sep 11 12:53:16 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737000860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.737000860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.842863954 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 11828087084 ps |
| CPU time | 32.97 seconds |
| Started | Sep 11 12:53:09 PM UTC 24 |
| Finished | Sep 11 12:53:43 PM UTC 24 |
| Peak memory | 261724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842863954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.842863954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.504323774 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 6753385067 ps |
| CPU time | 29.35 seconds |
| Started | Sep 11 12:53:08 PM UTC 24 |
| Finished | Sep 11 12:53:38 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504323774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.504323774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3128353944 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4426776679 ps |
| CPU time | 21.1 seconds |
| Started | Sep 11 12:53:08 PM UTC 24 |
| Finished | Sep 11 12:53:30 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128353944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3128353944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2177821280 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3614415516 ps |
| CPU time | 13.83 seconds |
| Started | Sep 11 12:53:21 PM UTC 24 |
| Finished | Sep 11 12:53:36 PM UTC 24 |
| Peak memory | 232776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177821280 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2177821280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1398541352 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 230130724540 ps |
| CPU time | 345 seconds |
| Started | Sep 11 12:53:26 PM UTC 24 |
| Finished | Sep 11 12:59:16 PM UTC 24 |
| Peak memory | 265852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398541352 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.1398541352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.727027863 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 9387418138 ps |
| CPU time | 51.58 seconds |
| Started | Sep 11 12:53:04 PM UTC 24 |
| Finished | Sep 11 12:53:57 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727027863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.727027863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1300975466 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 1194224244 ps |
| CPU time | 9.62 seconds |
| Started | Sep 11 12:53:04 PM UTC 24 |
| Finished | Sep 11 12:53:15 PM UTC 24 |
| Peak memory | 227468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300975466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1300975466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.4142378999 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 472527726 ps |
| CPU time | 3.02 seconds |
| Started | Sep 11 12:53:07 PM UTC 24 |
| Finished | Sep 11 12:53:12 PM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142378999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4142378999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.4268025794 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 38188377 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:53:06 PM UTC 24 |
| Finished | Sep 11 12:53:08 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268025794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4268025794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.2016551524 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 11272800676 ps |
| CPU time | 18.2 seconds |
| Started | Sep 11 12:53:09 PM UTC 24 |
| Finished | Sep 11 12:53:29 PM UTC 24 |
| Peak memory | 245384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016551524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2016551524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.5736041 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 70031931 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 12:53:46 PM UTC 24 |
| Finished | Sep 11 12:53:48 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5736041 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.5736041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.227616119 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 151102159 ps |
| CPU time | 4.6 seconds |
| Started | Sep 11 12:53:39 PM UTC 24 |
| Finished | Sep 11 12:53:45 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227616119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.227616119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.724434370 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 50472512 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:53:30 PM UTC 24 |
| Finished | Sep 11 12:53:32 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724434370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.724434370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.1031757122 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 69460442721 ps |
| CPU time | 44.39 seconds |
| Started | Sep 11 12:53:42 PM UTC 24 |
| Finished | Sep 11 12:54:28 PM UTC 24 |
| Peak memory | 247368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031757122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1031757122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3846936449 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 58882278107 ps |
| CPU time | 122.88 seconds |
| Started | Sep 11 12:53:44 PM UTC 24 |
| Finished | Sep 11 12:55:49 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846936449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3846936449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.666381941 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 4624671425 ps |
| CPU time | 44.29 seconds |
| Started | Sep 11 12:53:46 PM UTC 24 |
| Finished | Sep 11 12:54:32 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666381941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.666381941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.3865671097 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 42915100 ps |
| CPU time | 3.1 seconds |
| Started | Sep 11 12:53:41 PM UTC 24 |
| Finished | Sep 11 12:53:45 PM UTC 24 |
| Peak memory | 234860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865671097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3865671097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.2262379584 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 55116709312 ps |
| CPU time | 226.56 seconds |
| Started | Sep 11 12:53:41 PM UTC 24 |
| Finished | Sep 11 12:57:31 PM UTC 24 |
| Peak memory | 263748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262379584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.2262379584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.1103756232 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 181020455 ps |
| CPU time | 7.77 seconds |
| Started | Sep 11 12:53:38 PM UTC 24 |
| Finished | Sep 11 12:53:46 PM UTC 24 |
| Peak memory | 244988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103756232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1103756232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.3807171096 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 15191202250 ps |
| CPU time | 26.13 seconds |
| Started | Sep 11 12:53:38 PM UTC 24 |
| Finished | Sep 11 12:54:05 PM UTC 24 |
| Peak memory | 247388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807171096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3807171096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.830997528 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 28864973 ps |
| CPU time | 3.05 seconds |
| Started | Sep 11 12:53:36 PM UTC 24 |
| Finished | Sep 11 12:53:40 PM UTC 24 |
| Peak memory | 244956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830997528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.830997528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.2841966066 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1255735727 ps |
| CPU time | 6.46 seconds |
| Started | Sep 11 12:53:35 PM UTC 24 |
| Finished | Sep 11 12:53:42 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841966066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2841966066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.902490790 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 1103778876 ps |
| CPU time | 6.53 seconds |
| Started | Sep 11 12:53:41 PM UTC 24 |
| Finished | Sep 11 12:53:49 PM UTC 24 |
| Peak memory | 233492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902490790 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.902490790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.1734958408 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 314923317 ps |
| CPU time | 1.44 seconds |
| Started | Sep 11 12:53:46 PM UTC 24 |
| Finished | Sep 11 12:53:49 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734958408 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.1734958408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.3798902675 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 22430175449 ps |
| CPU time | 42.93 seconds |
| Started | Sep 11 12:53:32 PM UTC 24 |
| Finished | Sep 11 12:54:16 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798902675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3798902675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1465226368 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 702445645 ps |
| CPU time | 6.29 seconds |
| Started | Sep 11 12:53:32 PM UTC 24 |
| Finished | Sep 11 12:53:39 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465226368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1465226368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.1685544349 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 189473659 ps |
| CPU time | 4.05 seconds |
| Started | Sep 11 12:53:33 PM UTC 24 |
| Finished | Sep 11 12:53:38 PM UTC 24 |
| Peak memory | 227428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685544349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1685544349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3173554666 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 967322841 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 12:53:33 PM UTC 24 |
| Finished | Sep 11 12:53:36 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173554666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3173554666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.4255079994 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 55721747508 ps |
| CPU time | 28.29 seconds |
| Started | Sep 11 12:53:39 PM UTC 24 |
| Finished | Sep 11 12:54:09 PM UTC 24 |
| Peak memory | 245316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255079994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4255079994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.1312649209 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 45894832 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:33:24 PM UTC 24 |
| Finished | Sep 11 12:33:26 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312649209 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1312649209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2395351502 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 410737967 ps |
| CPU time | 9.86 seconds |
| Started | Sep 11 12:33:04 PM UTC 24 |
| Finished | Sep 11 12:33:15 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395351502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2395351502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.756033878 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 30765325 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 12:32:47 PM UTC 24 |
| Finished | Sep 11 12:32:49 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756033878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.756033878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.1382885748 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 17877499741 ps |
| CPU time | 113.8 seconds |
| Started | Sep 11 12:33:10 PM UTC 24 |
| Finished | Sep 11 12:35:07 PM UTC 24 |
| Peak memory | 261700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382885748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1382885748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2698544094 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 35973009087 ps |
| CPU time | 232.43 seconds |
| Started | Sep 11 12:33:13 PM UTC 24 |
| Finished | Sep 11 12:37:10 PM UTC 24 |
| Peak memory | 278108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698544094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2698544094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1271708552 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 25342110557 ps |
| CPU time | 245.14 seconds |
| Started | Sep 11 12:33:16 PM UTC 24 |
| Finished | Sep 11 12:37:25 PM UTC 24 |
| Peak memory | 276084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271708552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.1271708552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.1045683936 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 959987293 ps |
| CPU time | 18.8 seconds |
| Started | Sep 11 12:33:04 PM UTC 24 |
| Finished | Sep 11 12:33:24 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045683936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1045683936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2648273982 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 29152959 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 12:33:07 PM UTC 24 |
| Finished | Sep 11 12:33:09 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648273982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.2648273982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.4051043005 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 878448918 ps |
| CPU time | 13.96 seconds |
| Started | Sep 11 12:32:54 PM UTC 24 |
| Finished | Sep 11 12:33:09 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051043005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4051043005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.4142535906 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1884337363 ps |
| CPU time | 30.37 seconds |
| Started | Sep 11 12:32:56 PM UTC 24 |
| Finished | Sep 11 12:33:28 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142535906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4142535906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1292766246 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 921978403 ps |
| CPU time | 8.8 seconds |
| Started | Sep 11 12:32:54 PM UTC 24 |
| Finished | Sep 11 12:33:04 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292766246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.1292766246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1875536277 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 779563176 ps |
| CPU time | 6.14 seconds |
| Started | Sep 11 12:32:53 PM UTC 24 |
| Finished | Sep 11 12:33:00 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875536277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1875536277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2615928699 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3501115834 ps |
| CPU time | 15.48 seconds |
| Started | Sep 11 12:33:09 PM UTC 24 |
| Finished | Sep 11 12:33:26 PM UTC 24 |
| Peak memory | 233492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615928699 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.2615928699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3839034323 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 35629156 ps |
| CPU time | 1.52 seconds |
| Started | Sep 11 12:33:21 PM UTC 24 |
| Finished | Sep 11 12:33:23 PM UTC 24 |
| Peak memory | 257904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839034323 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3839034323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2650663500 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 47635379293 ps |
| CPU time | 631.94 seconds |
| Started | Sep 11 12:33:21 PM UTC 24 |
| Finished | Sep 11 12:44:01 PM UTC 24 |
| Peak memory | 280172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650663500 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.2650663500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.1818204763 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3885182193 ps |
| CPU time | 28.61 seconds |
| Started | Sep 11 12:32:50 PM UTC 24 |
| Finished | Sep 11 12:33:20 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818204763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1818204763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1538884724 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3615753241 ps |
| CPU time | 11.41 seconds |
| Started | Sep 11 12:32:50 PM UTC 24 |
| Finished | Sep 11 12:33:03 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538884724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1538884724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2850634615 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 27622854 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 12:32:52 PM UTC 24 |
| Finished | Sep 11 12:32:55 PM UTC 24 |
| Peak memory | 217168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850634615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2850634615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2686943510 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 70169362 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 12:32:51 PM UTC 24 |
| Finished | Sep 11 12:32:53 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686943510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2686943510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.3243223271 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 798332512 ps |
| CPU time | 10.91 seconds |
| Started | Sep 11 12:33:01 PM UTC 24 |
| Finished | Sep 11 12:33:13 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243223271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3243223271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.2008733684 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 13895692 ps |
| CPU time | 0.99 seconds |
| Started | Sep 11 12:54:07 PM UTC 24 |
| Finished | Sep 11 12:54:09 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008733684 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.2008733684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.731668376 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 137273980 ps |
| CPU time | 3.77 seconds |
| Started | Sep 11 12:53:56 PM UTC 24 |
| Finished | Sep 11 12:54:01 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731668376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.731668376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.1972467938 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 36040212 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:53:47 PM UTC 24 |
| Finished | Sep 11 12:53:50 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972467938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1972467938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.3319868933 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 727952471818 ps |
| CPU time | 281.65 seconds |
| Started | Sep 11 12:53:59 PM UTC 24 |
| Finished | Sep 11 12:58:45 PM UTC 24 |
| Peak memory | 261700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319868933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3319868933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.747144129 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 393542304587 ps |
| CPU time | 189.15 seconds |
| Started | Sep 11 12:54:02 PM UTC 24 |
| Finished | Sep 11 12:57:15 PM UTC 24 |
| Peak memory | 267920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747144129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.747144129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2640824800 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 6312026554 ps |
| CPU time | 53.54 seconds |
| Started | Sep 11 12:54:07 PM UTC 24 |
| Finished | Sep 11 12:55:02 PM UTC 24 |
| Peak memory | 229668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640824800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.2640824800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2108254064 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2732883372 ps |
| CPU time | 30.84 seconds |
| Started | Sep 11 12:53:58 PM UTC 24 |
| Finished | Sep 11 12:54:30 PM UTC 24 |
| Peak memory | 261636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108254064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2108254064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1960043014 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 88103974790 ps |
| CPU time | 130.04 seconds |
| Started | Sep 11 12:53:58 PM UTC 24 |
| Finished | Sep 11 12:56:10 PM UTC 24 |
| Peak memory | 261660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960043014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.1960043014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.2475820866 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1802381361 ps |
| CPU time | 18.68 seconds |
| Started | Sep 11 12:53:51 PM UTC 24 |
| Finished | Sep 11 12:54:11 PM UTC 24 |
| Peak memory | 231656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475820866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2475820866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.3206213253 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3272591274 ps |
| CPU time | 19.53 seconds |
| Started | Sep 11 12:53:52 PM UTC 24 |
| Finished | Sep 11 12:54:13 PM UTC 24 |
| Peak memory | 249408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206213253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3206213253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.654748830 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 3855917219 ps |
| CPU time | 17.63 seconds |
| Started | Sep 11 12:53:51 PM UTC 24 |
| Finished | Sep 11 12:54:10 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654748830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.654748830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2905934307 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2466009996 ps |
| CPU time | 5.51 seconds |
| Started | Sep 11 12:53:49 PM UTC 24 |
| Finished | Sep 11 12:53:56 PM UTC 24 |
| Peak memory | 235052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905934307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2905934307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3510684782 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 735979109 ps |
| CPU time | 5.3 seconds |
| Started | Sep 11 12:53:59 PM UTC 24 |
| Finished | Sep 11 12:54:05 PM UTC 24 |
| Peak memory | 233312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510684782 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.3510684782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.133184727 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 39481266 ps |
| CPU time | 1.4 seconds |
| Started | Sep 11 12:54:07 PM UTC 24 |
| Finished | Sep 11 12:54:09 PM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133184727 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.133184727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.2121567824 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1956107866 ps |
| CPU time | 44.72 seconds |
| Started | Sep 11 12:53:48 PM UTC 24 |
| Finished | Sep 11 12:54:34 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121567824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2121567824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1833288713 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1358971157 ps |
| CPU time | 6.17 seconds |
| Started | Sep 11 12:53:48 PM UTC 24 |
| Finished | Sep 11 12:53:55 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833288713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1833288713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.92776156 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 36338718 ps |
| CPU time | 1.73 seconds |
| Started | Sep 11 12:53:49 PM UTC 24 |
| Finished | Sep 11 12:53:52 PM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92776156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.92776156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1307767181 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 32093053 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:53:49 PM UTC 24 |
| Finished | Sep 11 12:53:52 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307767181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1307767181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.4223432765 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 796373863 ps |
| CPU time | 2.74 seconds |
| Started | Sep 11 12:53:54 PM UTC 24 |
| Finished | Sep 11 12:53:57 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223432765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4223432765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2427383614 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 30590461 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:54:25 PM UTC 24 |
| Finished | Sep 11 12:54:28 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427383614 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.2427383614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2094363111 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 773044125 ps |
| CPU time | 4.44 seconds |
| Started | Sep 11 12:54:15 PM UTC 24 |
| Finished | Sep 11 12:54:20 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094363111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2094363111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1901637054 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 14770921 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 12:54:07 PM UTC 24 |
| Finished | Sep 11 12:54:09 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901637054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1901637054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3534045190 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 9229318451 ps |
| CPU time | 84.39 seconds |
| Started | Sep 11 12:54:18 PM UTC 24 |
| Finished | Sep 11 12:55:44 PM UTC 24 |
| Peak memory | 247368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534045190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3534045190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1406330621 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4129122292 ps |
| CPU time | 54.42 seconds |
| Started | Sep 11 12:54:18 PM UTC 24 |
| Finished | Sep 11 12:55:14 PM UTC 24 |
| Peak memory | 261760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406330621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1406330621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.110855794 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 14518209747 ps |
| CPU time | 201.37 seconds |
| Started | Sep 11 12:54:19 PM UTC 24 |
| Finished | Sep 11 12:57:44 PM UTC 24 |
| Peak memory | 278128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110855794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.110855794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.957167866 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 978822135 ps |
| CPU time | 7.78 seconds |
| Started | Sep 11 12:54:15 PM UTC 24 |
| Finished | Sep 11 12:54:24 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957167866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.957167866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.249632894 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 10693285 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 12:54:15 PM UTC 24 |
| Finished | Sep 11 12:54:17 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249632894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.249632894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.841199061 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 3421765401 ps |
| CPU time | 20.66 seconds |
| Started | Sep 11 12:54:13 PM UTC 24 |
| Finished | Sep 11 12:54:34 PM UTC 24 |
| Peak memory | 235068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841199061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.841199061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.171895742 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 10579093086 ps |
| CPU time | 115 seconds |
| Started | Sep 11 12:54:15 PM UTC 24 |
| Finished | Sep 11 12:56:12 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171895742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.171895742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1450976355 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 7062778353 ps |
| CPU time | 10.17 seconds |
| Started | Sep 11 12:54:13 PM UTC 24 |
| Finished | Sep 11 12:54:24 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450976355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.1450976355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1993339117 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1183337162 ps |
| CPU time | 4.67 seconds |
| Started | Sep 11 12:54:13 PM UTC 24 |
| Finished | Sep 11 12:54:18 PM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993339117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1993339117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.1387856587 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 795493688 ps |
| CPU time | 9.3 seconds |
| Started | Sep 11 12:54:16 PM UTC 24 |
| Finished | Sep 11 12:54:27 PM UTC 24 |
| Peak memory | 233356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387856587 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.1387856587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.3222177293 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 591421095 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 12:54:22 PM UTC 24 |
| Finished | Sep 11 12:54:24 PM UTC 24 |
| Peak memory | 215728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222177293 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.3222177293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.2870619901 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 50991456 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:54:11 PM UTC 24 |
| Finished | Sep 11 12:54:13 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870619901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2870619901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.3751552418 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 982251646 ps |
| CPU time | 4.01 seconds |
| Started | Sep 11 12:54:11 PM UTC 24 |
| Finished | Sep 11 12:54:16 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751552418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3751552418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.3814258584 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 125698638 ps |
| CPU time | 2.48 seconds |
| Started | Sep 11 12:54:11 PM UTC 24 |
| Finished | Sep 11 12:54:14 PM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814258584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3814258584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.238344544 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 336205195 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:54:11 PM UTC 24 |
| Finished | Sep 11 12:54:13 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238344544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.238344544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.2784251208 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 7677669592 ps |
| CPU time | 13.36 seconds |
| Started | Sep 11 12:54:15 PM UTC 24 |
| Finished | Sep 11 12:54:29 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784251208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2784251208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.905141054 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 13876806 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:54:37 PM UTC 24 |
| Finished | Sep 11 12:54:39 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905141054 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.905141054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3108665931 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1093231836 ps |
| CPU time | 4.95 seconds |
| Started | Sep 11 12:54:31 PM UTC 24 |
| Finished | Sep 11 12:54:37 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108665931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3108665931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2490590793 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 45146594 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 12:54:26 PM UTC 24 |
| Finished | Sep 11 12:54:28 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490590793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2490590793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.4013065745 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2731521167 ps |
| CPU time | 37.18 seconds |
| Started | Sep 11 12:54:37 PM UTC 24 |
| Finished | Sep 11 12:55:16 PM UTC 24 |
| Peak memory | 263756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013065745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4013065745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2660821191 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 31432688508 ps |
| CPU time | 151.51 seconds |
| Started | Sep 11 12:54:37 PM UTC 24 |
| Finished | Sep 11 12:57:11 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660821191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2660821191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.1141297142 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 28843665679 ps |
| CPU time | 128.42 seconds |
| Started | Sep 11 12:54:37 PM UTC 24 |
| Finished | Sep 11 12:56:48 PM UTC 24 |
| Peak memory | 263784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141297142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.1141297142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3490389704 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 12037658165 ps |
| CPU time | 74.45 seconds |
| Started | Sep 11 12:54:33 PM UTC 24 |
| Finished | Sep 11 12:55:49 PM UTC 24 |
| Peak memory | 260816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490389704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.3490389704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2624780703 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 313811673 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 12:54:31 PM UTC 24 |
| Finished | Sep 11 12:54:35 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624780703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2624780703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.563573343 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 27816350 ps |
| CPU time | 2.59 seconds |
| Started | Sep 11 12:54:31 PM UTC 24 |
| Finished | Sep 11 12:54:35 PM UTC 24 |
| Peak memory | 233584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563573343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.563573343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2231376462 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 15196790538 ps |
| CPU time | 16.72 seconds |
| Started | Sep 11 12:54:29 PM UTC 24 |
| Finished | Sep 11 12:54:47 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231376462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.2231376462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2982630827 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2156061194 ps |
| CPU time | 11.57 seconds |
| Started | Sep 11 12:54:29 PM UTC 24 |
| Finished | Sep 11 12:54:42 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982630827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2982630827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2684770383 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 177886317 ps |
| CPU time | 6.75 seconds |
| Started | Sep 11 12:54:33 PM UTC 24 |
| Finished | Sep 11 12:54:41 PM UTC 24 |
| Peak memory | 233500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684770383 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2684770383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.1262661981 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 7855346950 ps |
| CPU time | 106.09 seconds |
| Started | Sep 11 12:54:37 PM UTC 24 |
| Finished | Sep 11 12:56:25 PM UTC 24 |
| Peak memory | 261820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262661981 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.1262661981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.2136912020 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2994489743 ps |
| CPU time | 30.94 seconds |
| Started | Sep 11 12:54:27 PM UTC 24 |
| Finished | Sep 11 12:54:59 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136912020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2136912020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2448119649 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 4443251845 ps |
| CPU time | 7.69 seconds |
| Started | Sep 11 12:54:26 PM UTC 24 |
| Finished | Sep 11 12:54:34 PM UTC 24 |
| Peak memory | 227664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448119649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2448119649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.4010246418 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 24264120 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 12:54:29 PM UTC 24 |
| Finished | Sep 11 12:54:31 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010246418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4010246418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1566692778 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 55965381 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 12:54:27 PM UTC 24 |
| Finished | Sep 11 12:54:30 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566692778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1566692778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.1821931671 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 825437975 ps |
| CPU time | 2.39 seconds |
| Started | Sep 11 12:54:31 PM UTC 24 |
| Finished | Sep 11 12:54:35 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821931671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1821931671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.3910884680 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 12942471 ps |
| CPU time | 1.08 seconds |
| Started | Sep 11 12:54:56 PM UTC 24 |
| Finished | Sep 11 12:54:58 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910884680 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.3910884680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.3380269863 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 515976751 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 12:54:48 PM UTC 24 |
| Finished | Sep 11 12:54:54 PM UTC 24 |
| Peak memory | 235076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380269863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3380269863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1073895000 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 34270452 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:54:37 PM UTC 24 |
| Finished | Sep 11 12:54:39 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073895000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1073895000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1845295571 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 65029431955 ps |
| CPU time | 141.99 seconds |
| Started | Sep 11 12:54:52 PM UTC 24 |
| Finished | Sep 11 12:57:17 PM UTC 24 |
| Peak memory | 261848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845295571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1845295571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3948127599 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 5206795442 ps |
| CPU time | 20.87 seconds |
| Started | Sep 11 12:54:52 PM UTC 24 |
| Finished | Sep 11 12:55:14 PM UTC 24 |
| Peak memory | 231632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948127599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3948127599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.959905608 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 4649781686 ps |
| CPU time | 41.56 seconds |
| Started | Sep 11 12:54:55 PM UTC 24 |
| Finished | Sep 11 12:55:38 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959905608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.959905608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.1339762120 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2185765516 ps |
| CPU time | 33.65 seconds |
| Started | Sep 11 12:54:48 PM UTC 24 |
| Finished | Sep 11 12:55:23 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339762120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1339762120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1597528611 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 3940449774 ps |
| CPU time | 65.9 seconds |
| Started | Sep 11 12:54:50 PM UTC 24 |
| Finished | Sep 11 12:55:57 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597528611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1597528611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.2141469114 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 476638711 ps |
| CPU time | 8.05 seconds |
| Started | Sep 11 12:54:42 PM UTC 24 |
| Finished | Sep 11 12:54:51 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141469114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2141469114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1604450759 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 1833558720 ps |
| CPU time | 14.41 seconds |
| Started | Sep 11 12:54:43 PM UTC 24 |
| Finished | Sep 11 12:54:59 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604450759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1604450759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3669540494 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3139329919 ps |
| CPU time | 22.17 seconds |
| Started | Sep 11 12:54:42 PM UTC 24 |
| Finished | Sep 11 12:55:05 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669540494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.3669540494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3403522576 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 27286421498 ps |
| CPU time | 19.85 seconds |
| Started | Sep 11 12:54:40 PM UTC 24 |
| Finished | Sep 11 12:55:01 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403522576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3403522576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3326748001 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 112691356 ps |
| CPU time | 4.64 seconds |
| Started | Sep 11 12:54:50 PM UTC 24 |
| Finished | Sep 11 12:54:55 PM UTC 24 |
| Peak memory | 233732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326748001 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.3326748001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.4147219742 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1316988575 ps |
| CPU time | 32.17 seconds |
| Started | Sep 11 12:54:56 PM UTC 24 |
| Finished | Sep 11 12:55:30 PM UTC 24 |
| Peak memory | 261628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147219742 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.4147219742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.2370087685 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 4279610799 ps |
| CPU time | 18.22 seconds |
| Started | Sep 11 12:54:37 PM UTC 24 |
| Finished | Sep 11 12:54:57 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370087685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2370087685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.4013577217 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 673678372 ps |
| CPU time | 9.36 seconds |
| Started | Sep 11 12:54:37 PM UTC 24 |
| Finished | Sep 11 12:54:48 PM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013577217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4013577217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2529913633 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1747069702 ps |
| CPU time | 5.92 seconds |
| Started | Sep 11 12:54:40 PM UTC 24 |
| Finished | Sep 11 12:54:47 PM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529913633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2529913633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2725935046 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 116876747 ps |
| CPU time | 1.33 seconds |
| Started | Sep 11 12:54:39 PM UTC 24 |
| Finished | Sep 11 12:54:41 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725935046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2725935046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2457553500 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4019849005 ps |
| CPU time | 19.12 seconds |
| Started | Sep 11 12:54:43 PM UTC 24 |
| Finished | Sep 11 12:55:04 PM UTC 24 |
| Peak memory | 245316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457553500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2457553500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3493424603 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 11200277 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:55:15 PM UTC 24 |
| Finished | Sep 11 12:55:18 PM UTC 24 |
| Peak memory | 214900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493424603 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3493424603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.4229680639 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 591022100 ps |
| CPU time | 7.04 seconds |
| Started | Sep 11 12:55:06 PM UTC 24 |
| Finished | Sep 11 12:55:14 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229680639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4229680639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.1194153401 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 46929883 ps |
| CPU time | 1.11 seconds |
| Started | Sep 11 12:54:57 PM UTC 24 |
| Finished | Sep 11 12:55:00 PM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194153401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1194153401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.3094642432 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 12829875320 ps |
| CPU time | 26.89 seconds |
| Started | Sep 11 12:55:11 PM UTC 24 |
| Finished | Sep 11 12:55:39 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094642432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3094642432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1821611316 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 10671629650 ps |
| CPU time | 125.91 seconds |
| Started | Sep 11 12:55:12 PM UTC 24 |
| Finished | Sep 11 12:57:21 PM UTC 24 |
| Peak memory | 263792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821611316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1821611316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1945980577 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 21361011035 ps |
| CPU time | 41.83 seconds |
| Started | Sep 11 12:55:12 PM UTC 24 |
| Finished | Sep 11 12:55:56 PM UTC 24 |
| Peak memory | 235068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945980577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1945980577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.232152614 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3611267630 ps |
| CPU time | 16.36 seconds |
| Started | Sep 11 12:55:06 PM UTC 24 |
| Finished | Sep 11 12:55:23 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232152614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.232152614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1035897518 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3627396879 ps |
| CPU time | 26.12 seconds |
| Started | Sep 11 12:55:07 PM UTC 24 |
| Finished | Sep 11 12:55:35 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035897518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.1035897518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.172871663 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 552753859 ps |
| CPU time | 6.92 seconds |
| Started | Sep 11 12:55:03 PM UTC 24 |
| Finished | Sep 11 12:55:11 PM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172871663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.172871663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.3437405003 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 5771307180 ps |
| CPU time | 33.46 seconds |
| Started | Sep 11 12:55:04 PM UTC 24 |
| Finished | Sep 11 12:55:39 PM UTC 24 |
| Peak memory | 245252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437405003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3437405003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.444413826 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1746551177 ps |
| CPU time | 7.48 seconds |
| Started | Sep 11 12:55:03 PM UTC 24 |
| Finished | Sep 11 12:55:11 PM UTC 24 |
| Peak memory | 248796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444413826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.444413826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.318435750 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 89326851 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 12:55:01 PM UTC 24 |
| Finished | Sep 11 12:55:04 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318435750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.318435750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.582121714 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2527601643 ps |
| CPU time | 8.83 seconds |
| Started | Sep 11 12:55:07 PM UTC 24 |
| Finished | Sep 11 12:55:17 PM UTC 24 |
| Peak memory | 231376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582121714 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.582121714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.583574910 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 4491908675 ps |
| CPU time | 32.63 seconds |
| Started | Sep 11 12:54:59 PM UTC 24 |
| Finished | Sep 11 12:55:33 PM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583574910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.583574910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.4115748946 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 40026418 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:54:59 PM UTC 24 |
| Finished | Sep 11 12:55:01 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115748946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4115748946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.2877703958 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 389082374 ps |
| CPU time | 6.99 seconds |
| Started | Sep 11 12:55:01 PM UTC 24 |
| Finished | Sep 11 12:55:09 PM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877703958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2877703958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.2664313403 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 34905328 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 12:55:01 PM UTC 24 |
| Finished | Sep 11 12:55:03 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664313403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2664313403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2845941132 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 384064617 ps |
| CPU time | 8.01 seconds |
| Started | Sep 11 12:55:04 PM UTC 24 |
| Finished | Sep 11 12:55:13 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845941132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2845941132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.669850644 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 23261127 ps |
| CPU time | 0.97 seconds |
| Started | Sep 11 12:55:30 PM UTC 24 |
| Finished | Sep 11 12:55:33 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669850644 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.669850644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.38816043 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 1912956113 ps |
| CPU time | 7.79 seconds |
| Started | Sep 11 12:55:22 PM UTC 24 |
| Finished | Sep 11 12:55:31 PM UTC 24 |
| Peak memory | 234884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38816043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.38816043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3086325120 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 44390023 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:55:15 PM UTC 24 |
| Finished | Sep 11 12:55:18 PM UTC 24 |
| Peak memory | 215284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086325120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3086325120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2906289373 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 36502316480 ps |
| CPU time | 198.5 seconds |
| Started | Sep 11 12:55:27 PM UTC 24 |
| Finished | Sep 11 12:58:48 PM UTC 24 |
| Peak memory | 265864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906289373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2906289373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3579071687 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 1344516644 ps |
| CPU time | 28.71 seconds |
| Started | Sep 11 12:55:27 PM UTC 24 |
| Finished | Sep 11 12:55:57 PM UTC 24 |
| Peak memory | 245312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579071687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3579071687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.791696918 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 2496563402 ps |
| CPU time | 47.67 seconds |
| Started | Sep 11 12:55:28 PM UTC 24 |
| Finished | Sep 11 12:56:17 PM UTC 24 |
| Peak memory | 263816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791696918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.791696918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1116104215 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 313043725 ps |
| CPU time | 11.63 seconds |
| Started | Sep 11 12:55:23 PM UTC 24 |
| Finished | Sep 11 12:55:36 PM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116104215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1116104215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1029196856 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 426105034 ps |
| CPU time | 16.65 seconds |
| Started | Sep 11 12:55:25 PM UTC 24 |
| Finished | Sep 11 12:55:43 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029196856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.1029196856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.1923548363 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 8425737557 ps |
| CPU time | 30.6 seconds |
| Started | Sep 11 12:55:21 PM UTC 24 |
| Finished | Sep 11 12:55:53 PM UTC 24 |
| Peak memory | 231560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923548363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1923548363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3705970188 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 489087355 ps |
| CPU time | 3.58 seconds |
| Started | Sep 11 12:55:21 PM UTC 24 |
| Finished | Sep 11 12:55:25 PM UTC 24 |
| Peak memory | 234760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705970188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3705970188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.748959177 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 9578333922 ps |
| CPU time | 24.73 seconds |
| Started | Sep 11 12:55:19 PM UTC 24 |
| Finished | Sep 11 12:55:45 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748959177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.748959177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1699674714 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 860552890 ps |
| CPU time | 6.63 seconds |
| Started | Sep 11 12:55:19 PM UTC 24 |
| Finished | Sep 11 12:55:27 PM UTC 24 |
| Peak memory | 235008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699674714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1699674714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1510941714 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 1225858626 ps |
| CPU time | 12.77 seconds |
| Started | Sep 11 12:55:25 PM UTC 24 |
| Finished | Sep 11 12:55:39 PM UTC 24 |
| Peak memory | 231244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510941714 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.1510941714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2876491413 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 13500378625 ps |
| CPU time | 211.89 seconds |
| Started | Sep 11 12:55:29 PM UTC 24 |
| Finished | Sep 11 12:59:05 PM UTC 24 |
| Peak memory | 284268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876491413 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.2876491413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3957336155 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 26804297164 ps |
| CPU time | 23.05 seconds |
| Started | Sep 11 12:55:17 PM UTC 24 |
| Finished | Sep 11 12:55:41 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957336155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3957336155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1670172646 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 296249162 ps |
| CPU time | 2.77 seconds |
| Started | Sep 11 12:55:15 PM UTC 24 |
| Finished | Sep 11 12:55:20 PM UTC 24 |
| Peak memory | 217076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670172646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1670172646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.2465918822 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 144253205 ps |
| CPU time | 2.26 seconds |
| Started | Sep 11 12:55:19 PM UTC 24 |
| Finished | Sep 11 12:55:22 PM UTC 24 |
| Peak memory | 227468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465918822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2465918822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2118120268 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 62399448 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 12:55:17 PM UTC 24 |
| Finished | Sep 11 12:55:19 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118120268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2118120268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.1680022683 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 17551232576 ps |
| CPU time | 44.19 seconds |
| Started | Sep 11 12:55:21 PM UTC 24 |
| Finished | Sep 11 12:56:06 PM UTC 24 |
| Peak memory | 235160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680022683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1680022683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.4286238330 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 51965847 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:55:42 PM UTC 24 |
| Finished | Sep 11 12:55:44 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286238330 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.4286238330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3480611874 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 106957650 ps |
| CPU time | 2.67 seconds |
| Started | Sep 11 12:55:40 PM UTC 24 |
| Finished | Sep 11 12:55:43 PM UTC 24 |
| Peak memory | 234608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480611874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3480611874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.4019902252 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 54089081 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 12:55:32 PM UTC 24 |
| Finished | Sep 11 12:55:34 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019902252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4019902252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.476819740 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 44155911101 ps |
| CPU time | 203.75 seconds |
| Started | Sep 11 12:55:42 PM UTC 24 |
| Finished | Sep 11 12:59:09 PM UTC 24 |
| Peak memory | 265796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476819740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.476819740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.853473733 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 42289959912 ps |
| CPU time | 430.64 seconds |
| Started | Sep 11 12:55:42 PM UTC 24 |
| Finished | Sep 11 01:02:58 PM UTC 24 |
| Peak memory | 278156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853473733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.853473733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2809238709 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 38357555301 ps |
| CPU time | 53.48 seconds |
| Started | Sep 11 12:55:42 PM UTC 24 |
| Finished | Sep 11 12:56:37 PM UTC 24 |
| Peak memory | 261768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809238709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.2809238709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.310507526 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 862614477 ps |
| CPU time | 4.67 seconds |
| Started | Sep 11 12:55:40 PM UTC 24 |
| Finished | Sep 11 12:55:45 PM UTC 24 |
| Peak memory | 235016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310507526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.310507526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3495314897 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 18711883721 ps |
| CPU time | 210.06 seconds |
| Started | Sep 11 12:55:40 PM UTC 24 |
| Finished | Sep 11 12:59:13 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495314897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.3495314897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.2619168841 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 1167900584 ps |
| CPU time | 10.92 seconds |
| Started | Sep 11 12:55:38 PM UTC 24 |
| Finished | Sep 11 12:55:50 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619168841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2619168841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.3116841485 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 2990678673 ps |
| CPU time | 6.53 seconds |
| Started | Sep 11 12:55:38 PM UTC 24 |
| Finished | Sep 11 12:55:45 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116841485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3116841485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3028496848 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 353928665 ps |
| CPU time | 5.5 seconds |
| Started | Sep 11 12:55:36 PM UTC 24 |
| Finished | Sep 11 12:55:43 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028496848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.3028496848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3103784296 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 57508096 ps |
| CPU time | 3.27 seconds |
| Started | Sep 11 12:55:36 PM UTC 24 |
| Finished | Sep 11 12:55:40 PM UTC 24 |
| Peak memory | 245248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103784296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3103784296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3136690441 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 8050727642 ps |
| CPU time | 14.22 seconds |
| Started | Sep 11 12:55:40 PM UTC 24 |
| Finished | Sep 11 12:55:55 PM UTC 24 |
| Peak memory | 231376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136690441 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.3136690441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.173572388 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 11160680302 ps |
| CPU time | 112.08 seconds |
| Started | Sep 11 12:55:42 PM UTC 24 |
| Finished | Sep 11 12:57:36 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173572388 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.173572388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.2653885180 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 488819761 ps |
| CPU time | 3.64 seconds |
| Started | Sep 11 12:55:34 PM UTC 24 |
| Finished | Sep 11 12:55:38 PM UTC 24 |
| Peak memory | 231568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653885180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2653885180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3238786713 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 6665598478 ps |
| CPU time | 5.57 seconds |
| Started | Sep 11 12:55:34 PM UTC 24 |
| Finished | Sep 11 12:55:41 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238786713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3238786713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.124273709 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 21147865 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 12:55:36 PM UTC 24 |
| Finished | Sep 11 12:55:38 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124273709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.124273709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1502688466 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 12509578 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:55:34 PM UTC 24 |
| Finished | Sep 11 12:55:36 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502688466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1502688466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.3366328313 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 4984302747 ps |
| CPU time | 20.75 seconds |
| Started | Sep 11 12:55:38 PM UTC 24 |
| Finished | Sep 11 12:56:00 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366328313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3366328313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.3609584306 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 30412095 ps |
| CPU time | 1.03 seconds |
| Started | Sep 11 12:55:56 PM UTC 24 |
| Finished | Sep 11 12:55:58 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609584306 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.3609584306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.967067864 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 1376505505 ps |
| CPU time | 6.44 seconds |
| Started | Sep 11 12:55:48 PM UTC 24 |
| Finished | Sep 11 12:55:55 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967067864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.967067864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3060696009 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 57464287 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 12:55:44 PM UTC 24 |
| Finished | Sep 11 12:55:47 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060696009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3060696009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3709456341 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 4736513574 ps |
| CPU time | 29.22 seconds |
| Started | Sep 11 12:55:51 PM UTC 24 |
| Finished | Sep 11 12:56:21 PM UTC 24 |
| Peak memory | 249412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709456341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3709456341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.4285364805 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 219364960102 ps |
| CPU time | 282.51 seconds |
| Started | Sep 11 12:55:51 PM UTC 24 |
| Finished | Sep 11 01:00:37 PM UTC 24 |
| Peak memory | 267876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285364805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4285364805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2653859079 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 235835069309 ps |
| CPU time | 511.29 seconds |
| Started | Sep 11 12:55:52 PM UTC 24 |
| Finished | Sep 11 01:04:30 PM UTC 24 |
| Peak memory | 267888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653859079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.2653859079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.792254359 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 6422676334 ps |
| CPU time | 28.67 seconds |
| Started | Sep 11 12:55:48 PM UTC 24 |
| Finished | Sep 11 12:56:18 PM UTC 24 |
| Peak memory | 235076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792254359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.792254359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.4080649226 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 18536893890 ps |
| CPU time | 146.32 seconds |
| Started | Sep 11 12:55:48 PM UTC 24 |
| Finished | Sep 11 12:58:17 PM UTC 24 |
| Peak memory | 267848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080649226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.4080649226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.1718691355 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 1721398070 ps |
| CPU time | 21.04 seconds |
| Started | Sep 11 12:55:46 PM UTC 24 |
| Finished | Sep 11 12:56:09 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718691355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1718691355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.3397546759 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 221605191 ps |
| CPU time | 3.64 seconds |
| Started | Sep 11 12:55:46 PM UTC 24 |
| Finished | Sep 11 12:55:51 PM UTC 24 |
| Peak memory | 241824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397546759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3397546759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3846750081 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 4829284866 ps |
| CPU time | 10.13 seconds |
| Started | Sep 11 12:55:46 PM UTC 24 |
| Finished | Sep 11 12:55:58 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846750081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.3846750081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.805078675 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1504423151 ps |
| CPU time | 14.25 seconds |
| Started | Sep 11 12:55:46 PM UTC 24 |
| Finished | Sep 11 12:56:02 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805078675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.805078675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.3223587303 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 389728168 ps |
| CPU time | 4.8 seconds |
| Started | Sep 11 12:55:51 PM UTC 24 |
| Finished | Sep 11 12:55:57 PM UTC 24 |
| Peak memory | 233564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223587303 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.3223587303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.2649221399 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 193565901 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 12:55:53 PM UTC 24 |
| Finished | Sep 11 12:55:56 PM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649221399 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.2649221399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.3945715654 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 14567730025 ps |
| CPU time | 39.23 seconds |
| Started | Sep 11 12:55:44 PM UTC 24 |
| Finished | Sep 11 12:56:25 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945715654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3945715654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2495875631 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 9604967590 ps |
| CPU time | 26.07 seconds |
| Started | Sep 11 12:55:44 PM UTC 24 |
| Finished | Sep 11 12:56:12 PM UTC 24 |
| Peak memory | 227588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495875631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2495875631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.3777203795 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 193898069 ps |
| CPU time | 1.89 seconds |
| Started | Sep 11 12:55:44 PM UTC 24 |
| Finished | Sep 11 12:55:47 PM UTC 24 |
| Peak memory | 226524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777203795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3777203795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3833974825 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 27917217 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:55:44 PM UTC 24 |
| Finished | Sep 11 12:55:47 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833974825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3833974825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.1910759411 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 2062720244 ps |
| CPU time | 8.06 seconds |
| Started | Sep 11 12:55:46 PM UTC 24 |
| Finished | Sep 11 12:55:56 PM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910759411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1910759411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.4052160337 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 13383449 ps |
| CPU time | 0.83 seconds |
| Started | Sep 11 12:56:06 PM UTC 24 |
| Finished | Sep 11 12:56:08 PM UTC 24 |
| Peak memory | 215732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052160337 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.4052160337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1818710024 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 56659920 ps |
| CPU time | 2.77 seconds |
| Started | Sep 11 12:56:01 PM UTC 24 |
| Finished | Sep 11 12:56:05 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818710024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1818710024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.223517257 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 105057750 ps |
| CPU time | 0.99 seconds |
| Started | Sep 11 12:55:56 PM UTC 24 |
| Finished | Sep 11 12:55:58 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223517257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.223517257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.289023428 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 1640419089 ps |
| CPU time | 23.12 seconds |
| Started | Sep 11 12:56:03 PM UTC 24 |
| Finished | Sep 11 12:56:27 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289023428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.289023428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2924385488 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 6459200078 ps |
| CPU time | 67.67 seconds |
| Started | Sep 11 12:56:03 PM UTC 24 |
| Finished | Sep 11 12:57:13 PM UTC 24 |
| Peak memory | 245372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924385488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2924385488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3111106323 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 43340824038 ps |
| CPU time | 433.76 seconds |
| Started | Sep 11 12:56:04 PM UTC 24 |
| Finished | Sep 11 01:03:24 PM UTC 24 |
| Peak memory | 282376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111106323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.3111106323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2689794255 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 142684800 ps |
| CPU time | 4.35 seconds |
| Started | Sep 11 12:56:03 PM UTC 24 |
| Finished | Sep 11 12:56:08 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689794255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2689794255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.2442726568 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 85296448093 ps |
| CPU time | 172.78 seconds |
| Started | Sep 11 12:56:03 PM UTC 24 |
| Finished | Sep 11 12:58:59 PM UTC 24 |
| Peak memory | 278092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442726568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.2442726568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3466971383 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2814687747 ps |
| CPU time | 4.91 seconds |
| Started | Sep 11 12:55:59 PM UTC 24 |
| Finished | Sep 11 12:56:05 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466971383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3466971383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.4088868522 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 320731071 ps |
| CPU time | 9.32 seconds |
| Started | Sep 11 12:56:01 PM UTC 24 |
| Finished | Sep 11 12:56:11 PM UTC 24 |
| Peak memory | 234868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088868522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4088868522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2034818270 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 910683020 ps |
| CPU time | 10.11 seconds |
| Started | Sep 11 12:55:59 PM UTC 24 |
| Finished | Sep 11 12:56:10 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034818270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2034818270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2599713736 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 71356019 ps |
| CPU time | 2.32 seconds |
| Started | Sep 11 12:55:59 PM UTC 24 |
| Finished | Sep 11 12:56:02 PM UTC 24 |
| Peak memory | 234440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599713736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2599713736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2912212296 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 1529871680 ps |
| CPU time | 8.09 seconds |
| Started | Sep 11 12:56:03 PM UTC 24 |
| Finished | Sep 11 12:56:12 PM UTC 24 |
| Peak memory | 231160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912212296 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2912212296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.4003976143 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 365857206 ps |
| CPU time | 1.37 seconds |
| Started | Sep 11 12:56:06 PM UTC 24 |
| Finished | Sep 11 12:56:08 PM UTC 24 |
| Peak memory | 215728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003976143 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.4003976143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.510877368 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 19466566841 ps |
| CPU time | 15.62 seconds |
| Started | Sep 11 12:55:59 PM UTC 24 |
| Finished | Sep 11 12:56:16 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510877368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.510877368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3168102249 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 41031562 ps |
| CPU time | 1.09 seconds |
| Started | Sep 11 12:55:59 PM UTC 24 |
| Finished | Sep 11 12:56:01 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168102249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3168102249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.2908944235 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 58823021 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 12:55:59 PM UTC 24 |
| Finished | Sep 11 12:56:02 PM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908944235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2908944235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.213587351 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 49131630 ps |
| CPU time | 1.3 seconds |
| Started | Sep 11 12:55:59 PM UTC 24 |
| Finished | Sep 11 12:56:01 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213587351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.213587351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.1414970991 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 24676743216 ps |
| CPU time | 24.22 seconds |
| Started | Sep 11 12:56:01 PM UTC 24 |
| Finished | Sep 11 12:56:27 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414970991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1414970991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.17145749 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 19539528 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:56:17 PM UTC 24 |
| Finished | Sep 11 12:56:19 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17145749 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.17145749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.787535660 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 749902785 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 12:56:13 PM UTC 24 |
| Finished | Sep 11 12:56:18 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787535660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.787535660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.1383710852 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 26539037 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 12:56:07 PM UTC 24 |
| Finished | Sep 11 12:56:10 PM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383710852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1383710852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.3000804723 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 27882274168 ps |
| CPU time | 171.87 seconds |
| Started | Sep 11 12:56:14 PM UTC 24 |
| Finished | Sep 11 12:59:08 PM UTC 24 |
| Peak memory | 261700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000804723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3000804723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2486301367 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3467401654 ps |
| CPU time | 17.77 seconds |
| Started | Sep 11 12:56:15 PM UTC 24 |
| Finished | Sep 11 12:56:34 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486301367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2486301367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1765752244 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 19273842645 ps |
| CPU time | 216.28 seconds |
| Started | Sep 11 12:56:16 PM UTC 24 |
| Finished | Sep 11 12:59:55 PM UTC 24 |
| Peak memory | 278152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765752244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.1765752244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.1053395923 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 119236333 ps |
| CPU time | 3.67 seconds |
| Started | Sep 11 12:56:14 PM UTC 24 |
| Finished | Sep 11 12:56:18 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053395923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1053395923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3182461701 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 41217888445 ps |
| CPU time | 140.23 seconds |
| Started | Sep 11 12:56:14 PM UTC 24 |
| Finished | Sep 11 12:58:36 PM UTC 24 |
| Peak memory | 278092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182461701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.3182461701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.137054700 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 223181724 ps |
| CPU time | 8.3 seconds |
| Started | Sep 11 12:56:11 PM UTC 24 |
| Finished | Sep 11 12:56:20 PM UTC 24 |
| Peak memory | 245076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137054700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.137054700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.778528636 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 608151814 ps |
| CPU time | 8.85 seconds |
| Started | Sep 11 12:56:13 PM UTC 24 |
| Finished | Sep 11 12:56:23 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778528636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.778528636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2616294343 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 59430209 ps |
| CPU time | 2.74 seconds |
| Started | Sep 11 12:56:11 PM UTC 24 |
| Finished | Sep 11 12:56:14 PM UTC 24 |
| Peak memory | 234044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616294343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.2616294343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1004264071 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2059563901 ps |
| CPU time | 14.6 seconds |
| Started | Sep 11 12:56:10 PM UTC 24 |
| Finished | Sep 11 12:56:26 PM UTC 24 |
| Peak memory | 245052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004264071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1004264071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1012474959 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 498998140 ps |
| CPU time | 4.86 seconds |
| Started | Sep 11 12:56:14 PM UTC 24 |
| Finished | Sep 11 12:56:20 PM UTC 24 |
| Peak memory | 231308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012474959 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.1012474959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.3291545433 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 5856128396 ps |
| CPU time | 91.17 seconds |
| Started | Sep 11 12:56:16 PM UTC 24 |
| Finished | Sep 11 12:57:49 PM UTC 24 |
| Peak memory | 261752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291545433 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.3291545433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1247229806 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 5145882371 ps |
| CPU time | 29.74 seconds |
| Started | Sep 11 12:56:10 PM UTC 24 |
| Finished | Sep 11 12:56:41 PM UTC 24 |
| Peak memory | 227728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247229806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1247229806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2406879214 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 349649413 ps |
| CPU time | 2.9 seconds |
| Started | Sep 11 12:56:10 PM UTC 24 |
| Finished | Sep 11 12:56:14 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406879214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2406879214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.2346283704 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 808756510 ps |
| CPU time | 5.52 seconds |
| Started | Sep 11 12:56:10 PM UTC 24 |
| Finished | Sep 11 12:56:17 PM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346283704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2346283704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.4150039490 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 111055815 ps |
| CPU time | 1.33 seconds |
| Started | Sep 11 12:56:10 PM UTC 24 |
| Finished | Sep 11 12:56:13 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150039490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4150039490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1988708303 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 12028800180 ps |
| CPU time | 16.86 seconds |
| Started | Sep 11 12:56:13 PM UTC 24 |
| Finished | Sep 11 12:56:31 PM UTC 24 |
| Peak memory | 247444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988708303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1988708303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.1538046442 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 39939397 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:34:13 PM UTC 24 |
| Finished | Sep 11 12:34:15 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538046442 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1538046442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3506915611 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 8942750579 ps |
| CPU time | 21.16 seconds |
| Started | Sep 11 12:33:55 PM UTC 24 |
| Finished | Sep 11 12:34:17 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506915611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3506915611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.1283120797 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 16532347 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 12:33:25 PM UTC 24 |
| Finished | Sep 11 12:33:27 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283120797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1283120797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2981186103 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 150674943 ps |
| CPU time | 6.25 seconds |
| Started | Sep 11 12:33:59 PM UTC 24 |
| Finished | Sep 11 12:34:06 PM UTC 24 |
| Peak memory | 234884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981186103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2981186103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2844581385 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 56109239489 ps |
| CPU time | 183.04 seconds |
| Started | Sep 11 12:34:00 PM UTC 24 |
| Finished | Sep 11 12:37:06 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844581385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.2844581385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.4259155961 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1461343612 ps |
| CPU time | 19.16 seconds |
| Started | Sep 11 12:33:38 PM UTC 24 |
| Finished | Sep 11 12:33:58 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259155961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4259155961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.184108686 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 15744768226 ps |
| CPU time | 50.18 seconds |
| Started | Sep 11 12:33:44 PM UTC 24 |
| Finished | Sep 11 12:34:36 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184108686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.184108686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3222517197 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2233475384 ps |
| CPU time | 15.52 seconds |
| Started | Sep 11 12:33:33 PM UTC 24 |
| Finished | Sep 11 12:33:51 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222517197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.3222517197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2289104007 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 5460126266 ps |
| CPU time | 26.69 seconds |
| Started | Sep 11 12:33:31 PM UTC 24 |
| Finished | Sep 11 12:34:00 PM UTC 24 |
| Peak memory | 245316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289104007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2289104007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1558965616 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 720375079 ps |
| CPU time | 8.79 seconds |
| Started | Sep 11 12:34:04 PM UTC 24 |
| Finished | Sep 11 12:34:14 PM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558965616 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.1558965616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2546790664 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 14115845006 ps |
| CPU time | 34.18 seconds |
| Started | Sep 11 12:33:28 PM UTC 24 |
| Finished | Sep 11 12:34:04 PM UTC 24 |
| Peak memory | 227588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546790664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2546790664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.1058588660 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2465846634 ps |
| CPU time | 8.82 seconds |
| Started | Sep 11 12:33:27 PM UTC 24 |
| Finished | Sep 11 12:33:37 PM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058588660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1058588660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3292876731 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 38736784 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 12:33:30 PM UTC 24 |
| Finished | Sep 11 12:33:33 PM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292876731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3292876731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.402411363 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 301660322 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 12:33:28 PM UTC 24 |
| Finished | Sep 11 12:33:31 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402411363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.402411363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.628891910 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1172292033 ps |
| CPU time | 13.77 seconds |
| Started | Sep 11 12:33:51 PM UTC 24 |
| Finished | Sep 11 12:34:06 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628891910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.628891910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.146714436 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 38161474 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:35:04 PM UTC 24 |
| Finished | Sep 11 12:35:06 PM UTC 24 |
| Peak memory | 215796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146714436 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.146714436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1828126989 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 3079194991 ps |
| CPU time | 8.08 seconds |
| Started | Sep 11 12:34:43 PM UTC 24 |
| Finished | Sep 11 12:34:52 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828126989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1828126989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2153270636 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 53413627 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 12:34:15 PM UTC 24 |
| Finished | Sep 11 12:34:17 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153270636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2153270636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.4216355691 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 146949638935 ps |
| CPU time | 382.66 seconds |
| Started | Sep 11 12:34:53 PM UTC 24 |
| Finished | Sep 11 12:41:21 PM UTC 24 |
| Peak memory | 261832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216355691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.4216355691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3668498005 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3155106072 ps |
| CPU time | 79.5 seconds |
| Started | Sep 11 12:34:53 PM UTC 24 |
| Finished | Sep 11 12:36:14 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668498005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3668498005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1492563137 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1372264181 ps |
| CPU time | 30.67 seconds |
| Started | Sep 11 12:34:54 PM UTC 24 |
| Finished | Sep 11 12:35:26 PM UTC 24 |
| Peak memory | 229508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492563137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.1492563137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3828007775 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 117037881 ps |
| CPU time | 5.16 seconds |
| Started | Sep 11 12:34:43 PM UTC 24 |
| Finished | Sep 11 12:34:49 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828007775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3828007775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2882407365 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2116307574 ps |
| CPU time | 35.14 seconds |
| Started | Sep 11 12:34:44 PM UTC 24 |
| Finished | Sep 11 12:35:20 PM UTC 24 |
| Peak memory | 265692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882407365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.2882407365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3137342139 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1086319429 ps |
| CPU time | 15.43 seconds |
| Started | Sep 11 12:34:35 PM UTC 24 |
| Finished | Sep 11 12:34:52 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137342139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3137342139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.1883426944 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2382564770 ps |
| CPU time | 25.74 seconds |
| Started | Sep 11 12:34:37 PM UTC 24 |
| Finished | Sep 11 12:35:04 PM UTC 24 |
| Peak memory | 245404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883426944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1883426944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.2095718901 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 148573715 ps |
| CPU time | 2.4 seconds |
| Started | Sep 11 12:34:32 PM UTC 24 |
| Finished | Sep 11 12:34:36 PM UTC 24 |
| Peak memory | 233412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095718901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.2095718901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1105296061 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 17043501471 ps |
| CPU time | 15.26 seconds |
| Started | Sep 11 12:34:25 PM UTC 24 |
| Finished | Sep 11 12:34:42 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105296061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1105296061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.4231940680 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 734097642 ps |
| CPU time | 13.24 seconds |
| Started | Sep 11 12:34:50 PM UTC 24 |
| Finished | Sep 11 12:35:04 PM UTC 24 |
| Peak memory | 233576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231940680 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.4231940680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.398755358 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13486848397 ps |
| CPU time | 62.11 seconds |
| Started | Sep 11 12:34:55 PM UTC 24 |
| Finished | Sep 11 12:36:00 PM UTC 24 |
| Peak memory | 249468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398755358 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.398755358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.1905683976 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1333592171 ps |
| CPU time | 22.07 seconds |
| Started | Sep 11 12:34:18 PM UTC 24 |
| Finished | Sep 11 12:34:41 PM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905683976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1905683976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2029791977 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 6277678905 ps |
| CPU time | 12.26 seconds |
| Started | Sep 11 12:34:18 PM UTC 24 |
| Finished | Sep 11 12:34:31 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029791977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2029791977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.738809488 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 28412359 ps |
| CPU time | 1.57 seconds |
| Started | Sep 11 12:34:22 PM UTC 24 |
| Finished | Sep 11 12:34:25 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738809488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.738809488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3841419139 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 122844130 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 12:34:19 PM UTC 24 |
| Finished | Sep 11 12:34:21 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841419139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3841419139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.2271290205 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 24375973498 ps |
| CPU time | 38.81 seconds |
| Started | Sep 11 12:34:37 PM UTC 24 |
| Finished | Sep 11 12:35:17 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271290205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2271290205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.679960431 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 54287698 ps |
| CPU time | 0.88 seconds |
| Started | Sep 11 12:35:50 PM UTC 24 |
| Finished | Sep 11 12:35:52 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679960431 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.679960431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1188681856 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 350241422 ps |
| CPU time | 6.92 seconds |
| Started | Sep 11 12:35:29 PM UTC 24 |
| Finished | Sep 11 12:35:37 PM UTC 24 |
| Peak memory | 245128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188681856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1188681856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2205728756 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 54204345 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 12:35:05 PM UTC 24 |
| Finished | Sep 11 12:35:08 PM UTC 24 |
| Peak memory | 215624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205728756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2205728756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2976623515 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 854374006 ps |
| CPU time | 6.47 seconds |
| Started | Sep 11 12:35:39 PM UTC 24 |
| Finished | Sep 11 12:35:46 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976623515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2976623515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.4208941473 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 13291336453 ps |
| CPU time | 158.67 seconds |
| Started | Sep 11 12:35:43 PM UTC 24 |
| Finished | Sep 11 12:38:24 PM UTC 24 |
| Peak memory | 278172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208941473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4208941473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.1624962459 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4439491628 ps |
| CPU time | 37.38 seconds |
| Started | Sep 11 12:35:29 PM UTC 24 |
| Finished | Sep 11 12:36:08 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624962459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1624962459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.3489652179 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 74562834 ps |
| CPU time | 2.83 seconds |
| Started | Sep 11 12:35:21 PM UTC 24 |
| Finished | Sep 11 12:35:25 PM UTC 24 |
| Peak memory | 234264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489652179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3489652179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.558172095 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 47517966684 ps |
| CPU time | 47 seconds |
| Started | Sep 11 12:35:26 PM UTC 24 |
| Finished | Sep 11 12:36:15 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558172095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.558172095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3633272866 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 7211272622 ps |
| CPU time | 35.4 seconds |
| Started | Sep 11 12:35:18 PM UTC 24 |
| Finished | Sep 11 12:35:55 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633272866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3633272866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3875774111 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3273863172 ps |
| CPU time | 9.53 seconds |
| Started | Sep 11 12:35:18 PM UTC 24 |
| Finished | Sep 11 12:35:29 PM UTC 24 |
| Peak memory | 235012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875774111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3875774111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.273443110 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 124633882 ps |
| CPU time | 3.94 seconds |
| Started | Sep 11 12:35:37 PM UTC 24 |
| Finished | Sep 11 12:35:42 PM UTC 24 |
| Peak memory | 233488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273443110 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.273443110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2174531085 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 6277720906 ps |
| CPU time | 18.89 seconds |
| Started | Sep 11 12:35:09 PM UTC 24 |
| Finished | Sep 11 12:35:29 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174531085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2174531085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3514608123 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2637411366 ps |
| CPU time | 20.51 seconds |
| Started | Sep 11 12:35:08 PM UTC 24 |
| Finished | Sep 11 12:35:29 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514608123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3514608123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.3578589626 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 148266658 ps |
| CPU time | 1.83 seconds |
| Started | Sep 11 12:35:14 PM UTC 24 |
| Finished | Sep 11 12:35:17 PM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578589626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3578589626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1995539135 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 75967239 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 12:35:11 PM UTC 24 |
| Finished | Sep 11 12:35:13 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995539135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1995539135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.2254942945 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 13005132996 ps |
| CPU time | 7.25 seconds |
| Started | Sep 11 12:35:27 PM UTC 24 |
| Finished | Sep 11 12:35:36 PM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254942945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2254942945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.717808920 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 14221416 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 12:36:22 PM UTC 24 |
| Finished | Sep 11 12:36:24 PM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717808920 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.717808920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2455023021 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5038668976 ps |
| CPU time | 20.48 seconds |
| Started | Sep 11 12:36:12 PM UTC 24 |
| Finished | Sep 11 12:36:34 PM UTC 24 |
| Peak memory | 235140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455023021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2455023021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.2022455393 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 41109980 ps |
| CPU time | 1.06 seconds |
| Started | Sep 11 12:35:50 PM UTC 24 |
| Finished | Sep 11 12:35:52 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022455393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2022455393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1995025959 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 9938873257 ps |
| CPU time | 60.55 seconds |
| Started | Sep 11 12:36:15 PM UTC 24 |
| Finished | Sep 11 12:37:18 PM UTC 24 |
| Peak memory | 265820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995025959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1995025959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2668837229 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 135350572099 ps |
| CPU time | 370.95 seconds |
| Started | Sep 11 12:36:15 PM UTC 24 |
| Finished | Sep 11 12:42:31 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668837229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2668837229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3548683845 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 163799789842 ps |
| CPU time | 484.4 seconds |
| Started | Sep 11 12:36:21 PM UTC 24 |
| Finished | Sep 11 12:44:32 PM UTC 24 |
| Peak memory | 267908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548683845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.3548683845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.1078478753 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 366910847 ps |
| CPU time | 11.67 seconds |
| Started | Sep 11 12:36:13 PM UTC 24 |
| Finished | Sep 11 12:36:26 PM UTC 24 |
| Peak memory | 249304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078478753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1078478753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2743759198 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 239582331 ps |
| CPU time | 9.1 seconds |
| Started | Sep 11 12:36:02 PM UTC 24 |
| Finished | Sep 11 12:36:12 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743759198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2743759198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2795101104 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2403480373 ps |
| CPU time | 11.48 seconds |
| Started | Sep 11 12:36:08 PM UTC 24 |
| Finished | Sep 11 12:36:21 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795101104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2795101104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2036345805 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 21905359808 ps |
| CPU time | 10.72 seconds |
| Started | Sep 11 12:36:01 PM UTC 24 |
| Finished | Sep 11 12:36:12 PM UTC 24 |
| Peak memory | 235016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036345805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.2036345805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3305710030 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 5989380373 ps |
| CPU time | 5.75 seconds |
| Started | Sep 11 12:36:00 PM UTC 24 |
| Finished | Sep 11 12:36:07 PM UTC 24 |
| Peak memory | 245376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305710030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3305710030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.4086093531 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 17880166412 ps |
| CPU time | 26.97 seconds |
| Started | Sep 11 12:36:13 PM UTC 24 |
| Finished | Sep 11 12:36:42 PM UTC 24 |
| Peak memory | 233448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086093531 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.4086093531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.3070323836 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 322488249800 ps |
| CPU time | 816.12 seconds |
| Started | Sep 11 12:36:21 PM UTC 24 |
| Finished | Sep 11 12:50:07 PM UTC 24 |
| Peak memory | 296552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070323836 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.3070323836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.928165172 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 98209167 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 12:35:55 PM UTC 24 |
| Finished | Sep 11 12:35:58 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928165172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.928165172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2189140390 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 21351049831 ps |
| CPU time | 26.22 seconds |
| Started | Sep 11 12:35:53 PM UTC 24 |
| Finished | Sep 11 12:36:21 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189140390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2189140390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.1617512956 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 24579392 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 12:35:59 PM UTC 24 |
| Finished | Sep 11 12:36:01 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617512956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1617512956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.1366921864 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 60640805 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 12:35:56 PM UTC 24 |
| Finished | Sep 11 12:35:59 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366921864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1366921864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.3923051609 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1470882895 ps |
| CPU time | 10.09 seconds |
| Started | Sep 11 12:36:09 PM UTC 24 |
| Finished | Sep 11 12:36:20 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923051609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3923051609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.2441128487 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 16469517 ps |
| CPU time | 0.93 seconds |
| Started | Sep 11 12:36:55 PM UTC 24 |
| Finished | Sep 11 12:36:56 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441128487 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2441128487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1390933906 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 130522680 ps |
| CPU time | 3.48 seconds |
| Started | Sep 11 12:36:45 PM UTC 24 |
| Finished | Sep 11 12:36:49 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390933906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1390933906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.787232830 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 18061985 ps |
| CPU time | 1.08 seconds |
| Started | Sep 11 12:36:22 PM UTC 24 |
| Finished | Sep 11 12:36:24 PM UTC 24 |
| Peak memory | 215792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787232830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.787232830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.118131338 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 8096823841 ps |
| CPU time | 109.14 seconds |
| Started | Sep 11 12:36:50 PM UTC 24 |
| Finished | Sep 11 12:38:41 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118131338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.118131338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3373121199 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 74926539083 ps |
| CPU time | 167.71 seconds |
| Started | Sep 11 12:36:51 PM UTC 24 |
| Finished | Sep 11 12:39:42 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373121199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3373121199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3181526169 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 53276068422 ps |
| CPU time | 328.82 seconds |
| Started | Sep 11 12:36:52 PM UTC 24 |
| Finished | Sep 11 12:42:26 PM UTC 24 |
| Peak memory | 263812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181526169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.3181526169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.467468319 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 138907962 ps |
| CPU time | 3.29 seconds |
| Started | Sep 11 12:36:48 PM UTC 24 |
| Finished | Sep 11 12:36:52 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467468319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.467468319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.260018925 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 31209508957 ps |
| CPU time | 81.02 seconds |
| Started | Sep 11 12:36:49 PM UTC 24 |
| Finished | Sep 11 12:38:12 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260018925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.260018925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3578828141 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 8533573498 ps |
| CPU time | 12.54 seconds |
| Started | Sep 11 12:36:37 PM UTC 24 |
| Finished | Sep 11 12:36:50 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578828141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3578828141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.593540714 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 103725337 ps |
| CPU time | 2.91 seconds |
| Started | Sep 11 12:36:43 PM UTC 24 |
| Finished | Sep 11 12:36:47 PM UTC 24 |
| Peak memory | 234608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593540714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.593540714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3291424141 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 887599191 ps |
| CPU time | 8.08 seconds |
| Started | Sep 11 12:36:34 PM UTC 24 |
| Finished | Sep 11 12:36:44 PM UTC 24 |
| Peak memory | 249356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291424141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.3291424141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2991126201 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 307800978 ps |
| CPU time | 5.91 seconds |
| Started | Sep 11 12:36:34 PM UTC 24 |
| Finished | Sep 11 12:36:42 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991126201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2991126201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.321532662 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1629160451 ps |
| CPU time | 6.23 seconds |
| Started | Sep 11 12:36:49 PM UTC 24 |
| Finished | Sep 11 12:36:56 PM UTC 24 |
| Peak memory | 233364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321532662 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.321532662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.2045419404 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 181992542655 ps |
| CPU time | 262.89 seconds |
| Started | Sep 11 12:36:53 PM UTC 24 |
| Finished | Sep 11 12:41:20 PM UTC 24 |
| Peak memory | 278220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045419404 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.2045419404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.4054253557 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1263450123 ps |
| CPU time | 7.08 seconds |
| Started | Sep 11 12:36:27 PM UTC 24 |
| Finished | Sep 11 12:36:35 PM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054253557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4054253557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1866990560 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 55999675474 ps |
| CPU time | 24.76 seconds |
| Started | Sep 11 12:36:25 PM UTC 24 |
| Finished | Sep 11 12:36:51 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866990560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1866990560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.400664618 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 15579348 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 12:36:31 PM UTC 24 |
| Finished | Sep 11 12:36:34 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400664618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.400664618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1204770118 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 51787852 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 12:36:28 PM UTC 24 |
| Finished | Sep 11 12:36:31 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204770118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1204770118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3440063639 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 87937125 ps |
| CPU time | 4.31 seconds |
| Started | Sep 11 12:36:43 PM UTC 24 |
| Finished | Sep 11 12:36:48 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440063639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3440063639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |