| T822 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3585185815 |
|
|
Sep 18 02:44:38 PM UTC 24 |
Sep 18 02:44:56 PM UTC 24 |
2450877592 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2817432197 |
|
|
Sep 18 02:43:06 PM UTC 24 |
Sep 18 02:44:56 PM UTC 24 |
3955320091 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.1955518434 |
|
|
Sep 18 02:44:46 PM UTC 24 |
Sep 18 02:44:57 PM UTC 24 |
155697427 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.2987863313 |
|
|
Sep 18 02:44:06 PM UTC 24 |
Sep 18 02:44:58 PM UTC 24 |
2461243278 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2543571966 |
|
|
Sep 18 02:28:14 PM UTC 24 |
Sep 18 02:44:59 PM UTC 24 |
389505360545 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.1045124579 |
|
|
Sep 18 02:44:48 PM UTC 24 |
Sep 18 02:44:59 PM UTC 24 |
1134291775 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3924616754 |
|
|
Sep 18 02:44:53 PM UTC 24 |
Sep 18 02:44:59 PM UTC 24 |
570035363 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1916731087 |
|
|
Sep 18 02:44:46 PM UTC 24 |
Sep 18 02:44:59 PM UTC 24 |
1037884136 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1820405268 |
|
|
Sep 18 02:44:58 PM UTC 24 |
Sep 18 02:45:00 PM UTC 24 |
12289965 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2190606070 |
|
|
Sep 18 02:44:59 PM UTC 24 |
Sep 18 02:45:01 PM UTC 24 |
34186689 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1026623181 |
|
|
Sep 18 02:45:01 PM UTC 24 |
Sep 18 02:45:03 PM UTC 24 |
150907272 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.3277112363 |
|
|
Sep 18 02:45:01 PM UTC 24 |
Sep 18 02:45:04 PM UTC 24 |
167203678 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1077707418 |
|
|
Sep 18 02:44:43 PM UTC 24 |
Sep 18 02:45:04 PM UTC 24 |
8217332488 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1151611929 |
|
|
Sep 18 02:44:10 PM UTC 24 |
Sep 18 02:45:05 PM UTC 24 |
2076876690 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2281520198 |
|
|
Sep 18 02:45:01 PM UTC 24 |
Sep 18 02:45:06 PM UTC 24 |
373965832 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.529776410 |
|
|
Sep 18 02:43:26 PM UTC 24 |
Sep 18 02:45:08 PM UTC 24 |
24819905608 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.370447990 |
|
|
Sep 18 02:45:05 PM UTC 24 |
Sep 18 02:45:09 PM UTC 24 |
356274937 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.1538597759 |
|
|
Sep 18 02:44:44 PM UTC 24 |
Sep 18 02:45:11 PM UTC 24 |
4280550064 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.3946390040 |
|
|
Sep 18 02:45:06 PM UTC 24 |
Sep 18 02:45:11 PM UTC 24 |
58477323 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1938682683 |
|
|
Sep 18 02:45:06 PM UTC 24 |
Sep 18 02:45:12 PM UTC 24 |
514672936 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.768078075 |
|
|
Sep 18 02:37:41 PM UTC 24 |
Sep 18 02:45:13 PM UTC 24 |
100872750307 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.237917401 |
|
|
Sep 18 02:44:50 PM UTC 24 |
Sep 18 02:45:15 PM UTC 24 |
6677457311 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.906289885 |
|
|
Sep 18 02:45:08 PM UTC 24 |
Sep 18 02:45:15 PM UTC 24 |
164863979 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3615007176 |
|
|
Sep 18 02:45:02 PM UTC 24 |
Sep 18 02:45:15 PM UTC 24 |
12977406746 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1108039814 |
|
|
Sep 18 02:45:16 PM UTC 24 |
Sep 18 02:45:18 PM UTC 24 |
22975331 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1196335004 |
|
|
Sep 18 02:45:16 PM UTC 24 |
Sep 18 02:45:18 PM UTC 24 |
13609758 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1012763933 |
|
|
Sep 18 02:45:05 PM UTC 24 |
Sep 18 02:45:18 PM UTC 24 |
766770984 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3052740394 |
|
|
Sep 18 02:44:47 PM UTC 24 |
Sep 18 02:45:18 PM UTC 24 |
10597825846 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.92241092 |
|
|
Sep 18 02:45:18 PM UTC 24 |
Sep 18 02:45:21 PM UTC 24 |
74114572 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.1857941002 |
|
|
Sep 18 02:44:55 PM UTC 24 |
Sep 18 02:45:21 PM UTC 24 |
1401259521 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.433152173 |
|
|
Sep 18 02:44:47 PM UTC 24 |
Sep 18 02:45:21 PM UTC 24 |
3140361790 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2331566050 |
|
|
Sep 18 02:45:20 PM UTC 24 |
Sep 18 02:45:22 PM UTC 24 |
52005832 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2232513931 |
|
|
Sep 18 02:44:59 PM UTC 24 |
Sep 18 02:45:23 PM UTC 24 |
9649169183 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1678891658 |
|
|
Sep 18 02:45:17 PM UTC 24 |
Sep 18 02:45:24 PM UTC 24 |
1421729386 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.4164093106 |
|
|
Sep 18 02:45:10 PM UTC 24 |
Sep 18 02:45:25 PM UTC 24 |
1011034982 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.3288776245 |
|
|
Sep 18 02:45:18 PM UTC 24 |
Sep 18 02:45:26 PM UTC 24 |
718323718 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2068292156 |
|
|
Sep 18 02:45:24 PM UTC 24 |
Sep 18 02:45:31 PM UTC 24 |
830226862 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2407980236 |
|
|
Sep 18 02:45:25 PM UTC 24 |
Sep 18 02:45:32 PM UTC 24 |
444365249 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1419957844 |
|
|
Sep 18 02:45:27 PM UTC 24 |
Sep 18 02:45:35 PM UTC 24 |
278128395 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.4252161199 |
|
|
Sep 18 02:45:21 PM UTC 24 |
Sep 18 02:45:37 PM UTC 24 |
614810330 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.495130403 |
|
|
Sep 18 02:45:20 PM UTC 24 |
Sep 18 02:45:38 PM UTC 24 |
17139349083 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1993387594 |
|
|
Sep 18 02:45:21 PM UTC 24 |
Sep 18 02:45:39 PM UTC 24 |
7668878259 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.2807454572 |
|
|
Sep 18 02:45:39 PM UTC 24 |
Sep 18 02:45:42 PM UTC 24 |
132601662 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.3895349866 |
|
|
Sep 18 02:45:40 PM UTC 24 |
Sep 18 02:45:42 PM UTC 24 |
16332649 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1357829799 |
|
|
Sep 18 02:44:11 PM UTC 24 |
Sep 18 02:45:43 PM UTC 24 |
7042257817 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1503455386 |
|
|
Sep 18 02:46:41 PM UTC 24 |
Sep 18 02:46:47 PM UTC 24 |
535186559 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2349086454 |
|
|
Sep 18 02:44:55 PM UTC 24 |
Sep 18 02:45:45 PM UTC 24 |
3943383277 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.921367483 |
|
|
Sep 18 02:45:44 PM UTC 24 |
Sep 18 02:45:46 PM UTC 24 |
59610679 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.262344582 |
|
|
Sep 18 02:45:46 PM UTC 24 |
Sep 18 02:45:48 PM UTC 24 |
13955466 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2603774365 |
|
|
Sep 18 02:45:43 PM UTC 24 |
Sep 18 02:45:48 PM UTC 24 |
724684752 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.1521635596 |
|
|
Sep 18 02:45:23 PM UTC 24 |
Sep 18 02:45:53 PM UTC 24 |
45567685632 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.612323735 |
|
|
Sep 18 02:45:01 PM UTC 24 |
Sep 18 02:45:56 PM UTC 24 |
13116258930 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2722912990 |
|
|
Sep 18 02:45:12 PM UTC 24 |
Sep 18 02:45:56 PM UTC 24 |
11911797497 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2793781151 |
|
|
Sep 18 02:45:49 PM UTC 24 |
Sep 18 02:45:57 PM UTC 24 |
1824346295 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.961903720 |
|
|
Sep 18 02:33:33 PM UTC 24 |
Sep 18 02:45:59 PM UTC 24 |
288634320934 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.2540877292 |
|
|
Sep 18 02:45:49 PM UTC 24 |
Sep 18 02:45:59 PM UTC 24 |
2140808718 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.582037621 |
|
|
Sep 18 02:45:57 PM UTC 24 |
Sep 18 02:46:01 PM UTC 24 |
53531794 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3486836931 |
|
|
Sep 18 02:45:38 PM UTC 24 |
Sep 18 02:46:02 PM UTC 24 |
4426393754 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.2214391686 |
|
|
Sep 18 02:42:14 PM UTC 24 |
Sep 18 02:46:04 PM UTC 24 |
92465046482 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2142738575 |
|
|
Sep 18 02:46:00 PM UTC 24 |
Sep 18 02:46:06 PM UTC 24 |
134408592 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2508115040 |
|
|
Sep 18 02:45:54 PM UTC 24 |
Sep 18 02:46:08 PM UTC 24 |
686698165 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1615162744 |
|
|
Sep 18 02:41:26 PM UTC 24 |
Sep 18 02:46:10 PM UTC 24 |
107641642236 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3311632434 |
|
|
Sep 18 02:46:09 PM UTC 24 |
Sep 18 02:46:11 PM UTC 24 |
15031369 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1942917336 |
|
|
Sep 18 02:45:48 PM UTC 24 |
Sep 18 02:46:13 PM UTC 24 |
12777619201 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.618196325 |
|
|
Sep 18 02:45:57 PM UTC 24 |
Sep 18 02:46:13 PM UTC 24 |
31767033313 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.4197387486 |
|
|
Sep 18 02:46:11 PM UTC 24 |
Sep 18 02:46:13 PM UTC 24 |
14334165 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.1387009016 |
|
|
Sep 18 02:41:22 PM UTC 24 |
Sep 18 02:46:13 PM UTC 24 |
389502192554 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3827290916 |
|
|
Sep 18 02:46:14 PM UTC 24 |
Sep 18 02:46:16 PM UTC 24 |
17213667 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.2436854249 |
|
|
Sep 18 02:46:14 PM UTC 24 |
Sep 18 02:46:17 PM UTC 24 |
60476026 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.50314674 |
|
|
Sep 18 02:39:43 PM UTC 24 |
Sep 18 02:46:17 PM UTC 24 |
43238770748 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3465047578 |
|
|
Sep 18 02:45:09 PM UTC 24 |
Sep 18 02:46:18 PM UTC 24 |
3179367863 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3564220642 |
|
|
Sep 18 02:46:15 PM UTC 24 |
Sep 18 02:46:20 PM UTC 24 |
232570232 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.2958895217 |
|
|
Sep 18 02:46:18 PM UTC 24 |
Sep 18 02:46:22 PM UTC 24 |
263134590 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.2505758030 |
|
|
Sep 18 02:45:43 PM UTC 24 |
Sep 18 02:46:24 PM UTC 24 |
36373290236 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1105897342 |
|
|
Sep 18 02:43:27 PM UTC 24 |
Sep 18 02:46:24 PM UTC 24 |
194630100572 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1496083642 |
|
|
Sep 18 02:46:12 PM UTC 24 |
Sep 18 02:46:25 PM UTC 24 |
3220387532 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2691317588 |
|
|
Sep 18 02:46:18 PM UTC 24 |
Sep 18 02:46:25 PM UTC 24 |
267705646 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3153798708 |
|
|
Sep 18 02:46:00 PM UTC 24 |
Sep 18 02:46:27 PM UTC 24 |
3652067782 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.465313734 |
|
|
Sep 18 02:46:20 PM UTC 24 |
Sep 18 02:46:28 PM UTC 24 |
1164476650 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3695281536 |
|
|
Sep 18 02:46:16 PM UTC 24 |
Sep 18 02:46:28 PM UTC 24 |
2400071526 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.2913739773 |
|
|
Sep 18 02:45:58 PM UTC 24 |
Sep 18 02:46:54 PM UTC 24 |
2369638570 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1868971849 |
|
|
Sep 18 02:46:21 PM UTC 24 |
Sep 18 02:46:31 PM UTC 24 |
772252389 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.276832860 |
|
|
Sep 18 02:46:29 PM UTC 24 |
Sep 18 02:46:31 PM UTC 24 |
17170873 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.3333142088 |
|
|
Sep 18 02:46:32 PM UTC 24 |
Sep 18 02:46:34 PM UTC 24 |
15148062 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.577746059 |
|
|
Sep 18 02:46:26 PM UTC 24 |
Sep 18 02:46:35 PM UTC 24 |
273871253 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1752571917 |
|
|
Sep 18 02:46:02 PM UTC 24 |
Sep 18 02:46:35 PM UTC 24 |
1403880541 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3892969511 |
|
|
Sep 18 02:46:36 PM UTC 24 |
Sep 18 02:46:38 PM UTC 24 |
137194140 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1460518031 |
|
|
Sep 18 02:46:36 PM UTC 24 |
Sep 18 02:46:38 PM UTC 24 |
56101614 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.3280176070 |
|
|
Sep 18 02:40:19 PM UTC 24 |
Sep 18 02:46:39 PM UTC 24 |
148468399167 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2777575759 |
|
|
Sep 18 02:33:58 PM UTC 24 |
Sep 18 02:46:41 PM UTC 24 |
68902795704 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2932683517 |
|
|
Sep 18 02:43:46 PM UTC 24 |
Sep 18 02:46:43 PM UTC 24 |
9784269727 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3483809435 |
|
|
Sep 18 02:46:39 PM UTC 24 |
Sep 18 02:46:43 PM UTC 24 |
63095742 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.38011296 |
|
|
Sep 18 02:46:23 PM UTC 24 |
Sep 18 02:46:44 PM UTC 24 |
7904379532 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3721253407 |
|
|
Sep 18 02:46:39 PM UTC 24 |
Sep 18 02:46:45 PM UTC 24 |
313339593 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3518591770 |
|
|
Sep 18 02:46:14 PM UTC 24 |
Sep 18 02:46:45 PM UTC 24 |
5014474270 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.4281519178 |
|
|
Sep 18 02:45:31 PM UTC 24 |
Sep 18 02:46:51 PM UTC 24 |
15871688060 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.3564968376 |
|
|
Sep 18 02:44:12 PM UTC 24 |
Sep 18 02:46:54 PM UTC 24 |
72340180606 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.1773925834 |
|
|
Sep 18 02:46:02 PM UTC 24 |
Sep 18 02:46:55 PM UTC 24 |
5546920229 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.3171802330 |
|
|
Sep 18 02:45:23 PM UTC 24 |
Sep 18 02:46:55 PM UTC 24 |
33770421327 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1489210833 |
|
|
Sep 18 02:46:33 PM UTC 24 |
Sep 18 02:46:57 PM UTC 24 |
11643575199 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.990807825 |
|
|
Sep 18 02:46:42 PM UTC 24 |
Sep 18 02:46:58 PM UTC 24 |
13106417025 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2008123433 |
|
|
Sep 18 02:45:27 PM UTC 24 |
Sep 18 02:46:59 PM UTC 24 |
11733386343 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2116796687 |
|
|
Sep 18 02:46:57 PM UTC 24 |
Sep 18 02:46:59 PM UTC 24 |
104027436 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3121165843 |
|
|
Sep 18 02:46:57 PM UTC 24 |
Sep 18 02:46:59 PM UTC 24 |
34902517 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.2041425993 |
|
|
Sep 18 02:46:59 PM UTC 24 |
Sep 18 02:47:01 PM UTC 24 |
161349746 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.842367153 |
|
|
Sep 18 02:43:47 PM UTC 24 |
Sep 18 02:47:01 PM UTC 24 |
22579362178 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.957207338 |
|
|
Sep 18 02:46:34 PM UTC 24 |
Sep 18 02:47:01 PM UTC 24 |
4814577630 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2099645203 |
|
|
Sep 18 02:46:44 PM UTC 24 |
Sep 18 02:47:02 PM UTC 24 |
1541231383 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.4211340276 |
|
|
Sep 18 02:46:47 PM UTC 24 |
Sep 18 02:47:02 PM UTC 24 |
2185893715 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2680880898 |
|
|
Sep 18 02:46:57 PM UTC 24 |
Sep 18 02:47:02 PM UTC 24 |
308256677 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.46736932 |
|
|
Sep 18 02:47:00 PM UTC 24 |
Sep 18 02:47:05 PM UTC 24 |
2134677492 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2735831649 |
|
|
Sep 18 02:40:46 PM UTC 24 |
Sep 18 02:47:06 PM UTC 24 |
76123946089 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1801167377 |
|
|
Sep 18 02:47:04 PM UTC 24 |
Sep 18 02:47:06 PM UTC 24 |
48887841 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3958645138 |
|
|
Sep 18 02:47:03 PM UTC 24 |
Sep 18 02:47:06 PM UTC 24 |
198656051 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.2083386336 |
|
|
Sep 18 02:47:03 PM UTC 24 |
Sep 18 02:47:10 PM UTC 24 |
516499858 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.499452785 |
|
|
Sep 18 02:46:44 PM UTC 24 |
Sep 18 02:47:11 PM UTC 24 |
17835379455 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1162233385 |
|
|
Sep 18 02:47:01 PM UTC 24 |
Sep 18 02:47:12 PM UTC 24 |
737179254 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.760600428 |
|
|
Sep 18 02:47:04 PM UTC 24 |
Sep 18 02:47:13 PM UTC 24 |
2077105936 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.709513982 |
|
|
Sep 18 02:47:07 PM UTC 24 |
Sep 18 02:47:14 PM UTC 24 |
280943233 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.2842089218 |
|
|
Sep 18 02:47:03 PM UTC 24 |
Sep 18 02:47:14 PM UTC 24 |
459452290 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.2534369871 |
|
|
Sep 18 02:47:12 PM UTC 24 |
Sep 18 02:47:14 PM UTC 24 |
23571276 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.1317397844 |
|
|
Sep 18 02:47:14 PM UTC 24 |
Sep 18 02:47:16 PM UTC 24 |
24726824 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3069558279 |
|
|
Sep 18 02:47:08 PM UTC 24 |
Sep 18 02:47:17 PM UTC 24 |
301058067 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3730266857 |
|
|
Sep 18 02:47:16 PM UTC 24 |
Sep 18 02:47:18 PM UTC 24 |
54233726 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.113401524 |
|
|
Sep 18 02:47:16 PM UTC 24 |
Sep 18 02:47:20 PM UTC 24 |
449948621 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.3473842382 |
|
|
Sep 18 02:47:03 PM UTC 24 |
Sep 18 02:47:21 PM UTC 24 |
20679631544 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.770244702 |
|
|
Sep 18 02:46:53 PM UTC 24 |
Sep 18 02:47:22 PM UTC 24 |
13463453143 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3711902067 |
|
|
Sep 18 02:47:19 PM UTC 24 |
Sep 18 02:47:24 PM UTC 24 |
568118291 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1986206588 |
|
|
Sep 18 02:38:09 PM UTC 24 |
Sep 18 02:47:24 PM UTC 24 |
65253974127 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1590577732 |
|
|
Sep 18 02:47:19 PM UTC 24 |
Sep 18 02:47:27 PM UTC 24 |
205570272 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2543666218 |
|
|
Sep 18 02:44:56 PM UTC 24 |
Sep 18 02:47:28 PM UTC 24 |
13040766909 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.510284842 |
|
|
Sep 18 02:47:01 PM UTC 24 |
Sep 18 02:47:31 PM UTC 24 |
8785282368 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.916601751 |
|
|
Sep 18 02:47:22 PM UTC 24 |
Sep 18 02:47:31 PM UTC 24 |
318892379 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1034385363 |
|
|
Sep 18 02:47:25 PM UTC 24 |
Sep 18 02:47:32 PM UTC 24 |
96225254 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.2506460645 |
|
|
Sep 18 02:43:44 PM UTC 24 |
Sep 18 02:47:33 PM UTC 24 |
44372328685 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2642168263 |
|
|
Sep 18 02:47:17 PM UTC 24 |
Sep 18 02:47:34 PM UTC 24 |
1349112519 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.1822705876 |
|
|
Sep 18 02:47:32 PM UTC 24 |
Sep 18 02:47:34 PM UTC 24 |
67505519 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.2989859915 |
|
|
Sep 18 02:46:59 PM UTC 24 |
Sep 18 02:47:35 PM UTC 24 |
10050627215 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.2580748648 |
|
|
Sep 18 02:47:33 PM UTC 24 |
Sep 18 02:47:36 PM UTC 24 |
25189364 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.4217178042 |
|
|
Sep 18 02:44:51 PM UTC 24 |
Sep 18 02:47:36 PM UTC 24 |
14905912869 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.3982044608 |
|
|
Sep 18 02:47:16 PM UTC 24 |
Sep 18 02:47:36 PM UTC 24 |
7552335814 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.2696176050 |
|
|
Sep 18 02:47:34 PM UTC 24 |
Sep 18 02:47:37 PM UTC 24 |
35044804 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3296435384 |
|
|
Sep 18 02:47:21 PM UTC 24 |
Sep 18 02:47:38 PM UTC 24 |
2593189569 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1079243466 |
|
|
Sep 18 02:47:36 PM UTC 24 |
Sep 18 02:47:39 PM UTC 24 |
19655415 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3604437050 |
|
|
Sep 18 02:47:36 PM UTC 24 |
Sep 18 02:47:39 PM UTC 24 |
135454704 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2838325478 |
|
|
Sep 18 02:47:14 PM UTC 24 |
Sep 18 02:47:39 PM UTC 24 |
14286080161 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.144285180 |
|
|
Sep 18 02:47:38 PM UTC 24 |
Sep 18 02:47:41 PM UTC 24 |
33289261 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2609634172 |
|
|
Sep 18 02:42:10 PM UTC 24 |
Sep 18 02:47:43 PM UTC 24 |
33247646097 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.3084823756 |
|
|
Sep 18 02:47:38 PM UTC 24 |
Sep 18 02:47:44 PM UTC 24 |
122864974 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.877509285 |
|
|
Sep 18 02:47:38 PM UTC 24 |
Sep 18 02:47:45 PM UTC 24 |
329746687 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.397355343 |
|
|
Sep 18 02:45:13 PM UTC 24 |
Sep 18 02:47:48 PM UTC 24 |
37107105761 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1364465683 |
|
|
Sep 18 02:47:40 PM UTC 24 |
Sep 18 02:47:48 PM UTC 24 |
625117791 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1766699226 |
|
|
Sep 18 02:41:20 PM UTC 24 |
Sep 18 02:47:49 PM UTC 24 |
179861133525 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.1627617758 |
|
|
Sep 18 02:47:28 PM UTC 24 |
Sep 18 02:47:50 PM UTC 24 |
1017341547 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2102983319 |
|
|
Sep 18 02:47:43 PM UTC 24 |
Sep 18 02:47:51 PM UTC 24 |
571636472 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.1350812314 |
|
|
Sep 18 02:47:50 PM UTC 24 |
Sep 18 02:47:52 PM UTC 24 |
38334398 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.578521163 |
|
|
Sep 18 02:47:42 PM UTC 24 |
Sep 18 02:47:55 PM UTC 24 |
919456740 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.858071256 |
|
|
Sep 18 02:47:21 PM UTC 24 |
Sep 18 02:47:55 PM UTC 24 |
3999223044 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.3179943029 |
|
|
Sep 18 02:47:40 PM UTC 24 |
Sep 18 02:47:57 PM UTC 24 |
1034047619 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.3824548279 |
|
|
Sep 18 02:47:24 PM UTC 24 |
Sep 18 02:47:59 PM UTC 24 |
6404701796 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3249142160 |
|
|
Sep 18 02:47:40 PM UTC 24 |
Sep 18 02:47:59 PM UTC 24 |
1453756858 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.3280966925 |
|
|
Sep 18 02:47:36 PM UTC 24 |
Sep 18 02:48:02 PM UTC 24 |
1715200829 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2344520234 |
|
|
Sep 18 02:46:41 PM UTC 24 |
Sep 18 02:48:05 PM UTC 24 |
7247376105 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4130523514 |
|
|
Sep 18 02:43:06 PM UTC 24 |
Sep 18 02:48:09 PM UTC 24 |
22996030430 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3961358079 |
|
|
Sep 18 02:46:25 PM UTC 24 |
Sep 18 02:48:11 PM UTC 24 |
25543704098 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.728419708 |
|
|
Sep 18 02:47:09 PM UTC 24 |
Sep 18 02:48:13 PM UTC 24 |
8203519426 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.205576521 |
|
|
Sep 18 02:39:24 PM UTC 24 |
Sep 18 02:48:17 PM UTC 24 |
222179030266 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.837877530 |
|
|
Sep 18 02:43:06 PM UTC 24 |
Sep 18 02:48:18 PM UTC 24 |
29493200619 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.75472750 |
|
|
Sep 18 02:47:25 PM UTC 24 |
Sep 18 02:48:33 PM UTC 24 |
9473990826 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2923684638 |
|
|
Sep 18 02:47:38 PM UTC 24 |
Sep 18 02:48:35 PM UTC 24 |
12443229073 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.1032100530 |
|
|
Sep 18 02:47:09 PM UTC 24 |
Sep 18 02:48:37 PM UTC 24 |
13573540060 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.2167152290 |
|
|
Sep 18 02:47:48 PM UTC 24 |
Sep 18 02:48:41 PM UTC 24 |
35679180664 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.119538416 |
|
|
Sep 18 02:44:39 PM UTC 24 |
Sep 18 02:48:43 PM UTC 24 |
47016185684 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2145072715 |
|
|
Sep 18 02:45:12 PM UTC 24 |
Sep 18 02:48:48 PM UTC 24 |
88207474534 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3096507849 |
|
|
Sep 18 02:45:36 PM UTC 24 |
Sep 18 02:48:54 PM UTC 24 |
13870268535 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.549481000 |
|
|
Sep 18 02:47:42 PM UTC 24 |
Sep 18 02:49:12 PM UTC 24 |
145568793608 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2304764523 |
|
|
Sep 18 02:46:26 PM UTC 24 |
Sep 18 02:49:17 PM UTC 24 |
20030311836 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.4294232913 |
|
|
Sep 18 02:43:43 PM UTC 24 |
Sep 18 02:49:23 PM UTC 24 |
178441696655 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3074214501 |
|
|
Sep 18 02:45:14 PM UTC 24 |
Sep 18 02:49:43 PM UTC 24 |
120246051637 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3934220668 |
|
|
Sep 18 02:40:23 PM UTC 24 |
Sep 18 02:49:48 PM UTC 24 |
63892788747 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.727360447 |
|
|
Sep 18 02:47:45 PM UTC 24 |
Sep 18 02:50:24 PM UTC 24 |
43630719786 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1025943418 |
|
|
Sep 18 02:46:05 PM UTC 24 |
Sep 18 02:50:24 PM UTC 24 |
48169664589 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2093508562 |
|
|
Sep 18 02:46:47 PM UTC 24 |
Sep 18 02:50:30 PM UTC 24 |
171820401981 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1768183227 |
|
|
Sep 18 02:43:29 PM UTC 24 |
Sep 18 02:50:39 PM UTC 24 |
400617900083 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1148163744 |
|
|
Sep 18 02:44:58 PM UTC 24 |
Sep 18 02:51:06 PM UTC 24 |
137188274164 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.647254094 |
|
|
Sep 18 02:47:50 PM UTC 24 |
Sep 18 02:51:08 PM UTC 24 |
15601303585 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2070644155 |
|
|
Sep 18 02:47:46 PM UTC 24 |
Sep 18 02:51:08 PM UTC 24 |
18843789236 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2946441016 |
|
|
Sep 18 02:46:48 PM UTC 24 |
Sep 18 02:51:20 PM UTC 24 |
22107182500 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.3488008982 |
|
|
Sep 18 02:42:42 PM UTC 24 |
Sep 18 02:51:22 PM UTC 24 |
36499729889 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1520100667 |
|
|
Sep 18 02:46:45 PM UTC 24 |
Sep 18 02:51:30 PM UTC 24 |
139953882762 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.6207813 |
|
|
Sep 18 02:37:38 PM UTC 24 |
Sep 18 02:52:21 PM UTC 24 |
138617125432 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.765827390 |
|
|
Sep 18 02:46:28 PM UTC 24 |
Sep 18 02:52:25 PM UTC 24 |
122620488721 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2920888562 |
|
|
Sep 18 02:47:32 PM UTC 24 |
Sep 18 02:52:47 PM UTC 24 |
33530439847 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.892431428 |
|
|
Sep 18 02:46:26 PM UTC 24 |
Sep 18 02:52:51 PM UTC 24 |
47695528399 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2105093121 |
|
|
Sep 18 02:45:33 PM UTC 24 |
Sep 18 02:53:29 PM UTC 24 |
341836089301 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.922913777 |
|
|
Sep 18 02:47:29 PM UTC 24 |
Sep 18 02:53:34 PM UTC 24 |
40349362983 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.296134996 |
|
|
Sep 18 02:46:07 PM UTC 24 |
Sep 18 02:55:15 PM UTC 24 |
242493308341 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.3066611347 |
|
|
Sep 18 02:41:05 PM UTC 24 |
Sep 18 02:55:27 PM UTC 24 |
585028084595 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2496082115 |
|
|
Sep 18 02:46:29 PM UTC 24 |
Sep 18 02:55:33 PM UTC 24 |
52541028243 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3571217801 |
|
|
Sep 18 02:42:19 PM UTC 24 |
Sep 18 02:56:53 PM UTC 24 |
143517953256 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1747438511 |
|
|
Sep 18 02:46:55 PM UTC 24 |
Sep 18 02:57:35 PM UTC 24 |
92754969745 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1012039782 |
|
|
Sep 18 02:43:29 PM UTC 24 |
Sep 18 02:58:12 PM UTC 24 |
385125119999 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1434394750 |
|
|
Sep 18 02:47:11 PM UTC 24 |
Sep 18 02:59:35 PM UTC 24 |
62399584622 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.1360221140 |
|
|
Sep 18 02:44:41 PM UTC 24 |
Sep 18 03:00:59 PM UTC 24 |
96739934266 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2449461 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:28 PM UTC 24 |
14015664 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.426964976 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:28 PM UTC 24 |
17454810 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.983918046 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
19779290 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1971123572 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
11725043 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4205544772 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
168402784 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3539180705 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
55917586 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.116213657 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
77549675 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.184797479 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
84678740 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2738920940 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
18372910 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3977619812 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
235023532 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2881080743 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
202242612 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1711627086 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:29 PM UTC 24 |
56090462 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.4119189143 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:30 PM UTC 24 |
414139854 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1443243987 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:30 PM UTC 24 |
63330119 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.36306764 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:31 PM UTC 24 |
11743520 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2148808121 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:31 PM UTC 24 |
12440919 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3164040283 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:31 PM UTC 24 |
217683016 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3519072235 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:31 PM UTC 24 |
173369418 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1037074640 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:32 PM UTC 24 |
80050546 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1038249616 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:32 PM UTC 24 |
64452724 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2058091964 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:32 PM UTC 24 |
107630802 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1413412817 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:32 PM UTC 24 |
11306093 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.319367796 |
|
|
Sep 18 01:18:09 PM UTC 24 |
Sep 18 01:18:12 PM UTC 24 |
28971015 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3650371214 |
|
|
Sep 18 01:18:08 PM UTC 24 |
Sep 18 01:18:13 PM UTC 24 |
212523287 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2271533018 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:33 PM UTC 24 |
16378418 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.255732322 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:33 PM UTC 24 |
12279256 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2199487497 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:33 PM UTC 24 |
114938360 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.231609458 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:33 PM UTC 24 |
186426309 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3130081406 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:33 PM UTC 24 |
164606004 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1434581634 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:33 PM UTC 24 |
13026584 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3834676856 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:33 PM UTC 24 |
171974370 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.3856892004 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:33 PM UTC 24 |
40337169 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.523076793 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:34 PM UTC 24 |
265934823 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2984059051 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:34 PM UTC 24 |
441117342 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3955071276 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:34 PM UTC 24 |
47059364 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3294447205 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:34 PM UTC 24 |
60704890 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.506010181 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:34 PM UTC 24 |
1927315589 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1610975044 |
|
|
Sep 18 01:17:26 PM UTC 24 |
Sep 18 01:17:35 PM UTC 24 |
1432700767 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2057496278 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:35 PM UTC 24 |
565156155 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.4022461534 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:35 PM UTC 24 |
146698426 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.100101802 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:35 PM UTC 24 |
697613868 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1358845872 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:35 PM UTC 24 |
57678263 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.686685613 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:36 PM UTC 24 |
1751744955 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3208835263 |
|
|
Sep 18 01:17:31 PM UTC 24 |
Sep 18 01:17:38 PM UTC 24 |
549733769 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4287515038 |
|
|
Sep 18 01:17:27 PM UTC 24 |
Sep 18 01:17:40 PM UTC 24 |
662643946 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1191281986 |
|
|
Sep 18 01:17:29 PM UTC 24 |
Sep 18 01:17:42 PM UTC 24 |
232539229 ps |