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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 98.38 93.99 98.62 89.36 97.19 95.57 99.26


Total test records in report: 1129
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T122 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.134428478 Sep 18 01:17:29 PM UTC 24 Sep 18 01:17:47 PM UTC 24 1090008771 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1200825866 Sep 18 01:17:31 PM UTC 24 Sep 18 01:17:49 PM UTC 24 4024987436 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.940508228 Sep 18 01:17:26 PM UTC 24 Sep 18 01:17:49 PM UTC 24 1204669891 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.651765065 Sep 18 01:17:29 PM UTC 24 Sep 18 01:17:50 PM UTC 24 4981616384 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.71011116 Sep 18 01:17:31 PM UTC 24 Sep 18 01:17:53 PM UTC 24 4993971016 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3447381206 Sep 18 01:17:27 PM UTC 24 Sep 18 01:17:56 PM UTC 24 1091697176 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1400490906 Sep 18 01:17:31 PM UTC 24 Sep 18 01:18:04 PM UTC 24 1969922125 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3741092641 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:10 PM UTC 24 18366046 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1741507914 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:10 PM UTC 24 10879114 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.186806429 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:10 PM UTC 24 62745385 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1688685740 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:14 PM UTC 24 1653919586 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1905926126 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:11 PM UTC 24 20206717 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.2810723602 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:11 PM UTC 24 15482329 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1210148347 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:11 PM UTC 24 29988039 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1748750890 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:11 PM UTC 24 47707555 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.771621305 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:11 PM UTC 24 94533423 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2044084481 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:11 PM UTC 24 119309786 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.51952191 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:12 PM UTC 24 144425233 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3372201290 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:12 PM UTC 24 102764473 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3059233323 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:12 PM UTC 24 160174889 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.793727641 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:12 PM UTC 24 36061454 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2644972914 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:12 PM UTC 24 70297948 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.190807717 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:12 PM UTC 24 30598489 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3130076117 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:12 PM UTC 24 304091343 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2193178597 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:12 PM UTC 24 31550877 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3687851268 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:12 PM UTC 24 151260843 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.153372425 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:12 PM UTC 24 166159081 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1958218593 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:13 PM UTC 24 524050338 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2747610467 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:13 PM UTC 24 221799534 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4174463753 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:13 PM UTC 24 167074572 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.16212832 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:13 PM UTC 24 211527208 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2617403884 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:14 PM UTC 24 95190650 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3421106435 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:14 PM UTC 24 1347043171 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3345909209 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:14 PM UTC 24 70032256 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2002203375 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:14 PM UTC 24 373885706 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.815854940 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:15 PM UTC 24 170580318 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.480884419 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:16 PM UTC 24 410700272 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.1436950572 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:16 PM UTC 24 119248791 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.4143067657 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:16 PM UTC 24 3468097244 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.135231767 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:16 PM UTC 24 399438088 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2106528666 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:23 PM UTC 24 699424359 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3932358164 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:23 PM UTC 24 9743165438 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2883892680 Sep 18 01:18:09 PM UTC 24 Sep 18 01:18:27 PM UTC 24 993013152 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3214201517 Sep 18 01:18:08 PM UTC 24 Sep 18 01:18:35 PM UTC 24 528001697 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.439030868 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:11 PM UTC 24 173278976 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3915628768 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:11 PM UTC 24 18248328 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.877304259 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:11 PM UTC 24 11532968 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.4284843193 Sep 18 01:19:14 PM UTC 24 Sep 18 01:19:16 PM UTC 24 35943347 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3044420533 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:12 PM UTC 24 87731788 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2772468448 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:12 PM UTC 24 13347490 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3178529972 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:12 PM UTC 24 14510147 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.980666871 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:12 PM UTC 24 75554464 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1969099481 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:12 PM UTC 24 48501784 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4129144035 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:12 PM UTC 24 41394744 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2277504558 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:12 PM UTC 24 270693900 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1648494815 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:12 PM UTC 24 637826974 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2917054483 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:12 PM UTC 24 48025230 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2659267674 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:12 PM UTC 24 31467935 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1267191400 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:12 PM UTC 24 273207661 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1974197749 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:13 PM UTC 24 277785637 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3555369316 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:13 PM UTC 24 89839755 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.978487757 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:13 PM UTC 24 53614897 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3821947297 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:13 PM UTC 24 226517402 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.778906474 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:13 PM UTC 24 59576713 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3809203921 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:13 PM UTC 24 601294913 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1985425805 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:13 PM UTC 24 460912343 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2873391400 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:13 PM UTC 24 201189198 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2086246498 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:13 PM UTC 24 869533745 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3891641305 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:13 PM UTC 24 186111996 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3990160709 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:14 PM UTC 24 310292851 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3713284592 Sep 18 01:19:12 PM UTC 24 Sep 18 01:19:14 PM UTC 24 84042184 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1941476316 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:14 PM UTC 24 357998371 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2448583551 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:14 PM UTC 24 426269278 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3454419665 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:14 PM UTC 24 202871332 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2826657097 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:14 PM UTC 24 176215360 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.660345883 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:14 PM UTC 24 249959416 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1751813917 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:14 PM UTC 24 584177411 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.899104862 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:14 PM UTC 24 140948545 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3488639691 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:14 PM UTC 24 162109196 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3064755824 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:14 PM UTC 24 150984560 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3002249421 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:14 PM UTC 24 526708417 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3524154590 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:14 PM UTC 24 857377628 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.4250103306 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 25048782 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.356448110 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:15 PM UTC 24 107022247 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1666198505 Sep 18 01:19:14 PM UTC 24 Sep 18 01:19:16 PM UTC 24 16010067 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1067640859 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 13569097 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.801309556 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:15 PM UTC 24 220193876 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2819473992 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:16 PM UTC 24 18855765 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2226230672 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 11375217 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3330741431 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 12306952 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2491589161 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:16 PM UTC 24 14651115 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.160114317 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:15 PM UTC 24 175892112 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3450601427 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 19924611 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3474313077 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 15676338 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1894218643 Sep 18 01:19:14 PM UTC 24 Sep 18 01:19:16 PM UTC 24 14141628 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1879425324 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 30388479 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1868895410 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 18622742 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.119154640 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 13415387 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.4012790903 Sep 18 01:19:12 PM UTC 24 Sep 18 01:19:15 PM UTC 24 388223194 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.4154725199 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 13621044 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1592271368 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:15 PM UTC 24 172128323 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.4219379317 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:15 PM UTC 24 767312382 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1072317107 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:15 PM UTC 24 380862870 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.451870621 Sep 18 01:19:12 PM UTC 24 Sep 18 01:19:16 PM UTC 24 500605750 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2832461808 Sep 18 01:19:14 PM UTC 24 Sep 18 01:19:16 PM UTC 24 26906282 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2339633190 Sep 18 01:19:14 PM UTC 24 Sep 18 01:19:16 PM UTC 24 28752109 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3420387551 Sep 18 01:19:14 PM UTC 24 Sep 18 01:19:16 PM UTC 24 22506439 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2870445359 Sep 18 01:19:14 PM UTC 24 Sep 18 01:19:16 PM UTC 24 20601536 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.756461627 Sep 18 01:19:12 PM UTC 24 Sep 18 01:19:16 PM UTC 24 66121973 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3417997445 Sep 18 01:19:13 PM UTC 24 Sep 18 01:19:16 PM UTC 24 384173886 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.3552177578 Sep 18 01:19:14 PM UTC 24 Sep 18 01:19:16 PM UTC 24 23277676 ps
T1117 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2198523912 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:16 PM UTC 24 14805983 ps
T1118 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1195967026 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:16 PM UTC 24 15036008 ps
T1119 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1839797958 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:17 PM UTC 24 211900237 ps
T1120 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2720443643 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:17 PM UTC 24 10855303 ps
T1121 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2320170872 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:17 PM UTC 24 60233289 ps
T1122 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.838006697 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:17 PM UTC 24 85574961 ps
T1123 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2210883365 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:17 PM UTC 24 41623359 ps
T1124 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1768973054 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:17 PM UTC 24 43082986 ps
T1125 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.911813497 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:17 PM UTC 24 12746202 ps
T1126 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1514390148 Sep 18 01:19:15 PM UTC 24 Sep 18 01:19:17 PM UTC 24 52228884 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1446072332 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:17 PM UTC 24 110843549 ps
T1127 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3606438650 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:18 PM UTC 24 366992054 ps
T1128 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1303459493 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:19 PM UTC 24 1445289417 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3475655885 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:22 PM UTC 24 613353220 ps
T1129 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2439238230 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:24 PM UTC 24 2560554552 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4266880514 Sep 18 01:19:09 PM UTC 24 Sep 18 01:19:27 PM UTC 24 305952443 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.669081994 Sep 18 01:19:12 PM UTC 24 Sep 18 01:19:31 PM UTC 24 2033894822 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.385646893 Sep 18 01:19:10 PM UTC 24 Sep 18 01:19:32 PM UTC 24 2023127726 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.2081232392
Short name T10
Test name
Test status
Simulation time 4071535632 ps
CPU time 10.26 seconds
Started Sep 18 02:22:16 PM UTC 24
Finished Sep 18 02:22:28 PM UTC 24
Peak memory 245064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081232392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2081232392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.459516840
Short name T29
Test name
Test status
Simulation time 33811612016 ps
CPU time 83.6 seconds
Started Sep 18 02:22:44 PM UTC 24
Finished Sep 18 02:24:09 PM UTC 24
Peak memory 234936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459516840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.459516840
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1926036298
Short name T45
Test name
Test status
Simulation time 34993066342 ps
CPU time 132.12 seconds
Started Sep 18 02:22:28 PM UTC 24
Finished Sep 18 02:24:43 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926036298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.1926036298
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.324072821
Short name T39
Test name
Test status
Simulation time 42340451037 ps
CPU time 562.88 seconds
Started Sep 18 02:25:08 PM UTC 24
Finished Sep 18 02:34:38 PM UTC 24
Peak memory 294340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324072821 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.324072821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1661128059
Short name T50
Test name
Test status
Simulation time 38540576750 ps
CPU time 137.47 seconds
Started Sep 18 02:24:10 PM UTC 24
Finished Sep 18 02:26:30 PM UTC 24
Peak memory 261896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661128059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1661128059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.506010181
Short name T104
Test name
Test status
Simulation time 1927315589 ps
CPU time 7 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:34 PM UTC 24
Peak memory 225344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506010181 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.506010181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.3243187571
Short name T31
Test name
Test status
Simulation time 8866256826 ps
CPU time 71.45 seconds
Started Sep 18 02:23:12 PM UTC 24
Finished Sep 18 02:24:25 PM UTC 24
Peak memory 227576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243187571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3243187571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2074328860
Short name T34
Test name
Test status
Simulation time 197363115634 ps
CPU time 339.87 seconds
Started Sep 18 02:22:46 PM UTC 24
Finished Sep 18 02:28:31 PM UTC 24
Peak memory 261764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074328860 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.2074328860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.536495254
Short name T2
Test name
Test status
Simulation time 17810688 ps
CPU time 1.21 seconds
Started Sep 18 02:21:44 PM UTC 24
Finished Sep 18 02:21:46 PM UTC 24
Peak memory 226932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536495254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.536495254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1377033895
Short name T60
Test name
Test status
Simulation time 2865171908 ps
CPU time 59.81 seconds
Started Sep 18 02:26:55 PM UTC 24
Finished Sep 18 02:27:56 PM UTC 24
Peak memory 275836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377033895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.1377033895
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.4149928300
Short name T208
Test name
Test status
Simulation time 73760662925 ps
CPU time 247.06 seconds
Started Sep 18 02:30:02 PM UTC 24
Finished Sep 18 02:34:13 PM UTC 24
Peak memory 277956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149928300 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.4149928300
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.100101802
Short name T113
Test name
Test status
Simulation time 697613868 ps
CPU time 4.9 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:35 PM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100101802 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.100101802
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.4043018003
Short name T13
Test name
Test status
Simulation time 2388306878 ps
CPU time 29.71 seconds
Started Sep 18 02:22:26 PM UTC 24
Finished Sep 18 02:22:57 PM UTC 24
Peak memory 263548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043018003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4043018003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.886597568
Short name T49
Test name
Test status
Simulation time 21630332643 ps
CPU time 135.24 seconds
Started Sep 18 02:29:04 PM UTC 24
Finished Sep 18 02:31:22 PM UTC 24
Peak memory 267712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886597568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.886597568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2440792963
Short name T14
Test name
Test status
Simulation time 82115952 ps
CPU time 1.92 seconds
Started Sep 18 02:22:58 PM UTC 24
Finished Sep 18 02:23:01 PM UTC 24
Peak memory 256996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440792963 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2440792963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3656352974
Short name T48
Test name
Test status
Simulation time 5525022869 ps
CPU time 110.2 seconds
Started Sep 18 02:29:06 PM UTC 24
Finished Sep 18 02:30:59 PM UTC 24
Peak memory 261528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656352974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.3656352974
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2637251288
Short name T185
Test name
Test status
Simulation time 16529342460 ps
CPU time 190.04 seconds
Started Sep 18 02:25:38 PM UTC 24
Finished Sep 18 02:28:51 PM UTC 24
Peak memory 265860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637251288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2637251288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1616964912
Short name T293
Test name
Test status
Simulation time 129237423221 ps
CPU time 422.12 seconds
Started Sep 18 02:33:29 PM UTC 24
Finished Sep 18 02:40:37 PM UTC 24
Peak memory 277960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616964912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.1616964912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.1186986627
Short name T87
Test name
Test status
Simulation time 118551094575 ps
CPU time 601.12 seconds
Started Sep 18 02:27:10 PM UTC 24
Finished Sep 18 02:37:19 PM UTC 24
Peak memory 279996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186986627 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.1186986627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3519072235
Short name T90
Test name
Test status
Simulation time 173369418 ps
CPU time 1.48 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:31 PM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519072235 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.3519072235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1809813972
Short name T67
Test name
Test status
Simulation time 3410332616 ps
CPU time 82.17 seconds
Started Sep 18 02:29:59 PM UTC 24
Finished Sep 18 02:31:23 PM UTC 24
Peak memory 267772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809813972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1809813972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2375642781
Short name T317
Test name
Test status
Simulation time 36846069661 ps
CPU time 412.36 seconds
Started Sep 18 02:35:59 PM UTC 24
Finished Sep 18 02:42:57 PM UTC 24
Peak memory 265928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375642781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.2375642781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.2043323862
Short name T47
Test name
Test status
Simulation time 54083780200 ps
CPU time 351.77 seconds
Started Sep 18 02:22:44 PM UTC 24
Finished Sep 18 02:28:41 PM UTC 24
Peak memory 267904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043323862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2043323862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2932683517
Short name T149
Test name
Test status
Simulation time 9784269727 ps
CPU time 173.61 seconds
Started Sep 18 02:43:46 PM UTC 24
Finished Sep 18 02:46:43 PM UTC 24
Peak memory 280068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932683517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.2932683517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.63619531
Short name T218
Test name
Test status
Simulation time 15012589628 ps
CPU time 173.62 seconds
Started Sep 18 02:35:18 PM UTC 24
Finished Sep 18 02:38:14 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63619531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.63619531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2008094092
Short name T46
Test name
Test status
Simulation time 15582410207 ps
CPU time 26.33 seconds
Started Sep 18 02:25:01 PM UTC 24
Finished Sep 18 02:25:29 PM UTC 24
Peak memory 229628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008094092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2008094092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.438747885
Short name T99
Test name
Test status
Simulation time 94578432847 ps
CPU time 470.17 seconds
Started Sep 18 02:24:52 PM UTC 24
Finished Sep 18 02:32:48 PM UTC 24
Peak memory 265592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438747885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.438747885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2812052681
Short name T215
Test name
Test status
Simulation time 23602121922 ps
CPU time 222.84 seconds
Started Sep 18 02:36:43 PM UTC 24
Finished Sep 18 02:40:30 PM UTC 24
Peak memory 267640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812052681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.2812052681
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.3021219069
Short name T171
Test name
Test status
Simulation time 117212175909 ps
CPU time 590.75 seconds
Started Sep 18 02:33:11 PM UTC 24
Finished Sep 18 02:43:08 PM UTC 24
Peak memory 267716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021219069 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.3021219069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.4034500093
Short name T25
Test name
Test status
Simulation time 19897847 ps
CPU time 1.12 seconds
Started Sep 18 02:23:02 PM UTC 24
Finished Sep 18 02:23:04 PM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034500093 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4034500093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.34118792
Short name T256
Test name
Test status
Simulation time 22960314677 ps
CPU time 261.4 seconds
Started Sep 18 02:31:24 PM UTC 24
Finished Sep 18 02:35:50 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34118792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.34118792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2841250817
Short name T43
Test name
Test status
Simulation time 7181647878 ps
CPU time 14.48 seconds
Started Sep 18 02:25:53 PM UTC 24
Finished Sep 18 02:26:08 PM UTC 24
Peak memory 227768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841250817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2841250817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2106528666
Short name T195
Test name
Test status
Simulation time 699424359 ps
CPU time 12.37 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:23 PM UTC 24
Peak memory 225412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106528666 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2106528666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1765369974
Short name T176
Test name
Test status
Simulation time 7839410988 ps
CPU time 112.68 seconds
Started Sep 18 02:30:59 PM UTC 24
Finished Sep 18 02:32:54 PM UTC 24
Peak memory 267720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765369974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.1765369974
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3834676856
Short name T103
Test name
Test status
Simulation time 171974370 ps
CPU time 3.38 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:33 PM UTC 24
Peak memory 225448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834676856 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3834676856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1843532158
Short name T181
Test name
Test status
Simulation time 13401175947 ps
CPU time 119.05 seconds
Started Sep 18 02:30:59 PM UTC 24
Finished Sep 18 02:33:01 PM UTC 24
Peak memory 267720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843532158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1843532158
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.2177175970
Short name T704
Test name
Test status
Simulation time 46899374638 ps
CPU time 90.61 seconds
Started Sep 18 02:40:41 PM UTC 24
Finished Sep 18 02:42:14 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177175970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2177175970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.947379715
Short name T111
Test name
Test status
Simulation time 8595348811 ps
CPU time 108.55 seconds
Started Sep 18 02:23:34 PM UTC 24
Finished Sep 18 02:25:26 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947379715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.947379715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1303459493
Short name T1128
Test name
Test status
Simulation time 1445289417 ps
CPU time 7.39 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:19 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303459493 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.1303459493
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.961903720
Short name T40
Test name
Test status
Simulation time 288634320934 ps
CPU time 736.68 seconds
Started Sep 18 02:33:33 PM UTC 24
Finished Sep 18 02:45:59 PM UTC 24
Peak memory 294616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961903720 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.961903720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.3266762298
Short name T440
Test name
Test status
Simulation time 566142263 ps
CPU time 5.84 seconds
Started Sep 18 02:33:51 PM UTC 24
Finished Sep 18 02:33:58 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266762298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3266762298
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.1667400085
Short name T214
Test name
Test status
Simulation time 10745738132 ps
CPU time 170.17 seconds
Started Sep 18 02:34:59 PM UTC 24
Finished Sep 18 02:37:52 PM UTC 24
Peak memory 284160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667400085 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.1667400085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.2631340174
Short name T312
Test name
Test status
Simulation time 61128810743 ps
CPU time 259.32 seconds
Started Sep 18 02:37:41 PM UTC 24
Finished Sep 18 02:42:04 PM UTC 24
Peak memory 267736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631340174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.2631340174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2915149294
Short name T223
Test name
Test status
Simulation time 10005245254 ps
CPU time 25.1 seconds
Started Sep 18 02:25:26 PM UTC 24
Finished Sep 18 02:25:53 PM UTC 24
Peak memory 234772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915149294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2915149294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3345909209
Short name T119
Test name
Test status
Simulation time 70032256 ps
CPU time 3.82 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:14 PM UTC 24
Peak memory 225680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345909209 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.3345909209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3996354441
Short name T7
Test name
Test status
Simulation time 2326997995 ps
CPU time 12.49 seconds
Started Sep 18 02:21:44 PM UTC 24
Finished Sep 18 02:21:58 PM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996354441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3996354441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.669081994
Short name T201
Test name
Test status
Simulation time 2033894822 ps
CPU time 18.5 seconds
Started Sep 18 01:19:12 PM UTC 24
Finished Sep 18 01:19:31 PM UTC 24
Peak memory 227416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669081994 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.669081994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2682868643
Short name T258
Test name
Test status
Simulation time 62143330440 ps
CPU time 436.43 seconds
Started Sep 18 02:32:42 PM UTC 24
Finished Sep 18 02:40:04 PM UTC 24
Peak memory 263812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682868643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.2682868643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.2540844551
Short name T304
Test name
Test status
Simulation time 258586830936 ps
CPU time 638.41 seconds
Started Sep 18 02:33:59 PM UTC 24
Finished Sep 18 02:44:45 PM UTC 24
Peak memory 280256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540844551 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.2540844551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.810910564
Short name T328
Test name
Test status
Simulation time 55693911078 ps
CPU time 431.65 seconds
Started Sep 18 02:35:25 PM UTC 24
Finished Sep 18 02:42:42 PM UTC 24
Peak memory 261644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810910564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.810910564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.301183860
Short name T334
Test name
Test status
Simulation time 5009066484 ps
CPU time 27.44 seconds
Started Sep 18 02:35:17 PM UTC 24
Finished Sep 18 02:35:45 PM UTC 24
Peak memory 245128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301183860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.301183860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2954054542
Short name T219
Test name
Test status
Simulation time 150776189125 ps
CPU time 284.2 seconds
Started Sep 18 02:35:59 PM UTC 24
Finished Sep 18 02:40:47 PM UTC 24
Peak memory 265544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954054542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2954054542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.2389488078
Short name T1
Test name
Test status
Simulation time 14551056 ps
CPU time 1.2 seconds
Started Sep 18 02:21:38 PM UTC 24
Finished Sep 18 02:21:40 PM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389488078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2389488078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1610975044
Short name T132
Test name
Test status
Simulation time 1432700767 ps
CPU time 6.95 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:35 PM UTC 24
Peak memory 225220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610975044 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.1610975044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.940508228
Short name T134
Test name
Test status
Simulation time 1204669891 ps
CPU time 21.34 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:49 PM UTC 24
Peak memory 225232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940508228 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.940508228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4205544772
Short name T88
Test name
Test status
Simulation time 168402784 ps
CPU time 1.41 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 224336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205544772 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.4205544772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.116213657
Short name T82
Test name
Test status
Simulation time 77549675 ps
CPU time 1.52 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 226564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=116213657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.spi_device_csr_mem_rw_with_rand_reset.116213657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2881080743
Short name T125
Test name
Test status
Simulation time 202242612 ps
CPU time 1.79 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 224328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881080743 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2881080743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2449461
Short name T1011
Test name
Test status
Simulation time 14015664 ps
CPU time 0.71 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:28 PM UTC 24
Peak memory 213184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449461 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2449461
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1711627086
Short name T126
Test name
Test status
Simulation time 56090462 ps
CPU time 2.02 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 225440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711627086 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1711627086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.426964976
Short name T1012
Test name
Test status
Simulation time 17454810 ps
CPU time 0.69 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:28 PM UTC 24
Peak memory 212020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426964976 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.426964976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1443243987
Short name T151
Test name
Test status
Simulation time 63330119 ps
CPU time 2.62 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:30 PM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443243987 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstand
ing.1443243987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.184797479
Short name T83
Test name
Test status
Simulation time 84678740 ps
CPU time 1.67 seconds
Started Sep 18 01:17:26 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 224540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184797479 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.184797479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.686685613
Short name T161
Test name
Test status
Simulation time 1751744955 ps
CPU time 7.81 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:36 PM UTC 24
Peak memory 225304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686685613 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.686685613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3447381206
Short name T1025
Test name
Test status
Simulation time 1091697176 ps
CPU time 27.76 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:56 PM UTC 24
Peak memory 215136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447381206 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.3447381206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3539180705
Short name T89
Test name
Test status
Simulation time 55917586 ps
CPU time 1.11 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539180705 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.3539180705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1037074640
Short name T120
Test name
Test status
Simulation time 80050546 ps
CPU time 1.8 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:32 PM UTC 24
Peak memory 226320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1037074640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.spi_device_csr_mem_rw_with_rand_reset.1037074640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.4119189143
Short name T127
Test name
Test status
Simulation time 414139854 ps
CPU time 2.32 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:30 PM UTC 24
Peak memory 225428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119189143 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4119189143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.983918046
Short name T1013
Test name
Test status
Simulation time 19779290 ps
CPU time 0.8 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983918046 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.983918046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2738920940
Short name T124
Test name
Test status
Simulation time 18372910 ps
CPU time 1.46 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 224396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738920940 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.2738920940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1971123572
Short name T1014
Test name
Test status
Simulation time 11725043 ps
CPU time 0.88 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 212052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971123572 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.1971123572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3164040283
Short name T152
Test name
Test status
Simulation time 217683016 ps
CPU time 3.24 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:31 PM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164040283 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand
ing.3164040283
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3977619812
Short name T84
Test name
Test status
Simulation time 235023532 ps
CPU time 1.52 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:29 PM UTC 24
Peak memory 226592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977619812 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3977619812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4287515038
Short name T108
Test name
Test status
Simulation time 662643946 ps
CPU time 12.32 seconds
Started Sep 18 01:17:27 PM UTC 24
Finished Sep 18 01:17:40 PM UTC 24
Peak memory 225408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287515038 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.4287515038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3990160709
Short name T1075
Test name
Test status
Simulation time 310292851 ps
CPU time 3.45 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 229584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3990160709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.spi_device_csr_mem_rw_with_rand_reset.3990160709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.319367796
Short name T1018
Test name
Test status
Simulation time 28971015 ps
CPU time 1.62 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 224352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319367796 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.319367796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1210148347
Short name T1032
Test name
Test status
Simulation time 29988039 ps
CPU time 0.83 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:11 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210148347 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.1210148347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2644972914
Short name T1037
Test name
Test status
Simulation time 70297948 ps
CPU time 1.7 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 224580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644972914 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstan
ding.2644972914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.135231767
Short name T193
Test name
Test status
Simulation time 399438088 ps
CPU time 6.23 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:16 PM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135231767 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.135231767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1974197749
Short name T1065
Test name
Test status
Simulation time 277785637 ps
CPU time 2.48 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 226996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1974197749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.spi_device_csr_mem_rw_with_rand_reset.1974197749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2277504558
Short name T1060
Test name
Test status
Simulation time 270693900 ps
CPU time 2.04 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 225228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277504558 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.2277504558
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.439030868
Short name T1050
Test name
Test status
Simulation time 173278976 ps
CPU time 0.65 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:11 PM UTC 24
Peak memory 212080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439030868 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.439030868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3524154590
Short name T1087
Test name
Test status
Simulation time 857377628 ps
CPU time 4.04 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524154590 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstan
ding.3524154590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.356448110
Short name T1089
Test name
Test status
Simulation time 107022247 ps
CPU time 4.51 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 227808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356448110 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.356448110
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3606438650
Short name T1127
Test name
Test status
Simulation time 366992054 ps
CPU time 7.52 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:18 PM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606438650 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.3606438650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.899104862
Short name T1083
Test name
Test status
Simulation time 140948545 ps
CPU time 3.47 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 227588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=899104862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 12.spi_device_csr_mem_rw_with_rand_reset.899104862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1267191400
Short name T1064
Test name
Test status
Simulation time 273207661 ps
CPU time 1.95 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 224352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267191400 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.1267191400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3915628768
Short name T1051
Test name
Test status
Simulation time 18248328 ps
CPU time 0.65 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:11 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915628768 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3915628768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1985425805
Short name T1071
Test name
Test status
Simulation time 460912343 ps
CPU time 2.7 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 225540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985425805 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan
ding.1985425805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.160114317
Short name T1097
Test name
Test status
Simulation time 175892112 ps
CPU time 4.55 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 227716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160114317 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.160114317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4266880514
Short name T198
Test name
Test status
Simulation time 305952443 ps
CPU time 16.82 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:27 PM UTC 24
Peak memory 225368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266880514 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.4266880514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2917054483
Short name T1062
Test name
Test status
Simulation time 48025230 ps
CPU time 1.72 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2917054483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.spi_device_csr_mem_rw_with_rand_reset.2917054483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.980666871
Short name T1057
Test name
Test status
Simulation time 75554464 ps
CPU time 1.23 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 224352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980666871 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.980666871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.877304259
Short name T1052
Test name
Test status
Simulation time 11532968 ps
CPU time 0.9 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:11 PM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877304259 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.877304259
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.660345883
Short name T1081
Test name
Test status
Simulation time 249959416 ps
CPU time 3.32 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 225528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660345883 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstand
ing.660345883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.801309556
Short name T1092
Test name
Test status
Simulation time 220193876 ps
CPU time 4.2 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 224840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801309556 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.801309556
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3475655885
Short name T200
Test name
Test status
Simulation time 613353220 ps
CPU time 11.39 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:22 PM UTC 24
Peak memory 223776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475655885 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.3475655885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2448583551
Short name T1078
Test name
Test status
Simulation time 426269278 ps
CPU time 2.76 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 227536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2448583551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.spi_device_csr_mem_rw_with_rand_reset.2448583551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1648494815
Short name T1061
Test name
Test status
Simulation time 637826974 ps
CPU time 1.35 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648494815 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.1648494815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3044420533
Short name T1054
Test name
Test status
Simulation time 87731788 ps
CPU time 0.84 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044420533 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.3044420533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3064755824
Short name T1085
Test name
Test status
Simulation time 150984560 ps
CPU time 3.4 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064755824 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstan
ding.3064755824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3488639691
Short name T1084
Test name
Test status
Simulation time 162109196 ps
CPU time 3.45 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488639691 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.3488639691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1839797958
Short name T1119
Test name
Test status
Simulation time 211900237 ps
CPU time 5.78 seconds
Started Sep 18 01:19:09 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 227616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839797958 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.1839797958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2873391400
Short name T1072
Test name
Test status
Simulation time 201189198 ps
CPU time 2.15 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2873391400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.spi_device_csr_mem_rw_with_rand_reset.2873391400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4129144035
Short name T1059
Test name
Test status
Simulation time 41394744 ps
CPU time 1.16 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 224352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129144035 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.4129144035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2772468448
Short name T1055
Test name
Test status
Simulation time 13347490 ps
CPU time 0.71 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772468448 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2772468448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.778906474
Short name T1069
Test name
Test status
Simulation time 59576713 ps
CPU time 1.85 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 224664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778906474 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstand
ing.778906474
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.4219379317
Short name T1107
Test name
Test status
Simulation time 767312382 ps
CPU time 4.58 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 225608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219379317 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.4219379317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1446072332
Short name T192
Test name
Test status
Simulation time 110843549 ps
CPU time 6 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 227540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446072332 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.1446072332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.978487757
Short name T1067
Test name
Test status
Simulation time 53614897 ps
CPU time 1.66 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 224516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=978487757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 16.spi_device_csr_mem_rw_with_rand_reset.978487757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2086246498
Short name T1073
Test name
Test status
Simulation time 869533745 ps
CPU time 2.13 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 214980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086246498 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.2086246498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3178529972
Short name T1056
Test name
Test status
Simulation time 14510147 ps
CPU time 0.76 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178529972 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.3178529972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3821947297
Short name T1068
Test name
Test status
Simulation time 226517402 ps
CPU time 1.74 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 224644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821947297 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstan
ding.3821947297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3809203921
Short name T1070
Test name
Test status
Simulation time 601294913 ps
CPU time 2.06 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809203921 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.3809203921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2439238230
Short name T1129
Test name
Test status
Simulation time 2560554552 ps
CPU time 12.47 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:24 PM UTC 24
Peak memory 233624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439238230 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.2439238230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1941476316
Short name T1077
Test name
Test status
Simulation time 357998371 ps
CPU time 2.2 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1941476316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.spi_device_csr_mem_rw_with_rand_reset.1941476316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3555369316
Short name T1066
Test name
Test status
Simulation time 89839755 ps
CPU time 1.47 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 224352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555369316 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.3555369316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2659267674
Short name T1063
Test name
Test status
Simulation time 31467935 ps
CPU time 0.97 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659267674 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.2659267674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1072317107
Short name T1108
Test name
Test status
Simulation time 380862870 ps
CPU time 4.06 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 225380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072317107 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan
ding.1072317107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1751813917
Short name T1082
Test name
Test status
Simulation time 584177411 ps
CPU time 2.71 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 227664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751813917 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.1751813917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2826657097
Short name T1080
Test name
Test status
Simulation time 176215360 ps
CPU time 2.48 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 227584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2826657097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.spi_device_csr_mem_rw_with_rand_reset.2826657097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3891641305
Short name T1074
Test name
Test status
Simulation time 186111996 ps
CPU time 1.94 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:13 PM UTC 24
Peak memory 224308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891641305 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.3891641305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1969099481
Short name T1058
Test name
Test status
Simulation time 48501784 ps
CPU time 0.64 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:12 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969099481 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.1969099481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3002249421
Short name T1086
Test name
Test status
Simulation time 526708417 ps
CPU time 2.71 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002249421 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan
ding.3002249421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3454419665
Short name T1079
Test name
Test status
Simulation time 202871332 ps
CPU time 2.41 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454419665 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3454419665
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.385646893
Short name T196
Test name
Test status
Simulation time 2023127726 ps
CPU time 20.39 seconds
Started Sep 18 01:19:10 PM UTC 24
Finished Sep 18 01:19:32 PM UTC 24
Peak memory 227540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385646893 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.385646893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3417997445
Short name T1115
Test name
Test status
Simulation time 384173886 ps
CPU time 2.42 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 227612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3417997445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.spi_device_csr_mem_rw_with_rand_reset.3417997445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.451870621
Short name T1109
Test name
Test status
Simulation time 500605750 ps
CPU time 2.92 seconds
Started Sep 18 01:19:12 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 225304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451870621 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.451870621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3713284592
Short name T1076
Test name
Test status
Simulation time 84042184 ps
CPU time 0.85 seconds
Started Sep 18 01:19:12 PM UTC 24
Finished Sep 18 01:19:14 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713284592 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.3713284592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.756461627
Short name T1114
Test name
Test status
Simulation time 66121973 ps
CPU time 3.46 seconds
Started Sep 18 01:19:12 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 225436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756461627 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstand
ing.756461627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.4012790903
Short name T1104
Test name
Test status
Simulation time 388223194 ps
CPU time 2.47 seconds
Started Sep 18 01:19:12 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012790903 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.4012790903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1191281986
Short name T133
Test name
Test status
Simulation time 232539229 ps
CPU time 11.38 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:42 PM UTC 24
Peak memory 225352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191281986 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.1191281986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.651765065
Short name T1024
Test name
Test status
Simulation time 4981616384 ps
CPU time 19.71 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:50 PM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651765065 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.651765065
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3130081406
Short name T105
Test name
Test status
Simulation time 164606004 ps
CPU time 2.62 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:33 PM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3130081406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.spi_device_csr_mem_rw_with_rand_reset.3130081406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2058091964
Short name T129
Test name
Test status
Simulation time 107630802 ps
CPU time 1.91 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:32 PM UTC 24
Peak memory 224328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058091964 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2058091964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2148808121
Short name T1016
Test name
Test status
Simulation time 12440919 ps
CPU time 1.14 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:31 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148808121 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2148808121
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1038249616
Short name T128
Test name
Test status
Simulation time 64452724 ps
CPU time 1.65 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:32 PM UTC 24
Peak memory 224396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038249616 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.1038249616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.36306764
Short name T1015
Test name
Test status
Simulation time 11743520 ps
CPU time 0.73 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:31 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36306764 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.36306764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3294447205
Short name T1023
Test name
Test status
Simulation time 60704890 ps
CPU time 3.94 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:34 PM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294447205 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand
ing.3294447205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.134428478
Short name T122
Test name
Test status
Simulation time 1090008771 ps
CPU time 17.05 seconds
Started Sep 18 01:17:29 PM UTC 24
Finished Sep 18 01:17:47 PM UTC 24
Peak memory 225476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134428478 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.134428478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.4250103306
Short name T1088
Test name
Test status
Simulation time 25048782 ps
CPU time 0.74 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250103306 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.4250103306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1067640859
Short name T1091
Test name
Test status
Simulation time 13569097 ps
CPU time 0.78 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067640859 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.1067640859
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3474313077
Short name T1099
Test name
Test status
Simulation time 15676338 ps
CPU time 0.88 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474313077 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.3474313077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1879425324
Short name T1101
Test name
Test status
Simulation time 30388479 ps
CPU time 0.95 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879425324 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1879425324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2226230672
Short name T1094
Test name
Test status
Simulation time 11375217 ps
CPU time 0.8 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226230672 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.2226230672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3330741431
Short name T1095
Test name
Test status
Simulation time 12306952 ps
CPU time 0.74 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330741431 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3330741431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1868895410
Short name T1102
Test name
Test status
Simulation time 18622742 ps
CPU time 0.82 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868895410 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.1868895410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.119154640
Short name T1103
Test name
Test status
Simulation time 13415387 ps
CPU time 0.8 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119154640 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.119154640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3450601427
Short name T1098
Test name
Test status
Simulation time 19924611 ps
CPU time 0.71 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450601427 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.3450601427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.4154725199
Short name T1105
Test name
Test status
Simulation time 13621044 ps
CPU time 0.78 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154725199 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.4154725199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.71011116
Short name T163
Test name
Test status
Simulation time 4993971016 ps
CPU time 20.98 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:53 PM UTC 24
Peak memory 227484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71011116 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.71011116
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1400490906
Short name T1026
Test name
Test status
Simulation time 1969922125 ps
CPU time 32.17 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:18:04 PM UTC 24
Peak memory 215068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400490906 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.1400490906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.231609458
Short name T1021
Test name
Test status
Simulation time 186426309 ps
CPU time 1.15 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:33 PM UTC 24
Peak memory 213708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231609458 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.231609458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1358845872
Short name T121
Test name
Test status
Simulation time 57678263 ps
CPU time 3.38 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:35 PM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1358845872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.spi_device_csr_mem_rw_with_rand_reset.1358845872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.523076793
Short name T131
Test name
Test status
Simulation time 265934823 ps
CPU time 1.95 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:34 PM UTC 24
Peak memory 224328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523076793 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.523076793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2271533018
Short name T1019
Test name
Test status
Simulation time 16378418 ps
CPU time 1.05 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:33 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271533018 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2271533018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2199487497
Short name T130
Test name
Test status
Simulation time 114938360 ps
CPU time 1.25 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:33 PM UTC 24
Peak memory 224396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199487497 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.2199487497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1413412817
Short name T1017
Test name
Test status
Simulation time 11306093 ps
CPU time 0.88 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:32 PM UTC 24
Peak memory 211772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413412817 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.1413412817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2057496278
Short name T160
Test name
Test status
Simulation time 565156155 ps
CPU time 2.91 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:35 PM UTC 24
Peak memory 225476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057496278 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstand
ing.2057496278
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1200825866
Short name T162
Test name
Test status
Simulation time 4024987436 ps
CPU time 17.15 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:49 PM UTC 24
Peak memory 227616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200825866 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1200825866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1592271368
Short name T1106
Test name
Test status
Simulation time 172128323 ps
CPU time 0.87 seconds
Started Sep 18 01:19:13 PM UTC 24
Finished Sep 18 01:19:15 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592271368 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.1592271368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3420387551
Short name T1112
Test name
Test status
Simulation time 22506439 ps
CPU time 0.68 seconds
Started Sep 18 01:19:14 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420387551 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.3420387551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2339633190
Short name T1111
Test name
Test status
Simulation time 28752109 ps
CPU time 0.62 seconds
Started Sep 18 01:19:14 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339633190 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.2339633190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.4284843193
Short name T1053
Test name
Test status
Simulation time 35943347 ps
CPU time 0.75 seconds
Started Sep 18 01:19:14 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284843193 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.4284843193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2870445359
Short name T1113
Test name
Test status
Simulation time 20601536 ps
CPU time 0.71 seconds
Started Sep 18 01:19:14 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870445359 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.2870445359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2832461808
Short name T1110
Test name
Test status
Simulation time 26906282 ps
CPU time 0.86 seconds
Started Sep 18 01:19:14 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832461808 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.2832461808
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1666198505
Short name T1090
Test name
Test status
Simulation time 16010067 ps
CPU time 0.69 seconds
Started Sep 18 01:19:14 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666198505 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.1666198505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1894218643
Short name T1100
Test name
Test status
Simulation time 14141628 ps
CPU time 0.83 seconds
Started Sep 18 01:19:14 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894218643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.1894218643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.3552177578
Short name T1116
Test name
Test status
Simulation time 23277676 ps
CPU time 0.79 seconds
Started Sep 18 01:19:14 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552177578 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.3552177578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2491589161
Short name T1096
Test name
Test status
Simulation time 14651115 ps
CPU time 0.78 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491589161 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.2491589161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.1436950572
Short name T1048
Test name
Test status
Simulation time 119248791 ps
CPU time 6.66 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:16 PM UTC 24
Peak memory 215052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436950572 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.1436950572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3214201517
Short name T1049
Test name
Test status
Simulation time 528001697 ps
CPU time 25.64 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:35 PM UTC 24
Peak memory 225232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214201517 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.3214201517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3955071276
Short name T91
Test name
Test status
Simulation time 47059364 ps
CPU time 1.73 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:34 PM UTC 24
Peak memory 224452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955071276 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.3955071276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3687851268
Short name T1041
Test name
Test status
Simulation time 151260843 ps
CPU time 2.94 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 227532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3687851268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.spi_device_csr_mem_rw_with_rand_reset.3687851268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.3856892004
Short name T159
Test name
Test status
Simulation time 40337169 ps
CPU time 1.3 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:33 PM UTC 24
Peak memory 224328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856892004 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3856892004
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1434581634
Short name T1022
Test name
Test status
Simulation time 13026584 ps
CPU time 1 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:33 PM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434581634 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1434581634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2984059051
Short name T135
Test name
Test status
Simulation time 441117342 ps
CPU time 1.67 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:34 PM UTC 24
Peak memory 224396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984059051 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.2984059051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.255732322
Short name T1020
Test name
Test status
Simulation time 12279256 ps
CPU time 0.79 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:33 PM UTC 24
Peak memory 212080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255732322 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.255732322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4174463753
Short name T1044
Test name
Test status
Simulation time 167074572 ps
CPU time 3.83 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:13 PM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174463753 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstand
ing.4174463753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.4022461534
Short name T106
Test name
Test status
Simulation time 146698426 ps
CPU time 3.19 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:35 PM UTC 24
Peak memory 225668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022461534 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4022461534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3208835263
Short name T107
Test name
Test status
Simulation time 549733769 ps
CPU time 6.4 seconds
Started Sep 18 01:17:31 PM UTC 24
Finished Sep 18 01:17:38 PM UTC 24
Peak memory 225300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208835263 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.3208835263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2198523912
Short name T1117
Test name
Test status
Simulation time 14805983 ps
CPU time 0.73 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198523912 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.2198523912
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2819473992
Short name T1093
Test name
Test status
Simulation time 18855765 ps
CPU time 0.67 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819473992 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.2819473992
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2320170872
Short name T1121
Test name
Test status
Simulation time 60233289 ps
CPU time 0.77 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320170872 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.2320170872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1195967026
Short name T1118
Test name
Test status
Simulation time 15036008 ps
CPU time 0.76 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:16 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195967026 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1195967026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2210883365
Short name T1123
Test name
Test status
Simulation time 41623359 ps
CPU time 0.81 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210883365 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.2210883365
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2720443643
Short name T1120
Test name
Test status
Simulation time 10855303 ps
CPU time 0.77 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720443643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.2720443643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1768973054
Short name T1124
Test name
Test status
Simulation time 43082986 ps
CPU time 0.79 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 212040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768973054 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.1768973054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1514390148
Short name T1126
Test name
Test status
Simulation time 52228884 ps
CPU time 0.77 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 212044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514390148 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.1514390148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.911813497
Short name T1125
Test name
Test status
Simulation time 12746202 ps
CPU time 0.72 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911813497 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.911813497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.838006697
Short name T1122
Test name
Test status
Simulation time 85574961 ps
CPU time 0.67 seconds
Started Sep 18 01:19:15 PM UTC 24
Finished Sep 18 01:19:17 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838006697 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.838006697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3059233323
Short name T118
Test name
Test status
Simulation time 160174889 ps
CPU time 2.47 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 229660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3059233323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.spi_device_csr_mem_rw_with_rand_reset.3059233323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.771621305
Short name T1033
Test name
Test status
Simulation time 94533423 ps
CPU time 1.89 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:11 PM UTC 24
Peak memory 224200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771621305 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.771621305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3741092641
Short name T1027
Test name
Test status
Simulation time 18366046 ps
CPU time 0.75 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:10 PM UTC 24
Peak memory 211896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741092641 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3741092641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2747610467
Short name T1043
Test name
Test status
Simulation time 221799534 ps
CPU time 3.47 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:13 PM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747610467 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstand
ing.2747610467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1958218593
Short name T114
Test name
Test status
Simulation time 524050338 ps
CPU time 3.23 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:13 PM UTC 24
Peak memory 225616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958218593 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1958218593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.4143067657
Short name T199
Test name
Test status
Simulation time 3468097244 ps
CPU time 6.76 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:16 PM UTC 24
Peak memory 227608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143067657 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.4143067657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.153372425
Short name T1042
Test name
Test status
Simulation time 166159081 ps
CPU time 2.61 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 229700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=153372425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.spi_device_csr_mem_rw_with_rand_reset.153372425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1748750890
Short name T136
Test name
Test status
Simulation time 47707555 ps
CPU time 1.53 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:11 PM UTC 24
Peak memory 224348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748750890 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1748750890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1741507914
Short name T1028
Test name
Test status
Simulation time 10879114 ps
CPU time 0.7 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:10 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741507914 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1741507914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3650371214
Short name T158
Test name
Test status
Simulation time 212523287 ps
CPU time 3.72 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:13 PM UTC 24
Peak memory 225452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650371214 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstand
ing.3650371214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1688685740
Short name T112
Test name
Test status
Simulation time 1653919586 ps
CPU time 4.22 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:14 PM UTC 24
Peak memory 227660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688685740 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1688685740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3932358164
Short name T194
Test name
Test status
Simulation time 9743165438 ps
CPU time 13.1 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:23 PM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932358164 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.3932358164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3130076117
Short name T1039
Test name
Test status
Simulation time 304091343 ps
CPU time 2.24 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 227608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3130076117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.spi_device_csr_mem_rw_with_rand_reset.3130076117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.51952191
Short name T1035
Test name
Test status
Simulation time 144425233 ps
CPU time 1.78 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51952191 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.51952191
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.186806429
Short name T1029
Test name
Test status
Simulation time 62745385 ps
CPU time 0.76 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:10 PM UTC 24
Peak memory 212084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186806429 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.186806429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2044084481
Short name T1034
Test name
Test status
Simulation time 119309786 ps
CPU time 1.71 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:11 PM UTC 24
Peak memory 224816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044084481 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand
ing.2044084481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3421106435
Short name T115
Test name
Test status
Simulation time 1347043171 ps
CPU time 4.12 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:14 PM UTC 24
Peak memory 227744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421106435 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3421106435
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.480884419
Short name T191
Test name
Test status
Simulation time 410700272 ps
CPU time 5.89 seconds
Started Sep 18 01:18:08 PM UTC 24
Finished Sep 18 01:18:16 PM UTC 24
Peak memory 225360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480884419 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.480884419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2617403884
Short name T1045
Test name
Test status
Simulation time 95190650 ps
CPU time 3.63 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:14 PM UTC 24
Peak memory 227664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2617403884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.spi_device_csr_mem_rw_with_rand_reset.2617403884
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.793727641
Short name T1036
Test name
Test status
Simulation time 36061454 ps
CPU time 1.99 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 224332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793727641 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.793727641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1905926126
Short name T1030
Test name
Test status
Simulation time 20206717 ps
CPU time 0.76 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:11 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905926126 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1905926126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2002203375
Short name T1046
Test name
Test status
Simulation time 373885706 ps
CPU time 4.11 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:14 PM UTC 24
Peak memory 225416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002203375 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand
ing.2002203375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.16212832
Short name T116
Test name
Test status
Simulation time 211527208 ps
CPU time 3.3 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:13 PM UTC 24
Peak memory 225556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16212832 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.16212832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2883892680
Short name T197
Test name
Test status
Simulation time 993013152 ps
CPU time 16.66 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:27 PM UTC 24
Peak memory 225368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883892680 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.2883892680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3372201290
Short name T117
Test name
Test status
Simulation time 102764473 ps
CPU time 1.75 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 226568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3372201290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.spi_device_csr_mem_rw_with_rand_reset.3372201290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.190807717
Short name T1038
Test name
Test status
Simulation time 30598489 ps
CPU time 1.83 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190807717 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.190807717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.2810723602
Short name T1031
Test name
Test status
Simulation time 15482329 ps
CPU time 0.97 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:11 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810723602 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2810723602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2193178597
Short name T1040
Test name
Test status
Simulation time 31550877 ps
CPU time 2.04 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:12 PM UTC 24
Peak memory 215232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193178597 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand
ing.2193178597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.815854940
Short name T1047
Test name
Test status
Simulation time 170580318 ps
CPU time 5.13 seconds
Started Sep 18 01:18:09 PM UTC 24
Finished Sep 18 01:18:15 PM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815854940 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.815854940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1073792020
Short name T24
Test name
Test status
Simulation time 46859102 ps
CPU time 2.98 seconds
Started Sep 18 02:22:25 PM UTC 24
Finished Sep 18 02:22:29 PM UTC 24
Peak memory 244616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073792020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1073792020
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.699907230
Short name T16
Test name
Test status
Simulation time 6273444070 ps
CPU time 40.87 seconds
Started Sep 18 02:22:33 PM UTC 24
Finished Sep 18 02:23:15 PM UTC 24
Peak memory 245312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699907230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.699907230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.3297248403
Short name T9
Test name
Test status
Simulation time 6685132858 ps
CPU time 25.84 seconds
Started Sep 18 02:21:58 PM UTC 24
Finished Sep 18 02:22:25 PM UTC 24
Peak memory 245336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297248403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3297248403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2932040929
Short name T8
Test name
Test status
Simulation time 796513925 ps
CPU time 15.21 seconds
Started Sep 18 02:21:59 PM UTC 24
Finished Sep 18 02:22:15 PM UTC 24
Peak memory 244952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932040929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2932040929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2972533767
Short name T12
Test name
Test status
Simulation time 18595055962 ps
CPU time 50.94 seconds
Started Sep 18 02:21:53 PM UTC 24
Finished Sep 18 02:22:45 PM UTC 24
Peak memory 245120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972533767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2972533767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2697956467
Short name T6
Test name
Test status
Simulation time 211988405 ps
CPU time 5.14 seconds
Started Sep 18 02:21:51 PM UTC 24
Finished Sep 18 02:21:57 PM UTC 24
Peak memory 245252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697956467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2697956467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3817228244
Short name T11
Test name
Test status
Simulation time 438687524 ps
CPU time 11.51 seconds
Started Sep 18 02:22:31 PM UTC 24
Finished Sep 18 02:22:43 PM UTC 24
Peak memory 229124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817228244 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.3817228244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.2973815537
Short name T3
Test name
Test status
Simulation time 20465918 ps
CPU time 1.16 seconds
Started Sep 18 02:21:46 PM UTC 24
Finished Sep 18 02:21:48 PM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973815537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2973815537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.1751354900
Short name T5
Test name
Test status
Simulation time 59110805 ps
CPU time 2.06 seconds
Started Sep 18 02:21:49 PM UTC 24
Finished Sep 18 02:21:52 PM UTC 24
Peak memory 227580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751354900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1751354900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.147139813
Short name T4
Test name
Test status
Simulation time 34770915 ps
CPU time 1.21 seconds
Started Sep 18 02:21:48 PM UTC 24
Finished Sep 18 02:21:50 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147139813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.147139813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.132975281
Short name T80
Test name
Test status
Simulation time 13466402 ps
CPU time 1.12 seconds
Started Sep 18 02:24:17 PM UTC 24
Finished Sep 18 02:24:19 PM UTC 24
Peak memory 213600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132975281 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.132975281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1667648534
Short name T37
Test name
Test status
Simulation time 118769920 ps
CPU time 6.79 seconds
Started Sep 18 02:23:39 PM UTC 24
Finished Sep 18 02:23:47 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667648534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1667648534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.482175405
Short name T15
Test name
Test status
Simulation time 20189803 ps
CPU time 1.24 seconds
Started Sep 18 02:23:05 PM UTC 24
Finished Sep 18 02:23:08 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482175405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.482175405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.664308456
Short name T58
Test name
Test status
Simulation time 17740157959 ps
CPU time 85.56 seconds
Started Sep 18 02:24:07 PM UTC 24
Finished Sep 18 02:25:35 PM UTC 24
Peak memory 261568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664308456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.664308456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.800139112
Short name T472
Test name
Test status
Simulation time 109536654495 ps
CPU time 652.16 seconds
Started Sep 18 02:24:11 PM UTC 24
Finished Sep 18 02:35:12 PM UTC 24
Peak memory 263676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800139112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.800139112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.454900184
Short name T38
Test name
Test status
Simulation time 765222415 ps
CPU time 15.48 seconds
Started Sep 18 02:23:48 PM UTC 24
Finished Sep 18 02:24:04 PM UTC 24
Peak memory 234952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454900184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.454900184
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.329918570
Short name T101
Test name
Test status
Simulation time 124430273743 ps
CPU time 272.7 seconds
Started Sep 18 02:23:55 PM UTC 24
Finished Sep 18 02:28:32 PM UTC 24
Peak memory 261496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329918570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.329918570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.559955696
Short name T17
Test name
Test status
Simulation time 478520838 ps
CPU time 6.7 seconds
Started Sep 18 02:23:26 PM UTC 24
Finished Sep 18 02:23:34 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559955696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.559955696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1477288911
Short name T18
Test name
Test status
Simulation time 5718249057 ps
CPU time 14.49 seconds
Started Sep 18 02:23:22 PM UTC 24
Finished Sep 18 02:23:38 PM UTC 24
Peak memory 234896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477288911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.1477288911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3852621086
Short name T55
Test name
Test status
Simulation time 19525605571 ps
CPU time 48.01 seconds
Started Sep 18 02:23:22 PM UTC 24
Finished Sep 18 02:24:12 PM UTC 24
Peak memory 251468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852621086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3852621086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1055727073
Short name T53
Test name
Test status
Simulation time 1584526359 ps
CPU time 20.39 seconds
Started Sep 18 02:24:05 PM UTC 24
Finished Sep 18 02:24:26 PM UTC 24
Peak memory 231428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055727073 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.1055727073
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4101550463
Short name T19
Test name
Test status
Simulation time 273171017 ps
CPU time 1.21 seconds
Started Sep 18 02:24:14 PM UTC 24
Finished Sep 18 02:24:16 PM UTC 24
Peak memory 256996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101550463 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4101550463
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.2691622886
Short name T20
Test name
Test status
Simulation time 72856296 ps
CPU time 1.72 seconds
Started Sep 18 02:24:12 PM UTC 24
Finished Sep 18 02:24:16 PM UTC 24
Peak memory 216820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691622886 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.2691622886
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1443527041
Short name T28
Test name
Test status
Simulation time 6914336469 ps
CPU time 22.86 seconds
Started Sep 18 02:23:10 PM UTC 24
Finished Sep 18 02:23:34 PM UTC 24
Peak memory 227508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443527041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1443527041
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.567147842
Short name T27
Test name
Test status
Simulation time 32469234 ps
CPU time 1.6 seconds
Started Sep 18 02:23:19 PM UTC 24
Finished Sep 18 02:23:21 PM UTC 24
Peak memory 227116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567147842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.567147842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.535961251
Short name T26
Test name
Test status
Simulation time 121971115 ps
CPU time 1.19 seconds
Started Sep 18 02:23:16 PM UTC 24
Finished Sep 18 02:23:18 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535961251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.535961251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.2868439033
Short name T41
Test name
Test status
Simulation time 975887810 ps
CPU time 16.72 seconds
Started Sep 18 02:23:36 PM UTC 24
Finished Sep 18 02:23:54 PM UTC 24
Peak memory 251080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868439033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2868439033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.1063782843
Short name T400
Test name
Test status
Simulation time 88538285 ps
CPU time 1.1 seconds
Started Sep 18 02:31:04 PM UTC 24
Finished Sep 18 02:31:07 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063782843 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.1063782843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1094950234
Short name T399
Test name
Test status
Simulation time 6532107525 ps
CPU time 15.24 seconds
Started Sep 18 02:30:45 PM UTC 24
Finished Sep 18 02:31:01 PM UTC 24
Peak memory 234784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094950234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1094950234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.1591353695
Short name T141
Test name
Test status
Simulation time 72664217 ps
CPU time 1.17 seconds
Started Sep 18 02:30:09 PM UTC 24
Finished Sep 18 02:30:11 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591353695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1591353695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1198841290
Short name T250
Test name
Test status
Simulation time 20612210483 ps
CPU time 147.19 seconds
Started Sep 18 02:30:55 PM UTC 24
Finished Sep 18 02:33:25 PM UTC 24
Peak memory 267584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198841290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1198841290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1191407033
Short name T336
Test name
Test status
Simulation time 6389545012 ps
CPU time 24.99 seconds
Started Sep 18 02:30:49 PM UTC 24
Finished Sep 18 02:31:15 PM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191407033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1191407033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.751287567
Short name T397
Test name
Test status
Simulation time 37360824 ps
CPU time 1.17 seconds
Started Sep 18 02:30:50 PM UTC 24
Finished Sep 18 02:30:52 PM UTC 24
Peak memory 226816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751287567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.751287567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.4072231169
Short name T212
Test name
Test status
Simulation time 2455446817 ps
CPU time 8.64 seconds
Started Sep 18 02:30:38 PM UTC 24
Finished Sep 18 02:30:48 PM UTC 24
Peak memory 245076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072231169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4072231169
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.3258073884
Short name T299
Test name
Test status
Simulation time 4042928607 ps
CPU time 21.59 seconds
Started Sep 18 02:30:40 PM UTC 24
Finished Sep 18 02:31:03 PM UTC 24
Peak memory 251532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258073884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3258073884
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1322075602
Short name T280
Test name
Test status
Simulation time 981139979 ps
CPU time 10.73 seconds
Started Sep 18 02:30:37 PM UTC 24
Finished Sep 18 02:30:49 PM UTC 24
Peak memory 244944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322075602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.1322075602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.702121588
Short name T268
Test name
Test status
Simulation time 1225844913 ps
CPU time 5.2 seconds
Started Sep 18 02:30:31 PM UTC 24
Finished Sep 18 02:30:37 PM UTC 24
Peak memory 245204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702121588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.702121588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1639847713
Short name T398
Test name
Test status
Simulation time 604823099 ps
CPU time 4.77 seconds
Started Sep 18 02:30:53 PM UTC 24
Finished Sep 18 02:30:59 PM UTC 24
Peak memory 233644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639847713 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1639847713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.2696055774
Short name T562
Test name
Test status
Simulation time 179122261520 ps
CPU time 445.95 seconds
Started Sep 18 02:31:02 PM UTC 24
Finished Sep 18 02:38:35 PM UTC 24
Peak memory 265668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696055774 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.2696055774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1086466541
Short name T339
Test name
Test status
Simulation time 1524494178 ps
CPU time 25.1 seconds
Started Sep 18 02:30:15 PM UTC 24
Finished Sep 18 02:30:41 PM UTC 24
Peak memory 227600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086466541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1086466541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.807650592
Short name T142
Test name
Test status
Simulation time 2123212149 ps
CPU time 9.82 seconds
Started Sep 18 02:30:13 PM UTC 24
Finished Sep 18 02:30:24 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807650592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.807650592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2064756384
Short name T144
Test name
Test status
Simulation time 71741720 ps
CPU time 1.66 seconds
Started Sep 18 02:30:28 PM UTC 24
Finished Sep 18 02:30:31 PM UTC 24
Peak memory 216104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064756384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2064756384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.437680667
Short name T143
Test name
Test status
Simulation time 131607459 ps
CPU time 1.51 seconds
Started Sep 18 02:30:25 PM UTC 24
Finished Sep 18 02:30:27 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437680667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.437680667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.740432059
Short name T227
Test name
Test status
Simulation time 6019262881 ps
CPU time 35.14 seconds
Started Sep 18 02:30:41 PM UTC 24
Finished Sep 18 02:31:18 PM UTC 24
Peak memory 251420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740432059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.740432059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.3965629401
Short name T77
Test name
Test status
Simulation time 120257473 ps
CPU time 1.04 seconds
Started Sep 18 02:31:39 PM UTC 24
Finished Sep 18 02:31:41 PM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965629401 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.3965629401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.660313678
Short name T74
Test name
Test status
Simulation time 2007194301 ps
CPU time 9.78 seconds
Started Sep 18 02:31:21 PM UTC 24
Finished Sep 18 02:31:32 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660313678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.660313678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.821805866
Short name T401
Test name
Test status
Simulation time 26398864 ps
CPU time 1.18 seconds
Started Sep 18 02:31:07 PM UTC 24
Finished Sep 18 02:31:09 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821805866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.821805866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.2137110781
Short name T228
Test name
Test status
Simulation time 18108714490 ps
CPU time 143.93 seconds
Started Sep 18 02:31:26 PM UTC 24
Finished Sep 18 02:33:52 PM UTC 24
Peak memory 261760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137110781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2137110781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3366048152
Short name T340
Test name
Test status
Simulation time 5432053169 ps
CPU time 108.52 seconds
Started Sep 18 02:31:26 PM UTC 24
Finished Sep 18 02:33:17 PM UTC 24
Peak memory 267968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366048152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3366048152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1368135874
Short name T647
Test name
Test status
Simulation time 54085979043 ps
CPU time 555.44 seconds
Started Sep 18 02:31:28 PM UTC 24
Finished Sep 18 02:40:51 PM UTC 24
Peak memory 267716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368135874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.1368135874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1597916733
Short name T331
Test name
Test status
Simulation time 114718879491 ps
CPU time 112.37 seconds
Started Sep 18 02:31:23 PM UTC 24
Finished Sep 18 02:33:18 PM UTC 24
Peak memory 251156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597916733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1597916733
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3292225924
Short name T225
Test name
Test status
Simulation time 4417389256 ps
CPU time 45.36 seconds
Started Sep 18 02:31:18 PM UTC 24
Finished Sep 18 02:32:06 PM UTC 24
Peak memory 235136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292225924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3292225924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2983679166
Short name T70
Test name
Test status
Simulation time 297578236 ps
CPU time 2.63 seconds
Started Sep 18 02:31:19 PM UTC 24
Finished Sep 18 02:31:23 PM UTC 24
Peak memory 234364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983679166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2983679166
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.4205571259
Short name T75
Test name
Test status
Simulation time 2559865379 ps
CPU time 21.4 seconds
Started Sep 18 02:31:15 PM UTC 24
Finished Sep 18 02:31:38 PM UTC 24
Peak memory 245020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205571259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.4205571259
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2664536187
Short name T403
Test name
Test status
Simulation time 32698698 ps
CPU time 2.99 seconds
Started Sep 18 02:31:14 PM UTC 24
Finished Sep 18 02:31:18 PM UTC 24
Peak memory 244884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664536187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2664536187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1758727697
Short name T76
Test name
Test status
Simulation time 3169315908 ps
CPU time 14.84 seconds
Started Sep 18 02:31:24 PM UTC 24
Finished Sep 18 02:31:40 PM UTC 24
Peak memory 233460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758727697 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.1758727697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1501644932
Short name T249
Test name
Test status
Simulation time 129961978395 ps
CPU time 393.27 seconds
Started Sep 18 02:31:32 PM UTC 24
Finished Sep 18 02:38:11 PM UTC 24
Peak memory 280064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501644932 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.1501644932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.1258855952
Short name T349
Test name
Test status
Simulation time 2214301496 ps
CPU time 7.78 seconds
Started Sep 18 02:31:11 PM UTC 24
Finished Sep 18 02:31:20 PM UTC 24
Peak memory 227576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258855952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1258855952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1073666957
Short name T404
Test name
Test status
Simulation time 2542942293 ps
CPU time 8.95 seconds
Started Sep 18 02:31:10 PM UTC 24
Finished Sep 18 02:31:20 PM UTC 24
Peak memory 227576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073666957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1073666957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.3880784014
Short name T72
Test name
Test status
Simulation time 961515693 ps
CPU time 11.2 seconds
Started Sep 18 02:31:13 PM UTC 24
Finished Sep 18 02:31:26 PM UTC 24
Peak memory 227604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880784014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3880784014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1157997390
Short name T402
Test name
Test status
Simulation time 1413213117 ps
CPU time 1.78 seconds
Started Sep 18 02:31:11 PM UTC 24
Finished Sep 18 02:31:14 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157997390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1157997390
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1847296272
Short name T407
Test name
Test status
Simulation time 19226462806 ps
CPU time 29.36 seconds
Started Sep 18 02:31:21 PM UTC 24
Finished Sep 18 02:31:52 PM UTC 24
Peak memory 261452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847296272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1847296272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.374179371
Short name T413
Test name
Test status
Simulation time 13974998 ps
CPU time 1.1 seconds
Started Sep 18 02:32:21 PM UTC 24
Finished Sep 18 02:32:24 PM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374179371 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.374179371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.91943731
Short name T409
Test name
Test status
Simulation time 265777923 ps
CPU time 5.69 seconds
Started Sep 18 02:32:03 PM UTC 24
Finished Sep 18 02:32:09 PM UTC 24
Peak memory 244892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91943731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.91943731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3762403615
Short name T78
Test name
Test status
Simulation time 15187549 ps
CPU time 1.16 seconds
Started Sep 18 02:31:41 PM UTC 24
Finished Sep 18 02:31:43 PM UTC 24
Peak memory 215888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762403615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3762403615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.3718717975
Short name T86
Test name
Test status
Simulation time 3076026917 ps
CPU time 61.06 seconds
Started Sep 18 02:32:10 PM UTC 24
Finished Sep 18 02:33:13 PM UTC 24
Peak memory 267836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718717975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3718717975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.3490111885
Short name T147
Test name
Test status
Simulation time 209729043366 ps
CPU time 357.94 seconds
Started Sep 18 02:32:13 PM UTC 24
Finished Sep 18 02:38:16 PM UTC 24
Peak memory 261628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490111885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3490111885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.77311115
Short name T410
Test name
Test status
Simulation time 445828962 ps
CPU time 5.18 seconds
Started Sep 18 02:32:14 PM UTC 24
Finished Sep 18 02:32:20 PM UTC 24
Peak memory 231564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77311115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.77311115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1283666468
Short name T330
Test name
Test status
Simulation time 529603845 ps
CPU time 9.47 seconds
Started Sep 18 02:32:07 PM UTC 24
Finished Sep 18 02:32:17 PM UTC 24
Peak memory 235020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283666468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1283666468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1251783148
Short name T287
Test name
Test status
Simulation time 4105923796 ps
CPU time 35.5 seconds
Started Sep 18 02:32:07 PM UTC 24
Finished Sep 18 02:32:44 PM UTC 24
Peak memory 261628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251783148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.1251783148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2922981297
Short name T278
Test name
Test status
Simulation time 1040902226 ps
CPU time 12.96 seconds
Started Sep 18 02:31:52 PM UTC 24
Finished Sep 18 02:32:06 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922981297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2922981297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.4029690548
Short name T294
Test name
Test status
Simulation time 2935226679 ps
CPU time 39.89 seconds
Started Sep 18 02:31:53 PM UTC 24
Finished Sep 18 02:32:34 PM UTC 24
Peak memory 245116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029690548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4029690548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3509359873
Short name T283
Test name
Test status
Simulation time 3486907975 ps
CPU time 20.33 seconds
Started Sep 18 02:31:50 PM UTC 24
Finished Sep 18 02:32:12 PM UTC 24
Peak memory 245312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509359873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3509359873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1643003327
Short name T300
Test name
Test status
Simulation time 4416104126 ps
CPU time 22.8 seconds
Started Sep 18 02:31:49 PM UTC 24
Finished Sep 18 02:32:13 PM UTC 24
Peak memory 245332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643003327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1643003327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.735236079
Short name T412
Test name
Test status
Simulation time 707735714 ps
CPU time 14.36 seconds
Started Sep 18 02:32:07 PM UTC 24
Finished Sep 18 02:32:22 PM UTC 24
Peak memory 233316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735236079 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.735236079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2390484720
Short name T411
Test name
Test status
Simulation time 339538098 ps
CPU time 1.83 seconds
Started Sep 18 02:32:18 PM UTC 24
Finished Sep 18 02:32:21 PM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390484720 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.2390484720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.642711317
Short name T345
Test name
Test status
Simulation time 1226887049 ps
CPU time 21.21 seconds
Started Sep 18 02:31:44 PM UTC 24
Finished Sep 18 02:32:06 PM UTC 24
Peak memory 227448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642711317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.642711317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1092237400
Short name T406
Test name
Test status
Simulation time 663230174 ps
CPU time 4.82 seconds
Started Sep 18 02:31:43 PM UTC 24
Finished Sep 18 02:31:49 PM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092237400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1092237400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.111491392
Short name T408
Test name
Test status
Simulation time 99229232 ps
CPU time 2.81 seconds
Started Sep 18 02:31:48 PM UTC 24
Finished Sep 18 02:31:52 PM UTC 24
Peak memory 227340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111491392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.111491392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3018370477
Short name T405
Test name
Test status
Simulation time 299144639 ps
CPU time 1.49 seconds
Started Sep 18 02:31:45 PM UTC 24
Finished Sep 18 02:31:47 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018370477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3018370477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.110758895
Short name T270
Test name
Test status
Simulation time 14017702360 ps
CPU time 27.08 seconds
Started Sep 18 02:31:55 PM UTC 24
Finished Sep 18 02:32:23 PM UTC 24
Peak memory 249164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110758895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.110758895
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3436671637
Short name T420
Test name
Test status
Simulation time 93806738 ps
CPU time 1.07 seconds
Started Sep 18 02:32:47 PM UTC 24
Finished Sep 18 02:32:50 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436671637 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.3436671637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1108826312
Short name T419
Test name
Test status
Simulation time 344339892 ps
CPU time 8.03 seconds
Started Sep 18 02:32:35 PM UTC 24
Finished Sep 18 02:32:44 PM UTC 24
Peak memory 245004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108826312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1108826312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.1172360220
Short name T414
Test name
Test status
Simulation time 27904165 ps
CPU time 1.22 seconds
Started Sep 18 02:32:22 PM UTC 24
Finished Sep 18 02:32:24 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172360220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1172360220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.109470868
Short name T224
Test name
Test status
Simulation time 74709134885 ps
CPU time 190.01 seconds
Started Sep 18 02:32:44 PM UTC 24
Finished Sep 18 02:35:57 PM UTC 24
Peak memory 261436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109470868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.109470868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.4185987254
Short name T210
Test name
Test status
Simulation time 4236825330 ps
CPU time 54.52 seconds
Started Sep 18 02:32:44 PM UTC 24
Finished Sep 18 02:33:40 PM UTC 24
Peak memory 247308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185987254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4185987254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1791771029
Short name T148
Test name
Test status
Simulation time 27254395473 ps
CPU time 327.91 seconds
Started Sep 18 02:32:45 PM UTC 24
Finished Sep 18 02:38:19 PM UTC 24
Peak memory 282052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791771029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.1791771029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3928306850
Short name T332
Test name
Test status
Simulation time 3166475308 ps
CPU time 37.39 seconds
Started Sep 18 02:32:40 PM UTC 24
Finished Sep 18 02:33:19 PM UTC 24
Peak memory 234828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928306850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3928306850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.529127684
Short name T209
Test name
Test status
Simulation time 401019257 ps
CPU time 11.06 seconds
Started Sep 18 02:32:29 PM UTC 24
Finished Sep 18 02:32:41 PM UTC 24
Peak memory 235012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529127684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.529127684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.3765886055
Short name T231
Test name
Test status
Simulation time 4070150290 ps
CPU time 33.13 seconds
Started Sep 18 02:32:34 PM UTC 24
Finished Sep 18 02:33:08 PM UTC 24
Peak memory 234884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765886055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3765886055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3131122467
Short name T220
Test name
Test status
Simulation time 11600801415 ps
CPU time 19.38 seconds
Started Sep 18 02:32:28 PM UTC 24
Finished Sep 18 02:32:49 PM UTC 24
Peak memory 245372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131122467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.3131122467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2283464656
Short name T295
Test name
Test status
Simulation time 1202329689 ps
CPU time 17.31 seconds
Started Sep 18 02:32:28 PM UTC 24
Finished Sep 18 02:32:47 PM UTC 24
Peak memory 251076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283464656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2283464656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1366620763
Short name T174
Test name
Test status
Simulation time 1249028956 ps
CPU time 7.66 seconds
Started Sep 18 02:32:43 PM UTC 24
Finished Sep 18 02:32:52 PM UTC 24
Peak memory 233588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366620763 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.1366620763
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.137318533
Short name T820
Test name
Test status
Simulation time 299832064652 ps
CPU time 717.83 seconds
Started Sep 18 02:32:47 PM UTC 24
Finished Sep 18 02:44:54 PM UTC 24
Peak memory 300420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137318533 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.137318533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.2460298354
Short name T341
Test name
Test status
Simulation time 1394161832 ps
CPU time 20.2 seconds
Started Sep 18 02:32:25 PM UTC 24
Finished Sep 18 02:32:46 PM UTC 24
Peak memory 231820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460298354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2460298354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.759295700
Short name T417
Test name
Test status
Simulation time 4215306256 ps
CPU time 9.01 seconds
Started Sep 18 02:32:24 PM UTC 24
Finished Sep 18 02:32:34 PM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759295700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.759295700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.4062229528
Short name T416
Test name
Test status
Simulation time 18727234 ps
CPU time 1.59 seconds
Started Sep 18 02:32:26 PM UTC 24
Finished Sep 18 02:32:29 PM UTC 24
Peak memory 227000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062229528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4062229528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2625436209
Short name T415
Test name
Test status
Simulation time 149567274 ps
CPU time 1.77 seconds
Started Sep 18 02:32:25 PM UTC 24
Finished Sep 18 02:32:28 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625436209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2625436209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.1005112174
Short name T418
Test name
Test status
Simulation time 42512849 ps
CPU time 3.28 seconds
Started Sep 18 02:32:35 PM UTC 24
Finished Sep 18 02:32:39 PM UTC 24
Peak memory 244616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005112174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1005112174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.2116542528
Short name T424
Test name
Test status
Simulation time 14619491 ps
CPU time 1.1 seconds
Started Sep 18 02:33:12 PM UTC 24
Finished Sep 18 02:33:14 PM UTC 24
Peak memory 213716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116542528 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.2116542528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3302866621
Short name T303
Test name
Test status
Simulation time 1725208807 ps
CPU time 7.5 seconds
Started Sep 18 02:33:02 PM UTC 24
Finished Sep 18 02:33:10 PM UTC 24
Peak memory 234892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302866621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3302866621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.2723947845
Short name T175
Test name
Test status
Simulation time 13120964 ps
CPU time 1.14 seconds
Started Sep 18 02:32:50 PM UTC 24
Finished Sep 18 02:32:52 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723947845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2723947845
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.964830165
Short name T422
Test name
Test status
Simulation time 39359085 ps
CPU time 1.11 seconds
Started Sep 18 02:33:08 PM UTC 24
Finished Sep 18 02:33:10 PM UTC 24
Peak memory 226808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964830165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.964830165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2394985806
Short name T69
Test name
Test status
Simulation time 42768855995 ps
CPU time 260.52 seconds
Started Sep 18 02:33:09 PM UTC 24
Finished Sep 18 02:37:34 PM UTC 24
Peak memory 263944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394985806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2394985806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.329847954
Short name T476
Test name
Test status
Simulation time 10632735371 ps
CPU time 124.61 seconds
Started Sep 18 02:33:09 PM UTC 24
Finished Sep 18 02:35:16 PM UTC 24
Peak memory 261584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329847954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.329847954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.3037454811
Short name T421
Test name
Test status
Simulation time 325868892 ps
CPU time 5.94 seconds
Started Sep 18 02:33:03 PM UTC 24
Finished Sep 18 02:33:10 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037454811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3037454811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2950984756
Short name T217
Test name
Test status
Simulation time 14595490537 ps
CPU time 58.97 seconds
Started Sep 18 02:33:05 PM UTC 24
Finished Sep 18 02:34:06 PM UTC 24
Peak memory 267592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950984756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.2950984756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3642982658
Short name T237
Test name
Test status
Simulation time 10559179301 ps
CPU time 29.19 seconds
Started Sep 18 02:32:56 PM UTC 24
Finished Sep 18 02:33:27 PM UTC 24
Peak memory 229876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642982658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3642982658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.756742825
Short name T423
Test name
Test status
Simulation time 894887108 ps
CPU time 13.91 seconds
Started Sep 18 02:32:56 PM UTC 24
Finished Sep 18 02:33:12 PM UTC 24
Peak memory 251340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756742825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.756742825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.443606333
Short name T182
Test name
Test status
Simulation time 802206777 ps
CPU time 7.95 seconds
Started Sep 18 02:32:55 PM UTC 24
Finished Sep 18 02:33:04 PM UTC 24
Peak memory 251144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443606333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.443606333
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3990950349
Short name T261
Test name
Test status
Simulation time 2545453771 ps
CPU time 15.52 seconds
Started Sep 18 02:32:55 PM UTC 24
Finished Sep 18 02:33:12 PM UTC 24
Peak memory 245388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990950349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3990950349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.478554834
Short name T429
Test name
Test status
Simulation time 3880862248 ps
CPU time 19.62 seconds
Started Sep 18 02:33:07 PM UTC 24
Finished Sep 18 02:33:28 PM UTC 24
Peak memory 231364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478554834 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.478554834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.2356654472
Short name T346
Test name
Test status
Simulation time 14139026091 ps
CPU time 32.86 seconds
Started Sep 18 02:32:53 PM UTC 24
Finished Sep 18 02:33:27 PM UTC 24
Peak memory 227508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356654472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2356654472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2280948324
Short name T180
Test name
Test status
Simulation time 6404797340 ps
CPU time 7.26 seconds
Started Sep 18 02:32:51 PM UTC 24
Finished Sep 18 02:33:00 PM UTC 24
Peak memory 227508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280948324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2280948324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.2257741653
Short name T179
Test name
Test status
Simulation time 72647168 ps
CPU time 1.71 seconds
Started Sep 18 02:32:53 PM UTC 24
Finished Sep 18 02:32:56 PM UTC 24
Peak memory 227140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257741653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2257741653
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.370879102
Short name T178
Test name
Test status
Simulation time 204433902 ps
CPU time 1.33 seconds
Started Sep 18 02:32:53 PM UTC 24
Finished Sep 18 02:32:55 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370879102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.370879102
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.439732145
Short name T296
Test name
Test status
Simulation time 447168323 ps
CPU time 4.56 seconds
Started Sep 18 02:33:00 PM UTC 24
Finished Sep 18 02:33:06 PM UTC 24
Peak memory 244944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439732145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.439732145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.1456553302
Short name T433
Test name
Test status
Simulation time 87899684 ps
CPU time 1.07 seconds
Started Sep 18 02:33:40 PM UTC 24
Finished Sep 18 02:33:42 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456553302 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.1456553302
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.1030216746
Short name T428
Test name
Test status
Simulation time 1109528324 ps
CPU time 6.47 seconds
Started Sep 18 02:33:20 PM UTC 24
Finished Sep 18 02:33:27 PM UTC 24
Peak memory 244896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030216746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1030216746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.1660488056
Short name T425
Test name
Test status
Simulation time 27772165 ps
CPU time 1.13 seconds
Started Sep 18 02:33:12 PM UTC 24
Finished Sep 18 02:33:14 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660488056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1660488056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.2220874948
Short name T253
Test name
Test status
Simulation time 21133675121 ps
CPU time 88.34 seconds
Started Sep 18 02:33:28 PM UTC 24
Finished Sep 18 02:34:58 PM UTC 24
Peak memory 267572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220874948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2220874948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1274772362
Short name T342
Test name
Test status
Simulation time 14176156746 ps
CPU time 34.03 seconds
Started Sep 18 02:33:28 PM UTC 24
Finished Sep 18 02:34:03 PM UTC 24
Peak memory 245316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274772362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1274772362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.2400999769
Short name T460
Test name
Test status
Simulation time 4213363975 ps
CPU time 74.22 seconds
Started Sep 18 02:33:24 PM UTC 24
Finished Sep 18 02:34:40 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400999769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2400999769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3671757611
Short name T202
Test name
Test status
Simulation time 22882543295 ps
CPU time 193.36 seconds
Started Sep 18 02:33:26 PM UTC 24
Finished Sep 18 02:36:42 PM UTC 24
Peak memory 261764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671757611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.3671757611
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.620625206
Short name T257
Test name
Test status
Simulation time 178391301 ps
CPU time 3.84 seconds
Started Sep 18 02:33:18 PM UTC 24
Finished Sep 18 02:33:23 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620625206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.620625206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.363112331
Short name T229
Test name
Test status
Simulation time 3022157662 ps
CPU time 43.71 seconds
Started Sep 18 02:33:19 PM UTC 24
Finished Sep 18 02:34:04 PM UTC 24
Peak memory 234868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363112331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.363112331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2475216225
Short name T282
Test name
Test status
Simulation time 6951411742 ps
CPU time 22.1 seconds
Started Sep 18 02:33:17 PM UTC 24
Finished Sep 18 02:33:41 PM UTC 24
Peak memory 245392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475216225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.2475216225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1175723459
Short name T279
Test name
Test status
Simulation time 9544402408 ps
CPU time 36.94 seconds
Started Sep 18 02:33:16 PM UTC 24
Finished Sep 18 02:33:55 PM UTC 24
Peak memory 245284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175723459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1175723459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.839183411
Short name T431
Test name
Test status
Simulation time 635724953 ps
CPU time 9.42 seconds
Started Sep 18 02:33:28 PM UTC 24
Finished Sep 18 02:33:39 PM UTC 24
Peak memory 233324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839183411 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.839183411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.1446492213
Short name T432
Test name
Test status
Simulation time 17703154866 ps
CPU time 26.22 seconds
Started Sep 18 02:33:14 PM UTC 24
Finished Sep 18 02:33:41 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446492213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1446492213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3632132418
Short name T430
Test name
Test status
Simulation time 23343056670 ps
CPU time 18.37 seconds
Started Sep 18 02:33:13 PM UTC 24
Finished Sep 18 02:33:32 PM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632132418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3632132418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1533288829
Short name T427
Test name
Test status
Simulation time 255213086 ps
CPU time 1.64 seconds
Started Sep 18 02:33:15 PM UTC 24
Finished Sep 18 02:33:18 PM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533288829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1533288829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3468129194
Short name T426
Test name
Test status
Simulation time 366413926 ps
CPU time 1.31 seconds
Started Sep 18 02:33:14 PM UTC 24
Finished Sep 18 02:33:16 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468129194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3468129194
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2385760484
Short name T436
Test name
Test status
Simulation time 22294403679 ps
CPU time 27.86 seconds
Started Sep 18 02:33:19 PM UTC 24
Finished Sep 18 02:33:48 PM UTC 24
Peak memory 245072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385760484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2385760484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.103998750
Short name T444
Test name
Test status
Simulation time 29134036 ps
CPU time 0.96 seconds
Started Sep 18 02:34:02 PM UTC 24
Finished Sep 18 02:34:04 PM UTC 24
Peak memory 215996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103998750 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.103998750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3391059632
Short name T259
Test name
Test status
Simulation time 2477062192 ps
CPU time 5.24 seconds
Started Sep 18 02:33:51 PM UTC 24
Finished Sep 18 02:33:57 PM UTC 24
Peak memory 235076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391059632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3391059632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.3267783502
Short name T434
Test name
Test status
Simulation time 16996373 ps
CPU time 1.17 seconds
Started Sep 18 02:33:40 PM UTC 24
Finished Sep 18 02:33:42 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267783502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3267783502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.3109173612
Short name T441
Test name
Test status
Simulation time 29691539 ps
CPU time 1.29 seconds
Started Sep 18 02:33:56 PM UTC 24
Finished Sep 18 02:33:58 PM UTC 24
Peak memory 226808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109173612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3109173612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1931023318
Short name T232
Test name
Test status
Simulation time 2568725218 ps
CPU time 66.65 seconds
Started Sep 18 02:33:58 PM UTC 24
Finished Sep 18 02:35:06 PM UTC 24
Peak memory 265656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931023318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1931023318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2777575759
Short name T318
Test name
Test status
Simulation time 68902795704 ps
CPU time 752.69 seconds
Started Sep 18 02:33:58 PM UTC 24
Finished Sep 18 02:46:41 PM UTC 24
Peak memory 267656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777575759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2777575759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.4189943999
Short name T205
Test name
Test status
Simulation time 290136534368 ps
CPU time 300.84 seconds
Started Sep 18 02:33:54 PM UTC 24
Finished Sep 18 02:38:59 PM UTC 24
Peak memory 267648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189943999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.4189943999
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.3626073202
Short name T298
Test name
Test status
Simulation time 4502971442 ps
CPU time 12.06 seconds
Started Sep 18 02:33:48 PM UTC 24
Finished Sep 18 02:34:02 PM UTC 24
Peak memory 231516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626073202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3626073202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.1003869095
Short name T446
Test name
Test status
Simulation time 8775973991 ps
CPU time 17.08 seconds
Started Sep 18 02:33:48 PM UTC 24
Finished Sep 18 02:34:07 PM UTC 24
Peak memory 244996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003869095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1003869095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.803765805
Short name T323
Test name
Test status
Simulation time 3425648981 ps
CPU time 8.07 seconds
Started Sep 18 02:33:46 PM UTC 24
Finished Sep 18 02:33:55 PM UTC 24
Peak memory 245120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803765805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.803765805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3377603627
Short name T438
Test name
Test status
Simulation time 621771245 ps
CPU time 4.16 seconds
Started Sep 18 02:33:44 PM UTC 24
Finished Sep 18 02:33:49 PM UTC 24
Peak memory 234812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377603627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3377603627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.267520709
Short name T442
Test name
Test status
Simulation time 85887533 ps
CPU time 5.45 seconds
Started Sep 18 02:33:55 PM UTC 24
Finished Sep 18 02:34:01 PM UTC 24
Peak memory 233804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267520709 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.267520709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.597356325
Short name T445
Test name
Test status
Simulation time 5559942169 ps
CPU time 21.33 seconds
Started Sep 18 02:33:42 PM UTC 24
Finished Sep 18 02:34:04 PM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597356325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.597356325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.946675739
Short name T439
Test name
Test status
Simulation time 1789612876 ps
CPU time 7.06 seconds
Started Sep 18 02:33:42 PM UTC 24
Finished Sep 18 02:33:50 PM UTC 24
Peak memory 227336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946675739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.946675739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.2391629723
Short name T437
Test name
Test status
Simulation time 3636251157 ps
CPU time 3.78 seconds
Started Sep 18 02:33:43 PM UTC 24
Finished Sep 18 02:33:48 PM UTC 24
Peak memory 227532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391629723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2391629723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3491283897
Short name T435
Test name
Test status
Simulation time 131552438 ps
CPU time 1.37 seconds
Started Sep 18 02:33:43 PM UTC 24
Finished Sep 18 02:33:45 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491283897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3491283897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.4024086100
Short name T274
Test name
Test status
Simulation time 861570105 ps
CPU time 12.68 seconds
Started Sep 18 02:33:49 PM UTC 24
Finished Sep 18 02:34:02 PM UTC 24
Peak memory 244944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024086100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4024086100
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.1633742999
Short name T454
Test name
Test status
Simulation time 28941915 ps
CPU time 0.93 seconds
Started Sep 18 02:34:23 PM UTC 24
Finished Sep 18 02:34:25 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633742999 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.1633742999
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.3072282146
Short name T456
Test name
Test status
Simulation time 16280734562 ps
CPU time 20.86 seconds
Started Sep 18 02:34:08 PM UTC 24
Finished Sep 18 02:34:31 PM UTC 24
Peak memory 245132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072282146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3072282146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.287047399
Short name T443
Test name
Test status
Simulation time 88218688 ps
CPU time 0.84 seconds
Started Sep 18 02:34:02 PM UTC 24
Finished Sep 18 02:34:04 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287047399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.287047399
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.820562497
Short name T517
Test name
Test status
Simulation time 54489024421 ps
CPU time 177.88 seconds
Started Sep 18 02:34:14 PM UTC 24
Finished Sep 18 02:37:15 PM UTC 24
Peak memory 261696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820562497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.820562497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2229817248
Short name T502
Test name
Test status
Simulation time 64751288563 ps
CPU time 143.29 seconds
Started Sep 18 02:34:16 PM UTC 24
Finished Sep 18 02:36:42 PM UTC 24
Peak memory 261692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229817248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2229817248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.368166577
Short name T326
Test name
Test status
Simulation time 28043133660 ps
CPU time 204.65 seconds
Started Sep 18 02:34:19 PM UTC 24
Finished Sep 18 02:37:47 PM UTC 24
Peak memory 268044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368166577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.368166577
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.2158972672
Short name T329
Test name
Test status
Simulation time 151782151 ps
CPU time 12.19 seconds
Started Sep 18 02:34:13 PM UTC 24
Finished Sep 18 02:34:26 PM UTC 24
Peak memory 247048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158972672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2158972672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.4181274076
Short name T238
Test name
Test status
Simulation time 79282145100 ps
CPU time 171.35 seconds
Started Sep 18 02:34:14 PM UTC 24
Finished Sep 18 02:37:08 PM UTC 24
Peak memory 261704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181274076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.4181274076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.3876313197
Short name T451
Test name
Test status
Simulation time 839215243 ps
CPU time 10.44 seconds
Started Sep 18 02:34:06 PM UTC 24
Finished Sep 18 02:34:18 PM UTC 24
Peak memory 234816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876313197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3876313197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.690276732
Short name T254
Test name
Test status
Simulation time 105024263 ps
CPU time 3.36 seconds
Started Sep 18 02:34:07 PM UTC 24
Finished Sep 18 02:34:12 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690276732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.690276732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.911550850
Short name T450
Test name
Test status
Simulation time 362226310 ps
CPU time 7.72 seconds
Started Sep 18 02:34:06 PM UTC 24
Finished Sep 18 02:34:15 PM UTC 24
Peak memory 245220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911550850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.911550850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1139987482
Short name T272
Test name
Test status
Simulation time 773899423 ps
CPU time 6.19 seconds
Started Sep 18 02:34:06 PM UTC 24
Finished Sep 18 02:34:13 PM UTC 24
Peak memory 234760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139987482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1139987482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.4210588925
Short name T453
Test name
Test status
Simulation time 3103507233 ps
CPU time 7.56 seconds
Started Sep 18 02:34:14 PM UTC 24
Finished Sep 18 02:34:22 PM UTC 24
Peak memory 233524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210588925 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.4210588925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.1963068376
Short name T164
Test name
Test status
Simulation time 658585473 ps
CPU time 1.54 seconds
Started Sep 18 02:34:20 PM UTC 24
Finished Sep 18 02:34:23 PM UTC 24
Peak memory 215932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963068376 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.1963068376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.4028604371
Short name T343
Test name
Test status
Simulation time 8654777493 ps
CPU time 60.42 seconds
Started Sep 18 02:34:05 PM UTC 24
Finished Sep 18 02:35:07 PM UTC 24
Peak memory 231628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028604371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4028604371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3817545932
Short name T449
Test name
Test status
Simulation time 2388345066 ps
CPU time 6.54 seconds
Started Sep 18 02:34:05 PM UTC 24
Finished Sep 18 02:34:12 PM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817545932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3817545932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.2635682037
Short name T448
Test name
Test status
Simulation time 119143887 ps
CPU time 1.76 seconds
Started Sep 18 02:34:05 PM UTC 24
Finished Sep 18 02:34:08 PM UTC 24
Peak memory 215812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635682037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2635682037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.773443514
Short name T447
Test name
Test status
Simulation time 77145543 ps
CPU time 1.18 seconds
Started Sep 18 02:34:05 PM UTC 24
Finished Sep 18 02:34:07 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773443514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.773443514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.1705856512
Short name T452
Test name
Test status
Simulation time 1184575914 ps
CPU time 10.52 seconds
Started Sep 18 02:34:07 PM UTC 24
Finished Sep 18 02:34:19 PM UTC 24
Peak memory 244948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705856512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1705856512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1093567244
Short name T464
Test name
Test status
Simulation time 85991576 ps
CPU time 1.06 seconds
Started Sep 18 02:34:59 PM UTC 24
Finished Sep 18 02:35:01 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093567244 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.1093567244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.701037506
Short name T474
Test name
Test status
Simulation time 11670557901 ps
CPU time 32.39 seconds
Started Sep 18 02:34:41 PM UTC 24
Finished Sep 18 02:35:15 PM UTC 24
Peak memory 234888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701037506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.701037506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.2821826381
Short name T455
Test name
Test status
Simulation time 29567471 ps
CPU time 1.16 seconds
Started Sep 18 02:34:23 PM UTC 24
Finished Sep 18 02:34:26 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821826381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2821826381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1641061068
Short name T513
Test name
Test status
Simulation time 15152569083 ps
CPU time 135.86 seconds
Started Sep 18 02:34:49 PM UTC 24
Finished Sep 18 02:37:07 PM UTC 24
Peak memory 261436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641061068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1641061068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.1816511162
Short name T539
Test name
Test status
Simulation time 39013530161 ps
CPU time 166.72 seconds
Started Sep 18 02:34:59 PM UTC 24
Finished Sep 18 02:37:49 PM UTC 24
Peak memory 261892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816511162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1816511162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2956443598
Short name T492
Test name
Test status
Simulation time 2744125137 ps
CPU time 64.91 seconds
Started Sep 18 02:34:59 PM UTC 24
Finished Sep 18 02:36:06 PM UTC 24
Peak memory 278276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956443598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.2956443598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.2555246928
Short name T462
Test name
Test status
Simulation time 92352563 ps
CPU time 4.25 seconds
Started Sep 18 02:34:42 PM UTC 24
Finished Sep 18 02:34:48 PM UTC 24
Peak memory 234888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555246928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2555246928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.2961707667
Short name T505
Test name
Test status
Simulation time 52112406368 ps
CPU time 122.19 seconds
Started Sep 18 02:34:48 PM UTC 24
Finished Sep 18 02:36:52 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961707667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.2961707667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.330733698
Short name T247
Test name
Test status
Simulation time 756393119 ps
CPU time 5.92 seconds
Started Sep 18 02:34:39 PM UTC 24
Finished Sep 18 02:34:46 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330733698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.330733698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.630757629
Short name T463
Test name
Test status
Simulation time 1762527160 ps
CPU time 16.91 seconds
Started Sep 18 02:34:40 PM UTC 24
Finished Sep 18 02:34:58 PM UTC 24
Peak memory 245192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630757629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.630757629
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.242619236
Short name T310
Test name
Test status
Simulation time 1689940527 ps
CPU time 4.92 seconds
Started Sep 18 02:34:36 PM UTC 24
Finished Sep 18 02:34:42 PM UTC 24
Peak memory 245208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242619236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.242619236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2532619909
Short name T461
Test name
Test status
Simulation time 260293963 ps
CPU time 6.16 seconds
Started Sep 18 02:34:33 PM UTC 24
Finished Sep 18 02:34:40 PM UTC 24
Peak memory 234756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532619909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2532619909
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3016751990
Short name T468
Test name
Test status
Simulation time 9085176394 ps
CPU time 17.1 seconds
Started Sep 18 02:34:49 PM UTC 24
Finished Sep 18 02:35:07 PM UTC 24
Peak memory 233604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016751990 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.3016751990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.1243773029
Short name T465
Test name
Test status
Simulation time 12524764408 ps
CPU time 35.01 seconds
Started Sep 18 02:34:27 PM UTC 24
Finished Sep 18 02:35:03 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243773029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1243773029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3639671113
Short name T459
Test name
Test status
Simulation time 8142764348 ps
CPU time 10.84 seconds
Started Sep 18 02:34:27 PM UTC 24
Finished Sep 18 02:34:39 PM UTC 24
Peak memory 227832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639671113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3639671113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.2739822981
Short name T458
Test name
Test status
Simulation time 80413639 ps
CPU time 1.93 seconds
Started Sep 18 02:34:32 PM UTC 24
Finished Sep 18 02:34:35 PM UTC 24
Peak memory 227124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739822981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2739822981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.4271685806
Short name T457
Test name
Test status
Simulation time 20641894 ps
CPU time 1.16 seconds
Started Sep 18 02:34:30 PM UTC 24
Finished Sep 18 02:34:32 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271685806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4271685806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.1454613899
Short name T301
Test name
Test status
Simulation time 1261433288 ps
CPU time 5.7 seconds
Started Sep 18 02:34:41 PM UTC 24
Finished Sep 18 02:34:48 PM UTC 24
Peak memory 234708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454613899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1454613899
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1222229271
Short name T482
Test name
Test status
Simulation time 15227164 ps
CPU time 1.14 seconds
Started Sep 18 02:35:28 PM UTC 24
Finished Sep 18 02:35:31 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222229271 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1222229271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2643622553
Short name T277
Test name
Test status
Simulation time 17223746424 ps
CPU time 23.21 seconds
Started Sep 18 02:35:15 PM UTC 24
Finished Sep 18 02:35:40 PM UTC 24
Peak memory 234836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643622553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2643622553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.20519308
Short name T466
Test name
Test status
Simulation time 55138195 ps
CPU time 0.98 seconds
Started Sep 18 02:35:02 PM UTC 24
Finished Sep 18 02:35:04 PM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20519308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.20519308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.3302745022
Short name T498
Test name
Test status
Simulation time 2612623096 ps
CPU time 65.12 seconds
Started Sep 18 02:35:21 PM UTC 24
Finished Sep 18 02:36:28 PM UTC 24
Peak memory 261824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302745022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3302745022
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1043272401
Short name T558
Test name
Test status
Simulation time 30909617229 ps
CPU time 184.91 seconds
Started Sep 18 02:35:17 PM UTC 24
Finished Sep 18 02:38:25 PM UTC 24
Peak memory 261452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043272401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.1043272401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2701735233
Short name T478
Test name
Test status
Simulation time 1446997304 ps
CPU time 7.65 seconds
Started Sep 18 02:35:11 PM UTC 24
Finished Sep 18 02:35:20 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701735233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2701735233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.1723688741
Short name T477
Test name
Test status
Simulation time 121957710 ps
CPU time 3.91 seconds
Started Sep 18 02:35:12 PM UTC 24
Finished Sep 18 02:35:17 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723688741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1723688741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.747755199
Short name T480
Test name
Test status
Simulation time 835909868 ps
CPU time 14.37 seconds
Started Sep 18 02:35:11 PM UTC 24
Finished Sep 18 02:35:27 PM UTC 24
Peak memory 244888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747755199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.747755199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3886198272
Short name T475
Test name
Test status
Simulation time 2677445300 ps
CPU time 7.2 seconds
Started Sep 18 02:35:08 PM UTC 24
Finished Sep 18 02:35:16 PM UTC 24
Peak memory 251268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886198272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3886198272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1015906456
Short name T479
Test name
Test status
Simulation time 342075650 ps
CPU time 5.45 seconds
Started Sep 18 02:35:18 PM UTC 24
Finished Sep 18 02:35:24 PM UTC 24
Peak memory 231172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015906456 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1015906456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.234012953
Short name T500
Test name
Test status
Simulation time 24844585089 ps
CPU time 62.96 seconds
Started Sep 18 02:35:27 PM UTC 24
Finished Sep 18 02:36:32 PM UTC 24
Peak memory 234912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234012953 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.234012953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.2389607325
Short name T470
Test name
Test status
Simulation time 190297401 ps
CPU time 3 seconds
Started Sep 18 02:35:07 PM UTC 24
Finished Sep 18 02:35:11 PM UTC 24
Peak memory 227396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389607325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2389607325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2185240061
Short name T471
Test name
Test status
Simulation time 691106460 ps
CPU time 5.14 seconds
Started Sep 18 02:35:06 PM UTC 24
Finished Sep 18 02:35:12 PM UTC 24
Peak memory 227356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185240061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2185240061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.3299142149
Short name T473
Test name
Test status
Simulation time 577953769 ps
CPU time 5.61 seconds
Started Sep 18 02:35:08 PM UTC 24
Finished Sep 18 02:35:15 PM UTC 24
Peak memory 227412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299142149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3299142149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.3634059441
Short name T469
Test name
Test status
Simulation time 139159343 ps
CPU time 1.39 seconds
Started Sep 18 02:35:08 PM UTC 24
Finished Sep 18 02:35:10 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634059441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3634059441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.2384761432
Short name T481
Test name
Test status
Simulation time 832372404 ps
CPU time 12.63 seconds
Started Sep 18 02:35:13 PM UTC 24
Finished Sep 18 02:35:27 PM UTC 24
Peak memory 251400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384761432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2384761432
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1481629167
Short name T81
Test name
Test status
Simulation time 14118899 ps
CPU time 1.1 seconds
Started Sep 18 02:25:18 PM UTC 24
Finished Sep 18 02:25:20 PM UTC 24
Peak memory 213596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481629167 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1481629167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2954801621
Short name T95
Test name
Test status
Simulation time 872698017 ps
CPU time 6.48 seconds
Started Sep 18 02:24:44 PM UTC 24
Finished Sep 18 02:24:51 PM UTC 24
Peak memory 234968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954801621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2954801621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.566185462
Short name T354
Test name
Test status
Simulation time 23042649 ps
CPU time 1.19 seconds
Started Sep 18 02:24:17 PM UTC 24
Finished Sep 18 02:24:19 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566185462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.566185462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3438817330
Short name T355
Test name
Test status
Simulation time 71603475 ps
CPU time 1.65 seconds
Started Sep 18 02:24:59 PM UTC 24
Finished Sep 18 02:25:02 PM UTC 24
Peak memory 226872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438817330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3438817330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.4111642403
Short name T177
Test name
Test status
Simulation time 166153537411 ps
CPU time 465.82 seconds
Started Sep 18 02:25:02 PM UTC 24
Finished Sep 18 02:32:54 PM UTC 24
Peak memory 268100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111642403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.4111642403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3813878781
Short name T110
Test name
Test status
Simulation time 198569832 ps
CPU time 12.58 seconds
Started Sep 18 02:24:47 PM UTC 24
Finished Sep 18 02:25:00 PM UTC 24
Peak memory 251140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813878781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3813878781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.2311410459
Short name T109
Test name
Test status
Simulation time 10711263070 ps
CPU time 13.99 seconds
Started Sep 18 02:24:30 PM UTC 24
Finished Sep 18 02:24:46 PM UTC 24
Peak memory 235076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311410459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2311410459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.975472718
Short name T96
Test name
Test status
Simulation time 2822118805 ps
CPU time 37.92 seconds
Started Sep 18 02:24:36 PM UTC 24
Finished Sep 18 02:25:16 PM UTC 24
Peak memory 247316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975472718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.975472718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.1929889824
Short name T183
Test name
Test status
Simulation time 9333974302 ps
CPU time 38.55 seconds
Started Sep 18 02:24:27 PM UTC 24
Finished Sep 18 02:25:07 PM UTC 24
Peak memory 245012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929889824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.1929889824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.398382887
Short name T56
Test name
Test status
Simulation time 15832976702 ps
CPU time 12.12 seconds
Started Sep 18 02:24:27 PM UTC 24
Finished Sep 18 02:24:40 PM UTC 24
Peak memory 234928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398382887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.398382887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3982825351
Short name T153
Test name
Test status
Simulation time 1680460320 ps
CPU time 19.1 seconds
Started Sep 18 02:24:54 PM UTC 24
Finished Sep 18 02:25:14 PM UTC 24
Peak memory 231172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982825351 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.3982825351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3774793652
Short name T21
Test name
Test status
Simulation time 86911445 ps
CPU time 1.92 seconds
Started Sep 18 02:25:15 PM UTC 24
Finished Sep 18 02:25:19 PM UTC 24
Peak memory 256996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774793652 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3774793652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3401646250
Short name T42
Test name
Test status
Simulation time 2082570087 ps
CPU time 34.3 seconds
Started Sep 18 02:24:23 PM UTC 24
Finished Sep 18 02:24:59 PM UTC 24
Peak memory 231804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401646250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3401646250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2545775858
Short name T30
Test name
Test status
Simulation time 396905837 ps
CPU time 2.29 seconds
Started Sep 18 02:24:20 PM UTC 24
Finished Sep 18 02:24:23 PM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545775858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2545775858
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.828453627
Short name T44
Test name
Test status
Simulation time 40293891 ps
CPU time 1.95 seconds
Started Sep 18 02:24:26 PM UTC 24
Finished Sep 18 02:24:29 PM UTC 24
Peak memory 227196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828453627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.828453627
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2941415682
Short name T32
Test name
Test status
Simulation time 49661900 ps
CPU time 1.29 seconds
Started Sep 18 02:24:24 PM UTC 24
Finished Sep 18 02:24:26 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941415682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2941415682
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.803860484
Short name T54
Test name
Test status
Simulation time 46045918494 ps
CPU time 10.34 seconds
Started Sep 18 02:24:42 PM UTC 24
Finished Sep 18 02:24:53 PM UTC 24
Peak memory 234828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803860484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.803860484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1658734185
Short name T493
Test name
Test status
Simulation time 53580988 ps
CPU time 1.14 seconds
Started Sep 18 02:36:06 PM UTC 24
Finished Sep 18 02:36:09 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658734185 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.1658734185
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.154209042
Short name T275
Test name
Test status
Simulation time 175020350 ps
CPU time 5.43 seconds
Started Sep 18 02:35:51 PM UTC 24
Finished Sep 18 02:35:58 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154209042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.154209042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.4076399786
Short name T483
Test name
Test status
Simulation time 57017620 ps
CPU time 1.17 seconds
Started Sep 18 02:35:32 PM UTC 24
Finished Sep 18 02:35:34 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076399786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4076399786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.691948283
Short name T288
Test name
Test status
Simulation time 33772839517 ps
CPU time 249.89 seconds
Started Sep 18 02:35:57 PM UTC 24
Finished Sep 18 02:40:11 PM UTC 24
Peak memory 277884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691948283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.691948283
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.2841807649
Short name T495
Test name
Test status
Simulation time 877755678 ps
CPU time 24.37 seconds
Started Sep 18 02:35:51 PM UTC 24
Finished Sep 18 02:36:17 PM UTC 24
Peak memory 261580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841807649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2841807649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.3477922834
Short name T639
Test name
Test status
Simulation time 29418053375 ps
CPU time 285.85 seconds
Started Sep 18 02:35:54 PM UTC 24
Finished Sep 18 02:40:45 PM UTC 24
Peak memory 261508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477922834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.3477922834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.2213804786
Short name T489
Test name
Test status
Simulation time 181494264 ps
CPU time 5.32 seconds
Started Sep 18 02:35:48 PM UTC 24
Finished Sep 18 02:35:54 PM UTC 24
Peak memory 234840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213804786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2213804786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.1537246553
Short name T292
Test name
Test status
Simulation time 42254683849 ps
CPU time 79.62 seconds
Started Sep 18 02:35:49 PM UTC 24
Finished Sep 18 02:37:10 PM UTC 24
Peak memory 251276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537246553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1537246553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2979974204
Short name T490
Test name
Test status
Simulation time 1064787755 ps
CPU time 6.5 seconds
Started Sep 18 02:35:48 PM UTC 24
Finished Sep 18 02:35:55 PM UTC 24
Peak memory 245188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979974204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.2979974204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.168386939
Short name T488
Test name
Test status
Simulation time 85886513 ps
CPU time 3.35 seconds
Started Sep 18 02:35:46 PM UTC 24
Finished Sep 18 02:35:51 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168386939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.168386939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3810737326
Short name T491
Test name
Test status
Simulation time 877984378 ps
CPU time 5.32 seconds
Started Sep 18 02:35:56 PM UTC 24
Finished Sep 18 02:36:02 PM UTC 24
Peak memory 229388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810737326 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.3810737326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.1516955713
Short name T166
Test name
Test status
Simulation time 2960590393 ps
CPU time 42.54 seconds
Started Sep 18 02:36:03 PM UTC 24
Finished Sep 18 02:36:47 PM UTC 24
Peak memory 261824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516955713 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.1516955713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.2346829996
Short name T486
Test name
Test status
Simulation time 1157155119 ps
CPU time 6.29 seconds
Started Sep 18 02:35:41 PM UTC 24
Finished Sep 18 02:35:48 PM UTC 24
Peak memory 227452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346829996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2346829996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1682086308
Short name T484
Test name
Test status
Simulation time 3817895165 ps
CPU time 8.13 seconds
Started Sep 18 02:35:35 PM UTC 24
Finished Sep 18 02:35:44 PM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682086308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1682086308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.4190106285
Short name T487
Test name
Test status
Simulation time 1351407208 ps
CPU time 4.32 seconds
Started Sep 18 02:35:45 PM UTC 24
Finished Sep 18 02:35:50 PM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190106285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4190106285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1838305227
Short name T485
Test name
Test status
Simulation time 19437619 ps
CPU time 1.18 seconds
Started Sep 18 02:35:44 PM UTC 24
Finished Sep 18 02:35:46 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838305227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1838305227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.2028824677
Short name T302
Test name
Test status
Simulation time 66882081 ps
CPU time 3.21 seconds
Started Sep 18 02:35:51 PM UTC 24
Finished Sep 18 02:35:56 PM UTC 24
Peak memory 234736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028824677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2028824677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.1316286841
Short name T508
Test name
Test status
Simulation time 12616571 ps
CPU time 1.05 seconds
Started Sep 18 02:36:56 PM UTC 24
Finished Sep 18 02:36:58 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316286841 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1316286841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2930868629
Short name T504
Test name
Test status
Simulation time 1347844624 ps
CPU time 8.23 seconds
Started Sep 18 02:36:37 PM UTC 24
Finished Sep 18 02:36:46 PM UTC 24
Peak memory 245256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930868629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2930868629
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.626500637
Short name T494
Test name
Test status
Simulation time 19693557 ps
CPU time 1.2 seconds
Started Sep 18 02:36:09 PM UTC 24
Finished Sep 18 02:36:12 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626500637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.626500637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.127301337
Short name T523
Test name
Test status
Simulation time 14394470682 ps
CPU time 35.32 seconds
Started Sep 18 02:36:47 PM UTC 24
Finished Sep 18 02:37:23 PM UTC 24
Peak memory 265788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127301337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.127301337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3177248469
Short name T632
Test name
Test status
Simulation time 76364432547 ps
CPU time 222.65 seconds
Started Sep 18 02:36:47 PM UTC 24
Finished Sep 18 02:40:33 PM UTC 24
Peak memory 263688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177248469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3177248469
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1165287325
Short name T541
Test name
Test status
Simulation time 14855424661 ps
CPU time 60.81 seconds
Started Sep 18 02:36:48 PM UTC 24
Finished Sep 18 02:37:50 PM UTC 24
Peak memory 263616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165287325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.1165287325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.2377112361
Short name T506
Test name
Test status
Simulation time 855221386 ps
CPU time 14.66 seconds
Started Sep 18 02:36:39 PM UTC 24
Finished Sep 18 02:36:55 PM UTC 24
Peak memory 234712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377112361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2377112361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.3928897363
Short name T510
Test name
Test status
Simulation time 7091785002 ps
CPU time 31.09 seconds
Started Sep 18 02:36:29 PM UTC 24
Finished Sep 18 02:37:01 PM UTC 24
Peak memory 234884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928897363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3928897363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.1101734432
Short name T526
Test name
Test status
Simulation time 2749915163 ps
CPU time 52.9 seconds
Started Sep 18 02:36:33 PM UTC 24
Finished Sep 18 02:37:27 PM UTC 24
Peak memory 263500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101734432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1101734432
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.314562207
Short name T503
Test name
Test status
Simulation time 1388338319 ps
CPU time 17.57 seconds
Started Sep 18 02:36:27 PM UTC 24
Finished Sep 18 02:36:46 PM UTC 24
Peak memory 244952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314562207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.314562207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.576929101
Short name T276
Test name
Test status
Simulation time 469516631 ps
CPU time 9.05 seconds
Started Sep 18 02:36:26 PM UTC 24
Finished Sep 18 02:36:36 PM UTC 24
Peak memory 234692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576929101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.576929101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.2576774289
Short name T507
Test name
Test status
Simulation time 2633320861 ps
CPU time 12.67 seconds
Started Sep 18 02:36:43 PM UTC 24
Finished Sep 18 02:36:57 PM UTC 24
Peak memory 229260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576774289 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.2576774289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.398421677
Short name T167
Test name
Test status
Simulation time 21522823676 ps
CPU time 119.72 seconds
Started Sep 18 02:36:53 PM UTC 24
Finished Sep 18 02:38:55 PM UTC 24
Peak memory 261896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398421677 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.398421677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.956192874
Short name T467
Test name
Test status
Simulation time 3834724021 ps
CPU time 43.95 seconds
Started Sep 18 02:36:18 PM UTC 24
Finished Sep 18 02:37:03 PM UTC 24
Peak memory 227704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956192874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.956192874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2761881931
Short name T499
Test name
Test status
Simulation time 3617849647 ps
CPU time 17.67 seconds
Started Sep 18 02:36:13 PM UTC 24
Finished Sep 18 02:36:32 PM UTC 24
Peak memory 227468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761881931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2761881931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.4071152462
Short name T497
Test name
Test status
Simulation time 10991955 ps
CPU time 1.08 seconds
Started Sep 18 02:36:24 PM UTC 24
Finished Sep 18 02:36:26 PM UTC 24
Peak memory 216016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071152462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4071152462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.265968958
Short name T496
Test name
Test status
Simulation time 144492435 ps
CPU time 1.3 seconds
Started Sep 18 02:36:23 PM UTC 24
Finished Sep 18 02:36:25 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265968958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.265968958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.3220969133
Short name T501
Test name
Test status
Simulation time 299911509 ps
CPU time 4.61 seconds
Started Sep 18 02:36:33 PM UTC 24
Finished Sep 18 02:36:39 PM UTC 24
Peak memory 234724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220969133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3220969133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.4239121156
Short name T522
Test name
Test status
Simulation time 12037613 ps
CPU time 1.09 seconds
Started Sep 18 02:37:21 PM UTC 24
Finished Sep 18 02:37:23 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239121156 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.4239121156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.322043480
Short name T266
Test name
Test status
Simulation time 5556819542 ps
CPU time 17.73 seconds
Started Sep 18 02:37:09 PM UTC 24
Finished Sep 18 02:37:28 PM UTC 24
Peak memory 245320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322043480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.322043480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.4007707320
Short name T509
Test name
Test status
Simulation time 45503767 ps
CPU time 1.18 seconds
Started Sep 18 02:36:58 PM UTC 24
Finished Sep 18 02:37:01 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007707320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4007707320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.803381414
Short name T570
Test name
Test status
Simulation time 26897313408 ps
CPU time 85.02 seconds
Started Sep 18 02:37:15 PM UTC 24
Finished Sep 18 02:38:43 PM UTC 24
Peak memory 249412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803381414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.803381414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2437653025
Short name T563
Test name
Test status
Simulation time 6986200697 ps
CPU time 75.3 seconds
Started Sep 18 02:37:18 PM UTC 24
Finished Sep 18 02:38:35 PM UTC 24
Peak memory 268032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437653025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2437653025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3588175533
Short name T566
Test name
Test status
Simulation time 9868931751 ps
CPU time 77.82 seconds
Started Sep 18 02:37:18 PM UTC 24
Finished Sep 18 02:38:38 PM UTC 24
Peak memory 261632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588175533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.3588175533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.4091188187
Short name T519
Test name
Test status
Simulation time 770372060 ps
CPU time 4.99 seconds
Started Sep 18 02:37:11 PM UTC 24
Finished Sep 18 02:37:17 PM UTC 24
Peak memory 245256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091188187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4091188187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.1538580953
Short name T518
Test name
Test status
Simulation time 37960519 ps
CPU time 1.17 seconds
Started Sep 18 02:37:14 PM UTC 24
Finished Sep 18 02:37:16 PM UTC 24
Peak memory 226876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538580953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.1538580953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.3433605267
Short name T516
Test name
Test status
Simulation time 874424210 ps
CPU time 4.95 seconds
Started Sep 18 02:37:09 PM UTC 24
Finished Sep 18 02:37:15 PM UTC 24
Peak memory 234748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433605267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3433605267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.1242054362
Short name T534
Test name
Test status
Simulation time 4411440985 ps
CPU time 30.04 seconds
Started Sep 18 02:37:09 PM UTC 24
Finished Sep 18 02:37:40 PM UTC 24
Peak memory 251288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242054362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1242054362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1955097254
Short name T297
Test name
Test status
Simulation time 910222748 ps
CPU time 7.27 seconds
Started Sep 18 02:37:05 PM UTC 24
Finished Sep 18 02:37:14 PM UTC 24
Peak memory 244944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955097254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.1955097254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1246562464
Short name T515
Test name
Test status
Simulation time 53007188 ps
CPU time 2.81 seconds
Started Sep 18 02:37:04 PM UTC 24
Finished Sep 18 02:37:08 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246562464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1246562464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.2217111511
Short name T520
Test name
Test status
Simulation time 1706766414 ps
CPU time 5.46 seconds
Started Sep 18 02:37:15 PM UTC 24
Finished Sep 18 02:37:22 PM UTC 24
Peak memory 233328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217111511 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.2217111511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.213790777
Short name T521
Test name
Test status
Simulation time 72158039 ps
CPU time 1.73 seconds
Started Sep 18 02:37:20 PM UTC 24
Finished Sep 18 02:37:23 PM UTC 24
Peak memory 216972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213790777 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.213790777
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1511322328
Short name T537
Test name
Test status
Simulation time 21014593412 ps
CPU time 42.17 seconds
Started Sep 18 02:37:02 PM UTC 24
Finished Sep 18 02:37:45 PM UTC 24
Peak memory 227576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511322328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1511322328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.754359093
Short name T511
Test name
Test status
Simulation time 26610343 ps
CPU time 1.1 seconds
Started Sep 18 02:37:00 PM UTC 24
Finished Sep 18 02:37:02 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754359093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.754359093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.730984634
Short name T514
Test name
Test status
Simulation time 177574970 ps
CPU time 3.18 seconds
Started Sep 18 02:37:03 PM UTC 24
Finished Sep 18 02:37:07 PM UTC 24
Peak memory 227452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730984634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.730984634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3170675862
Short name T512
Test name
Test status
Simulation time 51517494 ps
CPU time 1.19 seconds
Started Sep 18 02:37:02 PM UTC 24
Finished Sep 18 02:37:04 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170675862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3170675862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.214993405
Short name T527
Test name
Test status
Simulation time 1466914476 ps
CPU time 17.99 seconds
Started Sep 18 02:37:09 PM UTC 24
Finished Sep 18 02:37:28 PM UTC 24
Peak memory 245200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214993405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.214993405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.2443242903
Short name T536
Test name
Test status
Simulation time 25865050 ps
CPU time 1.12 seconds
Started Sep 18 02:37:43 PM UTC 24
Finished Sep 18 02:37:45 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443242903 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.2443242903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.2715886835
Short name T533
Test name
Test status
Simulation time 709982797 ps
CPU time 4.84 seconds
Started Sep 18 02:37:34 PM UTC 24
Finished Sep 18 02:37:40 PM UTC 24
Peak memory 234704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715886835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2715886835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.4138660117
Short name T524
Test name
Test status
Simulation time 114891935 ps
CPU time 1.18 seconds
Started Sep 18 02:37:22 PM UTC 24
Finished Sep 18 02:37:24 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138660117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4138660117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.335740647
Short name T306
Test name
Test status
Simulation time 101151270132 ps
CPU time 322.74 seconds
Started Sep 18 02:37:37 PM UTC 24
Finished Sep 18 02:43:05 PM UTC 24
Peak memory 265544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335740647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.335740647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.6207813
Short name T999
Test name
Test status
Simulation time 138617125432 ps
CPU time 872.09 seconds
Started Sep 18 02:37:38 PM UTC 24
Finished Sep 18 02:52:21 PM UTC 24
Peak memory 282304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6207813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.6207813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.983564676
Short name T335
Test name
Test status
Simulation time 17177055782 ps
CPU time 75.36 seconds
Started Sep 18 02:37:35 PM UTC 24
Finished Sep 18 02:38:52 PM UTC 24
Peak memory 249372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983564676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.983564676
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.1870361565
Short name T531
Test name
Test status
Simulation time 266033798 ps
CPU time 5.91 seconds
Started Sep 18 02:37:28 PM UTC 24
Finished Sep 18 02:37:36 PM UTC 24
Peak memory 235004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870361565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1870361565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.1170938976
Short name T551
Test name
Test status
Simulation time 7917758901 ps
CPU time 38.83 seconds
Started Sep 18 02:37:30 PM UTC 24
Finished Sep 18 02:38:10 PM UTC 24
Peak memory 261772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170938976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1170938976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2766382223
Short name T529
Test name
Test status
Simulation time 249927293 ps
CPU time 2.61 seconds
Started Sep 18 02:37:28 PM UTC 24
Finished Sep 18 02:37:33 PM UTC 24
Peak memory 234436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766382223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.2766382223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1460791245
Short name T530
Test name
Test status
Simulation time 134814727 ps
CPU time 4.41 seconds
Started Sep 18 02:37:28 PM UTC 24
Finished Sep 18 02:37:35 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460791245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1460791245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2651298646
Short name T535
Test name
Test status
Simulation time 90873593 ps
CPU time 5.12 seconds
Started Sep 18 02:37:36 PM UTC 24
Finished Sep 18 02:37:42 PM UTC 24
Peak memory 233280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651298646 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2651298646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.768078075
Short name T173
Test name
Test status
Simulation time 100872750307 ps
CPU time 445.99 seconds
Started Sep 18 02:37:41 PM UTC 24
Finished Sep 18 02:45:13 PM UTC 24
Peak memory 277968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768078075 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.768078075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3092497104
Short name T565
Test name
Test status
Simulation time 7982902168 ps
CPU time 69.37 seconds
Started Sep 18 02:37:25 PM UTC 24
Finished Sep 18 02:38:36 PM UTC 24
Peak memory 227832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092497104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3092497104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.4076587446
Short name T532
Test name
Test status
Simulation time 5225980899 ps
CPU time 12.07 seconds
Started Sep 18 02:37:25 PM UTC 24
Finished Sep 18 02:37:38 PM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076587446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4076587446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.1173248696
Short name T528
Test name
Test status
Simulation time 44883149 ps
CPU time 1.22 seconds
Started Sep 18 02:37:26 PM UTC 24
Finished Sep 18 02:37:29 PM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173248696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1173248696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3416560420
Short name T525
Test name
Test status
Simulation time 27513805 ps
CPU time 1.19 seconds
Started Sep 18 02:37:25 PM UTC 24
Finished Sep 18 02:37:27 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416560420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3416560420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.2471146752
Short name T204
Test name
Test status
Simulation time 69856406 ps
CPU time 3.09 seconds
Started Sep 18 02:37:30 PM UTC 24
Finished Sep 18 02:37:34 PM UTC 24
Peak memory 244944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471146752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2471146752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.1425701084
Short name T552
Test name
Test status
Simulation time 11761001 ps
CPU time 1.06 seconds
Started Sep 18 02:38:12 PM UTC 24
Finished Sep 18 02:38:14 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425701084 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.1425701084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3112331089
Short name T548
Test name
Test status
Simulation time 541566208 ps
CPU time 5.93 seconds
Started Sep 18 02:37:57 PM UTC 24
Finished Sep 18 02:38:05 PM UTC 24
Peak memory 245004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112331089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3112331089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.3557211345
Short name T538
Test name
Test status
Simulation time 37740057 ps
CPU time 1.2 seconds
Started Sep 18 02:37:46 PM UTC 24
Finished Sep 18 02:37:48 PM UTC 24
Peak memory 215888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557211345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3557211345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.154666415
Short name T633
Test name
Test status
Simulation time 94801574611 ps
CPU time 146.99 seconds
Started Sep 18 02:38:06 PM UTC 24
Finished Sep 18 02:40:36 PM UTC 24
Peak memory 261632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154666415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.154666415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3881783197
Short name T281
Test name
Test status
Simulation time 4926680097 ps
CPU time 85.33 seconds
Started Sep 18 02:38:08 PM UTC 24
Finished Sep 18 02:39:35 PM UTC 24
Peak memory 278144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881783197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3881783197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1986206588
Short name T940
Test name
Test status
Simulation time 65253974127 ps
CPU time 548.3 seconds
Started Sep 18 02:38:09 PM UTC 24
Finished Sep 18 02:47:24 PM UTC 24
Peak memory 273984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986206588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.1986206588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.1988322695
Short name T550
Test name
Test status
Simulation time 754464120 ps
CPU time 8.74 seconds
Started Sep 18 02:37:59 PM UTC 24
Finished Sep 18 02:38:08 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988322695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1988322695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.315634253
Short name T327
Test name
Test status
Simulation time 137019144446 ps
CPU time 325.07 seconds
Started Sep 18 02:37:59 PM UTC 24
Finished Sep 18 02:43:28 PM UTC 24
Peak memory 265928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315634253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.315634253
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3925169779
Short name T546
Test name
Test status
Simulation time 327367287 ps
CPU time 4.13 seconds
Started Sep 18 02:37:53 PM UTC 24
Finished Sep 18 02:37:58 PM UTC 24
Peak memory 229560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925169779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3925169779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1514160887
Short name T564
Test name
Test status
Simulation time 22015163464 ps
CPU time 41.32 seconds
Started Sep 18 02:37:53 PM UTC 24
Finished Sep 18 02:38:36 PM UTC 24
Peak memory 247192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514160887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1514160887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.4034687781
Short name T547
Test name
Test status
Simulation time 1335047848 ps
CPU time 6.48 seconds
Started Sep 18 02:37:52 PM UTC 24
Finished Sep 18 02:37:59 PM UTC 24
Peak memory 245008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034687781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.4034687781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3984155455
Short name T543
Test name
Test status
Simulation time 203751477 ps
CPU time 3.51 seconds
Started Sep 18 02:37:51 PM UTC 24
Finished Sep 18 02:37:55 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984155455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3984155455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.40915161
Short name T555
Test name
Test status
Simulation time 5045583160 ps
CPU time 19.74 seconds
Started Sep 18 02:38:00 PM UTC 24
Finished Sep 18 02:38:21 PM UTC 24
Peak memory 231412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40915161 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.40915161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.306902347
Short name T233
Test name
Test status
Simulation time 14630478370 ps
CPU time 70.89 seconds
Started Sep 18 02:38:12 PM UTC 24
Finished Sep 18 02:39:24 PM UTC 24
Peak memory 265992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306902347 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.306902347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.570030464
Short name T540
Test name
Test status
Simulation time 38738671 ps
CPU time 1.05 seconds
Started Sep 18 02:37:47 PM UTC 24
Finished Sep 18 02:37:49 PM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570030464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.570030464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1733807962
Short name T544
Test name
Test status
Simulation time 3139846336 ps
CPU time 9.56 seconds
Started Sep 18 02:37:46 PM UTC 24
Finished Sep 18 02:37:57 PM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733807962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1733807962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.796523826
Short name T545
Test name
Test status
Simulation time 204650430 ps
CPU time 7.6 seconds
Started Sep 18 02:37:50 PM UTC 24
Finished Sep 18 02:37:58 PM UTC 24
Peak memory 227388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796523826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.796523826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1832063207
Short name T542
Test name
Test status
Simulation time 365362910 ps
CPU time 1.37 seconds
Started Sep 18 02:37:50 PM UTC 24
Finished Sep 18 02:37:52 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832063207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1832063207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.422822260
Short name T549
Test name
Test status
Simulation time 4415100627 ps
CPU time 9.93 seconds
Started Sep 18 02:37:56 PM UTC 24
Finished Sep 18 02:38:08 PM UTC 24
Peak memory 235084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422822260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.422822260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.1859115626
Short name T568
Test name
Test status
Simulation time 25486197 ps
CPU time 1.12 seconds
Started Sep 18 02:38:38 PM UTC 24
Finished Sep 18 02:38:40 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859115626 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.1859115626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.834616350
Short name T267
Test name
Test status
Simulation time 129497481 ps
CPU time 2.9 seconds
Started Sep 18 02:38:27 PM UTC 24
Finished Sep 18 02:38:31 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834616350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.834616350
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.282974391
Short name T553
Test name
Test status
Simulation time 22059456 ps
CPU time 1.16 seconds
Started Sep 18 02:38:15 PM UTC 24
Finished Sep 18 02:38:17 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282974391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.282974391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.2718618445
Short name T246
Test name
Test status
Simulation time 10515142866 ps
CPU time 104.62 seconds
Started Sep 18 02:38:36 PM UTC 24
Finished Sep 18 02:40:23 PM UTC 24
Peak memory 263492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718618445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2718618445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3489986218
Short name T740
Test name
Test status
Simulation time 217147147609 ps
CPU time 268.04 seconds
Started Sep 18 02:38:36 PM UTC 24
Finished Sep 18 02:43:08 PM UTC 24
Peak memory 280064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489986218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3489986218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.3693606407
Short name T234
Test name
Test status
Simulation time 8085159844 ps
CPU time 76.2 seconds
Started Sep 18 02:38:37 PM UTC 24
Finished Sep 18 02:39:55 PM UTC 24
Peak memory 251464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693606407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.3693606407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.4049494318
Short name T571
Test name
Test status
Simulation time 470111625 ps
CPU time 11.25 seconds
Started Sep 18 02:38:30 PM UTC 24
Finished Sep 18 02:38:43 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049494318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4049494318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2902390771
Short name T677
Test name
Test status
Simulation time 106134553851 ps
CPU time 171.93 seconds
Started Sep 18 02:38:32 PM UTC 24
Finished Sep 18 02:41:26 PM UTC 24
Peak memory 261432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902390771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.2902390771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.3389260908
Short name T560
Test name
Test status
Simulation time 261264675 ps
CPU time 4.97 seconds
Started Sep 18 02:38:24 PM UTC 24
Finished Sep 18 02:38:30 PM UTC 24
Peak memory 234604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389260908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3389260908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2558084349
Short name T567
Test name
Test status
Simulation time 7805941408 ps
CPU time 13.46 seconds
Started Sep 18 02:38:24 PM UTC 24
Finished Sep 18 02:38:38 PM UTC 24
Peak memory 251532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558084349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2558084349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3035950473
Short name T559
Test name
Test status
Simulation time 98209805 ps
CPU time 3.46 seconds
Started Sep 18 02:38:22 PM UTC 24
Finished Sep 18 02:38:26 PM UTC 24
Peak memory 234588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035950473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3035950473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2478525207
Short name T577
Test name
Test status
Simulation time 5244782139 ps
CPU time 30.59 seconds
Started Sep 18 02:38:22 PM UTC 24
Finished Sep 18 02:38:53 PM UTC 24
Peak memory 245016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478525207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2478525207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2066081126
Short name T575
Test name
Test status
Simulation time 2252164771 ps
CPU time 18.27 seconds
Started Sep 18 02:38:32 PM UTC 24
Finished Sep 18 02:38:51 PM UTC 24
Peak memory 229260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066081126 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.2066081126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.2446675584
Short name T752
Test name
Test status
Simulation time 119611985256 ps
CPU time 282.23 seconds
Started Sep 18 02:38:37 PM UTC 24
Finished Sep 18 02:43:24 PM UTC 24
Peak memory 267712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446675584 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.2446675584
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.3705517550
Short name T586
Test name
Test status
Simulation time 3419245766 ps
CPU time 46.47 seconds
Started Sep 18 02:38:17 PM UTC 24
Finished Sep 18 02:39:05 PM UTC 24
Peak memory 231616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705517550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3705517550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1075384732
Short name T557
Test name
Test status
Simulation time 881685256 ps
CPU time 7.5 seconds
Started Sep 18 02:38:15 PM UTC 24
Finished Sep 18 02:38:23 PM UTC 24
Peak memory 227376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075384732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1075384732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.593333494
Short name T556
Test name
Test status
Simulation time 161495204 ps
CPU time 2.23 seconds
Started Sep 18 02:38:19 PM UTC 24
Finished Sep 18 02:38:23 PM UTC 24
Peak memory 227404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593333494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.593333494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1088865377
Short name T554
Test name
Test status
Simulation time 210528264 ps
CPU time 1.57 seconds
Started Sep 18 02:38:18 PM UTC 24
Finished Sep 18 02:38:21 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088865377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1088865377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.1756426901
Short name T572
Test name
Test status
Simulation time 6462111972 ps
CPU time 17.4 seconds
Started Sep 18 02:38:25 PM UTC 24
Finished Sep 18 02:38:44 PM UTC 24
Peak memory 234884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756426901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1756426901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3535924010
Short name T583
Test name
Test status
Simulation time 77636161 ps
CPU time 0.99 seconds
Started Sep 18 02:39:00 PM UTC 24
Finished Sep 18 02:39:02 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535924010 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3535924010
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.891176243
Short name T579
Test name
Test status
Simulation time 1148296857 ps
CPU time 3.71 seconds
Started Sep 18 02:38:53 PM UTC 24
Finished Sep 18 02:38:58 PM UTC 24
Peak memory 245004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891176243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.891176243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.570132124
Short name T569
Test name
Test status
Simulation time 76570376 ps
CPU time 1.12 seconds
Started Sep 18 02:38:40 PM UTC 24
Finished Sep 18 02:38:42 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570132124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.570132124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2098447843
Short name T685
Test name
Test status
Simulation time 22917007396 ps
CPU time 155.66 seconds
Started Sep 18 02:38:55 PM UTC 24
Finished Sep 18 02:41:33 PM UTC 24
Peak memory 261496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098447843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2098447843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.4232450108
Short name T624
Test name
Test status
Simulation time 3364574219 ps
CPU time 77.49 seconds
Started Sep 18 02:38:56 PM UTC 24
Finished Sep 18 02:40:15 PM UTC 24
Peak memory 261892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232450108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4232450108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.76936048
Short name T289
Test name
Test status
Simulation time 3569313558 ps
CPU time 20.88 seconds
Started Sep 18 02:38:57 PM UTC 24
Finished Sep 18 02:39:19 PM UTC 24
Peak memory 235272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76936048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.76936048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.3362821005
Short name T592
Test name
Test status
Simulation time 4194638678 ps
CPU time 27.88 seconds
Started Sep 18 02:38:53 PM UTC 24
Finished Sep 18 02:39:22 PM UTC 24
Peak memory 261696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362821005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3362821005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.1108856201
Short name T591
Test name
Test status
Simulation time 2344245651 ps
CPU time 25.91 seconds
Started Sep 18 02:38:53 PM UTC 24
Finished Sep 18 02:39:20 PM UTC 24
Peak memory 261704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108856201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.1108856201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2043722070
Short name T578
Test name
Test status
Simulation time 2651145894 ps
CPU time 7.71 seconds
Started Sep 18 02:38:47 PM UTC 24
Finished Sep 18 02:38:56 PM UTC 24
Peak memory 245320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043722070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2043722070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.335959536
Short name T588
Test name
Test status
Simulation time 3105452586 ps
CPU time 24 seconds
Started Sep 18 02:38:49 PM UTC 24
Finished Sep 18 02:39:14 PM UTC 24
Peak memory 247108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335959536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.335959536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2933255149
Short name T581
Test name
Test status
Simulation time 6143935212 ps
CPU time 13.31 seconds
Started Sep 18 02:38:46 PM UTC 24
Finished Sep 18 02:39:01 PM UTC 24
Peak memory 245376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933255149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.2933255149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.4140280763
Short name T576
Test name
Test status
Simulation time 1521244154 ps
CPU time 6.51 seconds
Started Sep 18 02:38:44 PM UTC 24
Finished Sep 18 02:38:52 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140280763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4140280763
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2746906133
Short name T582
Test name
Test status
Simulation time 220764850 ps
CPU time 5.46 seconds
Started Sep 18 02:38:54 PM UTC 24
Finished Sep 18 02:39:01 PM UTC 24
Peak memory 233380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746906133 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2746906133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.698017683
Short name T168
Test name
Test status
Simulation time 46900193437 ps
CPU time 113.13 seconds
Started Sep 18 02:38:59 PM UTC 24
Finished Sep 18 02:40:54 PM UTC 24
Peak memory 274124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698017683 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.698017683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.1907048123
Short name T596
Test name
Test status
Simulation time 1967271770 ps
CPU time 39.98 seconds
Started Sep 18 02:38:43 PM UTC 24
Finished Sep 18 02:39:24 PM UTC 24
Peak memory 227320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907048123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1907048123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.996664830
Short name T561
Test name
Test status
Simulation time 333944330 ps
CPU time 2.56 seconds
Started Sep 18 02:38:42 PM UTC 24
Finished Sep 18 02:38:45 PM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996664830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.996664830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.766493175
Short name T573
Test name
Test status
Simulation time 57730740 ps
CPU time 2.36 seconds
Started Sep 18 02:38:44 PM UTC 24
Finished Sep 18 02:38:47 PM UTC 24
Peak memory 227240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766493175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.766493175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2583902367
Short name T574
Test name
Test status
Simulation time 32042229 ps
CPU time 1.27 seconds
Started Sep 18 02:38:44 PM UTC 24
Finished Sep 18 02:38:46 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583902367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2583902367
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.2876105464
Short name T580
Test name
Test status
Simulation time 1672372036 ps
CPU time 7.73 seconds
Started Sep 18 02:38:52 PM UTC 24
Finished Sep 18 02:39:00 PM UTC 24
Peak memory 234844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876105464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2876105464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3432402831
Short name T598
Test name
Test status
Simulation time 15484363 ps
CPU time 1.15 seconds
Started Sep 18 02:39:26 PM UTC 24
Finished Sep 18 02:39:28 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432402831 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.3432402831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.2642646023
Short name T595
Test name
Test status
Simulation time 83831671 ps
CPU time 3.06 seconds
Started Sep 18 02:39:20 PM UTC 24
Finished Sep 18 02:39:24 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642646023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2642646023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.422085291
Short name T584
Test name
Test status
Simulation time 65110812 ps
CPU time 1.11 seconds
Started Sep 18 02:39:01 PM UTC 24
Finished Sep 18 02:39:04 PM UTC 24
Peak memory 215708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422085291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.422085291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.3819734427
Short name T614
Test name
Test status
Simulation time 4273591076 ps
CPU time 29.52 seconds
Started Sep 18 02:39:23 PM UTC 24
Finished Sep 18 02:39:54 PM UTC 24
Peak memory 261752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819734427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3819734427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.4093788327
Short name T696
Test name
Test status
Simulation time 5934964577 ps
CPU time 148.46 seconds
Started Sep 18 02:39:24 PM UTC 24
Finished Sep 18 02:41:55 PM UTC 24
Peak memory 278012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093788327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4093788327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.205576521
Short name T353
Test name
Test status
Simulation time 222179030266 ps
CPU time 525.77 seconds
Started Sep 18 02:39:24 PM UTC 24
Finished Sep 18 02:48:17 PM UTC 24
Peak memory 275916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205576521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.205576521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.2611548001
Short name T599
Test name
Test status
Simulation time 158078784 ps
CPU time 8.65 seconds
Started Sep 18 02:39:20 PM UTC 24
Finished Sep 18 02:39:29 PM UTC 24
Peak memory 246988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611548001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2611548001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3856758955
Short name T594
Test name
Test status
Simulation time 16116570 ps
CPU time 1.23 seconds
Started Sep 18 02:39:21 PM UTC 24
Finished Sep 18 02:39:23 PM UTC 24
Peak memory 226876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856758955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.3856758955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.1112427580
Short name T590
Test name
Test status
Simulation time 164014026 ps
CPU time 5.67 seconds
Started Sep 18 02:39:12 PM UTC 24
Finished Sep 18 02:39:19 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112427580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1112427580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.3088912699
Short name T607
Test name
Test status
Simulation time 5350112328 ps
CPU time 25.94 seconds
Started Sep 18 02:39:14 PM UTC 24
Finished Sep 18 02:39:42 PM UTC 24
Peak memory 234888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088912699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3088912699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1408368977
Short name T325
Test name
Test status
Simulation time 22788285377 ps
CPU time 32.12 seconds
Started Sep 18 02:39:06 PM UTC 24
Finished Sep 18 02:39:40 PM UTC 24
Peak memory 249168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408368977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.1408368977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.90141525
Short name T597
Test name
Test status
Simulation time 56793742365 ps
CPU time 19.34 seconds
Started Sep 18 02:39:06 PM UTC 24
Finished Sep 18 02:39:27 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90141525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.90141525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2830895022
Short name T601
Test name
Test status
Simulation time 288722866 ps
CPU time 8.4 seconds
Started Sep 18 02:39:23 PM UTC 24
Finished Sep 18 02:39:33 PM UTC 24
Peak memory 233676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830895022 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.2830895022
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.619323560
Short name T722
Test name
Test status
Simulation time 95719337301 ps
CPU time 187.55 seconds
Started Sep 18 02:39:26 PM UTC 24
Finished Sep 18 02:42:36 PM UTC 24
Peak memory 279956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619323560 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.619323560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1883067446
Short name T589
Test name
Test status
Simulation time 6179612517 ps
CPU time 12.99 seconds
Started Sep 18 02:39:02 PM UTC 24
Finished Sep 18 02:39:16 PM UTC 24
Peak memory 227508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883067446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1883067446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.646226659
Short name T593
Test name
Test status
Simulation time 7083490142 ps
CPU time 20.13 seconds
Started Sep 18 02:39:01 PM UTC 24
Finished Sep 18 02:39:23 PM UTC 24
Peak memory 227324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646226659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.646226659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1225104
Short name T587
Test name
Test status
Simulation time 893186202 ps
CPU time 5.52 seconds
Started Sep 18 02:39:05 PM UTC 24
Finished Sep 18 02:39:11 PM UTC 24
Peak memory 227588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_dev
ice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1225104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.4109744051
Short name T585
Test name
Test status
Simulation time 22322822 ps
CPU time 1.2 seconds
Started Sep 18 02:39:03 PM UTC 24
Finished Sep 18 02:39:05 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109744051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4109744051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.4041076311
Short name T604
Test name
Test status
Simulation time 2548707559 ps
CPU time 20.16 seconds
Started Sep 18 02:39:17 PM UTC 24
Finished Sep 18 02:39:38 PM UTC 24
Peak memory 245188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041076311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4041076311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.845740673
Short name T613
Test name
Test status
Simulation time 13824935 ps
CPU time 1.13 seconds
Started Sep 18 02:39:51 PM UTC 24
Finished Sep 18 02:39:53 PM UTC 24
Peak memory 213360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845740673 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.845740673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1512109146
Short name T609
Test name
Test status
Simulation time 61726882 ps
CPU time 3.37 seconds
Started Sep 18 02:39:41 PM UTC 24
Finished Sep 18 02:39:46 PM UTC 24
Peak memory 244888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512109146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1512109146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.2721108196
Short name T600
Test name
Test status
Simulation time 12034504 ps
CPU time 1.16 seconds
Started Sep 18 02:39:28 PM UTC 24
Finished Sep 18 02:39:31 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721108196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2721108196
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.321921891
Short name T644
Test name
Test status
Simulation time 4698224213 ps
CPU time 60.32 seconds
Started Sep 18 02:39:47 PM UTC 24
Finished Sep 18 02:40:49 PM UTC 24
Peak memory 261760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321921891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.321921891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2062872200
Short name T641
Test name
Test status
Simulation time 29983740805 ps
CPU time 56.82 seconds
Started Sep 18 02:39:47 PM UTC 24
Finished Sep 18 02:40:46 PM UTC 24
Peak memory 261440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062872200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2062872200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3700765472
Short name T322
Test name
Test status
Simulation time 16005068063 ps
CPU time 63.82 seconds
Started Sep 18 02:39:47 PM UTC 24
Finished Sep 18 02:40:53 PM UTC 24
Peak memory 261892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700765472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.3700765472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.3104816785
Short name T621
Test name
Test status
Simulation time 2737588856 ps
CPU time 26.02 seconds
Started Sep 18 02:39:43 PM UTC 24
Finished Sep 18 02:40:10 PM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104816785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3104816785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.50314674
Short name T308
Test name
Test status
Simulation time 43238770748 ps
CPU time 388.62 seconds
Started Sep 18 02:39:43 PM UTC 24
Finished Sep 18 02:46:17 PM UTC 24
Peak memory 265796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50314674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.50314674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.4110278270
Short name T606
Test name
Test status
Simulation time 115304138 ps
CPU time 2.52 seconds
Started Sep 18 02:39:38 PM UTC 24
Finished Sep 18 02:39:42 PM UTC 24
Peak memory 234724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110278270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4110278270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.3660304565
Short name T611
Test name
Test status
Simulation time 101830446 ps
CPU time 6.12 seconds
Started Sep 18 02:39:39 PM UTC 24
Finished Sep 18 02:39:46 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660304565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3660304565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3584247396
Short name T313
Test name
Test status
Simulation time 1759738783 ps
CPU time 9.22 seconds
Started Sep 18 02:39:36 PM UTC 24
Finished Sep 18 02:39:46 PM UTC 24
Peak memory 244884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584247396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.3584247396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1318700536
Short name T610
Test name
Test status
Simulation time 996022983 ps
CPU time 10.56 seconds
Started Sep 18 02:39:35 PM UTC 24
Finished Sep 18 02:39:46 PM UTC 24
Peak memory 244948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318700536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1318700536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1967425440
Short name T617
Test name
Test status
Simulation time 19977375196 ps
CPU time 17.49 seconds
Started Sep 18 02:39:45 PM UTC 24
Finished Sep 18 02:40:04 PM UTC 24
Peak memory 233460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967425440 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.1967425440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.3052611719
Short name T612
Test name
Test status
Simulation time 124952068 ps
CPU time 1.69 seconds
Started Sep 18 02:39:48 PM UTC 24
Finished Sep 18 02:39:50 PM UTC 24
Peak memory 217064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052611719 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.3052611719
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.2803137881
Short name T619
Test name
Test status
Simulation time 5750204758 ps
CPU time 33.34 seconds
Started Sep 18 02:39:30 PM UTC 24
Finished Sep 18 02:40:05 PM UTC 24
Peak memory 227832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803137881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2803137881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.1916371532
Short name T605
Test name
Test status
Simulation time 4945111129 ps
CPU time 9.59 seconds
Started Sep 18 02:39:29 PM UTC 24
Finished Sep 18 02:39:40 PM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916371532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1916371532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.4278348875
Short name T603
Test name
Test status
Simulation time 205592117 ps
CPU time 1.9 seconds
Started Sep 18 02:39:33 PM UTC 24
Finished Sep 18 02:39:37 PM UTC 24
Peak memory 217140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278348875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4278348875
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1038374536
Short name T602
Test name
Test status
Simulation time 319062573 ps
CPU time 1.18 seconds
Started Sep 18 02:39:31 PM UTC 24
Finished Sep 18 02:39:34 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038374536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1038374536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.1172154389
Short name T608
Test name
Test status
Simulation time 33794068 ps
CPU time 2.93 seconds
Started Sep 18 02:39:40 PM UTC 24
Finished Sep 18 02:39:44 PM UTC 24
Peak memory 234428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172154389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1172154389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.575516642
Short name T629
Test name
Test status
Simulation time 35534218 ps
CPU time 1.09 seconds
Started Sep 18 02:40:25 PM UTC 24
Finished Sep 18 02:40:27 PM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575516642 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.575516642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3943239672
Short name T628
Test name
Test status
Simulation time 11940962223 ps
CPU time 12.4 seconds
Started Sep 18 02:40:12 PM UTC 24
Finished Sep 18 02:40:25 PM UTC 24
Peak memory 245084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943239672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3943239672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.344543307
Short name T615
Test name
Test status
Simulation time 18643575 ps
CPU time 1.17 seconds
Started Sep 18 02:39:54 PM UTC 24
Finished Sep 18 02:39:56 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344543307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.344543307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.3427640969
Short name T625
Test name
Test status
Simulation time 119624850 ps
CPU time 1.36 seconds
Started Sep 18 02:40:16 PM UTC 24
Finished Sep 18 02:40:18 PM UTC 24
Peak memory 226868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427640969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3427640969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.3280176070
Short name T309
Test name
Test status
Simulation time 148468399167 ps
CPU time 375.3 seconds
Started Sep 18 02:40:19 PM UTC 24
Finished Sep 18 02:46:39 PM UTC 24
Peak memory 284100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280176070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3280176070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.377991520
Short name T651
Test name
Test status
Simulation time 4816594076 ps
CPU time 30.82 seconds
Started Sep 18 02:40:21 PM UTC 24
Finished Sep 18 02:40:53 PM UTC 24
Peak memory 229612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377991520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.377991520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.3754235077
Short name T626
Test name
Test status
Simulation time 178103521 ps
CPU time 7.92 seconds
Started Sep 18 02:40:12 PM UTC 24
Finished Sep 18 02:40:20 PM UTC 24
Peak memory 234628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754235077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3754235077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.1384186530
Short name T819
Test name
Test status
Simulation time 226934023870 ps
CPU time 276.08 seconds
Started Sep 18 02:40:12 PM UTC 24
Finished Sep 18 02:44:52 PM UTC 24
Peak memory 267648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384186530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.1384186530
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.577298075
Short name T635
Test name
Test status
Simulation time 6803873796 ps
CPU time 29.61 seconds
Started Sep 18 02:40:06 PM UTC 24
Finished Sep 18 02:40:37 PM UTC 24
Peak memory 245204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577298075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.577298075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.2726578098
Short name T638
Test name
Test status
Simulation time 8375532180 ps
CPU time 34.86 seconds
Started Sep 18 02:40:06 PM UTC 24
Finished Sep 18 02:40:42 PM UTC 24
Peak memory 245124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726578098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2726578098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2136570741
Short name T311
Test name
Test status
Simulation time 13192722550 ps
CPU time 37.87 seconds
Started Sep 18 02:40:05 PM UTC 24
Finished Sep 18 02:40:44 PM UTC 24
Peak memory 251408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136570741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.2136570741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.798129157
Short name T622
Test name
Test status
Simulation time 429757376 ps
CPU time 5.05 seconds
Started Sep 18 02:40:05 PM UTC 24
Finished Sep 18 02:40:11 PM UTC 24
Peak memory 244996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798129157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.798129157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3078743965
Short name T627
Test name
Test status
Simulation time 288831310 ps
CPU time 6.98 seconds
Started Sep 18 02:40:16 PM UTC 24
Finished Sep 18 02:40:24 PM UTC 24
Peak memory 231180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078743965 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.3078743965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3934220668
Short name T988
Test name
Test status
Simulation time 63892788747 ps
CPU time 557.28 seconds
Started Sep 18 02:40:23 PM UTC 24
Finished Sep 18 02:49:48 PM UTC 24
Peak memory 294592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934220668 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3934220668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.356957200
Short name T674
Test name
Test status
Simulation time 41634463114 ps
CPU time 82.58 seconds
Started Sep 18 02:39:56 PM UTC 24
Finished Sep 18 02:41:21 PM UTC 24
Peak memory 227468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356957200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.356957200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.1093508015
Short name T620
Test name
Test status
Simulation time 9569746810 ps
CPU time 13.27 seconds
Started Sep 18 02:39:55 PM UTC 24
Finished Sep 18 02:40:09 PM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093508015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1093508015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.3632173942
Short name T618
Test name
Test status
Simulation time 809291640 ps
CPU time 3.84 seconds
Started Sep 18 02:40:00 PM UTC 24
Finished Sep 18 02:40:05 PM UTC 24
Peak memory 227336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632173942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3632173942
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2520037449
Short name T616
Test name
Test status
Simulation time 70829317 ps
CPU time 1.46 seconds
Started Sep 18 02:39:57 PM UTC 24
Finished Sep 18 02:40:00 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520037449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2520037449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.3171676842
Short name T623
Test name
Test status
Simulation time 93005218 ps
CPU time 3.33 seconds
Started Sep 18 02:40:10 PM UTC 24
Finished Sep 18 02:40:15 PM UTC 24
Peak memory 244948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171676842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3171676842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3967731585
Short name T359
Test name
Test status
Simulation time 23709489 ps
CPU time 1.11 seconds
Started Sep 18 02:25:49 PM UTC 24
Finished Sep 18 02:25:52 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967731585 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3967731585
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2780364793
Short name T358
Test name
Test status
Simulation time 30293643 ps
CPU time 2.94 seconds
Started Sep 18 02:25:31 PM UTC 24
Finished Sep 18 02:25:35 PM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780364793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2780364793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.4173559082
Short name T356
Test name
Test status
Simulation time 18768185 ps
CPU time 1.2 seconds
Started Sep 18 02:25:18 PM UTC 24
Finished Sep 18 02:25:20 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173559082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4173559082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.4093634998
Short name T51
Test name
Test status
Simulation time 2315768597 ps
CPU time 69.42 seconds
Started Sep 18 02:25:42 PM UTC 24
Finished Sep 18 02:26:54 PM UTC 24
Peak memory 261948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093634998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4093634998
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.163761749
Short name T64
Test name
Test status
Simulation time 29200579121 ps
CPU time 154.05 seconds
Started Sep 18 02:25:43 PM UTC 24
Finished Sep 18 02:28:20 PM UTC 24
Peak memory 263812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163761749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.163761749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.690497994
Short name T52
Test name
Test status
Simulation time 53164012 ps
CPU time 5.59 seconds
Started Sep 18 02:25:36 PM UTC 24
Finished Sep 18 02:25:43 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690497994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.690497994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.579708247
Short name T62
Test name
Test status
Simulation time 3656143279 ps
CPU time 59.82 seconds
Started Sep 18 02:25:36 PM UTC 24
Finished Sep 18 02:26:37 PM UTC 24
Peak memory 261712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579708247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.579708247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.375596720
Short name T57
Test name
Test status
Simulation time 114611488 ps
CPU time 6.06 seconds
Started Sep 18 02:25:27 PM UTC 24
Finished Sep 18 02:25:35 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375596720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.375596720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.2672579823
Short name T123
Test name
Test status
Simulation time 245627756 ps
CPU time 7.26 seconds
Started Sep 18 02:25:28 PM UTC 24
Finished Sep 18 02:25:37 PM UTC 24
Peak memory 245016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672579823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2672579823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3909914131
Short name T61
Test name
Test status
Simulation time 3397424721 ps
CPU time 12.55 seconds
Started Sep 18 02:25:27 PM UTC 24
Finished Sep 18 02:25:41 PM UTC 24
Peak memory 245128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909914131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.3909914131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.4198937207
Short name T154
Test name
Test status
Simulation time 381489073 ps
CPU time 6.05 seconds
Started Sep 18 02:25:36 PM UTC 24
Finished Sep 18 02:25:43 PM UTC 24
Peak memory 233944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198937207 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.4198937207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.3112831832
Short name T22
Test name
Test status
Simulation time 54857241 ps
CPU time 1.51 seconds
Started Sep 18 02:25:46 PM UTC 24
Finished Sep 18 02:25:49 PM UTC 24
Peak memory 256996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112831832 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3112831832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.203279120
Short name T165
Test name
Test status
Simulation time 64172817137 ps
CPU time 591.58 seconds
Started Sep 18 02:25:44 PM UTC 24
Finished Sep 18 02:35:43 PM UTC 24
Peak memory 280012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203279120 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.203279120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2996218068
Short name T65
Test name
Test status
Simulation time 14555440103 ps
CPU time 21.82 seconds
Started Sep 18 02:25:22 PM UTC 24
Finished Sep 18 02:25:46 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996218068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2996218068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2282847512
Short name T93
Test name
Test status
Simulation time 1517919154 ps
CPU time 6.24 seconds
Started Sep 18 02:25:20 PM UTC 24
Finished Sep 18 02:25:28 PM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282847512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2282847512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3146441053
Short name T357
Test name
Test status
Simulation time 12098882 ps
CPU time 1.08 seconds
Started Sep 18 02:25:24 PM UTC 24
Finished Sep 18 02:25:27 PM UTC 24
Peak memory 216016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146441053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3146441053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1289256529
Short name T92
Test name
Test status
Simulation time 355021819 ps
CPU time 1.4 seconds
Started Sep 18 02:25:22 PM UTC 24
Finished Sep 18 02:25:25 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289256529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1289256529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.3527827202
Short name T100
Test name
Test status
Simulation time 32356934982 ps
CPU time 17.29 seconds
Started Sep 18 02:25:30 PM UTC 24
Finished Sep 18 02:25:48 PM UTC 24
Peak memory 245060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527827202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3527827202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.453885625
Short name T645
Test name
Test status
Simulation time 11301542 ps
CPU time 1.11 seconds
Started Sep 18 02:40:49 PM UTC 24
Finished Sep 18 02:40:51 PM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453885625 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.453885625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.4271245298
Short name T640
Test name
Test status
Simulation time 102159984 ps
CPU time 4.08 seconds
Started Sep 18 02:40:40 PM UTC 24
Finished Sep 18 02:40:45 PM UTC 24
Peak memory 234720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271245298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4271245298
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.2285069859
Short name T630
Test name
Test status
Simulation time 39801923 ps
CPU time 1.1 seconds
Started Sep 18 02:40:26 PM UTC 24
Finished Sep 18 02:40:28 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285069859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2285069859
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.1031212628
Short name T659
Test name
Test status
Simulation time 11017619074 ps
CPU time 18.53 seconds
Started Sep 18 02:40:45 PM UTC 24
Finished Sep 18 02:41:04 PM UTC 24
Peak memory 247412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031212628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1031212628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2479192660
Short name T324
Test name
Test status
Simulation time 41984004219 ps
CPU time 107.61 seconds
Started Sep 18 02:40:46 PM UTC 24
Finished Sep 18 02:42:36 PM UTC 24
Peak memory 263500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479192660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2479192660
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2735831649
Short name T923
Test name
Test status
Simulation time 76123946089 ps
CPU time 375.25 seconds
Started Sep 18 02:40:46 PM UTC 24
Finished Sep 18 02:47:06 PM UTC 24
Peak memory 267724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735831649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.2735831649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3270396391
Short name T676
Test name
Test status
Simulation time 1904071864 ps
CPU time 40.02 seconds
Started Sep 18 02:40:43 PM UTC 24
Finished Sep 18 02:41:25 PM UTC 24
Peak memory 261572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270396391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.3270396391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.727552371
Short name T656
Test name
Test status
Simulation time 3241760858 ps
CPU time 22.62 seconds
Started Sep 18 02:40:37 PM UTC 24
Finished Sep 18 02:41:00 PM UTC 24
Peak memory 245068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727552371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.727552371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.3227558727
Short name T660
Test name
Test status
Simulation time 11781040546 ps
CPU time 25.52 seconds
Started Sep 18 02:40:38 PM UTC 24
Finished Sep 18 02:41:05 PM UTC 24
Peak memory 245276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227558727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3227558727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3957042177
Short name T643
Test name
Test status
Simulation time 1660367830 ps
CPU time 10.77 seconds
Started Sep 18 02:40:37 PM UTC 24
Finished Sep 18 02:40:48 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957042177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.3957042177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3695639292
Short name T636
Test name
Test status
Simulation time 248834376 ps
CPU time 4.53 seconds
Started Sep 18 02:40:33 PM UTC 24
Finished Sep 18 02:40:39 PM UTC 24
Peak memory 245272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695639292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3695639292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.3440903266
Short name T655
Test name
Test status
Simulation time 7816164263 ps
CPU time 14.24 seconds
Started Sep 18 02:40:45 PM UTC 24
Finished Sep 18 02:41:00 PM UTC 24
Peak memory 233488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440903266 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.3440903266
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.189990873
Short name T169
Test name
Test status
Simulation time 949012038 ps
CPU time 15.94 seconds
Started Sep 18 02:40:47 PM UTC 24
Finished Sep 18 02:41:04 PM UTC 24
Peak memory 234756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189990873 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.189990873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.2915139407
Short name T637
Test name
Test status
Simulation time 1240037030 ps
CPU time 10.44 seconds
Started Sep 18 02:40:29 PM UTC 24
Finished Sep 18 02:40:40 PM UTC 24
Peak memory 227448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915139407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2915139407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3083464518
Short name T670
Test name
Test status
Simulation time 19166186904 ps
CPU time 47.91 seconds
Started Sep 18 02:40:28 PM UTC 24
Finished Sep 18 02:41:17 PM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083464518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3083464518
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.1003056558
Short name T634
Test name
Test status
Simulation time 76443689 ps
CPU time 1.66 seconds
Started Sep 18 02:40:33 PM UTC 24
Finished Sep 18 02:40:36 PM UTC 24
Peak memory 227124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003056558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1003056558
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.951986261
Short name T631
Test name
Test status
Simulation time 39569197 ps
CPU time 1.24 seconds
Started Sep 18 02:40:30 PM UTC 24
Finished Sep 18 02:40:32 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951986261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.951986261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.1741812557
Short name T642
Test name
Test status
Simulation time 1556522786 ps
CPU time 8.07 seconds
Started Sep 18 02:40:38 PM UTC 24
Finished Sep 18 02:40:47 PM UTC 24
Peak memory 234704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741812557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1741812557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.1311541249
Short name T662
Test name
Test status
Simulation time 44018694 ps
CPU time 1.12 seconds
Started Sep 18 02:41:05 PM UTC 24
Finished Sep 18 02:41:08 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311541249 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.1311541249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.270799474
Short name T657
Test name
Test status
Simulation time 132461927 ps
CPU time 6.77 seconds
Started Sep 18 02:40:56 PM UTC 24
Finished Sep 18 02:41:04 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270799474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.270799474
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.1304131157
Short name T646
Test name
Test status
Simulation time 47206622 ps
CPU time 1.18 seconds
Started Sep 18 02:40:49 PM UTC 24
Finished Sep 18 02:40:51 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304131157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1304131157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.2681646694
Short name T687
Test name
Test status
Simulation time 5494533003 ps
CPU time 31.01 seconds
Started Sep 18 02:41:02 PM UTC 24
Finished Sep 18 02:41:34 PM UTC 24
Peak memory 251200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681646694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2681646694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1627643745
Short name T724
Test name
Test status
Simulation time 4334401565 ps
CPU time 93.77 seconds
Started Sep 18 02:41:05 PM UTC 24
Finished Sep 18 02:42:41 PM UTC 24
Peak memory 267712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627643745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1627643745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2052513108
Short name T216
Test name
Test status
Simulation time 16989414205 ps
CPU time 146.14 seconds
Started Sep 18 02:41:05 PM UTC 24
Finished Sep 18 02:43:34 PM UTC 24
Peak memory 277956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052513108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.2052513108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.4242294547
Short name T680
Test name
Test status
Simulation time 1469699571 ps
CPU time 30.02 seconds
Started Sep 18 02:40:57 PM UTC 24
Finished Sep 18 02:41:29 PM UTC 24
Peak memory 245212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242294547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4242294547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.1622110888
Short name T730
Test name
Test status
Simulation time 19860676287 ps
CPU time 107.77 seconds
Started Sep 18 02:40:59 PM UTC 24
Finished Sep 18 02:42:49 PM UTC 24
Peak memory 263492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622110888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.1622110888
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.851941928
Short name T654
Test name
Test status
Simulation time 207695158 ps
CPU time 2.92 seconds
Started Sep 18 02:40:55 PM UTC 24
Finished Sep 18 02:40:59 PM UTC 24
Peak memory 233600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851941928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.851941928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.352930291
Short name T706
Test name
Test status
Simulation time 9521913804 ps
CPU time 82.26 seconds
Started Sep 18 02:40:55 PM UTC 24
Finished Sep 18 02:42:19 PM UTC 24
Peak memory 244864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352930291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.352930291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.604233118
Short name T658
Test name
Test status
Simulation time 4360264822 ps
CPU time 9.66 seconds
Started Sep 18 02:40:53 PM UTC 24
Finished Sep 18 02:41:04 PM UTC 24
Peak memory 245128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604233118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.604233118
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.4037866713
Short name T652
Test name
Test status
Simulation time 650753030 ps
CPU time 3.13 seconds
Started Sep 18 02:40:51 PM UTC 24
Finished Sep 18 02:40:55 PM UTC 24
Peak memory 234900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037866713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4037866713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1876643724
Short name T665
Test name
Test status
Simulation time 923760024 ps
CPU time 9.64 seconds
Started Sep 18 02:41:01 PM UTC 24
Finished Sep 18 02:41:11 PM UTC 24
Peak memory 233332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876643724 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.1876643724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.3066611347
Short name T1006
Test name
Test status
Simulation time 585028084595 ps
CPU time 851.61 seconds
Started Sep 18 02:41:05 PM UTC 24
Finished Sep 18 02:55:27 PM UTC 24
Peak memory 300540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066611347 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.3066611347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.2548233233
Short name T661
Test name
Test status
Simulation time 1122546440 ps
CPU time 14.17 seconds
Started Sep 18 02:40:51 PM UTC 24
Finished Sep 18 02:41:07 PM UTC 24
Peak memory 227344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548233233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2548233233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.4177853369
Short name T668
Test name
Test status
Simulation time 13655645186 ps
CPU time 23.26 seconds
Started Sep 18 02:40:50 PM UTC 24
Finished Sep 18 02:41:14 PM UTC 24
Peak memory 227464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177853369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4177853369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.1946197579
Short name T653
Test name
Test status
Simulation time 207710916 ps
CPU time 4.03 seconds
Started Sep 18 02:40:51 PM UTC 24
Finished Sep 18 02:40:56 PM UTC 24
Peak memory 227640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946197579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1946197579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.804759880
Short name T650
Test name
Test status
Simulation time 34677600 ps
CPU time 1.17 seconds
Started Sep 18 02:40:51 PM UTC 24
Finished Sep 18 02:40:53 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804759880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.804759880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.3861602648
Short name T664
Test name
Test status
Simulation time 7672570155 ps
CPU time 14.44 seconds
Started Sep 18 02:40:55 PM UTC 24
Finished Sep 18 02:41:10 PM UTC 24
Peak memory 245328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861602648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3861602648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.3025314998
Short name T681
Test name
Test status
Simulation time 11765494 ps
CPU time 1.1 seconds
Started Sep 18 02:41:27 PM UTC 24
Finished Sep 18 02:41:29 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025314998 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.3025314998
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.4000973918
Short name T678
Test name
Test status
Simulation time 1307883520 ps
CPU time 8.31 seconds
Started Sep 18 02:41:18 PM UTC 24
Finished Sep 18 02:41:27 PM UTC 24
Peak memory 234976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000973918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4000973918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.1428837922
Short name T663
Test name
Test status
Simulation time 36189230 ps
CPU time 1.26 seconds
Started Sep 18 02:41:06 PM UTC 24
Finished Sep 18 02:41:09 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428837922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1428837922
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.1387009016
Short name T883
Test name
Test status
Simulation time 389502192554 ps
CPU time 287.53 seconds
Started Sep 18 02:41:22 PM UTC 24
Finished Sep 18 02:46:13 PM UTC 24
Peak memory 265792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387009016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1387009016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.855937163
Short name T764
Test name
Test status
Simulation time 49223072065 ps
CPU time 131.74 seconds
Started Sep 18 02:41:22 PM UTC 24
Finished Sep 18 02:43:36 PM UTC 24
Peak memory 251580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855937163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.855937163
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1615162744
Short name T878
Test name
Test status
Simulation time 107641642236 ps
CPU time 279.84 seconds
Started Sep 18 02:41:26 PM UTC 24
Finished Sep 18 02:46:10 PM UTC 24
Peak memory 267720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615162744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1615162744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.1298093666
Short name T679
Test name
Test status
Simulation time 188908270 ps
CPU time 6.39 seconds
Started Sep 18 02:41:20 PM UTC 24
Finished Sep 18 02:41:28 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298093666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1298093666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1766699226
Short name T963
Test name
Test status
Simulation time 179861133525 ps
CPU time 383.46 seconds
Started Sep 18 02:41:20 PM UTC 24
Finished Sep 18 02:47:49 PM UTC 24
Peak memory 267844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766699226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.1766699226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.3868434584
Short name T671
Test name
Test status
Simulation time 1216652775 ps
CPU time 3.33 seconds
Started Sep 18 02:41:14 PM UTC 24
Finished Sep 18 02:41:19 PM UTC 24
Peak memory 234576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868434584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3868434584
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.3984197886
Short name T714
Test name
Test status
Simulation time 60212849105 ps
CPU time 68.65 seconds
Started Sep 18 02:41:16 PM UTC 24
Finished Sep 18 02:42:26 PM UTC 24
Peak memory 245124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984197886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3984197886
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.2213784138
Short name T672
Test name
Test status
Simulation time 614619286 ps
CPU time 4.72 seconds
Started Sep 18 02:41:13 PM UTC 24
Finished Sep 18 02:41:19 PM UTC 24
Peak memory 244992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213784138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.2213784138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2805586862
Short name T673
Test name
Test status
Simulation time 1309721987 ps
CPU time 6.03 seconds
Started Sep 18 02:41:12 PM UTC 24
Finished Sep 18 02:41:19 PM UTC 24
Peak memory 234916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805586862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2805586862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3906550669
Short name T686
Test name
Test status
Simulation time 1617909193 ps
CPU time 11.5 seconds
Started Sep 18 02:41:20 PM UTC 24
Finished Sep 18 02:41:33 PM UTC 24
Peak memory 233668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906550669 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.3906550669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.1335470967
Short name T170
Test name
Test status
Simulation time 3225350189 ps
CPU time 37.37 seconds
Started Sep 18 02:41:27 PM UTC 24
Finished Sep 18 02:42:06 PM UTC 24
Peak memory 251048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335470967 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.1335470967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.3297882423
Short name T675
Test name
Test status
Simulation time 5418923900 ps
CPU time 10.7 seconds
Started Sep 18 02:41:09 PM UTC 24
Finished Sep 18 02:41:21 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297882423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3297882423
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3471021250
Short name T669
Test name
Test status
Simulation time 7695385596 ps
CPU time 6.08 seconds
Started Sep 18 02:41:08 PM UTC 24
Finished Sep 18 02:41:15 PM UTC 24
Peak memory 227724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471021250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3471021250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.697218821
Short name T667
Test name
Test status
Simulation time 70231409 ps
CPU time 1.62 seconds
Started Sep 18 02:41:11 PM UTC 24
Finished Sep 18 02:41:14 PM UTC 24
Peak memory 217164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697218821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.697218821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.3838282961
Short name T666
Test name
Test status
Simulation time 37440376 ps
CPU time 1.39 seconds
Started Sep 18 02:41:10 PM UTC 24
Finished Sep 18 02:41:12 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838282961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3838282961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.463031914
Short name T239
Test name
Test status
Simulation time 505235995 ps
CPU time 12.2 seconds
Started Sep 18 02:41:16 PM UTC 24
Finished Sep 18 02:41:29 PM UTC 24
Peak memory 245200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463031914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.463031914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.2670332324
Short name T694
Test name
Test status
Simulation time 17019613 ps
CPU time 1.06 seconds
Started Sep 18 02:41:50 PM UTC 24
Finished Sep 18 02:41:52 PM UTC 24
Peak memory 213776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670332324 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.2670332324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3682276816
Short name T688
Test name
Test status
Simulation time 125792493 ps
CPU time 3.28 seconds
Started Sep 18 02:41:35 PM UTC 24
Finished Sep 18 02:41:39 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682276816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3682276816
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.583194496
Short name T682
Test name
Test status
Simulation time 14935570 ps
CPU time 1.16 seconds
Started Sep 18 02:41:28 PM UTC 24
Finished Sep 18 02:41:30 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583194496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.583194496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.4136877950
Short name T809
Test name
Test status
Simulation time 64869821931 ps
CPU time 178.87 seconds
Started Sep 18 02:41:41 PM UTC 24
Finished Sep 18 02:44:43 PM UTC 24
Peak memory 277956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136877950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4136877950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1249114335
Short name T307
Test name
Test status
Simulation time 8958265130 ps
CPU time 130 seconds
Started Sep 18 02:41:41 PM UTC 24
Finished Sep 18 02:43:54 PM UTC 24
Peak memory 261576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249114335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1249114335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3093283857
Short name T755
Test name
Test status
Simulation time 48076278172 ps
CPU time 101.6 seconds
Started Sep 18 02:41:44 PM UTC 24
Finished Sep 18 02:43:27 PM UTC 24
Peak memory 267972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093283857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.3093283857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.4245416942
Short name T691
Test name
Test status
Simulation time 210386267 ps
CPU time 5.77 seconds
Started Sep 18 02:41:36 PM UTC 24
Finished Sep 18 02:41:43 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245416942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4245416942
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.3548780639
Short name T284
Test name
Test status
Simulation time 10246784104 ps
CPU time 93.92 seconds
Started Sep 18 02:41:40 PM UTC 24
Finished Sep 18 02:43:16 PM UTC 24
Peak memory 265540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548780639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.3548780639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.37448143
Short name T693
Test name
Test status
Simulation time 2796105682 ps
CPU time 15.83 seconds
Started Sep 18 02:41:33 PM UTC 24
Finished Sep 18 02:41:50 PM UTC 24
Peak memory 234772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37448143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.37448143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.535013163
Short name T697
Test name
Test status
Simulation time 5971993020 ps
CPU time 22.26 seconds
Started Sep 18 02:41:34 PM UTC 24
Finished Sep 18 02:41:57 PM UTC 24
Peak memory 234780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535013163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.535013163
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.3074619547
Short name T290
Test name
Test status
Simulation time 30370513857 ps
CPU time 9.74 seconds
Started Sep 18 02:41:33 PM UTC 24
Finished Sep 18 02:41:44 PM UTC 24
Peak memory 234768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074619547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.3074619547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3547005652
Short name T690
Test name
Test status
Simulation time 1620149815 ps
CPU time 8.33 seconds
Started Sep 18 02:41:31 PM UTC 24
Finished Sep 18 02:41:40 PM UTC 24
Peak memory 235008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547005652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3547005652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.595191269
Short name T692
Test name
Test status
Simulation time 1031358407 ps
CPU time 7.91 seconds
Started Sep 18 02:41:40 PM UTC 24
Finished Sep 18 02:41:49 PM UTC 24
Peak memory 231232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595191269 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.595191269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.635099757
Short name T782
Test name
Test status
Simulation time 7657193371 ps
CPU time 130.45 seconds
Started Sep 18 02:41:45 PM UTC 24
Finished Sep 18 02:43:58 PM UTC 24
Peak memory 251660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635099757 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.635099757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.2936013055
Short name T707
Test name
Test status
Simulation time 11027016901 ps
CPU time 48.23 seconds
Started Sep 18 02:41:30 PM UTC 24
Finished Sep 18 02:42:19 PM UTC 24
Peak memory 227728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936013055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2936013055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.3253722177
Short name T689
Test name
Test status
Simulation time 13254029703 ps
CPU time 8.59 seconds
Started Sep 18 02:41:30 PM UTC 24
Finished Sep 18 02:41:39 PM UTC 24
Peak memory 229836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253722177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3253722177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.3634065714
Short name T683
Test name
Test status
Simulation time 32567482 ps
CPU time 1.34 seconds
Started Sep 18 02:41:30 PM UTC 24
Finished Sep 18 02:41:32 PM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634065714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3634065714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.4030074938
Short name T684
Test name
Test status
Simulation time 237916353 ps
CPU time 1.58 seconds
Started Sep 18 02:41:30 PM UTC 24
Finished Sep 18 02:41:32 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030074938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4030074938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.148405808
Short name T649
Test name
Test status
Simulation time 22936794926 ps
CPU time 32.51 seconds
Started Sep 18 02:41:35 PM UTC 24
Finished Sep 18 02:42:09 PM UTC 24
Peak memory 251260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148405808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.148405808
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.2075317024
Short name T710
Test name
Test status
Simulation time 28202306 ps
CPU time 1.1 seconds
Started Sep 18 02:42:20 PM UTC 24
Finished Sep 18 02:42:22 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075317024 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2075317024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.4209683710
Short name T703
Test name
Test status
Simulation time 332786265 ps
CPU time 3.4 seconds
Started Sep 18 02:42:09 PM UTC 24
Finished Sep 18 02:42:13 PM UTC 24
Peak memory 234624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209683710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4209683710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.3001261097
Short name T695
Test name
Test status
Simulation time 43921509 ps
CPU time 1.11 seconds
Started Sep 18 02:41:51 PM UTC 24
Finished Sep 18 02:41:53 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001261097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3001261097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.2214391686
Short name T875
Test name
Test status
Simulation time 92465046482 ps
CPU time 225.91 seconds
Started Sep 18 02:42:14 PM UTC 24
Finished Sep 18 02:46:04 PM UTC 24
Peak memory 283960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214391686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2214391686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.194639054
Short name T316
Test name
Test status
Simulation time 4418883664 ps
CPU time 100.91 seconds
Started Sep 18 02:42:14 PM UTC 24
Finished Sep 18 02:43:58 PM UTC 24
Peak memory 263612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194639054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.194639054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3571217801
Short name T1008
Test name
Test status
Simulation time 143517953256 ps
CPU time 863.32 seconds
Started Sep 18 02:42:19 PM UTC 24
Finished Sep 18 02:56:53 PM UTC 24
Peak memory 280004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571217801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.3571217801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.151091221
Short name T709
Test name
Test status
Simulation time 208688961 ps
CPU time 11.07 seconds
Started Sep 18 02:42:10 PM UTC 24
Finished Sep 18 02:42:22 PM UTC 24
Peak memory 263692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151091221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.151091221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2609634172
Short name T319
Test name
Test status
Simulation time 33247646097 ps
CPU time 328.09 seconds
Started Sep 18 02:42:10 PM UTC 24
Finished Sep 18 02:47:43 PM UTC 24
Peak memory 263812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609634172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.2609634172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.3673647544
Short name T702
Test name
Test status
Simulation time 1576768104 ps
CPU time 7.37 seconds
Started Sep 18 02:42:04 PM UTC 24
Finished Sep 18 02:42:13 PM UTC 24
Peak memory 234636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673647544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3673647544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.4196128447
Short name T648
Test name
Test status
Simulation time 113196899 ps
CPU time 2.92 seconds
Started Sep 18 02:42:04 PM UTC 24
Finished Sep 18 02:42:08 PM UTC 24
Peak memory 244632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196128447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4196128447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.196649093
Short name T718
Test name
Test status
Simulation time 11256990697 ps
CPU time 26.19 seconds
Started Sep 18 02:42:03 PM UTC 24
Finished Sep 18 02:42:30 PM UTC 24
Peak memory 251224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196649093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.196649093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.4078151342
Short name T705
Test name
Test status
Simulation time 1905849041 ps
CPU time 16.35 seconds
Started Sep 18 02:42:00 PM UTC 24
Finished Sep 18 02:42:17 PM UTC 24
Peak memory 261332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078151342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4078151342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.549607413
Short name T716
Test name
Test status
Simulation time 3851990902 ps
CPU time 13.08 seconds
Started Sep 18 02:42:13 PM UTC 24
Finished Sep 18 02:42:27 PM UTC 24
Peak memory 231360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549607413 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.549607413
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.1422778482
Short name T712
Test name
Test status
Simulation time 97790198 ps
CPU time 1.63 seconds
Started Sep 18 02:42:20 PM UTC 24
Finished Sep 18 02:42:23 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422778482 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.1422778482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.1230480337
Short name T701
Test name
Test status
Simulation time 5705467754 ps
CPU time 10.5 seconds
Started Sep 18 02:41:55 PM UTC 24
Finished Sep 18 02:42:08 PM UTC 24
Peak memory 227536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230480337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1230480337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.4084997756
Short name T700
Test name
Test status
Simulation time 6123592617 ps
CPU time 9.42 seconds
Started Sep 18 02:41:53 PM UTC 24
Finished Sep 18 02:42:04 PM UTC 24
Peak memory 227532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084997756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4084997756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.4053332418
Short name T699
Test name
Test status
Simulation time 222455869 ps
CPU time 3.65 seconds
Started Sep 18 02:41:58 PM UTC 24
Finished Sep 18 02:42:02 PM UTC 24
Peak memory 227456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053332418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4053332418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.3159782675
Short name T698
Test name
Test status
Simulation time 38907422 ps
CPU time 1.06 seconds
Started Sep 18 02:41:57 PM UTC 24
Finished Sep 18 02:42:00 PM UTC 24
Peak memory 216016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159782675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3159782675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.1908973545
Short name T708
Test name
Test status
Simulation time 986868404 ps
CPU time 11.79 seconds
Started Sep 18 02:42:07 PM UTC 24
Finished Sep 18 02:42:19 PM UTC 24
Peak memory 261332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908973545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1908973545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.1325675794
Short name T728
Test name
Test status
Simulation time 20486260 ps
CPU time 1.1 seconds
Started Sep 18 02:42:44 PM UTC 24
Finished Sep 18 02:42:46 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325675794 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.1325675794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1065484671
Short name T721
Test name
Test status
Simulation time 63593483 ps
CPU time 2.97 seconds
Started Sep 18 02:42:32 PM UTC 24
Finished Sep 18 02:42:36 PM UTC 24
Peak memory 234760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065484671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1065484671
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.4087921471
Short name T711
Test name
Test status
Simulation time 54546143 ps
CPU time 1.12 seconds
Started Sep 18 02:42:20 PM UTC 24
Finished Sep 18 02:42:22 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087921471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4087921471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2113376963
Short name T797
Test name
Test status
Simulation time 68962998253 ps
CPU time 103.33 seconds
Started Sep 18 02:42:37 PM UTC 24
Finished Sep 18 02:44:23 PM UTC 24
Peak memory 267832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113376963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2113376963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1824337355
Short name T226
Test name
Test status
Simulation time 5010152266 ps
CPU time 74.93 seconds
Started Sep 18 02:42:37 PM UTC 24
Finished Sep 18 02:43:54 PM UTC 24
Peak memory 261632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824337355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1824337355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.3149828186
Short name T787
Test name
Test status
Simulation time 38026995588 ps
CPU time 89.63 seconds
Started Sep 18 02:42:37 PM UTC 24
Finished Sep 18 02:44:09 PM UTC 24
Peak memory 263880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149828186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.3149828186
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.1234161865
Short name T732
Test name
Test status
Simulation time 2982739738 ps
CPU time 14.64 seconds
Started Sep 18 02:42:35 PM UTC 24
Finished Sep 18 02:42:51 PM UTC 24
Peak memory 245336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234161865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1234161865
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3984386187
Short name T738
Test name
Test status
Simulation time 5887291027 ps
CPU time 26.42 seconds
Started Sep 18 02:42:37 PM UTC 24
Finished Sep 18 02:43:05 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984386187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.3984386187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3594902699
Short name T720
Test name
Test status
Simulation time 4791953239 ps
CPU time 7.55 seconds
Started Sep 18 02:42:27 PM UTC 24
Finished Sep 18 02:42:36 PM UTC 24
Peak memory 245124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594902699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3594902699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.1431729543
Short name T733
Test name
Test status
Simulation time 2030756358 ps
CPU time 21.01 seconds
Started Sep 18 02:42:28 PM UTC 24
Finished Sep 18 02:42:51 PM UTC 24
Peak memory 249040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431729543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1431729543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.565752802
Short name T719
Test name
Test status
Simulation time 1359922241 ps
CPU time 5.98 seconds
Started Sep 18 02:42:27 PM UTC 24
Finished Sep 18 02:42:34 PM UTC 24
Peak memory 251232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565752802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.565752802
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3318206605
Short name T723
Test name
Test status
Simulation time 4317562210 ps
CPU time 8.07 seconds
Started Sep 18 02:42:27 PM UTC 24
Finished Sep 18 02:42:36 PM UTC 24
Peak memory 234600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318206605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3318206605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1683056280
Short name T726
Test name
Test status
Simulation time 399204339 ps
CPU time 5.72 seconds
Started Sep 18 02:42:37 PM UTC 24
Finished Sep 18 02:42:44 PM UTC 24
Peak memory 229196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683056280 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.1683056280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.3488008982
Short name T997
Test name
Test status
Simulation time 36499729889 ps
CPU time 513.51 seconds
Started Sep 18 02:42:42 PM UTC 24
Finished Sep 18 02:51:22 PM UTC 24
Peak memory 277952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488008982 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.3488008982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.1072631437
Short name T736
Test name
Test status
Simulation time 5209875309 ps
CPU time 34.77 seconds
Started Sep 18 02:42:24 PM UTC 24
Finished Sep 18 02:43:00 PM UTC 24
Peak memory 227424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072631437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1072631437
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.497793342
Short name T713
Test name
Test status
Simulation time 17403366 ps
CPU time 1.1 seconds
Started Sep 18 02:42:24 PM UTC 24
Finished Sep 18 02:42:26 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497793342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.497793342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.1435662122
Short name T717
Test name
Test status
Simulation time 29308568 ps
CPU time 2.27 seconds
Started Sep 18 02:42:24 PM UTC 24
Finished Sep 18 02:42:27 PM UTC 24
Peak memory 217420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435662122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1435662122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3399629147
Short name T715
Test name
Test status
Simulation time 27387912 ps
CPU time 1.26 seconds
Started Sep 18 02:42:24 PM UTC 24
Finished Sep 18 02:42:26 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399629147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3399629147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.2779547305
Short name T725
Test name
Test status
Simulation time 8726595196 ps
CPU time 12.84 seconds
Started Sep 18 02:42:28 PM UTC 24
Finished Sep 18 02:42:43 PM UTC 24
Peak memory 251476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779547305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2779547305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.3637763521
Short name T742
Test name
Test status
Simulation time 13981661 ps
CPU time 1.15 seconds
Started Sep 18 02:43:10 PM UTC 24
Finished Sep 18 02:43:12 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637763521 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.3637763521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1694888362
Short name T741
Test name
Test status
Simulation time 419809256 ps
CPU time 10.25 seconds
Started Sep 18 02:42:58 PM UTC 24
Finished Sep 18 02:43:09 PM UTC 24
Peak memory 234756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694888362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1694888362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.1023173978
Short name T727
Test name
Test status
Simulation time 39382438 ps
CPU time 1.13 seconds
Started Sep 18 02:42:44 PM UTC 24
Finished Sep 18 02:42:46 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023173978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1023173978
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2817432197
Short name T321
Test name
Test status
Simulation time 3955320091 ps
CPU time 107.43 seconds
Started Sep 18 02:43:06 PM UTC 24
Finished Sep 18 02:44:56 PM UTC 24
Peak memory 267572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817432197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2817432197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.837877530
Short name T977
Test name
Test status
Simulation time 29493200619 ps
CPU time 307.27 seconds
Started Sep 18 02:43:06 PM UTC 24
Finished Sep 18 02:48:18 PM UTC 24
Peak memory 265660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837877530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.837877530
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4130523514
Short name T974
Test name
Test status
Simulation time 22996030430 ps
CPU time 297.89 seconds
Started Sep 18 02:43:06 PM UTC 24
Finished Sep 18 02:48:09 PM UTC 24
Peak memory 261640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130523514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.4130523514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.639713704
Short name T739
Test name
Test status
Simulation time 969826710 ps
CPU time 6.5 seconds
Started Sep 18 02:42:58 PM UTC 24
Finished Sep 18 02:43:05 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639713704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.639713704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1224535499
Short name T285
Test name
Test status
Simulation time 13517832170 ps
CPU time 94.35 seconds
Started Sep 18 02:43:01 PM UTC 24
Finished Sep 18 02:44:37 PM UTC 24
Peak memory 265600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224535499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.1224535499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.2004342829
Short name T735
Test name
Test status
Simulation time 30246080 ps
CPU time 3.22 seconds
Started Sep 18 02:42:52 PM UTC 24
Finished Sep 18 02:42:56 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004342829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2004342829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.3330017654
Short name T758
Test name
Test status
Simulation time 2357825339 ps
CPU time 36.27 seconds
Started Sep 18 02:42:52 PM UTC 24
Finished Sep 18 02:43:30 PM UTC 24
Peak memory 245384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330017654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3330017654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.4202256501
Short name T745
Test name
Test status
Simulation time 779031158 ps
CPU time 21.96 seconds
Started Sep 18 02:42:51 PM UTC 24
Finished Sep 18 02:43:14 PM UTC 24
Peak memory 244920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202256501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.4202256501
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.3777284755
Short name T750
Test name
Test status
Simulation time 7259040848 ps
CPU time 28.75 seconds
Started Sep 18 02:42:50 PM UTC 24
Finished Sep 18 02:43:20 PM UTC 24
Peak memory 234840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777284755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3777284755
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.3317156720
Short name T749
Test name
Test status
Simulation time 10828325384 ps
CPU time 15.8 seconds
Started Sep 18 02:43:02 PM UTC 24
Finished Sep 18 02:43:19 PM UTC 24
Peak memory 233588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317156720 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.3317156720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.4180875785
Short name T172
Test name
Test status
Simulation time 43542345 ps
CPU time 1.43 seconds
Started Sep 18 02:43:09 PM UTC 24
Finished Sep 18 02:43:11 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180875785 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.4180875785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.1698460267
Short name T744
Test name
Test status
Simulation time 14063895010 ps
CPU time 23.94 seconds
Started Sep 18 02:42:47 PM UTC 24
Finished Sep 18 02:43:13 PM UTC 24
Peak memory 229888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698460267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1698460267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2299784256
Short name T729
Test name
Test status
Simulation time 36782799 ps
CPU time 1.13 seconds
Started Sep 18 02:42:45 PM UTC 24
Finished Sep 18 02:42:47 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299784256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2299784256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.1971131693
Short name T734
Test name
Test status
Simulation time 41289977 ps
CPU time 2.94 seconds
Started Sep 18 02:42:49 PM UTC 24
Finished Sep 18 02:42:53 PM UTC 24
Peak memory 227392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971131693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1971131693
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.2739922209
Short name T731
Test name
Test status
Simulation time 61431924 ps
CPU time 1.3 seconds
Started Sep 18 02:42:47 PM UTC 24
Finished Sep 18 02:42:50 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739922209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2739922209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1725724815
Short name T737
Test name
Test status
Simulation time 216931577 ps
CPU time 6.41 seconds
Started Sep 18 02:42:53 PM UTC 24
Finished Sep 18 02:43:01 PM UTC 24
Peak memory 234884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725724815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1725724815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.2173992770
Short name T759
Test name
Test status
Simulation time 78708376 ps
CPU time 1.12 seconds
Started Sep 18 02:43:29 PM UTC 24
Finished Sep 18 02:43:31 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173992770 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.2173992770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.2968019641
Short name T757
Test name
Test status
Simulation time 1431155691 ps
CPU time 6.17 seconds
Started Sep 18 02:43:20 PM UTC 24
Finished Sep 18 02:43:28 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968019641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2968019641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.3286735560
Short name T743
Test name
Test status
Simulation time 37955526 ps
CPU time 1.19 seconds
Started Sep 18 02:43:10 PM UTC 24
Finished Sep 18 02:43:12 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286735560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3286735560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.529776410
Short name T835
Test name
Test status
Simulation time 24819905608 ps
CPU time 99.34 seconds
Started Sep 18 02:43:26 PM UTC 24
Finished Sep 18 02:45:08 PM UTC 24
Peak memory 261436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529776410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.529776410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1105897342
Short name T890
Test name
Test status
Simulation time 194630100572 ps
CPU time 174.2 seconds
Started Sep 18 02:43:27 PM UTC 24
Finished Sep 18 02:46:24 PM UTC 24
Peak memory 265924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105897342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1105897342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1768183227
Short name T992
Test name
Test status
Simulation time 400617900083 ps
CPU time 424.44 seconds
Started Sep 18 02:43:29 PM UTC 24
Finished Sep 18 02:50:39 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768183227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1768183227
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.595330760
Short name T766
Test name
Test status
Simulation time 865089896 ps
CPU time 17.49 seconds
Started Sep 18 02:43:22 PM UTC 24
Finished Sep 18 02:43:40 PM UTC 24
Peak memory 245192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595330760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.595330760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3618204157
Short name T775
Test name
Test status
Simulation time 6941814724 ps
CPU time 24.29 seconds
Started Sep 18 02:43:23 PM UTC 24
Finished Sep 18 02:43:48 PM UTC 24
Peak memory 245080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618204157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.3618204157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.90997445
Short name T754
Test name
Test status
Simulation time 508624368 ps
CPU time 8.33 seconds
Started Sep 18 02:43:17 PM UTC 24
Finished Sep 18 02:43:26 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90997445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.90997445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1146716611
Short name T761
Test name
Test status
Simulation time 8476457074 ps
CPU time 11.99 seconds
Started Sep 18 02:43:19 PM UTC 24
Finished Sep 18 02:43:32 PM UTC 24
Peak memory 245132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146716611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1146716611
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.549490740
Short name T751
Test name
Test status
Simulation time 105700291 ps
CPU time 3.85 seconds
Started Sep 18 02:43:17 PM UTC 24
Finished Sep 18 02:43:22 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549490740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.549490740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.3271014828
Short name T756
Test name
Test status
Simulation time 5296343756 ps
CPU time 10.9 seconds
Started Sep 18 02:43:16 PM UTC 24
Finished Sep 18 02:43:28 PM UTC 24
Peak memory 235096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271014828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3271014828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1814224254
Short name T762
Test name
Test status
Simulation time 1057949843 ps
CPU time 7.35 seconds
Started Sep 18 02:43:25 PM UTC 24
Finished Sep 18 02:43:33 PM UTC 24
Peak memory 233328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814224254 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1814224254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1012039782
Short name T150
Test name
Test status
Simulation time 385125119999 ps
CPU time 872.96 seconds
Started Sep 18 02:43:29 PM UTC 24
Finished Sep 18 02:58:12 PM UTC 24
Peak memory 294400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012039782 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.1012039782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.616383989
Short name T772
Test name
Test status
Simulation time 19152587373 ps
CPU time 30.37 seconds
Started Sep 18 02:43:13 PM UTC 24
Finished Sep 18 02:43:45 PM UTC 24
Peak memory 227528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616383989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.616383989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3790716258
Short name T748
Test name
Test status
Simulation time 1498131920 ps
CPU time 5.76 seconds
Started Sep 18 02:43:12 PM UTC 24
Finished Sep 18 02:43:19 PM UTC 24
Peak memory 227764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790716258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3790716258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.2766411264
Short name T747
Test name
Test status
Simulation time 259501805 ps
CPU time 3.86 seconds
Started Sep 18 02:43:14 PM UTC 24
Finished Sep 18 02:43:18 PM UTC 24
Peak memory 227348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766411264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2766411264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.4042185358
Short name T746
Test name
Test status
Simulation time 135766487 ps
CPU time 1.19 seconds
Started Sep 18 02:43:13 PM UTC 24
Finished Sep 18 02:43:16 PM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042185358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4042185358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.1752154853
Short name T753
Test name
Test status
Simulation time 677375338 ps
CPU time 3.26 seconds
Started Sep 18 02:43:20 PM UTC 24
Finished Sep 18 02:43:25 PM UTC 24
Peak memory 234960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752154853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1752154853
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.1931701216
Short name T776
Test name
Test status
Simulation time 26596140 ps
CPU time 1.08 seconds
Started Sep 18 02:43:49 PM UTC 24
Finished Sep 18 02:43:51 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931701216 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.1931701216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.396570017
Short name T780
Test name
Test status
Simulation time 2943676663 ps
CPU time 14.65 seconds
Started Sep 18 02:43:41 PM UTC 24
Finished Sep 18 02:43:57 PM UTC 24
Peak memory 234784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396570017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.396570017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.1490247663
Short name T760
Test name
Test status
Simulation time 15921773 ps
CPU time 1.14 seconds
Started Sep 18 02:43:30 PM UTC 24
Finished Sep 18 02:43:32 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490247663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1490247663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.2506460645
Short name T946
Test name
Test status
Simulation time 44372328685 ps
CPU time 225.28 seconds
Started Sep 18 02:43:44 PM UTC 24
Finished Sep 18 02:47:33 PM UTC 24
Peak memory 263864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506460645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2506460645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1222168008
Short name T803
Test name
Test status
Simulation time 12492182496 ps
CPU time 47.51 seconds
Started Sep 18 02:43:45 PM UTC 24
Finished Sep 18 02:44:34 PM UTC 24
Peak memory 229612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222168008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1222168008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.3105416035
Short name T807
Test name
Test status
Simulation time 4380225491 ps
CPU time 58.12 seconds
Started Sep 18 02:43:43 PM UTC 24
Finished Sep 18 02:44:42 PM UTC 24
Peak memory 235080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105416035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3105416035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.4294232913
Short name T986
Test name
Test status
Simulation time 178441696655 ps
CPU time 335.95 seconds
Started Sep 18 02:43:43 PM UTC 24
Finished Sep 18 02:49:23 PM UTC 24
Peak memory 261488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294232913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.4294232913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.164241657
Short name T771
Test name
Test status
Simulation time 188830648 ps
CPU time 6.31 seconds
Started Sep 18 02:43:37 PM UTC 24
Finished Sep 18 02:43:44 PM UTC 24
Peak memory 235004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164241657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.164241657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.3939315360
Short name T770
Test name
Test status
Simulation time 840983581 ps
CPU time 5.36 seconds
Started Sep 18 02:43:37 PM UTC 24
Finished Sep 18 02:43:43 PM UTC 24
Peak memory 234628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939315360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3939315360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.2887680039
Short name T773
Test name
Test status
Simulation time 2614566101 ps
CPU time 9.26 seconds
Started Sep 18 02:43:36 PM UTC 24
Finished Sep 18 02:43:46 PM UTC 24
Peak memory 245328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887680039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.2887680039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.4058359900
Short name T768
Test name
Test status
Simulation time 530129082 ps
CPU time 6.01 seconds
Started Sep 18 02:43:35 PM UTC 24
Finished Sep 18 02:43:42 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058359900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4058359900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.4095391326
Short name T779
Test name
Test status
Simulation time 4788790324 ps
CPU time 12.71 seconds
Started Sep 18 02:43:43 PM UTC 24
Finished Sep 18 02:43:57 PM UTC 24
Peak memory 231300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095391326 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.4095391326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.842367153
Short name T917
Test name
Test status
Simulation time 22579362178 ps
CPU time 190.45 seconds
Started Sep 18 02:43:47 PM UTC 24
Finished Sep 18 02:47:01 PM UTC 24
Peak memory 261576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842367153 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.842367153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1247681478
Short name T774
Test name
Test status
Simulation time 1007658742 ps
CPU time 14.05 seconds
Started Sep 18 02:43:32 PM UTC 24
Finished Sep 18 02:43:47 PM UTC 24
Peak memory 227664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247681478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1247681478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.4198689008
Short name T767
Test name
Test status
Simulation time 2244867941 ps
CPU time 9.43 seconds
Started Sep 18 02:43:31 PM UTC 24
Finished Sep 18 02:43:41 PM UTC 24
Peak memory 227776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198689008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4198689008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.1103610996
Short name T765
Test name
Test status
Simulation time 246947971 ps
CPU time 1.84 seconds
Started Sep 18 02:43:33 PM UTC 24
Finished Sep 18 02:43:36 PM UTC 24
Peak memory 227060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103610996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1103610996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2788617883
Short name T763
Test name
Test status
Simulation time 53342726 ps
CPU time 1.5 seconds
Started Sep 18 02:43:33 PM UTC 24
Finished Sep 18 02:43:36 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788617883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2788617883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.846430993
Short name T769
Test name
Test status
Simulation time 132874791 ps
CPU time 3.57 seconds
Started Sep 18 02:43:37 PM UTC 24
Finished Sep 18 02:43:42 PM UTC 24
Peak memory 234712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846430993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.846430993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.4038004841
Short name T792
Test name
Test status
Simulation time 70575984 ps
CPU time 1.08 seconds
Started Sep 18 02:44:15 PM UTC 24
Finished Sep 18 02:44:17 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038004841 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.4038004841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.316109248
Short name T785
Test name
Test status
Simulation time 91236842 ps
CPU time 2.99 seconds
Started Sep 18 02:43:59 PM UTC 24
Finished Sep 18 02:44:04 PM UTC 24
Peak memory 245148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316109248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.316109248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.705943498
Short name T777
Test name
Test status
Simulation time 19573659 ps
CPU time 1.23 seconds
Started Sep 18 02:43:50 PM UTC 24
Finished Sep 18 02:43:52 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705943498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.705943498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.2987863313
Short name T824
Test name
Test status
Simulation time 2461243278 ps
CPU time 50.72 seconds
Started Sep 18 02:44:06 PM UTC 24
Finished Sep 18 02:44:58 PM UTC 24
Peak memory 267644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987863313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2987863313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1151611929
Short name T833
Test name
Test status
Simulation time 2076876690 ps
CPU time 53.54 seconds
Started Sep 18 02:44:10 PM UTC 24
Finished Sep 18 02:45:05 PM UTC 24
Peak memory 267648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151611929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1151611929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1357829799
Short name T240
Test name
Test status
Simulation time 7042257817 ps
CPU time 90.01 seconds
Started Sep 18 02:44:11 PM UTC 24
Finished Sep 18 02:45:43 PM UTC 24
Peak memory 265748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357829799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.1357829799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.1752079625
Short name T791
Test name
Test status
Simulation time 10182088435 ps
CPU time 13.62 seconds
Started Sep 18 02:44:01 PM UTC 24
Finished Sep 18 02:44:16 PM UTC 24
Peak memory 249532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752079625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1752079625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.4121421647
Short name T801
Test name
Test status
Simulation time 2477689525 ps
CPU time 22 seconds
Started Sep 18 02:44:05 PM UTC 24
Finished Sep 18 02:44:28 PM UTC 24
Peak memory 261440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121421647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.4121421647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.2777539846
Short name T786
Test name
Test status
Simulation time 623693757 ps
CPU time 4.68 seconds
Started Sep 18 02:43:59 PM UTC 24
Finished Sep 18 02:44:05 PM UTC 24
Peak memory 245000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777539846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2777539846
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.974274903
Short name T789
Test name
Test status
Simulation time 824895701 ps
CPU time 10.94 seconds
Started Sep 18 02:43:59 PM UTC 24
Finished Sep 18 02:44:12 PM UTC 24
Peak memory 235012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974274903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.974274903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2531488989
Short name T790
Test name
Test status
Simulation time 1207569406 ps
CPU time 14.14 seconds
Started Sep 18 02:43:58 PM UTC 24
Finished Sep 18 02:44:14 PM UTC 24
Peak memory 234712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531488989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.2531488989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1298242532
Short name T793
Test name
Test status
Simulation time 19603884651 ps
CPU time 17.69 seconds
Started Sep 18 02:43:58 PM UTC 24
Finished Sep 18 02:44:17 PM UTC 24
Peak memory 251264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298242532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1298242532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2505993436
Short name T788
Test name
Test status
Simulation time 169944580 ps
CPU time 4.04 seconds
Started Sep 18 02:44:05 PM UTC 24
Finished Sep 18 02:44:10 PM UTC 24
Peak memory 231540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505993436 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.2505993436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.3564968376
Short name T908
Test name
Test status
Simulation time 72340180606 ps
CPU time 159.17 seconds
Started Sep 18 02:44:12 PM UTC 24
Finished Sep 18 02:46:54 PM UTC 24
Peak memory 249280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564968376 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.3564968376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.328300341
Short name T795
Test name
Test status
Simulation time 1553883122 ps
CPU time 26.4 seconds
Started Sep 18 02:43:53 PM UTC 24
Finished Sep 18 02:44:21 PM UTC 24
Peak memory 227340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328300341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.328300341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.2706775680
Short name T781
Test name
Test status
Simulation time 2330938022 ps
CPU time 4.19 seconds
Started Sep 18 02:43:52 PM UTC 24
Finished Sep 18 02:43:58 PM UTC 24
Peak memory 227756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706775680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2706775680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.1340912328
Short name T783
Test name
Test status
Simulation time 219790078 ps
CPU time 4.53 seconds
Started Sep 18 02:43:55 PM UTC 24
Finished Sep 18 02:44:01 PM UTC 24
Peak memory 227668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340912328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1340912328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3741214886
Short name T778
Test name
Test status
Simulation time 44604772 ps
CPU time 1.38 seconds
Started Sep 18 02:43:54 PM UTC 24
Finished Sep 18 02:43:57 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741214886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3741214886
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.3227156529
Short name T784
Test name
Test status
Simulation time 56336783 ps
CPU time 2.97 seconds
Started Sep 18 02:43:59 PM UTC 24
Finished Sep 18 02:44:04 PM UTC 24
Peak memory 234396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227156529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3227156529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.1768636379
Short name T362
Test name
Test status
Simulation time 31553195 ps
CPU time 1.12 seconds
Started Sep 18 02:26:32 PM UTC 24
Finished Sep 18 02:26:34 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768636379 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1768636379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4263188851
Short name T203
Test name
Test status
Simulation time 79316638 ps
CPU time 3.59 seconds
Started Sep 18 02:26:09 PM UTC 24
Finished Sep 18 02:26:13 PM UTC 24
Peak memory 244996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263188851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4263188851
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.160369824
Short name T360
Test name
Test status
Simulation time 63732592 ps
CPU time 1.2 seconds
Started Sep 18 02:25:50 PM UTC 24
Finished Sep 18 02:25:52 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160369824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.160369824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.3875459166
Short name T79
Test name
Test status
Simulation time 1985570078 ps
CPU time 62.88 seconds
Started Sep 18 02:26:15 PM UTC 24
Finished Sep 18 02:27:20 PM UTC 24
Peak memory 263624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875459166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3875459166
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2622232505
Short name T146
Test name
Test status
Simulation time 26215211400 ps
CPU time 261.5 seconds
Started Sep 18 02:26:18 PM UTC 24
Finished Sep 18 02:30:43 PM UTC 24
Peak memory 267700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622232505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2622232505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.2670564472
Short name T73
Test name
Test status
Simulation time 113812127943 ps
CPU time 296.35 seconds
Started Sep 18 02:26:26 PM UTC 24
Finished Sep 18 02:31:27 PM UTC 24
Peak memory 263620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670564472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.2670564472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2165626928
Short name T367
Test name
Test status
Simulation time 6216354869 ps
CPU time 37.24 seconds
Started Sep 18 02:26:10 PM UTC 24
Finished Sep 18 02:26:48 PM UTC 24
Peak memory 251524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165626928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2165626928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3098111820
Short name T361
Test name
Test status
Simulation time 40501079 ps
CPU time 1.17 seconds
Started Sep 18 02:26:12 PM UTC 24
Finished Sep 18 02:26:14 PM UTC 24
Peak memory 226812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098111820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.3098111820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1479019421
Short name T244
Test name
Test status
Simulation time 275086936 ps
CPU time 5.66 seconds
Started Sep 18 02:25:58 PM UTC 24
Finished Sep 18 02:26:05 PM UTC 24
Peak memory 234952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479019421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1479019421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.325007754
Short name T211
Test name
Test status
Simulation time 19548535047 ps
CPU time 54.08 seconds
Started Sep 18 02:26:02 PM UTC 24
Finished Sep 18 02:26:58 PM UTC 24
Peak memory 234776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325007754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.325007754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.2889171707
Short name T207
Test name
Test status
Simulation time 15278650429 ps
CPU time 27.98 seconds
Started Sep 18 02:25:58 PM UTC 24
Finished Sep 18 02:26:28 PM UTC 24
Peak memory 234832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889171707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.2889171707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2229050598
Short name T59
Test name
Test status
Simulation time 885157971 ps
CPU time 9.37 seconds
Started Sep 18 02:25:57 PM UTC 24
Finished Sep 18 02:26:07 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229050598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2229050598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.944467144
Short name T155
Test name
Test status
Simulation time 501565717 ps
CPU time 10.19 seconds
Started Sep 18 02:26:14 PM UTC 24
Finished Sep 18 02:26:25 PM UTC 24
Peak memory 231436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944467144 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.944467144
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3115021002
Short name T33
Test name
Test status
Simulation time 374043870 ps
CPU time 1.9 seconds
Started Sep 18 02:26:30 PM UTC 24
Finished Sep 18 02:26:33 PM UTC 24
Peak memory 256996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115021002 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3115021002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.3750383232
Short name T23
Test name
Test status
Simulation time 61367824 ps
CPU time 1.71 seconds
Started Sep 18 02:26:28 PM UTC 24
Finished Sep 18 02:26:31 PM UTC 24
Peak memory 217028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750383232 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.3750383232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.4245540675
Short name T352
Test name
Test status
Simulation time 1140549612 ps
CPU time 3.27 seconds
Started Sep 18 02:25:53 PM UTC 24
Finished Sep 18 02:25:57 PM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245540675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4245540675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3225450723
Short name T66
Test name
Test status
Simulation time 63002068 ps
CPU time 4.35 seconds
Started Sep 18 02:25:56 PM UTC 24
Finished Sep 18 02:26:02 PM UTC 24
Peak memory 227384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225450723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3225450723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.198374596
Short name T94
Test name
Test status
Simulation time 35341383 ps
CPU time 1.2 seconds
Started Sep 18 02:25:54 PM UTC 24
Finished Sep 18 02:25:56 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198374596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.198374596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.259067886
Short name T188
Test name
Test status
Simulation time 1179186400 ps
CPU time 4.78 seconds
Started Sep 18 02:26:06 PM UTC 24
Finished Sep 18 02:26:11 PM UTC 24
Peak memory 234644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259067886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.259067886
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.3918628570
Short name T810
Test name
Test status
Simulation time 28924122 ps
CPU time 1.15 seconds
Started Sep 18 02:44:42 PM UTC 24
Finished Sep 18 02:44:44 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918628570 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.3918628570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1781492369
Short name T804
Test name
Test status
Simulation time 321969729 ps
CPU time 9.13 seconds
Started Sep 18 02:44:27 PM UTC 24
Finished Sep 18 02:44:38 PM UTC 24
Peak memory 245260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781492369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1781492369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.919204596
Short name T794
Test name
Test status
Simulation time 60945142 ps
CPU time 1.19 seconds
Started Sep 18 02:44:17 PM UTC 24
Finished Sep 18 02:44:19 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919204596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.919204596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.547314579
Short name T811
Test name
Test status
Simulation time 447588743 ps
CPU time 5.64 seconds
Started Sep 18 02:44:38 PM UTC 24
Finished Sep 18 02:44:45 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547314579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.547314579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3585185815
Short name T822
Test name
Test status
Simulation time 2450877592 ps
CPU time 16.28 seconds
Started Sep 18 02:44:38 PM UTC 24
Finished Sep 18 02:44:56 PM UTC 24
Peak memory 231740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585185815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3585185815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.119538416
Short name T981
Test name
Test status
Simulation time 47016185684 ps
CPU time 241.23 seconds
Started Sep 18 02:44:39 PM UTC 24
Finished Sep 18 02:48:43 PM UTC 24
Peak memory 263944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119538416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.119538416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.1260926555
Short name T815
Test name
Test status
Simulation time 2636782718 ps
CPU time 17.79 seconds
Started Sep 18 02:44:29 PM UTC 24
Finished Sep 18 02:44:48 PM UTC 24
Peak memory 245376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260926555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1260926555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3060441440
Short name T816
Test name
Test status
Simulation time 5600683563 ps
CPU time 16.89 seconds
Started Sep 18 02:44:31 PM UTC 24
Finished Sep 18 02:44:49 PM UTC 24
Peak memory 234820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060441440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.3060441440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1838605746
Short name T802
Test name
Test status
Simulation time 178132296 ps
CPU time 5.01 seconds
Started Sep 18 02:44:24 PM UTC 24
Finished Sep 18 02:44:30 PM UTC 24
Peak memory 234752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838605746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1838605746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.3118472597
Short name T817
Test name
Test status
Simulation time 2206474520 ps
CPU time 22.53 seconds
Started Sep 18 02:44:25 PM UTC 24
Finished Sep 18 02:44:49 PM UTC 24
Peak memory 245064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118472597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3118472597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.972347334
Short name T808
Test name
Test status
Simulation time 14929197324 ps
CPU time 17.59 seconds
Started Sep 18 02:44:24 PM UTC 24
Finished Sep 18 02:44:43 PM UTC 24
Peak memory 245024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972347334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.972347334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.1562115823
Short name T814
Test name
Test status
Simulation time 4907700025 ps
CPU time 21.62 seconds
Started Sep 18 02:44:24 PM UTC 24
Finished Sep 18 02:44:47 PM UTC 24
Peak memory 245124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562115823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1562115823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.4093717957
Short name T805
Test name
Test status
Simulation time 265455474 ps
CPU time 3.67 seconds
Started Sep 18 02:44:35 PM UTC 24
Finished Sep 18 02:44:40 PM UTC 24
Peak memory 233228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093717957 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.4093717957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.1360221140
Short name T315
Test name
Test status
Simulation time 96739934266 ps
CPU time 967.8 seconds
Started Sep 18 02:44:41 PM UTC 24
Finished Sep 18 03:00:59 PM UTC 24
Peak memory 310720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360221140 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.1360221140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.2812720850
Short name T800
Test name
Test status
Simulation time 961251217 ps
CPU time 7.61 seconds
Started Sep 18 02:44:18 PM UTC 24
Finished Sep 18 02:44:27 PM UTC 24
Peak memory 227388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812720850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2812720850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1238405310
Short name T799
Test name
Test status
Simulation time 1761194115 ps
CPU time 5.77 seconds
Started Sep 18 02:44:18 PM UTC 24
Finished Sep 18 02:44:25 PM UTC 24
Peak memory 227696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238405310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1238405310
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3590486083
Short name T798
Test name
Test status
Simulation time 270785328 ps
CPU time 1.58 seconds
Started Sep 18 02:44:21 PM UTC 24
Finished Sep 18 02:44:24 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590486083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3590486083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2272227031
Short name T796
Test name
Test status
Simulation time 42092897 ps
CPU time 1.19 seconds
Started Sep 18 02:44:20 PM UTC 24
Finished Sep 18 02:44:22 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272227031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2272227031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.4112673056
Short name T806
Test name
Test status
Simulation time 3926861102 ps
CPU time 13.14 seconds
Started Sep 18 02:44:26 PM UTC 24
Finished Sep 18 02:44:41 PM UTC 24
Peak memory 245388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112673056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4112673056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1820405268
Short name T828
Test name
Test status
Simulation time 12289965 ps
CPU time 1.11 seconds
Started Sep 18 02:44:58 PM UTC 24
Finished Sep 18 02:45:00 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820405268 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.1820405268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3576297613
Short name T821
Test name
Test status
Simulation time 192617700 ps
CPU time 3.91 seconds
Started Sep 18 02:44:50 PM UTC 24
Finished Sep 18 02:44:54 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576297613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3576297613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.2928728914
Short name T812
Test name
Test status
Simulation time 106339948 ps
CPU time 1.24 seconds
Started Sep 18 02:44:43 PM UTC 24
Finished Sep 18 02:44:45 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928728914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2928728914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.1857941002
Short name T848
Test name
Test status
Simulation time 1401259521 ps
CPU time 24.12 seconds
Started Sep 18 02:44:55 PM UTC 24
Finished Sep 18 02:45:21 PM UTC 24
Peak memory 249280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857941002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1857941002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2349086454
Short name T864
Test name
Test status
Simulation time 3943383277 ps
CPU time 48.14 seconds
Started Sep 18 02:44:55 PM UTC 24
Finished Sep 18 02:45:45 PM UTC 24
Peak memory 251320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349086454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2349086454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2543666218
Short name T942
Test name
Test status
Simulation time 13040766909 ps
CPU time 149.34 seconds
Started Sep 18 02:44:56 PM UTC 24
Finished Sep 18 02:47:28 PM UTC 24
Peak memory 276232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543666218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.2543666218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.237917401
Short name T840
Test name
Test status
Simulation time 6677457311 ps
CPU time 23.99 seconds
Started Sep 18 02:44:50 PM UTC 24
Finished Sep 18 02:45:15 PM UTC 24
Peak memory 235072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237917401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.237917401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.4217178042
Short name T951
Test name
Test status
Simulation time 14905912869 ps
CPU time 162.17 seconds
Started Sep 18 02:44:51 PM UTC 24
Finished Sep 18 02:47:36 PM UTC 24
Peak memory 261636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217178042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.4217178042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.433152173
Short name T849
Test name
Test status
Simulation time 3140361790 ps
CPU time 32.86 seconds
Started Sep 18 02:44:47 PM UTC 24
Finished Sep 18 02:45:21 PM UTC 24
Peak memory 234780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433152173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.433152173
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3052740394
Short name T846
Test name
Test status
Simulation time 10597825846 ps
CPU time 30.01 seconds
Started Sep 18 02:44:47 PM UTC 24
Finished Sep 18 02:45:18 PM UTC 24
Peak memory 234888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052740394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3052740394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.867371933
Short name T818
Test name
Test status
Simulation time 81557105 ps
CPU time 3.22 seconds
Started Sep 18 02:44:46 PM UTC 24
Finished Sep 18 02:44:50 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867371933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.867371933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1916731087
Short name T827
Test name
Test status
Simulation time 1037884136 ps
CPU time 12.27 seconds
Started Sep 18 02:44:46 PM UTC 24
Finished Sep 18 02:44:59 PM UTC 24
Peak memory 234848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916731087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1916731087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3924616754
Short name T826
Test name
Test status
Simulation time 570035363 ps
CPU time 4.96 seconds
Started Sep 18 02:44:53 PM UTC 24
Finished Sep 18 02:44:59 PM UTC 24
Peak memory 231156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924616754 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3924616754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1148163744
Short name T993
Test name
Test status
Simulation time 137188274164 ps
CPU time 363.17 seconds
Started Sep 18 02:44:58 PM UTC 24
Finished Sep 18 02:51:06 PM UTC 24
Peak memory 284156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148163744 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.1148163744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.1538597759
Short name T837
Test name
Test status
Simulation time 4280550064 ps
CPU time 24.86 seconds
Started Sep 18 02:44:44 PM UTC 24
Finished Sep 18 02:45:11 PM UTC 24
Peak memory 227764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538597759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1538597759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1077707418
Short name T832
Test name
Test status
Simulation time 8217332488 ps
CPU time 20.22 seconds
Started Sep 18 02:44:43 PM UTC 24
Finished Sep 18 02:45:04 PM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077707418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1077707418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.1955518434
Short name T823
Test name
Test status
Simulation time 155697427 ps
CPU time 9.84 seconds
Started Sep 18 02:44:46 PM UTC 24
Finished Sep 18 02:44:57 PM UTC 24
Peak memory 227340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955518434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1955518434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3420476442
Short name T813
Test name
Test status
Simulation time 178551665 ps
CPU time 0.96 seconds
Started Sep 18 02:44:44 PM UTC 24
Finished Sep 18 02:44:46 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420476442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3420476442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.1045124579
Short name T825
Test name
Test status
Simulation time 1134291775 ps
CPU time 9.49 seconds
Started Sep 18 02:44:48 PM UTC 24
Finished Sep 18 02:44:59 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045124579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1045124579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1196335004
Short name T844
Test name
Test status
Simulation time 13609758 ps
CPU time 1.11 seconds
Started Sep 18 02:45:16 PM UTC 24
Finished Sep 18 02:45:18 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196335004 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.1196335004
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1938682683
Short name T839
Test name
Test status
Simulation time 514672936 ps
CPU time 4.31 seconds
Started Sep 18 02:45:06 PM UTC 24
Finished Sep 18 02:45:12 PM UTC 24
Peak memory 234656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938682683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1938682683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2190606070
Short name T829
Test name
Test status
Simulation time 34186689 ps
CPU time 1.19 seconds
Started Sep 18 02:44:59 PM UTC 24
Finished Sep 18 02:45:01 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190606070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2190606070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2722912990
Short name T870
Test name
Test status
Simulation time 11911797497 ps
CPU time 42.65 seconds
Started Sep 18 02:45:12 PM UTC 24
Finished Sep 18 02:45:56 PM UTC 24
Peak memory 261440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722912990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2722912990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2145072715
Short name T982
Test name
Test status
Simulation time 88207474534 ps
CPU time 212.89 seconds
Started Sep 18 02:45:12 PM UTC 24
Finished Sep 18 02:48:48 PM UTC 24
Peak memory 276160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145072715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2145072715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.397355343
Short name T961
Test name
Test status
Simulation time 37107105761 ps
CPU time 152.38 seconds
Started Sep 18 02:45:13 PM UTC 24
Finished Sep 18 02:47:48 PM UTC 24
Peak memory 261576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397355343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.397355343
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.906289885
Short name T841
Test name
Test status
Simulation time 164863979 ps
CPU time 6.47 seconds
Started Sep 18 02:45:08 PM UTC 24
Finished Sep 18 02:45:15 PM UTC 24
Peak memory 234696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906289885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.906289885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3465047578
Short name T886
Test name
Test status
Simulation time 3179367863 ps
CPU time 67.75 seconds
Started Sep 18 02:45:09 PM UTC 24
Finished Sep 18 02:46:18 PM UTC 24
Peak memory 261504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465047578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.3465047578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.370447990
Short name T836
Test name
Test status
Simulation time 356274937 ps
CPU time 3.55 seconds
Started Sep 18 02:45:05 PM UTC 24
Finished Sep 18 02:45:09 PM UTC 24
Peak memory 234552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370447990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.370447990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1012763933
Short name T845
Test name
Test status
Simulation time 766770984 ps
CPU time 12.45 seconds
Started Sep 18 02:45:05 PM UTC 24
Finished Sep 18 02:45:18 PM UTC 24
Peak memory 244892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012763933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1012763933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3615007176
Short name T842
Test name
Test status
Simulation time 12977406746 ps
CPU time 11.84 seconds
Started Sep 18 02:45:02 PM UTC 24
Finished Sep 18 02:45:15 PM UTC 24
Peak memory 245068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615007176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.3615007176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2281520198
Short name T834
Test name
Test status
Simulation time 373965832 ps
CPU time 4.08 seconds
Started Sep 18 02:45:01 PM UTC 24
Finished Sep 18 02:45:06 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281520198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2281520198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.4164093106
Short name T853
Test name
Test status
Simulation time 1011034982 ps
CPU time 14.33 seconds
Started Sep 18 02:45:10 PM UTC 24
Finished Sep 18 02:45:25 PM UTC 24
Peak memory 231156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164093106 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.4164093106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3074214501
Short name T987
Test name
Test status
Simulation time 120246051637 ps
CPU time 264.83 seconds
Started Sep 18 02:45:14 PM UTC 24
Finished Sep 18 02:49:43 PM UTC 24
Peak memory 263616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074214501 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.3074214501
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.612323735
Short name T869
Test name
Test status
Simulation time 13116258930 ps
CPU time 53.31 seconds
Started Sep 18 02:45:01 PM UTC 24
Finished Sep 18 02:45:56 PM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612323735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.612323735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2232513931
Short name T851
Test name
Test status
Simulation time 9649169183 ps
CPU time 22.63 seconds
Started Sep 18 02:44:59 PM UTC 24
Finished Sep 18 02:45:23 PM UTC 24
Peak memory 227548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232513931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2232513931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.3277112363
Short name T831
Test name
Test status
Simulation time 167203678 ps
CPU time 1.61 seconds
Started Sep 18 02:45:01 PM UTC 24
Finished Sep 18 02:45:04 PM UTC 24
Peak memory 217080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277112363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3277112363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1026623181
Short name T830
Test name
Test status
Simulation time 150907272 ps
CPU time 1.31 seconds
Started Sep 18 02:45:01 PM UTC 24
Finished Sep 18 02:45:03 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026623181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1026623181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.3946390040
Short name T838
Test name
Test status
Simulation time 58477323 ps
CPU time 3.41 seconds
Started Sep 18 02:45:06 PM UTC 24
Finished Sep 18 02:45:11 PM UTC 24
Peak memory 244944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946390040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3946390040
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.2807454572
Short name T861
Test name
Test status
Simulation time 132601662 ps
CPU time 1.06 seconds
Started Sep 18 02:45:39 PM UTC 24
Finished Sep 18 02:45:42 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807454572 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.2807454572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2068292156
Short name T855
Test name
Test status
Simulation time 830226862 ps
CPU time 5.65 seconds
Started Sep 18 02:45:24 PM UTC 24
Finished Sep 18 02:45:31 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068292156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2068292156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1108039814
Short name T843
Test name
Test status
Simulation time 22975331 ps
CPU time 1.05 seconds
Started Sep 18 02:45:16 PM UTC 24
Finished Sep 18 02:45:18 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108039814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1108039814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.4281519178
Short name T314
Test name
Test status
Simulation time 15871688060 ps
CPU time 77.34 seconds
Started Sep 18 02:45:31 PM UTC 24
Finished Sep 18 02:46:51 PM UTC 24
Peak memory 263488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281519178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4281519178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2105093121
Short name T1003
Test name
Test status
Simulation time 341836089301 ps
CPU time 470.01 seconds
Started Sep 18 02:45:33 PM UTC 24
Finished Sep 18 02:53:29 PM UTC 24
Peak memory 278156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105093121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2105093121
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3096507849
Short name T983
Test name
Test status
Simulation time 13870268535 ps
CPU time 194.47 seconds
Started Sep 18 02:45:36 PM UTC 24
Finished Sep 18 02:48:54 PM UTC 24
Peak memory 263620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096507849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.3096507849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2407980236
Short name T856
Test name
Test status
Simulation time 444365249 ps
CPU time 5.38 seconds
Started Sep 18 02:45:25 PM UTC 24
Finished Sep 18 02:45:32 PM UTC 24
Peak memory 245000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407980236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2407980236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2008123433
Short name T913
Test name
Test status
Simulation time 11733386343 ps
CPU time 89.77 seconds
Started Sep 18 02:45:27 PM UTC 24
Finished Sep 18 02:46:59 PM UTC 24
Peak memory 263752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008123433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.2008123433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1993387594
Short name T860
Test name
Test status
Simulation time 7668878259 ps
CPU time 16.24 seconds
Started Sep 18 02:45:21 PM UTC 24
Finished Sep 18 02:45:39 PM UTC 24
Peak memory 234768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993387594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1993387594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.3171802330
Short name T910
Test name
Test status
Simulation time 33770421327 ps
CPU time 90.38 seconds
Started Sep 18 02:45:23 PM UTC 24
Finished Sep 18 02:46:55 PM UTC 24
Peak memory 244432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171802330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3171802330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.4252161199
Short name T858
Test name
Test status
Simulation time 614810330 ps
CPU time 14.38 seconds
Started Sep 18 02:45:21 PM UTC 24
Finished Sep 18 02:45:37 PM UTC 24
Peak memory 244948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252161199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.4252161199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.495130403
Short name T859
Test name
Test status
Simulation time 17139349083 ps
CPU time 17.29 seconds
Started Sep 18 02:45:20 PM UTC 24
Finished Sep 18 02:45:38 PM UTC 24
Peak memory 245376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495130403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.495130403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1419957844
Short name T857
Test name
Test status
Simulation time 278128395 ps
CPU time 7.21 seconds
Started Sep 18 02:45:27 PM UTC 24
Finished Sep 18 02:45:35 PM UTC 24
Peak memory 231244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419957844 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.1419957844
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3486836931
Short name T874
Test name
Test status
Simulation time 4426393754 ps
CPU time 22.2 seconds
Started Sep 18 02:45:38 PM UTC 24
Finished Sep 18 02:46:02 PM UTC 24
Peak memory 229644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486836931 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.3486836931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.3288776245
Short name T854
Test name
Test status
Simulation time 718323718 ps
CPU time 6.97 seconds
Started Sep 18 02:45:18 PM UTC 24
Finished Sep 18 02:45:26 PM UTC 24
Peak memory 229392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288776245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3288776245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1678891658
Short name T852
Test name
Test status
Simulation time 1421729386 ps
CPU time 6.2 seconds
Started Sep 18 02:45:17 PM UTC 24
Finished Sep 18 02:45:24 PM UTC 24
Peak memory 227448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678891658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1678891658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2331566050
Short name T850
Test name
Test status
Simulation time 52005832 ps
CPU time 1.33 seconds
Started Sep 18 02:45:20 PM UTC 24
Finished Sep 18 02:45:22 PM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331566050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2331566050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.92241092
Short name T847
Test name
Test status
Simulation time 74114572 ps
CPU time 1.28 seconds
Started Sep 18 02:45:18 PM UTC 24
Finished Sep 18 02:45:21 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92241092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.92241092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.1521635596
Short name T868
Test name
Test status
Simulation time 45567685632 ps
CPU time 28.67 seconds
Started Sep 18 02:45:23 PM UTC 24
Finished Sep 18 02:45:53 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521635596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1521635596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3311632434
Short name T879
Test name
Test status
Simulation time 15031369 ps
CPU time 1.09 seconds
Started Sep 18 02:46:09 PM UTC 24
Finished Sep 18 02:46:11 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311632434 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3311632434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.582037621
Short name T873
Test name
Test status
Simulation time 53531794 ps
CPU time 3.12 seconds
Started Sep 18 02:45:57 PM UTC 24
Finished Sep 18 02:46:01 PM UTC 24
Peak memory 244992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582037621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.582037621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.3895349866
Short name T862
Test name
Test status
Simulation time 16332649 ps
CPU time 1.2 seconds
Started Sep 18 02:45:40 PM UTC 24
Finished Sep 18 02:45:42 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895349866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3895349866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.1773925834
Short name T909
Test name
Test status
Simulation time 5546920229 ps
CPU time 50.9 seconds
Started Sep 18 02:46:02 PM UTC 24
Finished Sep 18 02:46:55 PM UTC 24
Peak memory 251192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773925834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1773925834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1752571917
Short name T901
Test name
Test status
Simulation time 1403880541 ps
CPU time 31.36 seconds
Started Sep 18 02:46:02 PM UTC 24
Finished Sep 18 02:46:35 PM UTC 24
Peak memory 261500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752571917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1752571917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1025943418
Short name T990
Test name
Test status
Simulation time 48169664589 ps
CPU time 255.91 seconds
Started Sep 18 02:46:05 PM UTC 24
Finished Sep 18 02:50:24 PM UTC 24
Peak memory 267716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025943418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1025943418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.2913739773
Short name T896
Test name
Test status
Simulation time 2369638570 ps
CPU time 53.84 seconds
Started Sep 18 02:45:58 PM UTC 24
Finished Sep 18 02:46:54 PM UTC 24
Peak memory 251276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913739773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2913739773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3153798708
Short name T893
Test name
Test status
Simulation time 3652067782 ps
CPU time 25.91 seconds
Started Sep 18 02:46:00 PM UTC 24
Finished Sep 18 02:46:27 PM UTC 24
Peak memory 235076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153798708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.3153798708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.2540877292
Short name T872
Test name
Test status
Simulation time 2140808718 ps
CPU time 8.64 seconds
Started Sep 18 02:45:49 PM UTC 24
Finished Sep 18 02:45:59 PM UTC 24
Peak memory 245188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540877292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2540877292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2508115040
Short name T877
Test name
Test status
Simulation time 686698165 ps
CPU time 13.24 seconds
Started Sep 18 02:45:54 PM UTC 24
Finished Sep 18 02:46:08 PM UTC 24
Peak memory 244996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508115040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2508115040
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2793781151
Short name T871
Test name
Test status
Simulation time 1824346295 ps
CPU time 6.96 seconds
Started Sep 18 02:45:49 PM UTC 24
Finished Sep 18 02:45:57 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793781151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.2793781151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1942917336
Short name T880
Test name
Test status
Simulation time 12777619201 ps
CPU time 23.48 seconds
Started Sep 18 02:45:48 PM UTC 24
Finished Sep 18 02:46:13 PM UTC 24
Peak memory 234776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942917336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1942917336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2142738575
Short name T876
Test name
Test status
Simulation time 134408592 ps
CPU time 5.57 seconds
Started Sep 18 02:46:00 PM UTC 24
Finished Sep 18 02:46:06 PM UTC 24
Peak memory 233332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142738575 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.2142738575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.296134996
Short name T1005
Test name
Test status
Simulation time 242493308341 ps
CPU time 541.2 seconds
Started Sep 18 02:46:07 PM UTC 24
Finished Sep 18 02:55:15 PM UTC 24
Peak memory 277964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296134996 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.296134996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.2505758030
Short name T889
Test name
Test status
Simulation time 36373290236 ps
CPU time 39.53 seconds
Started Sep 18 02:45:43 PM UTC 24
Finished Sep 18 02:46:24 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505758030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2505758030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2603774365
Short name T867
Test name
Test status
Simulation time 724684752 ps
CPU time 4.15 seconds
Started Sep 18 02:45:43 PM UTC 24
Finished Sep 18 02:45:48 PM UTC 24
Peak memory 227336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603774365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2603774365
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.262344582
Short name T866
Test name
Test status
Simulation time 13955466 ps
CPU time 1.14 seconds
Started Sep 18 02:45:46 PM UTC 24
Finished Sep 18 02:45:48 PM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262344582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.262344582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.921367483
Short name T865
Test name
Test status
Simulation time 59610679 ps
CPU time 1.18 seconds
Started Sep 18 02:45:44 PM UTC 24
Finished Sep 18 02:45:46 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921367483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.921367483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.618196325
Short name T881
Test name
Test status
Simulation time 31767033313 ps
CPU time 14.27 seconds
Started Sep 18 02:45:57 PM UTC 24
Finished Sep 18 02:46:13 PM UTC 24
Peak memory 245072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618196325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.618196325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.276832860
Short name T898
Test name
Test status
Simulation time 17170873 ps
CPU time 1.11 seconds
Started Sep 18 02:46:29 PM UTC 24
Finished Sep 18 02:46:31 PM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276832860 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.276832860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1868971849
Short name T897
Test name
Test status
Simulation time 772252389 ps
CPU time 8.77 seconds
Started Sep 18 02:46:21 PM UTC 24
Finished Sep 18 02:46:31 PM UTC 24
Peak memory 234656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868971849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1868971849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.4197387486
Short name T882
Test name
Test status
Simulation time 14334165 ps
CPU time 1.13 seconds
Started Sep 18 02:46:11 PM UTC 24
Finished Sep 18 02:46:13 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197387486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4197387486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.892431428
Short name T1002
Test name
Test status
Simulation time 47695528399 ps
CPU time 380.58 seconds
Started Sep 18 02:46:26 PM UTC 24
Finished Sep 18 02:52:51 PM UTC 24
Peak memory 277824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892431428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.892431428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2304764523
Short name T985
Test name
Test status
Simulation time 20030311836 ps
CPU time 168.08 seconds
Started Sep 18 02:46:26 PM UTC 24
Finished Sep 18 02:49:17 PM UTC 24
Peak memory 263680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304764523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2304764523
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.765827390
Short name T1000
Test name
Test status
Simulation time 122620488721 ps
CPU time 352.45 seconds
Started Sep 18 02:46:28 PM UTC 24
Finished Sep 18 02:52:25 PM UTC 24
Peak memory 280272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765827390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.765827390
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.38011296
Short name T905
Test name
Test status
Simulation time 7904379532 ps
CPU time 20.05 seconds
Started Sep 18 02:46:23 PM UTC 24
Finished Sep 18 02:46:44 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38011296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.38011296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3961358079
Short name T975
Test name
Test status
Simulation time 25543704098 ps
CPU time 103.13 seconds
Started Sep 18 02:46:25 PM UTC 24
Finished Sep 18 02:48:11 PM UTC 24
Peak memory 278148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961358079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.3961358079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.2958895217
Short name T888
Test name
Test status
Simulation time 263134590 ps
CPU time 3.16 seconds
Started Sep 18 02:46:18 PM UTC 24
Finished Sep 18 02:46:22 PM UTC 24
Peak memory 233168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958895217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2958895217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2691317588
Short name T892
Test name
Test status
Simulation time 267705646 ps
CPU time 5.94 seconds
Started Sep 18 02:46:18 PM UTC 24
Finished Sep 18 02:46:25 PM UTC 24
Peak memory 234756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691317588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2691317588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3695281536
Short name T895
Test name
Test status
Simulation time 2400071526 ps
CPU time 11.12 seconds
Started Sep 18 02:46:16 PM UTC 24
Finished Sep 18 02:46:28 PM UTC 24
Peak memory 251268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695281536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.3695281536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3564220642
Short name T887
Test name
Test status
Simulation time 232570232 ps
CPU time 3.84 seconds
Started Sep 18 02:46:15 PM UTC 24
Finished Sep 18 02:46:20 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564220642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3564220642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.577746059
Short name T900
Test name
Test status
Simulation time 273871253 ps
CPU time 7.94 seconds
Started Sep 18 02:46:26 PM UTC 24
Finished Sep 18 02:46:35 PM UTC 24
Peak memory 233616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577746059 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.577746059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2496082115
Short name T1007
Test name
Test status
Simulation time 52541028243 ps
CPU time 536.56 seconds
Started Sep 18 02:46:29 PM UTC 24
Finished Sep 18 02:55:33 PM UTC 24
Peak memory 264000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496082115 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.2496082115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3518591770
Short name T907
Test name
Test status
Simulation time 5014474270 ps
CPU time 30.55 seconds
Started Sep 18 02:46:14 PM UTC 24
Finished Sep 18 02:46:45 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518591770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3518591770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1496083642
Short name T891
Test name
Test status
Simulation time 3220387532 ps
CPU time 11.64 seconds
Started Sep 18 02:46:12 PM UTC 24
Finished Sep 18 02:46:25 PM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496083642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1496083642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.2436854249
Short name T885
Test name
Test status
Simulation time 60476026 ps
CPU time 1.93 seconds
Started Sep 18 02:46:14 PM UTC 24
Finished Sep 18 02:46:17 PM UTC 24
Peak memory 227296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436854249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2436854249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3827290916
Short name T884
Test name
Test status
Simulation time 17213667 ps
CPU time 1.18 seconds
Started Sep 18 02:46:14 PM UTC 24
Finished Sep 18 02:46:16 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827290916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3827290916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.465313734
Short name T894
Test name
Test status
Simulation time 1164476650 ps
CPU time 6.49 seconds
Started Sep 18 02:46:20 PM UTC 24
Finished Sep 18 02:46:28 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465313734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.465313734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3121165843
Short name T915
Test name
Test status
Simulation time 34902517 ps
CPU time 1.16 seconds
Started Sep 18 02:46:57 PM UTC 24
Finished Sep 18 02:46:59 PM UTC 24
Peak memory 213592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121165843 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3121165843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2099645203
Short name T919
Test name
Test status
Simulation time 1541231383 ps
CPU time 16.9 seconds
Started Sep 18 02:46:44 PM UTC 24
Finished Sep 18 02:47:02 PM UTC 24
Peak memory 235020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099645203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2099645203
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.3333142088
Short name T899
Test name
Test status
Simulation time 15148062 ps
CPU time 0.94 seconds
Started Sep 18 02:46:32 PM UTC 24
Finished Sep 18 02:46:34 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333142088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3333142088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2093508562
Short name T991
Test name
Test status
Simulation time 171820401981 ps
CPU time 220.21 seconds
Started Sep 18 02:46:47 PM UTC 24
Finished Sep 18 02:50:30 PM UTC 24
Peak memory 261504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093508562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2093508562
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2946441016
Short name T996
Test name
Test status
Simulation time 22107182500 ps
CPU time 267.82 seconds
Started Sep 18 02:46:48 PM UTC 24
Finished Sep 18 02:51:20 PM UTC 24
Peak memory 267900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946441016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2946441016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.770244702
Short name T938
Test name
Test status
Simulation time 13463453143 ps
CPU time 28.57 seconds
Started Sep 18 02:46:53 PM UTC 24
Finished Sep 18 02:47:22 PM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770244702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.770244702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.499452785
Short name T927
Test name
Test status
Simulation time 17835379455 ps
CPU time 26.2 seconds
Started Sep 18 02:46:44 PM UTC 24
Finished Sep 18 02:47:11 PM UTC 24
Peak memory 247492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499452785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.499452785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1520100667
Short name T998
Test name
Test status
Simulation time 139953882762 ps
CPU time 280.86 seconds
Started Sep 18 02:46:45 PM UTC 24
Finished Sep 18 02:51:30 PM UTC 24
Peak memory 261504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520100667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.1520100667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1503455386
Short name T863
Test name
Test status
Simulation time 535186559 ps
CPU time 5.25 seconds
Started Sep 18 02:46:41 PM UTC 24
Finished Sep 18 02:46:47 PM UTC 24
Peak memory 234760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503455386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1503455386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2344520234
Short name T973
Test name
Test status
Simulation time 7247376105 ps
CPU time 82.36 seconds
Started Sep 18 02:46:41 PM UTC 24
Finished Sep 18 02:48:05 PM UTC 24
Peak memory 261720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344520234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2344520234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3483809435
Short name T904
Test name
Test status
Simulation time 63095742 ps
CPU time 2.49 seconds
Started Sep 18 02:46:39 PM UTC 24
Finished Sep 18 02:46:43 PM UTC 24
Peak memory 234292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483809435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.3483809435
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3721253407
Short name T906
Test name
Test status
Simulation time 313339593 ps
CPU time 4.91 seconds
Started Sep 18 02:46:39 PM UTC 24
Finished Sep 18 02:46:45 PM UTC 24
Peak memory 244500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721253407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3721253407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.4211340276
Short name T920
Test name
Test status
Simulation time 2185893715 ps
CPU time 14.34 seconds
Started Sep 18 02:46:47 PM UTC 24
Finished Sep 18 02:47:02 PM UTC 24
Peak memory 233460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211340276 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.4211340276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1747438511
Short name T1009
Test name
Test status
Simulation time 92754969745 ps
CPU time 632.34 seconds
Started Sep 18 02:46:55 PM UTC 24
Finished Sep 18 02:57:35 PM UTC 24
Peak memory 284092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747438511 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.1747438511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.957207338
Short name T918
Test name
Test status
Simulation time 4814577630 ps
CPU time 25.47 seconds
Started Sep 18 02:46:34 PM UTC 24
Finished Sep 18 02:47:01 PM UTC 24
Peak memory 227512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957207338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.957207338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1489210833
Short name T911
Test name
Test status
Simulation time 11643575199 ps
CPU time 23.23 seconds
Started Sep 18 02:46:33 PM UTC 24
Finished Sep 18 02:46:57 PM UTC 24
Peak memory 227532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489210833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1489210833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1460518031
Short name T903
Test name
Test status
Simulation time 56101614 ps
CPU time 1.3 seconds
Started Sep 18 02:46:36 PM UTC 24
Finished Sep 18 02:46:38 PM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460518031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1460518031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3892969511
Short name T902
Test name
Test status
Simulation time 137194140 ps
CPU time 1.26 seconds
Started Sep 18 02:46:36 PM UTC 24
Finished Sep 18 02:46:38 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892969511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3892969511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.990807825
Short name T912
Test name
Test status
Simulation time 13106417025 ps
CPU time 14.51 seconds
Started Sep 18 02:46:42 PM UTC 24
Finished Sep 18 02:46:58 PM UTC 24
Peak memory 241928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990807825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.990807825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.2534369871
Short name T932
Test name
Test status
Simulation time 23571276 ps
CPU time 1.13 seconds
Started Sep 18 02:47:12 PM UTC 24
Finished Sep 18 02:47:14 PM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534369871 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.2534369871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3958645138
Short name T925
Test name
Test status
Simulation time 198656051 ps
CPU time 2.84 seconds
Started Sep 18 02:47:03 PM UTC 24
Finished Sep 18 02:47:06 PM UTC 24
Peak memory 245316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958645138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3958645138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2116796687
Short name T914
Test name
Test status
Simulation time 104027436 ps
CPU time 1.15 seconds
Started Sep 18 02:46:57 PM UTC 24
Finished Sep 18 02:46:59 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116796687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2116796687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3069558279
Short name T934
Test name
Test status
Simulation time 301058067 ps
CPU time 7.69 seconds
Started Sep 18 02:47:08 PM UTC 24
Finished Sep 18 02:47:17 PM UTC 24
Peak memory 235012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069558279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3069558279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.1032100530
Short name T979
Test name
Test status
Simulation time 13573540060 ps
CPU time 86.42 seconds
Started Sep 18 02:47:09 PM UTC 24
Finished Sep 18 02:48:37 PM UTC 24
Peak memory 282108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032100530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1032100530
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.728419708
Short name T976
Test name
Test status
Simulation time 8203519426 ps
CPU time 62.93 seconds
Started Sep 18 02:47:09 PM UTC 24
Finished Sep 18 02:48:13 PM UTC 24
Peak memory 234940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728419708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.728419708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.760600428
Short name T929
Test name
Test status
Simulation time 2077105936 ps
CPU time 7.99 seconds
Started Sep 18 02:47:04 PM UTC 24
Finished Sep 18 02:47:13 PM UTC 24
Peak memory 234712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760600428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.760600428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1801167377
Short name T924
Test name
Test status
Simulation time 48887841 ps
CPU time 1.21 seconds
Started Sep 18 02:47:04 PM UTC 24
Finished Sep 18 02:47:06 PM UTC 24
Peak memory 226816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801167377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.1801167377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.2842089218
Short name T931
Test name
Test status
Simulation time 459452290 ps
CPU time 10.42 seconds
Started Sep 18 02:47:03 PM UTC 24
Finished Sep 18 02:47:14 PM UTC 24
Peak memory 244944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842089218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2842089218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.2083386336
Short name T926
Test name
Test status
Simulation time 516499858 ps
CPU time 6.24 seconds
Started Sep 18 02:47:03 PM UTC 24
Finished Sep 18 02:47:10 PM UTC 24
Peak memory 234972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083386336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2083386336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1162233385
Short name T928
Test name
Test status
Simulation time 737179254 ps
CPU time 10.88 seconds
Started Sep 18 02:47:01 PM UTC 24
Finished Sep 18 02:47:12 PM UTC 24
Peak memory 245068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162233385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.1162233385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.510284842
Short name T943
Test name
Test status
Simulation time 8785282368 ps
CPU time 29.1 seconds
Started Sep 18 02:47:01 PM UTC 24
Finished Sep 18 02:47:31 PM UTC 24
Peak memory 234528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510284842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.510284842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.709513982
Short name T930
Test name
Test status
Simulation time 280943233 ps
CPU time 6.09 seconds
Started Sep 18 02:47:07 PM UTC 24
Finished Sep 18 02:47:14 PM UTC 24
Peak memory 234704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709513982 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.709513982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1434394750
Short name T1010
Test name
Test status
Simulation time 62399584622 ps
CPU time 734.24 seconds
Started Sep 18 02:47:11 PM UTC 24
Finished Sep 18 02:59:35 PM UTC 24
Peak memory 275952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434394750 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.1434394750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.2989859915
Short name T949
Test name
Test status
Simulation time 10050627215 ps
CPU time 35.28 seconds
Started Sep 18 02:46:59 PM UTC 24
Finished Sep 18 02:47:35 PM UTC 24
Peak memory 227792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989859915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2989859915
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2680880898
Short name T921
Test name
Test status
Simulation time 308256677 ps
CPU time 4.4 seconds
Started Sep 18 02:46:57 PM UTC 24
Finished Sep 18 02:47:02 PM UTC 24
Peak memory 227336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680880898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2680880898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.46736932
Short name T922
Test name
Test status
Simulation time 2134677492 ps
CPU time 3.92 seconds
Started Sep 18 02:47:00 PM UTC 24
Finished Sep 18 02:47:05 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46736932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.46736932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.2041425993
Short name T916
Test name
Test status
Simulation time 161349746 ps
CPU time 1.27 seconds
Started Sep 18 02:46:59 PM UTC 24
Finished Sep 18 02:47:01 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041425993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2041425993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.3473842382
Short name T937
Test name
Test status
Simulation time 20679631544 ps
CPU time 16.95 seconds
Started Sep 18 02:47:03 PM UTC 24
Finished Sep 18 02:47:21 PM UTC 24
Peak memory 245076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473842382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3473842382
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.2580748648
Short name T950
Test name
Test status
Simulation time 25189364 ps
CPU time 1.16 seconds
Started Sep 18 02:47:33 PM UTC 24
Finished Sep 18 02:47:36 PM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580748648 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.2580748648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.916601751
Short name T944
Test name
Test status
Simulation time 318892379 ps
CPU time 7.26 seconds
Started Sep 18 02:47:22 PM UTC 24
Finished Sep 18 02:47:31 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916601751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.916601751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.1317397844
Short name T933
Test name
Test status
Simulation time 24726824 ps
CPU time 1.16 seconds
Started Sep 18 02:47:14 PM UTC 24
Finished Sep 18 02:47:16 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317397844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1317397844
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.1627617758
Short name T964
Test name
Test status
Simulation time 1017341547 ps
CPU time 20.84 seconds
Started Sep 18 02:47:28 PM UTC 24
Finished Sep 18 02:47:50 PM UTC 24
Peak memory 234704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627617758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1627617758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.922913777
Short name T1004
Test name
Test status
Simulation time 40349362983 ps
CPU time 359.74 seconds
Started Sep 18 02:47:29 PM UTC 24
Finished Sep 18 02:53:34 PM UTC 24
Peak memory 263676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922913777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.922913777
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2920888562
Short name T1001
Test name
Test status
Simulation time 33530439847 ps
CPU time 310.95 seconds
Started Sep 18 02:47:32 PM UTC 24
Finished Sep 18 02:52:47 PM UTC 24
Peak memory 261572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920888562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.2920888562
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.3824548279
Short name T970
Test name
Test status
Simulation time 6404701796 ps
CPU time 33.16 seconds
Started Sep 18 02:47:24 PM UTC 24
Finished Sep 18 02:47:59 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824548279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3824548279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.75472750
Short name T320
Test name
Test status
Simulation time 9473990826 ps
CPU time 65.57 seconds
Started Sep 18 02:47:25 PM UTC 24
Finished Sep 18 02:48:33 PM UTC 24
Peak memory 265800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75472750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.75472750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1590577732
Short name T941
Test name
Test status
Simulation time 205570272 ps
CPU time 6.59 seconds
Started Sep 18 02:47:19 PM UTC 24
Finished Sep 18 02:47:27 PM UTC 24
Peak memory 234248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590577732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1590577732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.858071256
Short name T968
Test name
Test status
Simulation time 3999223044 ps
CPU time 32.02 seconds
Started Sep 18 02:47:21 PM UTC 24
Finished Sep 18 02:47:55 PM UTC 24
Peak memory 234804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858071256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.858071256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3711902067
Short name T939
Test name
Test status
Simulation time 568118291 ps
CPU time 3.59 seconds
Started Sep 18 02:47:19 PM UTC 24
Finished Sep 18 02:47:24 PM UTC 24
Peak memory 244444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711902067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.3711902067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2642168263
Short name T947
Test name
Test status
Simulation time 1349112519 ps
CPU time 16.17 seconds
Started Sep 18 02:47:17 PM UTC 24
Finished Sep 18 02:47:34 PM UTC 24
Peak memory 244948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642168263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2642168263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1034385363
Short name T945
Test name
Test status
Simulation time 96225254 ps
CPU time 5.46 seconds
Started Sep 18 02:47:25 PM UTC 24
Finished Sep 18 02:47:32 PM UTC 24
Peak memory 233420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034385363 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.1034385363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.1822705876
Short name T948
Test name
Test status
Simulation time 67505519 ps
CPU time 1.63 seconds
Started Sep 18 02:47:32 PM UTC 24
Finished Sep 18 02:47:34 PM UTC 24
Peak memory 217008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822705876 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.1822705876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.3982044608
Short name T952
Test name
Test status
Simulation time 7552335814 ps
CPU time 19.45 seconds
Started Sep 18 02:47:16 PM UTC 24
Finished Sep 18 02:47:36 PM UTC 24
Peak memory 227536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982044608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3982044608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2838325478
Short name T957
Test name
Test status
Simulation time 14286080161 ps
CPU time 24.11 seconds
Started Sep 18 02:47:14 PM UTC 24
Finished Sep 18 02:47:39 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838325478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2838325478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.113401524
Short name T936
Test name
Test status
Simulation time 449948621 ps
CPU time 2.74 seconds
Started Sep 18 02:47:16 PM UTC 24
Finished Sep 18 02:47:20 PM UTC 24
Peak memory 227392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113401524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.113401524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3730266857
Short name T935
Test name
Test status
Simulation time 54233726 ps
CPU time 1.36 seconds
Started Sep 18 02:47:16 PM UTC 24
Finished Sep 18 02:47:18 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730266857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3730266857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3296435384
Short name T954
Test name
Test status
Simulation time 2593189569 ps
CPU time 15.32 seconds
Started Sep 18 02:47:21 PM UTC 24
Finished Sep 18 02:47:38 PM UTC 24
Peak memory 263424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296435384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3296435384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.1350812314
Short name T966
Test name
Test status
Simulation time 38334398 ps
CPU time 1.12 seconds
Started Sep 18 02:47:50 PM UTC 24
Finished Sep 18 02:47:52 PM UTC 24
Peak memory 213656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350812314 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.1350812314
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3249142160
Short name T971
Test name
Test status
Simulation time 1453756858 ps
CPU time 17.65 seconds
Started Sep 18 02:47:40 PM UTC 24
Finished Sep 18 02:47:59 PM UTC 24
Peak memory 245168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249142160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3249142160
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.2696176050
Short name T953
Test name
Test status
Simulation time 35044804 ps
CPU time 1.23 seconds
Started Sep 18 02:47:34 PM UTC 24
Finished Sep 18 02:47:37 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696176050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2696176050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.727360447
Short name T989
Test name
Test status
Simulation time 43630719786 ps
CPU time 156.71 seconds
Started Sep 18 02:47:45 PM UTC 24
Finished Sep 18 02:50:24 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727360447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.727360447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2070644155
Short name T995
Test name
Test status
Simulation time 18843789236 ps
CPU time 199.36 seconds
Started Sep 18 02:47:46 PM UTC 24
Finished Sep 18 02:51:08 PM UTC 24
Peak memory 261624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070644155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2070644155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.2167152290
Short name T980
Test name
Test status
Simulation time 35679180664 ps
CPU time 50.93 seconds
Started Sep 18 02:47:48 PM UTC 24
Finished Sep 18 02:48:41 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167152290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.2167152290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.578521163
Short name T967
Test name
Test status
Simulation time 919456740 ps
CPU time 11.39 seconds
Started Sep 18 02:47:42 PM UTC 24
Finished Sep 18 02:47:55 PM UTC 24
Peak memory 247048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578521163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.578521163
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.549481000
Short name T984
Test name
Test status
Simulation time 145568793608 ps
CPU time 88.61 seconds
Started Sep 18 02:47:42 PM UTC 24
Finished Sep 18 02:49:12 PM UTC 24
Peak memory 251212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549481000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.549481000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.3084823756
Short name T959
Test name
Test status
Simulation time 122864974 ps
CPU time 4.22 seconds
Started Sep 18 02:47:38 PM UTC 24
Finished Sep 18 02:47:44 PM UTC 24
Peak memory 234632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084823756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3084823756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.3179943029
Short name T969
Test name
Test status
Simulation time 1034047619 ps
CPU time 15.18 seconds
Started Sep 18 02:47:40 PM UTC 24
Finished Sep 18 02:47:57 PM UTC 24
Peak memory 234752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179943029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3179943029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2923684638
Short name T978
Test name
Test status
Simulation time 12443229073 ps
CPU time 55.05 seconds
Started Sep 18 02:47:38 PM UTC 24
Finished Sep 18 02:48:35 PM UTC 24
Peak memory 251264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923684638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.2923684638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.877509285
Short name T960
Test name
Test status
Simulation time 329746687 ps
CPU time 6.04 seconds
Started Sep 18 02:47:38 PM UTC 24
Finished Sep 18 02:47:45 PM UTC 24
Peak memory 234940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877509285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.877509285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2102983319
Short name T965
Test name
Test status
Simulation time 571636472 ps
CPU time 6.96 seconds
Started Sep 18 02:47:43 PM UTC 24
Finished Sep 18 02:47:51 PM UTC 24
Peak memory 231436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102983319 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.2102983319
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.647254094
Short name T994
Test name
Test status
Simulation time 15601303585 ps
CPU time 194 seconds
Started Sep 18 02:47:50 PM UTC 24
Finished Sep 18 02:51:08 PM UTC 24
Peak memory 278024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647254094 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.647254094
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.3280966925
Short name T972
Test name
Test status
Simulation time 1715200829 ps
CPU time 24.1 seconds
Started Sep 18 02:47:36 PM UTC 24
Finished Sep 18 02:48:02 PM UTC 24
Peak memory 227376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280966925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3280966925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1079243466
Short name T955
Test name
Test status
Simulation time 19655415 ps
CPU time 1.12 seconds
Started Sep 18 02:47:36 PM UTC 24
Finished Sep 18 02:47:39 PM UTC 24
Peak memory 215876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079243466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1079243466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.144285180
Short name T958
Test name
Test status
Simulation time 33289261 ps
CPU time 1.63 seconds
Started Sep 18 02:47:38 PM UTC 24
Finished Sep 18 02:47:41 PM UTC 24
Peak memory 227124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144285180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.144285180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3604437050
Short name T956
Test name
Test status
Simulation time 135454704 ps
CPU time 1.05 seconds
Started Sep 18 02:47:36 PM UTC 24
Finished Sep 18 02:47:39 PM UTC 24
Peak memory 216016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604437050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3604437050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1364465683
Short name T962
Test name
Test status
Simulation time 625117791 ps
CPU time 6.86 seconds
Started Sep 18 02:47:40 PM UTC 24
Finished Sep 18 02:47:48 PM UTC 24
Peak memory 244964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364465683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1364465683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2337827569
Short name T370
Test name
Test status
Simulation time 12238364 ps
CPU time 1.08 seconds
Started Sep 18 02:27:11 PM UTC 24
Finished Sep 18 02:27:14 PM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337827569 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2337827569
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3812580700
Short name T265
Test name
Test status
Simulation time 2688895620 ps
CPU time 26.5 seconds
Started Sep 18 02:26:54 PM UTC 24
Finished Sep 18 02:27:21 PM UTC 24
Peak memory 234880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812580700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3812580700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.3396731847
Short name T363
Test name
Test status
Simulation time 62982896 ps
CPU time 1.17 seconds
Started Sep 18 02:26:34 PM UTC 24
Finished Sep 18 02:26:36 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396731847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3396731847
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.709928192
Short name T260
Test name
Test status
Simulation time 69694683322 ps
CPU time 707.98 seconds
Started Sep 18 02:26:56 PM UTC 24
Finished Sep 18 02:38:53 PM UTC 24
Peak memory 281988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709928192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.709928192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2457450374
Short name T138
Test name
Test status
Simulation time 33000910999 ps
CPU time 180.43 seconds
Started Sep 18 02:26:58 PM UTC 24
Finished Sep 18 02:30:01 PM UTC 24
Peak memory 263676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457450374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2457450374
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2759612634
Short name T235
Test name
Test status
Simulation time 64089644155 ps
CPU time 869.78 seconds
Started Sep 18 02:26:59 PM UTC 24
Finished Sep 18 02:41:40 PM UTC 24
Peak memory 294336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759612634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.2759612634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2931157454
Short name T190
Test name
Test status
Simulation time 843643949 ps
CPU time 13.69 seconds
Started Sep 18 02:26:55 PM UTC 24
Finished Sep 18 02:27:09 PM UTC 24
Peak memory 247232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931157454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2931157454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.1812073758
Short name T263
Test name
Test status
Simulation time 115683284 ps
CPU time 6.11 seconds
Started Sep 18 02:26:45 PM UTC 24
Finished Sep 18 02:26:52 PM UTC 24
Peak memory 245192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812073758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1812073758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1923020545
Short name T97
Test name
Test status
Simulation time 3513113845 ps
CPU time 42 seconds
Started Sep 18 02:26:49 PM UTC 24
Finished Sep 18 02:27:33 PM UTC 24
Peak memory 245276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923020545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1923020545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.653148827
Short name T63
Test name
Test status
Simulation time 436715528 ps
CPU time 11.96 seconds
Started Sep 18 02:26:44 PM UTC 24
Finished Sep 18 02:26:57 PM UTC 24
Peak memory 251132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653148827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.653148827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.597382596
Short name T184
Test name
Test status
Simulation time 1049865013 ps
CPU time 8.77 seconds
Started Sep 18 02:26:44 PM UTC 24
Finished Sep 18 02:26:54 PM UTC 24
Peak memory 261656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597382596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.597382596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.4013556370
Short name T156
Test name
Test status
Simulation time 701582284 ps
CPU time 13.14 seconds
Started Sep 18 02:26:56 PM UTC 24
Finished Sep 18 02:27:10 PM UTC 24
Peak memory 229120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013556370 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.4013556370
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1955124328
Short name T350
Test name
Test status
Simulation time 491127004 ps
CPU time 4.35 seconds
Started Sep 18 02:26:38 PM UTC 24
Finished Sep 18 02:26:43 PM UTC 24
Peak memory 227400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955124328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1955124328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.819681575
Short name T368
Test name
Test status
Simulation time 5644292025 ps
CPU time 11.8 seconds
Started Sep 18 02:26:37 PM UTC 24
Finished Sep 18 02:26:50 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819681575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.819681575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3907815031
Short name T366
Test name
Test status
Simulation time 229336288 ps
CPU time 1.56 seconds
Started Sep 18 02:26:41 PM UTC 24
Finished Sep 18 02:26:44 PM UTC 24
Peak memory 217076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907815031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3907815031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.159819618
Short name T365
Test name
Test status
Simulation time 35355953 ps
CPU time 1.12 seconds
Started Sep 18 02:26:38 PM UTC 24
Finished Sep 18 02:26:40 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159819618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.159819618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3724817046
Short name T369
Test name
Test status
Simulation time 103720106 ps
CPU time 2.97 seconds
Started Sep 18 02:26:50 PM UTC 24
Finished Sep 18 02:26:55 PM UTC 24
Peak memory 233816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724817046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3724817046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1023600975
Short name T375
Test name
Test status
Simulation time 15616694 ps
CPU time 1.07 seconds
Started Sep 18 02:28:20 PM UTC 24
Finished Sep 18 02:28:22 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023600975 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1023600975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.470037041
Short name T374
Test name
Test status
Simulation time 5239665669 ps
CPU time 16.56 seconds
Started Sep 18 02:27:37 PM UTC 24
Finished Sep 18 02:27:55 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470037041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.470037041
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.283965174
Short name T371
Test name
Test status
Simulation time 20695213 ps
CPU time 1.24 seconds
Started Sep 18 02:27:15 PM UTC 24
Finished Sep 18 02:27:17 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283965174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.283965174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.711755482
Short name T213
Test name
Test status
Simulation time 16163128554 ps
CPU time 189.12 seconds
Started Sep 18 02:27:58 PM UTC 24
Finished Sep 18 02:31:10 PM UTC 24
Peak memory 261576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711755482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.711755482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2804502330
Short name T71
Test name
Test status
Simulation time 40896616887 ps
CPU time 203.64 seconds
Started Sep 18 02:27:58 PM UTC 24
Finished Sep 18 02:31:25 PM UTC 24
Peak memory 261560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804502330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2804502330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.929324533
Short name T137
Test name
Test status
Simulation time 4538216959 ps
CPU time 113.25 seconds
Started Sep 18 02:28:05 PM UTC 24
Finished Sep 18 02:30:01 PM UTC 24
Peak memory 261824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929324533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.929324533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1255407569
Short name T242
Test name
Test status
Simulation time 1788252381 ps
CPU time 38.14 seconds
Started Sep 18 02:27:44 PM UTC 24
Finished Sep 18 02:28:23 PM UTC 24
Peak memory 234968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255407569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1255407569
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.380904213
Short name T102
Test name
Test status
Simulation time 2503915010 ps
CPU time 58.03 seconds
Started Sep 18 02:27:56 PM UTC 24
Finished Sep 18 02:28:55 PM UTC 24
Peak memory 263616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380904213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.380904213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.1421611576
Short name T245
Test name
Test status
Simulation time 9117814154 ps
CPU time 26.8 seconds
Started Sep 18 02:27:28 PM UTC 24
Finished Sep 18 02:27:57 PM UTC 24
Peak memory 245256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421611576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1421611576
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.229370174
Short name T262
Test name
Test status
Simulation time 609129944 ps
CPU time 4.43 seconds
Started Sep 18 02:27:31 PM UTC 24
Finished Sep 18 02:27:37 PM UTC 24
Peak memory 245252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229370174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.229370174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3915254042
Short name T291
Test name
Test status
Simulation time 42198752636 ps
CPU time 59.77 seconds
Started Sep 18 02:27:28 PM UTC 24
Finished Sep 18 02:28:30 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915254042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.3915254042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1327707765
Short name T252
Test name
Test status
Simulation time 152150068 ps
CPU time 3.28 seconds
Started Sep 18 02:27:23 PM UTC 24
Finished Sep 18 02:27:28 PM UTC 24
Peak memory 245004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327707765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1327707765
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2166114490
Short name T157
Test name
Test status
Simulation time 706523652 ps
CPU time 6.63 seconds
Started Sep 18 02:27:57 PM UTC 24
Finished Sep 18 02:28:04 PM UTC 24
Peak memory 233320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166114490 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2166114490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2543571966
Short name T305
Test name
Test status
Simulation time 389505360545 ps
CPU time 992.68 seconds
Started Sep 18 02:28:14 PM UTC 24
Finished Sep 18 02:44:59 PM UTC 24
Peak memory 282048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543571966 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.2543571966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2774381145
Short name T337
Test name
Test status
Simulation time 17125794156 ps
CPU time 36.45 seconds
Started Sep 18 02:27:19 PM UTC 24
Finished Sep 18 02:27:57 PM UTC 24
Peak memory 227836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774381145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2774381145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.966902111
Short name T373
Test name
Test status
Simulation time 4883380131 ps
CPU time 8.6 seconds
Started Sep 18 02:27:18 PM UTC 24
Finished Sep 18 02:27:28 PM UTC 24
Peak memory 229560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966902111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.966902111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.3367736628
Short name T351
Test name
Test status
Simulation time 127722852 ps
CPU time 7.03 seconds
Started Sep 18 02:27:22 PM UTC 24
Finished Sep 18 02:27:30 PM UTC 24
Peak memory 227340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367736628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3367736628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.848342266
Short name T372
Test name
Test status
Simulation time 92993347 ps
CPU time 1.38 seconds
Started Sep 18 02:27:20 PM UTC 24
Finished Sep 18 02:27:23 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848342266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.848342266
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.2158065303
Short name T189
Test name
Test status
Simulation time 6524003563 ps
CPU time 8.1 seconds
Started Sep 18 02:27:33 PM UTC 24
Finished Sep 18 02:27:43 PM UTC 24
Peak memory 234768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158065303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2158065303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.777055106
Short name T382
Test name
Test status
Simulation time 11164550 ps
CPU time 1.08 seconds
Started Sep 18 02:28:45 PM UTC 24
Finished Sep 18 02:28:47 PM UTC 24
Peak memory 213660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777055106 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.777055106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.567331936
Short name T98
Test name
Test status
Simulation time 190493351 ps
CPU time 2.92 seconds
Started Sep 18 02:28:32 PM UTC 24
Finished Sep 18 02:28:36 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567331936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.567331936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.3491619952
Short name T376
Test name
Test status
Simulation time 41598313 ps
CPU time 1.14 seconds
Started Sep 18 02:28:23 PM UTC 24
Finished Sep 18 02:28:26 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491619952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3491619952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.3275899884
Short name T187
Test name
Test status
Simulation time 28804356323 ps
CPU time 120.54 seconds
Started Sep 18 02:28:37 PM UTC 24
Finished Sep 18 02:30:39 PM UTC 24
Peak memory 263548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275899884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3275899884
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2310210770
Short name T68
Test name
Test status
Simulation time 38228734842 ps
CPU time 305.68 seconds
Started Sep 18 02:28:38 PM UTC 24
Finished Sep 18 02:33:48 PM UTC 24
Peak memory 267772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310210770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2310210770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1344199796
Short name T251
Test name
Test status
Simulation time 36246393139 ps
CPU time 151.75 seconds
Started Sep 18 02:28:38 PM UTC 24
Finished Sep 18 02:31:12 PM UTC 24
Peak memory 263620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344199796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.1344199796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.2689872985
Short name T333
Test name
Test status
Simulation time 1624750088 ps
CPU time 28.53 seconds
Started Sep 18 02:28:33 PM UTC 24
Finished Sep 18 02:29:03 PM UTC 24
Peak memory 245192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689872985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2689872985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.3914381769
Short name T381
Test name
Test status
Simulation time 57938126 ps
CPU time 3.18 seconds
Started Sep 18 02:28:31 PM UTC 24
Finished Sep 18 02:28:35 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914381769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3914381769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.1391528855
Short name T264
Test name
Test status
Simulation time 4054158605 ps
CPU time 28.15 seconds
Started Sep 18 02:28:32 PM UTC 24
Finished Sep 18 02:29:02 PM UTC 24
Peak memory 263512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391528855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1391528855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1952106500
Short name T380
Test name
Test status
Simulation time 60614986 ps
CPU time 3.24 seconds
Started Sep 18 02:28:30 PM UTC 24
Finished Sep 18 02:28:34 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952106500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.1952106500
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.845741586
Short name T273
Test name
Test status
Simulation time 1042286513 ps
CPU time 7.37 seconds
Started Sep 18 02:28:28 PM UTC 24
Finished Sep 18 02:28:36 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845741586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.845741586
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2671225789
Short name T383
Test name
Test status
Simulation time 3574090584 ps
CPU time 9.66 seconds
Started Sep 18 02:28:37 PM UTC 24
Finished Sep 18 02:28:47 PM UTC 24
Peak memory 234040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671225789 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.2671225789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.128309149
Short name T35
Test name
Test status
Simulation time 47034835 ps
CPU time 1.65 seconds
Started Sep 18 02:28:42 PM UTC 24
Finished Sep 18 02:28:45 PM UTC 24
Peak memory 216952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128309149 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.128309149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.854505049
Short name T344
Test name
Test status
Simulation time 806615709 ps
CPU time 6.93 seconds
Started Sep 18 02:28:25 PM UTC 24
Finished Sep 18 02:28:33 PM UTC 24
Peak memory 227384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854505049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.854505049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1749069885
Short name T378
Test name
Test status
Simulation time 12990624 ps
CPU time 1.11 seconds
Started Sep 18 02:28:25 PM UTC 24
Finished Sep 18 02:28:27 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749069885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1749069885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.1671957826
Short name T347
Test name
Test status
Simulation time 371552405 ps
CPU time 2.75 seconds
Started Sep 18 02:28:28 PM UTC 24
Finished Sep 18 02:28:32 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671957826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1671957826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3048985226
Short name T379
Test name
Test status
Simulation time 130523644 ps
CPU time 1.23 seconds
Started Sep 18 02:28:27 PM UTC 24
Finished Sep 18 02:28:29 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048985226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3048985226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.1851378262
Short name T271
Test name
Test status
Simulation time 84852384 ps
CPU time 3.22 seconds
Started Sep 18 02:28:32 PM UTC 24
Finished Sep 18 02:28:36 PM UTC 24
Peak memory 234756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851378262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1851378262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.238353716
Short name T392
Test name
Test status
Simulation time 31959426 ps
CPU time 1.19 seconds
Started Sep 18 02:29:09 PM UTC 24
Finished Sep 18 02:29:11 PM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238353716 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.238353716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.4016982997
Short name T255
Test name
Test status
Simulation time 232005383 ps
CPU time 2.81 seconds
Started Sep 18 02:28:58 PM UTC 24
Finished Sep 18 02:29:02 PM UTC 24
Peak memory 244880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016982997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4016982997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.642995604
Short name T385
Test name
Test status
Simulation time 45216921 ps
CPU time 1.23 seconds
Started Sep 18 02:28:48 PM UTC 24
Finished Sep 18 02:28:50 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642995604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.642995604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1093314419
Short name T243
Test name
Test status
Simulation time 45558287079 ps
CPU time 216.06 seconds
Started Sep 18 02:29:03 PM UTC 24
Finished Sep 18 02:32:42 PM UTC 24
Peak memory 263740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093314419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1093314419
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.112772861
Short name T391
Test name
Test status
Simulation time 501705067 ps
CPU time 8.12 seconds
Started Sep 18 02:29:01 PM UTC 24
Finished Sep 18 02:29:11 PM UTC 24
Peak memory 244952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112772861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.112772861
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2711902525
Short name T85
Test name
Test status
Simulation time 38361784486 ps
CPU time 176.13 seconds
Started Sep 18 02:29:03 PM UTC 24
Finished Sep 18 02:32:02 PM UTC 24
Peak memory 261188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711902525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.2711902525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2923900864
Short name T389
Test name
Test status
Simulation time 1844438978 ps
CPU time 5.96 seconds
Started Sep 18 02:28:55 PM UTC 24
Finished Sep 18 02:29:02 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923900864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2923900864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3536427278
Short name T388
Test name
Test status
Simulation time 60973635 ps
CPU time 3.05 seconds
Started Sep 18 02:28:56 PM UTC 24
Finished Sep 18 02:29:00 PM UTC 24
Peak memory 244924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536427278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3536427278
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2533860978
Short name T241
Test name
Test status
Simulation time 1683734989 ps
CPU time 13.02 seconds
Started Sep 18 02:28:54 PM UTC 24
Finished Sep 18 02:29:08 PM UTC 24
Peak memory 244956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533860978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.2533860978
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1004769736
Short name T236
Test name
Test status
Simulation time 5180981582 ps
CPU time 10.13 seconds
Started Sep 18 02:28:54 PM UTC 24
Finished Sep 18 02:29:05 PM UTC 24
Peak memory 245076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004769736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1004769736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1510320
Short name T393
Test name
Test status
Simulation time 597872261 ps
CPU time 8.45 seconds
Started Sep 18 02:29:03 PM UTC 24
Finished Sep 18 02:29:12 PM UTC 24
Peak memory 231176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510320 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.1510320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.2350242834
Short name T36
Test name
Test status
Simulation time 124080388660 ps
CPU time 59.24 seconds
Started Sep 18 02:29:06 PM UTC 24
Finished Sep 18 02:30:07 PM UTC 24
Peak memory 229676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350242834 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.2350242834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2114944806
Short name T386
Test name
Test status
Simulation time 27432353 ps
CPU time 1.12 seconds
Started Sep 18 02:28:51 PM UTC 24
Finished Sep 18 02:28:53 PM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114944806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2114944806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1463878699
Short name T390
Test name
Test status
Simulation time 1203758927 ps
CPU time 12.82 seconds
Started Sep 18 02:28:51 PM UTC 24
Finished Sep 18 02:29:05 PM UTC 24
Peak memory 227380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463878699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1463878699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.356924082
Short name T348
Test name
Test status
Simulation time 814297214 ps
CPU time 3.16 seconds
Started Sep 18 02:28:54 PM UTC 24
Finished Sep 18 02:28:58 PM UTC 24
Peak memory 227532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356924082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.356924082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3150064170
Short name T387
Test name
Test status
Simulation time 94379217 ps
CPU time 1.1 seconds
Started Sep 18 02:28:52 PM UTC 24
Finished Sep 18 02:28:55 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150064170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3150064170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.1826510975
Short name T206
Test name
Test status
Simulation time 5598988182 ps
CPU time 12.65 seconds
Started Sep 18 02:28:57 PM UTC 24
Finished Sep 18 02:29:11 PM UTC 24
Peak memory 234880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826510975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1826510975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.618664106
Short name T140
Test name
Test status
Simulation time 11538836 ps
CPU time 1.09 seconds
Started Sep 18 02:30:08 PM UTC 24
Finished Sep 18 02:30:10 PM UTC 24
Peak memory 215644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618664106 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.618664106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.840276229
Short name T395
Test name
Test status
Simulation time 678658080 ps
CPU time 6 seconds
Started Sep 18 02:29:45 PM UTC 24
Finished Sep 18 02:29:52 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840276229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.840276229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.2484985805
Short name T377
Test name
Test status
Simulation time 53844665 ps
CPU time 1.23 seconds
Started Sep 18 02:29:11 PM UTC 24
Finished Sep 18 02:29:13 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484985805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2484985805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.56135359
Short name T230
Test name
Test status
Simulation time 144077107286 ps
CPU time 379.54 seconds
Started Sep 18 02:29:57 PM UTC 24
Finished Sep 18 02:36:22 PM UTC 24
Peak memory 263808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56135359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.56135359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1946888232
Short name T186
Test name
Test status
Simulation time 30225645041 ps
CPU time 110.7 seconds
Started Sep 18 02:30:01 PM UTC 24
Finished Sep 18 02:31:54 PM UTC 24
Peak memory 261896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946888232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.1946888232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.2622777245
Short name T396
Test name
Test status
Simulation time 1826224792 ps
CPU time 7.47 seconds
Started Sep 18 02:29:47 PM UTC 24
Finished Sep 18 02:29:56 PM UTC 24
Peak memory 244888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622777245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2622777245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.640087448
Short name T145
Test name
Test status
Simulation time 12465184694 ps
CPU time 41.42 seconds
Started Sep 18 02:29:54 PM UTC 24
Finished Sep 18 02:30:36 PM UTC 24
Peak memory 251196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640087448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.640087448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.1384019397
Short name T248
Test name
Test status
Simulation time 7545858089 ps
CPU time 26.11 seconds
Started Sep 18 02:29:19 PM UTC 24
Finished Sep 18 02:29:47 PM UTC 24
Peak memory 234876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384019397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1384019397
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3807399154
Short name T221
Test name
Test status
Simulation time 406644472 ps
CPU time 14.2 seconds
Started Sep 18 02:29:29 PM UTC 24
Finished Sep 18 02:29:45 PM UTC 24
Peak memory 251088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807399154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3807399154
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.967891564
Short name T286
Test name
Test status
Simulation time 565536635 ps
CPU time 10.71 seconds
Started Sep 18 02:29:19 PM UTC 24
Finished Sep 18 02:29:31 PM UTC 24
Peak memory 234896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967891564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.967891564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.4256080121
Short name T222
Test name
Test status
Simulation time 376954799 ps
CPU time 9.17 seconds
Started Sep 18 02:29:18 PM UTC 24
Finished Sep 18 02:29:29 PM UTC 24
Peak memory 234648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256080121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4256080121
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.827384519
Short name T139
Test name
Test status
Simulation time 3281472603 ps
CPU time 11.93 seconds
Started Sep 18 02:29:56 PM UTC 24
Finished Sep 18 02:30:09 PM UTC 24
Peak memory 233460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827384519 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.827384519
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.733577780
Short name T338
Test name
Test status
Simulation time 7733017292 ps
CPU time 39.05 seconds
Started Sep 18 02:29:14 PM UTC 24
Finished Sep 18 02:29:54 PM UTC 24
Peak memory 227768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733577780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.733577780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.900469564
Short name T394
Test name
Test status
Simulation time 446049597 ps
CPU time 4.85 seconds
Started Sep 18 02:29:12 PM UTC 24
Finished Sep 18 02:29:18 PM UTC 24
Peak memory 227592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900469564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.900469564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2996674860
Short name T384
Test name
Test status
Simulation time 94229726 ps
CPU time 1.92 seconds
Started Sep 18 02:29:16 PM UTC 24
Finished Sep 18 02:29:19 PM UTC 24
Peak memory 227136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996674860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2996674860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2429281648
Short name T364
Test name
Test status
Simulation time 15732030 ps
CPU time 0.96 seconds
Started Sep 18 02:29:15 PM UTC 24
Finished Sep 18 02:29:17 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429281648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2429281648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.190220718
Short name T269
Test name
Test status
Simulation time 26891647619 ps
CPU time 23.92 seconds
Started Sep 18 02:29:32 PM UTC 24
Finished Sep 18 02:29:58 PM UTC 24
Peak memory 229756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190220718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.190220718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%