| T842 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.720772687 |
|
|
Sep 24 02:46:37 PM UTC 24 |
Sep 24 02:46:47 PM UTC 24 |
1928019515 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2797047726 |
|
|
Sep 24 02:45:18 PM UTC 24 |
Sep 24 02:46:48 PM UTC 24 |
9778262201 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1711731141 |
|
|
Sep 24 02:46:46 PM UTC 24 |
Sep 24 02:46:48 PM UTC 24 |
37486378 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.921439286 |
|
|
Sep 24 02:44:15 PM UTC 24 |
Sep 24 02:46:49 PM UTC 24 |
123121110879 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2460834368 |
|
|
Sep 24 02:46:47 PM UTC 24 |
Sep 24 02:46:49 PM UTC 24 |
72083823 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2482302168 |
|
|
Sep 24 02:46:48 PM UTC 24 |
Sep 24 02:46:50 PM UTC 24 |
16086616 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.3741866728 |
|
|
Sep 24 02:46:30 PM UTC 24 |
Sep 24 02:46:50 PM UTC 24 |
4597901028 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.3389975967 |
|
|
Sep 24 02:45:58 PM UTC 24 |
Sep 24 02:46:50 PM UTC 24 |
17098795960 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3807178056 |
|
|
Sep 24 02:46:49 PM UTC 24 |
Sep 24 02:46:51 PM UTC 24 |
22732817 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.2412952478 |
|
|
Sep 24 02:46:34 PM UTC 24 |
Sep 24 02:46:51 PM UTC 24 |
7025321245 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.3397917000 |
|
|
Sep 24 02:46:50 PM UTC 24 |
Sep 24 02:46:57 PM UTC 24 |
552432200 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.1687475917 |
|
|
Sep 24 02:46:49 PM UTC 24 |
Sep 24 02:46:52 PM UTC 24 |
64362131 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2201236682 |
|
|
Sep 24 02:46:26 PM UTC 24 |
Sep 24 02:46:52 PM UTC 24 |
873756848 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.76543766 |
|
|
Sep 24 02:46:32 PM UTC 24 |
Sep 24 02:46:53 PM UTC 24 |
11464965899 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1525485890 |
|
|
Sep 24 02:46:50 PM UTC 24 |
Sep 24 02:46:55 PM UTC 24 |
314342271 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1150945035 |
|
|
Sep 24 02:46:51 PM UTC 24 |
Sep 24 02:46:56 PM UTC 24 |
181127423 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.4252055183 |
|
|
Sep 24 02:46:50 PM UTC 24 |
Sep 24 02:46:56 PM UTC 24 |
675429666 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2061487528 |
|
|
Sep 24 02:44:36 PM UTC 24 |
Sep 24 02:46:57 PM UTC 24 |
19269248274 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.618467289 |
|
|
Sep 24 02:43:51 PM UTC 24 |
Sep 24 02:46:58 PM UTC 24 |
71459072763 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1893508878 |
|
|
Sep 24 02:46:57 PM UTC 24 |
Sep 24 02:47:00 PM UTC 24 |
18387487 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.4042294172 |
|
|
Sep 24 02:46:51 PM UTC 24 |
Sep 24 02:47:00 PM UTC 24 |
1316769179 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.3917408 |
|
|
Sep 24 02:46:58 PM UTC 24 |
Sep 24 02:47:01 PM UTC 24 |
15175191 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.2123044656 |
|
|
Sep 24 02:42:03 PM UTC 24 |
Sep 24 02:47:02 PM UTC 24 |
40117788369 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3678394110 |
|
|
Sep 24 02:46:49 PM UTC 24 |
Sep 24 02:47:02 PM UTC 24 |
2016194041 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3214174778 |
|
|
Sep 24 02:47:01 PM UTC 24 |
Sep 24 02:47:03 PM UTC 24 |
87698197 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1812536902 |
|
|
Sep 24 02:46:48 PM UTC 24 |
Sep 24 02:47:03 PM UTC 24 |
12827725982 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.646596881 |
|
|
Sep 24 02:44:26 PM UTC 24 |
Sep 24 02:47:04 PM UTC 24 |
97981649432 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.1607953174 |
|
|
Sep 24 02:47:01 PM UTC 24 |
Sep 24 02:47:05 PM UTC 24 |
103193380 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.4238306994 |
|
|
Sep 24 02:46:53 PM UTC 24 |
Sep 24 02:47:05 PM UTC 24 |
549304817 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1806514531 |
|
|
Sep 24 02:46:59 PM UTC 24 |
Sep 24 02:47:06 PM UTC 24 |
3714925074 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.2171368893 |
|
|
Sep 24 02:46:52 PM UTC 24 |
Sep 24 02:47:08 PM UTC 24 |
6082042434 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.999121864 |
|
|
Sep 24 02:47:06 PM UTC 24 |
Sep 24 02:47:08 PM UTC 24 |
13136819 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.1668882877 |
|
|
Sep 24 02:47:00 PM UTC 24 |
Sep 24 02:47:11 PM UTC 24 |
2620080097 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.3998679020 |
|
|
Sep 24 02:47:06 PM UTC 24 |
Sep 24 02:47:13 PM UTC 24 |
117902686 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1305125026 |
|
|
Sep 24 02:47:06 PM UTC 24 |
Sep 24 02:47:14 PM UTC 24 |
481649019 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1977631519 |
|
|
Sep 24 02:43:32 PM UTC 24 |
Sep 24 02:47:14 PM UTC 24 |
86089246068 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.877311989 |
|
|
Sep 24 02:47:04 PM UTC 24 |
Sep 24 02:47:14 PM UTC 24 |
3918011383 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4220340871 |
|
|
Sep 24 02:47:07 PM UTC 24 |
Sep 24 02:47:15 PM UTC 24 |
545745355 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.1021754725 |
|
|
Sep 24 02:45:04 PM UTC 24 |
Sep 24 02:47:15 PM UTC 24 |
16806520063 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1691718197 |
|
|
Sep 24 02:47:03 PM UTC 24 |
Sep 24 02:47:16 PM UTC 24 |
1201561612 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1381836294 |
|
|
Sep 24 02:45:29 PM UTC 24 |
Sep 24 02:47:16 PM UTC 24 |
6261283957 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.2870435177 |
|
|
Sep 24 02:47:14 PM UTC 24 |
Sep 24 02:47:17 PM UTC 24 |
23788678 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.3419602296 |
|
|
Sep 24 02:45:06 PM UTC 24 |
Sep 24 02:47:19 PM UTC 24 |
31279744501 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2184573991 |
|
|
Sep 24 02:47:16 PM UTC 24 |
Sep 24 02:47:19 PM UTC 24 |
15790327 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.4057412134 |
|
|
Sep 24 02:47:16 PM UTC 24 |
Sep 24 02:47:19 PM UTC 24 |
59177390 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1156194635 |
|
|
Sep 24 02:47:17 PM UTC 24 |
Sep 24 02:47:20 PM UTC 24 |
14978156 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3660542531 |
|
|
Sep 24 02:45:22 PM UTC 24 |
Sep 24 02:47:21 PM UTC 24 |
25230168023 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.286392705 |
|
|
Sep 24 02:46:48 PM UTC 24 |
Sep 24 02:47:22 PM UTC 24 |
16423024983 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.1967385377 |
|
|
Sep 24 02:45:09 PM UTC 24 |
Sep 24 02:47:23 PM UTC 24 |
62253451414 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1310904084 |
|
|
Sep 24 02:47:03 PM UTC 24 |
Sep 24 02:47:24 PM UTC 24 |
4471155804 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2796660333 |
|
|
Sep 24 02:47:04 PM UTC 24 |
Sep 24 02:47:25 PM UTC 24 |
1068547636 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2926581471 |
|
|
Sep 24 02:47:21 PM UTC 24 |
Sep 24 02:47:27 PM UTC 24 |
333056594 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1113767426 |
|
|
Sep 24 02:47:17 PM UTC 24 |
Sep 24 02:47:30 PM UTC 24 |
4107004564 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.3818995617 |
|
|
Sep 24 02:47:19 PM UTC 24 |
Sep 24 02:47:32 PM UTC 24 |
2658707735 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.4201504621 |
|
|
Sep 24 02:47:23 PM UTC 24 |
Sep 24 02:47:33 PM UTC 24 |
300365143 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.747048629 |
|
|
Sep 24 02:47:21 PM UTC 24 |
Sep 24 02:47:33 PM UTC 24 |
4822740767 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.1187999844 |
|
|
Sep 24 02:41:20 PM UTC 24 |
Sep 24 02:47:33 PM UTC 24 |
37694902842 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.639805508 |
|
|
Sep 24 02:47:32 PM UTC 24 |
Sep 24 02:47:34 PM UTC 24 |
14145928 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.2467606404 |
|
|
Sep 24 02:47:34 PM UTC 24 |
Sep 24 02:47:36 PM UTC 24 |
26676001 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2326820501 |
|
|
Sep 24 02:47:35 PM UTC 24 |
Sep 24 02:47:37 PM UTC 24 |
12978553 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.545830007 |
|
|
Sep 24 02:47:37 PM UTC 24 |
Sep 24 02:47:39 PM UTC 24 |
67277613 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3457061783 |
|
|
Sep 24 02:47:26 PM UTC 24 |
Sep 24 02:47:41 PM UTC 24 |
1112895666 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.2001807960 |
|
|
Sep 24 02:46:05 PM UTC 24 |
Sep 24 02:47:41 PM UTC 24 |
3885056214 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.4284481192 |
|
|
Sep 24 02:47:38 PM UTC 24 |
Sep 24 02:47:42 PM UTC 24 |
965508934 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.2419424986 |
|
|
Sep 24 02:47:09 PM UTC 24 |
Sep 24 02:47:43 PM UTC 24 |
13764206085 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2467674524 |
|
|
Sep 24 02:47:18 PM UTC 24 |
Sep 24 02:47:44 PM UTC 24 |
4392512359 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2473430975 |
|
|
Sep 24 02:47:16 PM UTC 24 |
Sep 24 02:47:48 PM UTC 24 |
18962876235 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3330473007 |
|
|
Sep 24 02:47:44 PM UTC 24 |
Sep 24 02:47:48 PM UTC 24 |
225929669 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.3716297285 |
|
|
Sep 24 02:47:16 PM UTC 24 |
Sep 24 02:47:49 PM UTC 24 |
2092912228 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2480047255 |
|
|
Sep 24 02:47:40 PM UTC 24 |
Sep 24 02:47:51 PM UTC 24 |
1697599331 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.1681754855 |
|
|
Sep 24 02:47:42 PM UTC 24 |
Sep 24 02:47:54 PM UTC 24 |
1132563172 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2020973021 |
|
|
Sep 24 02:47:02 PM UTC 24 |
Sep 24 02:47:55 PM UTC 24 |
14318595481 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.636820323 |
|
|
Sep 24 02:47:41 PM UTC 24 |
Sep 24 02:47:55 PM UTC 24 |
717670271 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.2417049533 |
|
|
Sep 24 02:47:44 PM UTC 24 |
Sep 24 02:47:55 PM UTC 24 |
353390776 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.665993950 |
|
|
Sep 24 02:47:49 PM UTC 24 |
Sep 24 02:47:57 PM UTC 24 |
293679988 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3713436731 |
|
|
Sep 24 02:47:56 PM UTC 24 |
Sep 24 02:47:58 PM UTC 24 |
19736935 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1794563182 |
|
|
Sep 24 02:47:56 PM UTC 24 |
Sep 24 02:47:58 PM UTC 24 |
80778357 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.2277563863 |
|
|
Sep 24 02:47:35 PM UTC 24 |
Sep 24 02:47:59 PM UTC 24 |
1826984204 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.2536563584 |
|
|
Sep 24 02:47:57 PM UTC 24 |
Sep 24 02:47:59 PM UTC 24 |
33996887 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2214101812 |
|
|
Sep 24 02:47:59 PM UTC 24 |
Sep 24 02:48:02 PM UTC 24 |
437415526 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.22744322 |
|
|
Sep 24 02:47:45 PM UTC 24 |
Sep 24 02:48:03 PM UTC 24 |
1561111467 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3060725132 |
|
|
Sep 24 02:48:00 PM UTC 24 |
Sep 24 02:48:03 PM UTC 24 |
19379889 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1144785249 |
|
|
Sep 24 02:47:58 PM UTC 24 |
Sep 24 02:48:03 PM UTC 24 |
983660218 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2403829313 |
|
|
Sep 24 02:47:34 PM UTC 24 |
Sep 24 02:48:08 PM UTC 24 |
28802410386 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2834025636 |
|
|
Sep 24 02:37:00 PM UTC 24 |
Sep 24 02:48:09 PM UTC 24 |
62536544596 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1134167345 |
|
|
Sep 24 02:45:33 PM UTC 24 |
Sep 24 02:48:11 PM UTC 24 |
82709102530 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3011958330 |
|
|
Sep 24 02:48:02 PM UTC 24 |
Sep 24 02:48:11 PM UTC 24 |
4429525699 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2904430535 |
|
|
Sep 24 02:48:09 PM UTC 24 |
Sep 24 02:48:13 PM UTC 24 |
113299250 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.1395371445 |
|
|
Sep 24 02:45:42 PM UTC 24 |
Sep 24 02:48:15 PM UTC 24 |
91291839816 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2255965325 |
|
|
Sep 24 02:48:04 PM UTC 24 |
Sep 24 02:48:15 PM UTC 24 |
1334115114 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3102831288 |
|
|
Sep 24 02:48:11 PM UTC 24 |
Sep 24 02:48:17 PM UTC 24 |
306994859 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.2899903239 |
|
|
Sep 24 02:43:18 PM UTC 24 |
Sep 24 02:48:19 PM UTC 24 |
116408146126 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.2674365020 |
|
|
Sep 24 02:48:05 PM UTC 24 |
Sep 24 02:48:20 PM UTC 24 |
3012240710 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.968584502 |
|
|
Sep 24 02:45:08 PM UTC 24 |
Sep 24 02:48:20 PM UTC 24 |
46651823186 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3517891505 |
|
|
Sep 24 02:48:20 PM UTC 24 |
Sep 24 02:48:22 PM UTC 24 |
14997888 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3337439283 |
|
|
Sep 24 02:45:47 PM UTC 24 |
Sep 24 02:48:24 PM UTC 24 |
343427617466 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2817174674 |
|
|
Sep 24 02:48:23 PM UTC 24 |
Sep 24 02:48:25 PM UTC 24 |
35036685 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2695888772 |
|
|
Sep 24 02:48:16 PM UTC 24 |
Sep 24 02:48:27 PM UTC 24 |
1192937478 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.4268111020 |
|
|
Sep 24 02:46:56 PM UTC 24 |
Sep 24 02:48:27 PM UTC 24 |
4606165482 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.4144672203 |
|
|
Sep 24 02:48:25 PM UTC 24 |
Sep 24 02:48:27 PM UTC 24 |
68995974 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.3510680582 |
|
|
Sep 24 02:48:04 PM UTC 24 |
Sep 24 02:48:28 PM UTC 24 |
6861084697 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.2891845252 |
|
|
Sep 24 02:48:25 PM UTC 24 |
Sep 24 02:48:29 PM UTC 24 |
143243598 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.694636279 |
|
|
Sep 24 02:48:27 PM UTC 24 |
Sep 24 02:48:31 PM UTC 24 |
111053703 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.4162395174 |
|
|
Sep 24 02:48:30 PM UTC 24 |
Sep 24 02:48:34 PM UTC 24 |
56305090 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1303795616 |
|
|
Sep 24 02:48:30 PM UTC 24 |
Sep 24 02:48:35 PM UTC 24 |
120977766 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.4208501716 |
|
|
Sep 24 02:47:59 PM UTC 24 |
Sep 24 02:48:37 PM UTC 24 |
4059413684 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3505598075 |
|
|
Sep 24 02:47:12 PM UTC 24 |
Sep 24 02:48:42 PM UTC 24 |
9664327027 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.4064103520 |
|
|
Sep 24 02:48:36 PM UTC 24 |
Sep 24 02:48:43 PM UTC 24 |
294492232 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1622769498 |
|
|
Sep 24 02:48:30 PM UTC 24 |
Sep 24 02:48:43 PM UTC 24 |
1123164177 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.1580589588 |
|
|
Sep 24 02:48:10 PM UTC 24 |
Sep 24 02:48:44 PM UTC 24 |
9093030286 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3494101279 |
|
|
Sep 24 02:48:30 PM UTC 24 |
Sep 24 02:48:45 PM UTC 24 |
567407509 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2637088239 |
|
|
Sep 24 02:45:22 PM UTC 24 |
Sep 24 02:48:45 PM UTC 24 |
19576253886 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.2668286012 |
|
|
Sep 24 02:47:26 PM UTC 24 |
Sep 24 02:48:45 PM UTC 24 |
7261348839 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.2599322519 |
|
|
Sep 24 02:48:32 PM UTC 24 |
Sep 24 02:48:46 PM UTC 24 |
1126163100 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.813778770 |
|
|
Sep 24 02:48:48 PM UTC 24 |
Sep 24 02:48:50 PM UTC 24 |
47554595 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.2391054756 |
|
|
Sep 24 02:48:48 PM UTC 24 |
Sep 24 02:48:50 PM UTC 24 |
33643320 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.2843861545 |
|
|
Sep 24 02:48:48 PM UTC 24 |
Sep 24 02:48:50 PM UTC 24 |
22205935 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.3832473523 |
|
|
Sep 24 02:48:23 PM UTC 24 |
Sep 24 02:48:50 PM UTC 24 |
22735048120 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2457287676 |
|
|
Sep 24 02:48:48 PM UTC 24 |
Sep 24 02:48:51 PM UTC 24 |
48082715 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.12038007 |
|
|
Sep 24 02:48:25 PM UTC 24 |
Sep 24 02:48:52 PM UTC 24 |
3315013609 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.764250929 |
|
|
Sep 24 02:46:53 PM UTC 24 |
Sep 24 02:48:53 PM UTC 24 |
27995804736 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2533202482 |
|
|
Sep 24 02:48:14 PM UTC 24 |
Sep 24 02:48:53 PM UTC 24 |
2866485475 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.2456842160 |
|
|
Sep 24 02:43:52 PM UTC 24 |
Sep 24 02:48:54 PM UTC 24 |
27049922292 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.2761397989 |
|
|
Sep 24 02:48:52 PM UTC 24 |
Sep 24 02:48:56 PM UTC 24 |
75643607 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3703918913 |
|
|
Sep 24 02:48:48 PM UTC 24 |
Sep 24 02:48:56 PM UTC 24 |
1723582602 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3214639218 |
|
|
Sep 24 02:48:00 PM UTC 24 |
Sep 24 02:48:58 PM UTC 24 |
11327361393 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.1982577629 |
|
|
Sep 24 02:48:52 PM UTC 24 |
Sep 24 02:49:02 PM UTC 24 |
245282104 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1652882732 |
|
|
Sep 24 02:41:33 PM UTC 24 |
Sep 24 02:49:03 PM UTC 24 |
39422340630 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.625960494 |
|
|
Sep 24 02:47:48 PM UTC 24 |
Sep 24 02:49:04 PM UTC 24 |
3691879114 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1971144993 |
|
|
Sep 24 02:48:52 PM UTC 24 |
Sep 24 02:49:05 PM UTC 24 |
1259927152 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2788065094 |
|
|
Sep 24 02:48:55 PM UTC 24 |
Sep 24 02:49:05 PM UTC 24 |
1621839768 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3159468036 |
|
|
Sep 24 02:48:55 PM UTC 24 |
Sep 24 02:49:06 PM UTC 24 |
4415307269 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.786106491 |
|
|
Sep 24 02:42:53 PM UTC 24 |
Sep 24 02:50:46 PM UTC 24 |
100716580462 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1374660048 |
|
|
Sep 24 02:48:18 PM UTC 24 |
Sep 24 02:49:09 PM UTC 24 |
2941580383 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.295085897 |
|
|
Sep 24 02:49:07 PM UTC 24 |
Sep 24 02:49:09 PM UTC 24 |
13864326 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1990483055 |
|
|
Sep 24 02:49:07 PM UTC 24 |
Sep 24 02:49:09 PM UTC 24 |
43016479 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3065643027 |
|
|
Sep 24 02:49:07 PM UTC 24 |
Sep 24 02:49:09 PM UTC 24 |
80058587 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1121598275 |
|
|
Sep 24 02:48:53 PM UTC 24 |
Sep 24 02:49:12 PM UTC 24 |
2904814910 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.3597252300 |
|
|
Sep 24 02:48:30 PM UTC 24 |
Sep 24 02:49:12 PM UTC 24 |
9614218426 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2715596291 |
|
|
Sep 24 02:49:11 PM UTC 24 |
Sep 24 02:49:14 PM UTC 24 |
88969467 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.708855160 |
|
|
Sep 24 02:49:11 PM UTC 24 |
Sep 24 02:49:14 PM UTC 24 |
29464540 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1707563549 |
|
|
Sep 24 02:48:58 PM UTC 24 |
Sep 24 02:49:14 PM UTC 24 |
1439091408 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2146158174 |
|
|
Sep 24 02:48:52 PM UTC 24 |
Sep 24 02:49:17 PM UTC 24 |
69441390507 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.2030174557 |
|
|
Sep 24 02:46:42 PM UTC 24 |
Sep 24 02:49:17 PM UTC 24 |
39364709779 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.4262448834 |
|
|
Sep 24 02:49:13 PM UTC 24 |
Sep 24 02:49:19 PM UTC 24 |
171659641 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.270148359 |
|
|
Sep 24 02:49:15 PM UTC 24 |
Sep 24 02:49:21 PM UTC 24 |
89116580 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1976164719 |
|
|
Sep 24 02:49:15 PM UTC 24 |
Sep 24 02:49:23 PM UTC 24 |
2417549254 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.769772258 |
|
|
Sep 24 02:48:55 PM UTC 24 |
Sep 24 02:49:24 PM UTC 24 |
1088297732 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.3027116545 |
|
|
Sep 24 02:49:18 PM UTC 24 |
Sep 24 02:49:25 PM UTC 24 |
323622974 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2947909422 |
|
|
Sep 24 02:47:19 PM UTC 24 |
Sep 24 02:49:26 PM UTC 24 |
46216393478 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2451871268 |
|
|
Sep 24 02:48:55 PM UTC 24 |
Sep 24 02:49:28 PM UTC 24 |
7975605103 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.310588174 |
|
|
Sep 24 02:49:12 PM UTC 24 |
Sep 24 02:49:28 PM UTC 24 |
697459613 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.3597889345 |
|
|
Sep 24 02:49:25 PM UTC 24 |
Sep 24 02:49:28 PM UTC 24 |
13929398 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1335140486 |
|
|
Sep 24 02:49:15 PM UTC 24 |
Sep 24 02:49:38 PM UTC 24 |
5247704608 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.2728311458 |
|
|
Sep 24 02:45:22 PM UTC 24 |
Sep 24 02:49:38 PM UTC 24 |
56492968812 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3382531071 |
|
|
Sep 24 02:49:04 PM UTC 24 |
Sep 24 02:49:42 PM UTC 24 |
6475046020 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.818128937 |
|
|
Sep 24 02:46:05 PM UTC 24 |
Sep 24 02:49:50 PM UTC 24 |
18009988470 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.4223241037 |
|
|
Sep 24 02:49:04 PM UTC 24 |
Sep 24 02:49:51 PM UTC 24 |
1906672877 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.3728498537 |
|
|
Sep 24 02:48:58 PM UTC 24 |
Sep 24 02:49:56 PM UTC 24 |
3443698301 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2837282716 |
|
|
Sep 24 02:46:19 PM UTC 24 |
Sep 24 02:49:59 PM UTC 24 |
22165169671 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2434138005 |
|
|
Sep 24 02:49:15 PM UTC 24 |
Sep 24 02:50:00 PM UTC 24 |
33579424294 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3142139736 |
|
|
Sep 24 02:49:11 PM UTC 24 |
Sep 24 02:50:01 PM UTC 24 |
34552921678 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.2503565925 |
|
|
Sep 24 02:48:38 PM UTC 24 |
Sep 24 02:50:01 PM UTC 24 |
10647489450 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.353102782 |
|
|
Sep 24 02:49:21 PM UTC 24 |
Sep 24 02:50:02 PM UTC 24 |
50105055954 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2706475778 |
|
|
Sep 24 02:43:21 PM UTC 24 |
Sep 24 02:50:06 PM UTC 24 |
90676003072 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.111533503 |
|
|
Sep 24 02:49:07 PM UTC 24 |
Sep 24 02:50:16 PM UTC 24 |
42166393199 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.1388108206 |
|
|
Sep 24 02:46:56 PM UTC 24 |
Sep 24 02:50:21 PM UTC 24 |
212372172344 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.381293232 |
|
|
Sep 24 02:41:03 PM UTC 24 |
Sep 24 02:50:22 PM UTC 24 |
45753359039 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.4280750554 |
|
|
Sep 24 02:46:43 PM UTC 24 |
Sep 24 02:50:40 PM UTC 24 |
116186973977 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1705236725 |
|
|
Sep 24 02:47:52 PM UTC 24 |
Sep 24 02:50:42 PM UTC 24 |
20492462204 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3169402757 |
|
|
Sep 24 02:48:45 PM UTC 24 |
Sep 24 02:50:43 PM UTC 24 |
5652417064 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.4270103508 |
|
|
Sep 24 02:46:01 PM UTC 24 |
Sep 24 02:50:53 PM UTC 24 |
103417107258 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2982749643 |
|
|
Sep 24 02:49:00 PM UTC 24 |
Sep 24 02:50:54 PM UTC 24 |
22014885955 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.4124381450 |
|
|
Sep 24 02:46:53 PM UTC 24 |
Sep 24 02:50:56 PM UTC 24 |
20555376876 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2808735388 |
|
|
Sep 24 02:46:40 PM UTC 24 |
Sep 24 02:51:07 PM UTC 24 |
29987845915 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.2074576528 |
|
|
Sep 24 02:46:26 PM UTC 24 |
Sep 24 02:51:08 PM UTC 24 |
71535893610 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.204255989 |
|
|
Sep 24 02:45:49 PM UTC 24 |
Sep 24 02:51:09 PM UTC 24 |
23511370858 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3480684156 |
|
|
Sep 24 02:46:24 PM UTC 24 |
Sep 24 02:51:13 PM UTC 24 |
33453728984 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3973434468 |
|
|
Sep 24 02:46:45 PM UTC 24 |
Sep 24 02:51:13 PM UTC 24 |
102251235614 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.3346111279 |
|
|
Sep 24 02:48:45 PM UTC 24 |
Sep 24 02:51:23 PM UTC 24 |
11925728577 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2226651575 |
|
|
Sep 24 02:47:56 PM UTC 24 |
Sep 24 02:51:41 PM UTC 24 |
48429012519 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3017377887 |
|
|
Sep 24 02:47:23 PM UTC 24 |
Sep 24 02:51:42 PM UTC 24 |
91645448817 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2343831892 |
|
|
Sep 24 02:38:09 PM UTC 24 |
Sep 24 02:51:46 PM UTC 24 |
776707776552 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1910607649 |
|
|
Sep 24 02:48:36 PM UTC 24 |
Sep 24 02:51:48 PM UTC 24 |
78313385149 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.4220296415 |
|
|
Sep 24 02:48:17 PM UTC 24 |
Sep 24 02:51:54 PM UTC 24 |
17188954722 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2913259244 |
|
|
Sep 24 02:48:11 PM UTC 24 |
Sep 24 02:52:05 PM UTC 24 |
28109947250 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3122924096 |
|
|
Sep 24 02:49:18 PM UTC 24 |
Sep 24 02:52:10 PM UTC 24 |
27379310204 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3007971600 |
|
|
Sep 24 02:45:48 PM UTC 24 |
Sep 24 02:52:35 PM UTC 24 |
140374410598 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.318355497 |
|
|
Sep 24 02:46:54 PM UTC 24 |
Sep 24 02:52:37 PM UTC 24 |
148507496319 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.3098061055 |
|
|
Sep 24 02:44:54 PM UTC 24 |
Sep 24 02:52:40 PM UTC 24 |
176454782584 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3591828826 |
|
|
Sep 24 02:44:26 PM UTC 24 |
Sep 24 02:52:54 PM UTC 24 |
203883586076 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1096479895 |
|
|
Sep 24 02:43:43 PM UTC 24 |
Sep 24 02:53:04 PM UTC 24 |
150836046460 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2452062940 |
|
|
Sep 24 02:45:31 PM UTC 24 |
Sep 24 02:53:36 PM UTC 24 |
38162461682 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.3440409475 |
|
|
Sep 24 02:49:20 PM UTC 24 |
Sep 24 02:53:49 PM UTC 24 |
107212947039 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1644868891 |
|
|
Sep 24 02:47:28 PM UTC 24 |
Sep 24 02:54:12 PM UTC 24 |
406707510852 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2378250608 |
|
|
Sep 24 02:43:22 PM UTC 24 |
Sep 24 02:54:16 PM UTC 24 |
45689427436 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3739586777 |
|
|
Sep 24 02:49:21 PM UTC 24 |
Sep 24 02:54:18 PM UTC 24 |
191074018008 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3949116417 |
|
|
Sep 24 02:47:09 PM UTC 24 |
Sep 24 02:54:40 PM UTC 24 |
45373484525 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2999021140 |
|
|
Sep 24 02:47:26 PM UTC 24 |
Sep 24 02:54:54 PM UTC 24 |
48032789132 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3103521087 |
|
|
Sep 24 02:47:13 PM UTC 24 |
Sep 24 02:55:09 PM UTC 24 |
69779885313 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.756487451 |
|
|
Sep 24 02:47:50 PM UTC 24 |
Sep 24 02:55:25 PM UTC 24 |
60758696582 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.4222471256 |
|
|
Sep 24 02:49:25 PM UTC 24 |
Sep 24 02:56:19 PM UTC 24 |
140374930653 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3955457030 |
|
|
Sep 24 02:45:46 PM UTC 24 |
Sep 24 02:57:15 PM UTC 24 |
404031533045 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1239833811 |
|
|
Sep 24 02:48:45 PM UTC 24 |
Sep 24 02:58:33 PM UTC 24 |
1135238765251 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1111747685 |
|
|
Sep 24 02:47:31 PM UTC 24 |
Sep 24 02:59:04 PM UTC 24 |
82049076937 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.1903934087 |
|
|
Sep 24 02:43:43 PM UTC 24 |
Sep 24 03:02:04 PM UTC 24 |
1185659155752 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3633589193 |
|
|
Sep 24 02:09:17 PM UTC 24 |
Sep 24 02:09:20 PM UTC 24 |
101051899 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.400517513 |
|
|
Sep 24 02:09:26 PM UTC 24 |
Sep 24 02:09:28 PM UTC 24 |
46124226 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1377673583 |
|
|
Sep 24 02:09:29 PM UTC 24 |
Sep 24 02:09:31 PM UTC 24 |
24903466 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2833995282 |
|
|
Sep 24 02:09:32 PM UTC 24 |
Sep 24 02:09:36 PM UTC 24 |
113237743 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1555173361 |
|
|
Sep 24 02:09:36 PM UTC 24 |
Sep 24 02:09:39 PM UTC 24 |
106953303 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.1915466968 |
|
|
Sep 24 02:09:37 PM UTC 24 |
Sep 24 02:09:40 PM UTC 24 |
39043830 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3997137064 |
|
|
Sep 24 02:09:40 PM UTC 24 |
Sep 24 02:09:47 PM UTC 24 |
209230663 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1018966804 |
|
|
Sep 24 02:09:41 PM UTC 24 |
Sep 24 02:09:48 PM UTC 24 |
257589692 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3873356022 |
|
|
Sep 24 02:09:21 PM UTC 24 |
Sep 24 02:09:51 PM UTC 24 |
314223434 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3088043256 |
|
|
Sep 24 02:09:52 PM UTC 24 |
Sep 24 02:09:54 PM UTC 24 |
33912998 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2087470803 |
|
|
Sep 24 02:09:37 PM UTC 24 |
Sep 24 02:09:54 PM UTC 24 |
2331682432 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1316754190 |
|
|
Sep 24 02:09:47 PM UTC 24 |
Sep 24 02:09:57 PM UTC 24 |
291939934 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2230033336 |
|
|
Sep 24 02:09:55 PM UTC 24 |
Sep 24 02:09:57 PM UTC 24 |
39269016 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4031010710 |
|
|
Sep 24 02:09:37 PM UTC 24 |
Sep 24 02:09:58 PM UTC 24 |
2527031481 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1386537025 |
|
|
Sep 24 02:09:55 PM UTC 24 |
Sep 24 02:09:58 PM UTC 24 |
46984215 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3421432102 |
|
|
Sep 24 02:09:56 PM UTC 24 |
Sep 24 02:09:59 PM UTC 24 |
58726448 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1531213662 |
|
|
Sep 24 02:09:58 PM UTC 24 |
Sep 24 02:10:02 PM UTC 24 |
1685846808 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3313208026 |
|
|
Sep 24 02:09:59 PM UTC 24 |
Sep 24 02:10:05 PM UTC 24 |
109670919 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2564526935 |
|
|
Sep 24 02:09:59 PM UTC 24 |
Sep 24 02:10:06 PM UTC 24 |
101855264 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.1589938304 |
|
|
Sep 24 02:10:02 PM UTC 24 |
Sep 24 02:10:06 PM UTC 24 |
30590231 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2636680051 |
|
|
Sep 24 02:10:06 PM UTC 24 |
Sep 24 02:10:09 PM UTC 24 |
111911801 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2948587533 |
|
|
Sep 24 02:09:49 PM UTC 24 |
Sep 24 02:10:10 PM UTC 24 |
1123950475 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2942516836 |
|
|
Sep 24 02:10:08 PM UTC 24 |
Sep 24 02:10:10 PM UTC 24 |
14079756 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1722750032 |
|
|
Sep 24 02:10:10 PM UTC 24 |
Sep 24 02:10:12 PM UTC 24 |
17153656 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1635405501 |
|
|
Sep 24 02:10:11 PM UTC 24 |
Sep 24 02:10:13 PM UTC 24 |
99012398 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.571021823 |
|
|
Sep 24 02:10:11 PM UTC 24 |
Sep 24 02:10:15 PM UTC 24 |
988125407 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2862707857 |
|
|
Sep 24 02:09:59 PM UTC 24 |
Sep 24 02:10:16 PM UTC 24 |
2192875563 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1379037565 |
|
|
Sep 24 02:09:58 PM UTC 24 |
Sep 24 02:10:16 PM UTC 24 |
188147519 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.352454687 |
|
|
Sep 24 02:10:14 PM UTC 24 |
Sep 24 02:10:19 PM UTC 24 |
41433860 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1737708330 |
|
|
Sep 24 02:10:15 PM UTC 24 |
Sep 24 02:10:20 PM UTC 24 |
50645936 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.3360072564 |
|
|
Sep 24 02:10:17 PM UTC 24 |
Sep 24 02:10:20 PM UTC 24 |
123325281 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1464202781 |
|
|
Sep 24 02:10:20 PM UTC 24 |
Sep 24 02:10:22 PM UTC 24 |
35191182 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1696802393 |
|
|
Sep 24 02:10:21 PM UTC 24 |
Sep 24 02:10:23 PM UTC 24 |
14497514 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1154516843 |
|
|
Sep 24 02:10:21 PM UTC 24 |
Sep 24 02:10:25 PM UTC 24 |
23788036 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2741311902 |
|
|
Sep 24 02:10:23 PM UTC 24 |
Sep 24 02:10:27 PM UTC 24 |
45253980 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2210642860 |
|
|
Sep 24 02:10:25 PM UTC 24 |
Sep 24 02:10:28 PM UTC 24 |
208677720 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1823301421 |
|
|
Sep 24 02:10:13 PM UTC 24 |
Sep 24 02:10:31 PM UTC 24 |
191405491 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2869135193 |
|
|
Sep 24 02:10:29 PM UTC 24 |
Sep 24 02:10:36 PM UTC 24 |
60507443 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2818864701 |
|
|
Sep 24 02:10:32 PM UTC 24 |
Sep 24 02:10:36 PM UTC 24 |
93573180 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.3462847696 |
|
|
Sep 24 02:10:05 PM UTC 24 |
Sep 24 02:10:36 PM UTC 24 |
3397337590 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.4097613496 |
|
|
Sep 24 02:10:37 PM UTC 24 |
Sep 24 02:10:39 PM UTC 24 |
26937877 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1402578745 |
|
|
Sep 24 02:10:17 PM UTC 24 |
Sep 24 02:10:40 PM UTC 24 |
2178066029 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.1897234080 |
|
|
Sep 24 02:10:36 PM UTC 24 |
Sep 24 02:10:40 PM UTC 24 |
30225701 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3503988245 |
|
|
Sep 24 02:10:28 PM UTC 24 |
Sep 24 02:10:41 PM UTC 24 |
1228671726 ps |