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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.57 99.11


Total test records in report: 1131
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T1026 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.701202729 Sep 24 02:10:40 PM UTC 24 Sep 24 02:10:42 PM UTC 24 13591262 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2448388547 Sep 24 02:10:40 PM UTC 24 Sep 24 02:10:43 PM UTC 24 20650538 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3771273473 Sep 24 02:10:41 PM UTC 24 Sep 24 02:10:44 PM UTC 24 80050263 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1932611420 Sep 24 02:10:41 PM UTC 24 Sep 24 02:10:45 PM UTC 24 42786143 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4237038796 Sep 24 02:10:26 PM UTC 24 Sep 24 02:10:45 PM UTC 24 532044990 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.3466958116 Sep 24 02:10:14 PM UTC 24 Sep 24 02:10:46 PM UTC 24 6060802396 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.715455011 Sep 24 02:10:44 PM UTC 24 Sep 24 02:10:47 PM UTC 24 31341414 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.467703637 Sep 24 02:10:46 PM UTC 24 Sep 24 02:10:48 PM UTC 24 26810632 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3634688889 Sep 24 02:10:45 PM UTC 24 Sep 24 02:10:49 PM UTC 24 105638675 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3606693032 Sep 24 02:10:47 PM UTC 24 Sep 24 02:10:50 PM UTC 24 73759986 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.864819536 Sep 24 02:10:45 PM UTC 24 Sep 24 02:10:51 PM UTC 24 121782386 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3508588357 Sep 24 02:10:48 PM UTC 24 Sep 24 02:10:53 PM UTC 24 45089587 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.291500969 Sep 24 02:10:52 PM UTC 24 Sep 24 02:10:55 PM UTC 24 108701865 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2817478552 Sep 24 02:10:49 PM UTC 24 Sep 24 02:10:56 PM UTC 24 1000765581 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.560879457 Sep 24 02:10:50 PM UTC 24 Sep 24 02:10:58 PM UTC 24 218834224 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3760761424 Sep 24 02:10:54 PM UTC 24 Sep 24 02:10:59 PM UTC 24 40100411 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2486747317 Sep 24 02:10:55 PM UTC 24 Sep 24 02:11:00 PM UTC 24 93992957 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1210051441 Sep 24 02:10:51 PM UTC 24 Sep 24 02:11:01 PM UTC 24 108576461 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4218296403 Sep 24 02:10:43 PM UTC 24 Sep 24 02:11:02 PM UTC 24 1103976980 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2151749516 Sep 24 02:10:57 PM UTC 24 Sep 24 02:11:02 PM UTC 24 166320955 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.4193675083 Sep 24 02:11:01 PM UTC 24 Sep 24 02:11:03 PM UTC 24 19417125 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.144283423 Sep 24 02:10:59 PM UTC 24 Sep 24 02:11:04 PM UTC 24 203879691 ps
T1038 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3968491549 Sep 24 02:11:02 PM UTC 24 Sep 24 02:11:05 PM UTC 24 150679172 ps
T1039 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.1952274925 Sep 24 02:10:44 PM UTC 24 Sep 24 02:11:06 PM UTC 24 2416518108 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1427568504 Sep 24 02:11:03 PM UTC 24 Sep 24 02:11:06 PM UTC 24 68121920 ps
T1040 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2448137207 Sep 24 02:11:06 PM UTC 24 Sep 24 02:11:09 PM UTC 24 15659566 ps
T1041 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3080543407 Sep 24 02:11:03 PM UTC 24 Sep 24 02:11:09 PM UTC 24 185772871 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2679582813 Sep 24 02:11:04 PM UTC 24 Sep 24 02:11:09 PM UTC 24 38178700 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.353525936 Sep 24 02:10:46 PM UTC 24 Sep 24 02:11:09 PM UTC 24 560220726 ps
T1042 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3717255430 Sep 24 02:11:06 PM UTC 24 Sep 24 02:11:11 PM UTC 24 42225531 ps
T1043 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3192245156 Sep 24 02:11:10 PM UTC 24 Sep 24 02:11:12 PM UTC 24 13487332 ps
T1044 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3276209664 Sep 24 02:11:07 PM UTC 24 Sep 24 02:11:13 PM UTC 24 159075219 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1803433859 Sep 24 02:10:37 PM UTC 24 Sep 24 02:11:13 PM UTC 24 1092814437 ps
T1045 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3669992500 Sep 24 02:11:07 PM UTC 24 Sep 24 02:11:13 PM UTC 24 80669675 ps
T1046 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.2133021594 Sep 24 02:11:10 PM UTC 24 Sep 24 02:11:13 PM UTC 24 38818238 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.1435249552 Sep 24 02:11:05 PM UTC 24 Sep 24 02:11:14 PM UTC 24 215882185 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1567881415 Sep 24 02:11:10 PM UTC 24 Sep 24 02:11:14 PM UTC 24 67830168 ps
T1047 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1980617621 Sep 24 02:11:12 PM UTC 24 Sep 24 02:11:16 PM UTC 24 110380258 ps
T1048 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1784542678 Sep 24 02:11:14 PM UTC 24 Sep 24 02:11:16 PM UTC 24 12725563 ps
T1049 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.5222179 Sep 24 02:11:13 PM UTC 24 Sep 24 02:11:18 PM UTC 24 179755805 ps
T1050 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2141445519 Sep 24 02:11:14 PM UTC 24 Sep 24 02:11:19 PM UTC 24 154624433 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.931454879 Sep 24 02:11:15 PM UTC 24 Sep 24 02:11:20 PM UTC 24 291571248 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1716942402 Sep 24 02:11:15 PM UTC 24 Sep 24 02:11:21 PM UTC 24 405469355 ps
T1051 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.172340277 Sep 24 02:11:19 PM UTC 24 Sep 24 02:11:21 PM UTC 24 19873201 ps
T1052 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.326684180 Sep 24 02:11:14 PM UTC 24 Sep 24 02:11:22 PM UTC 24 99528269 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.28403871 Sep 24 02:11:20 PM UTC 24 Sep 24 02:11:24 PM UTC 24 304321549 ps
T1053 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1833324550 Sep 24 02:11:21 PM UTC 24 Sep 24 02:11:25 PM UTC 24 651025825 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2554982627 Sep 24 02:11:16 PM UTC 24 Sep 24 02:11:25 PM UTC 24 1745742680 ps
T1054 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2151434666 Sep 24 02:11:23 PM UTC 24 Sep 24 02:11:25 PM UTC 24 47126655 ps
T1055 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2511356560 Sep 24 02:11:22 PM UTC 24 Sep 24 02:11:28 PM UTC 24 61983774 ps
T1056 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1877199084 Sep 24 02:11:24 PM UTC 24 Sep 24 02:11:29 PM UTC 24 39229955 ps
T1057 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3665511228 Sep 24 02:11:25 PM UTC 24 Sep 24 02:11:29 PM UTC 24 104061237 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.3265148709 Sep 24 02:11:22 PM UTC 24 Sep 24 02:11:30 PM UTC 24 1174207075 ps
T1058 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.150092539 Sep 24 02:11:29 PM UTC 24 Sep 24 02:11:32 PM UTC 24 47210205 ps
T1059 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.201107380 Sep 24 02:11:30 PM UTC 24 Sep 24 02:11:33 PM UTC 24 54724406 ps
T1060 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2180957490 Sep 24 02:11:25 PM UTC 24 Sep 24 02:11:33 PM UTC 24 163833292 ps
T1061 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2616247309 Sep 24 02:11:26 PM UTC 24 Sep 24 02:11:34 PM UTC 24 74547913 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3949104429 Sep 24 02:11:31 PM UTC 24 Sep 24 02:11:34 PM UTC 24 161349381 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2249930676 Sep 24 02:11:00 PM UTC 24 Sep 24 02:11:35 PM UTC 24 11741593603 ps
T1062 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.969674890 Sep 24 02:11:32 PM UTC 24 Sep 24 02:11:36 PM UTC 24 89240611 ps
T1063 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.578681547 Sep 24 02:11:34 PM UTC 24 Sep 24 02:11:36 PM UTC 24 16156299 ps
T1064 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.472222373 Sep 24 02:11:10 PM UTC 24 Sep 24 02:11:38 PM UTC 24 5942180084 ps
T1065 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3971580263 Sep 24 02:11:33 PM UTC 24 Sep 24 02:11:39 PM UTC 24 467040485 ps
T1066 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3703216511 Sep 24 02:11:35 PM UTC 24 Sep 24 02:11:39 PM UTC 24 68713984 ps
T1067 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3854827987 Sep 24 02:11:35 PM UTC 24 Sep 24 02:11:40 PM UTC 24 100786218 ps
T1068 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2362408462 Sep 24 02:11:38 PM UTC 24 Sep 24 02:11:40 PM UTC 24 15476107 ps
T1069 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2633362674 Sep 24 02:11:36 PM UTC 24 Sep 24 02:11:40 PM UTC 24 88157694 ps
T1070 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2994240145 Sep 24 02:11:29 PM UTC 24 Sep 24 02:11:40 PM UTC 24 265563600 ps
T1071 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.842455831 Sep 24 02:11:35 PM UTC 24 Sep 24 02:11:42 PM UTC 24 157839510 ps
T1072 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3302008232 Sep 24 02:11:41 PM UTC 24 Sep 24 02:11:43 PM UTC 24 11403149 ps
T1073 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4069145473 Sep 24 02:11:40 PM UTC 24 Sep 24 02:11:43 PM UTC 24 31066540 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3039611799 Sep 24 02:11:40 PM UTC 24 Sep 24 02:11:44 PM UTC 24 317016956 ps
T1074 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.729974950 Sep 24 02:11:14 PM UTC 24 Sep 24 02:11:44 PM UTC 24 1794936885 ps
T1075 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.563185566 Sep 24 02:11:40 PM UTC 24 Sep 24 02:11:45 PM UTC 24 73774176 ps
T1076 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.395024267 Sep 24 02:11:41 PM UTC 24 Sep 24 02:11:45 PM UTC 24 101734347 ps
T1077 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3512076397 Sep 24 02:11:17 PM UTC 24 Sep 24 02:11:45 PM UTC 24 309915331 ps
T1078 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1360822166 Sep 24 02:11:41 PM UTC 24 Sep 24 02:11:46 PM UTC 24 84261424 ps
T1079 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1198002339 Sep 24 02:11:43 PM UTC 24 Sep 24 02:11:47 PM UTC 24 91486372 ps
T1080 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3849744086 Sep 24 02:11:45 PM UTC 24 Sep 24 02:11:48 PM UTC 24 119138616 ps
T1081 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.708788864 Sep 24 02:11:44 PM UTC 24 Sep 24 02:11:48 PM UTC 24 57443191 ps
T1082 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.503893038 Sep 24 02:11:45 PM UTC 24 Sep 24 02:11:49 PM UTC 24 109226754 ps
T1083 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.137268047 Sep 24 02:11:23 PM UTC 24 Sep 24 02:11:49 PM UTC 24 1200725526 ps
T1084 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.4221623728 Sep 24 02:11:45 PM UTC 24 Sep 24 02:11:50 PM UTC 24 85471162 ps
T1085 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.430287355 Sep 24 02:11:44 PM UTC 24 Sep 24 02:11:51 PM UTC 24 666590275 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1951534272 Sep 24 02:11:49 PM UTC 24 Sep 24 02:11:51 PM UTC 24 41887800 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2631617676 Sep 24 02:12:00 PM UTC 24 Sep 24 02:12:02 PM UTC 24 15375646 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.1480995032 Sep 24 02:11:49 PM UTC 24 Sep 24 02:11:52 PM UTC 24 39521696 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3621216189 Sep 24 02:11:47 PM UTC 24 Sep 24 02:11:53 PM UTC 24 53270987 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2327655095 Sep 24 02:11:34 PM UTC 24 Sep 24 02:11:53 PM UTC 24 1619800299 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3957781697 Sep 24 02:11:47 PM UTC 24 Sep 24 02:11:54 PM UTC 24 124629668 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.4138685942 Sep 24 02:11:52 PM UTC 24 Sep 24 02:11:54 PM UTC 24 14252352 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3588619455 Sep 24 02:11:50 PM UTC 24 Sep 24 02:11:55 PM UTC 24 155051348 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3632045282 Sep 24 02:11:50 PM UTC 24 Sep 24 02:11:55 PM UTC 24 221961848 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3663150597 Sep 24 02:11:52 PM UTC 24 Sep 24 02:11:56 PM UTC 24 27852906 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2327945926 Sep 24 02:11:53 PM UTC 24 Sep 24 02:11:57 PM UTC 24 305990318 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3643477841 Sep 24 02:11:56 PM UTC 24 Sep 24 02:11:58 PM UTC 24 27059176 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.596011516 Sep 24 02:11:55 PM UTC 24 Sep 24 02:11:58 PM UTC 24 46169293 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.645027854 Sep 24 02:11:56 PM UTC 24 Sep 24 02:11:58 PM UTC 24 11971013 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2644722208 Sep 24 02:11:45 PM UTC 24 Sep 24 02:11:58 PM UTC 24 317565993 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.2797465497 Sep 24 02:11:57 PM UTC 24 Sep 24 02:11:59 PM UTC 24 15875748 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2599145196 Sep 24 02:11:57 PM UTC 24 Sep 24 02:11:59 PM UTC 24 32550980 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3143453910 Sep 24 02:11:54 PM UTC 24 Sep 24 02:12:00 PM UTC 24 328093474 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.1244145397 Sep 24 02:11:58 PM UTC 24 Sep 24 02:12:00 PM UTC 24 20150401 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3551771624 Sep 24 02:11:51 PM UTC 24 Sep 24 02:12:00 PM UTC 24 492687811 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.4251449737 Sep 24 02:11:59 PM UTC 24 Sep 24 02:12:01 PM UTC 24 30622978 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3111164877 Sep 24 02:11:59 PM UTC 24 Sep 24 02:12:01 PM UTC 24 11719680 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1977904962 Sep 24 02:11:59 PM UTC 24 Sep 24 02:12:01 PM UTC 24 42496871 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2614006068 Sep 24 02:11:41 PM UTC 24 Sep 24 02:12:01 PM UTC 24 652437073 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.603409373 Sep 24 02:11:59 PM UTC 24 Sep 24 02:12:01 PM UTC 24 95447771 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.3111580500 Sep 24 02:12:00 PM UTC 24 Sep 24 02:12:02 PM UTC 24 41451768 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2953176005 Sep 24 02:12:00 PM UTC 24 Sep 24 02:12:02 PM UTC 24 22551654 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1877967944 Sep 24 02:12:01 PM UTC 24 Sep 24 02:12:03 PM UTC 24 61614537 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3538996955 Sep 24 02:12:01 PM UTC 24 Sep 24 02:12:04 PM UTC 24 22220155 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.113301136 Sep 24 02:11:38 PM UTC 24 Sep 24 02:12:04 PM UTC 24 1120807577 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3390151696 Sep 24 02:12:01 PM UTC 24 Sep 24 02:12:04 PM UTC 24 134755350 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3197098643 Sep 24 02:12:03 PM UTC 24 Sep 24 02:12:05 PM UTC 24 20936469 ps
T1117 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3662970193 Sep 24 02:12:03 PM UTC 24 Sep 24 02:12:05 PM UTC 24 163306116 ps
T1118 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3896757305 Sep 24 02:12:03 PM UTC 24 Sep 24 02:12:05 PM UTC 24 38041600 ps
T1119 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.58369308 Sep 24 02:12:03 PM UTC 24 Sep 24 02:12:05 PM UTC 24 18299526 ps
T1120 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.269475011 Sep 24 02:12:04 PM UTC 24 Sep 24 02:12:06 PM UTC 24 12737284 ps
T1121 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2189308537 Sep 24 02:12:04 PM UTC 24 Sep 24 02:12:06 PM UTC 24 13109027 ps
T1122 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2138726186 Sep 24 02:12:04 PM UTC 24 Sep 24 02:12:06 PM UTC 24 70235208 ps
T1123 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1833735957 Sep 24 02:12:04 PM UTC 24 Sep 24 02:12:06 PM UTC 24 36866007 ps
T1124 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2161931252 Sep 24 02:12:04 PM UTC 24 Sep 24 02:12:06 PM UTC 24 15424876 ps
T1125 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1359293012 Sep 24 02:12:04 PM UTC 24 Sep 24 02:12:06 PM UTC 24 33477306 ps
T1126 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.4009847944 Sep 24 02:12:04 PM UTC 24 Sep 24 02:12:06 PM UTC 24 17388967 ps
T1127 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.454565693 Sep 24 02:12:04 PM UTC 24 Sep 24 02:12:07 PM UTC 24 17805860 ps
T1128 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.4215327818 Sep 24 02:11:48 PM UTC 24 Sep 24 02:12:07 PM UTC 24 235178554 ps
T1129 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2867905864 Sep 24 02:12:05 PM UTC 24 Sep 24 02:12:08 PM UTC 24 124932323 ps
T1130 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2014302545 Sep 24 02:12:06 PM UTC 24 Sep 24 02:12:08 PM UTC 24 30626682 ps
T1131 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.1483138627 Sep 24 02:11:51 PM UTC 24 Sep 24 02:12:25 PM UTC 24 4208759235 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.3517095133
Short name T10
Test name
Test status
Simulation time 86823295 ps
CPU time 2.49 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:36:46 PM UTC 24
Peak memory 234636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517095133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3517095133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2243455198
Short name T53
Test name
Test status
Simulation time 3646869213 ps
CPU time 33.42 seconds
Started Sep 24 02:36:58 PM UTC 24
Finished Sep 24 02:37:33 PM UTC 24
Peak memory 267760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243455198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.2243455198
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.1554316974
Short name T11
Test name
Test status
Simulation time 41603539887 ps
CPU time 31.5 seconds
Started Sep 24 02:37:05 PM UTC 24
Finished Sep 24 02:37:38 PM UTC 24
Peak memory 245376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554316974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1554316974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.833899218
Short name T30
Test name
Test status
Simulation time 3160611881 ps
CPU time 17.95 seconds
Started Sep 24 02:36:45 PM UTC 24
Finished Sep 24 02:37:04 PM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833899218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.833899218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.3751890145
Short name T36
Test name
Test status
Simulation time 2365292907 ps
CPU time 30.29 seconds
Started Sep 24 02:37:29 PM UTC 24
Finished Sep 24 02:38:00 PM UTC 24
Peak memory 249216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751890145 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.3751890145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.1736137550
Short name T46
Test name
Test status
Simulation time 4949992014 ps
CPU time 83.06 seconds
Started Sep 24 02:37:12 PM UTC 24
Finished Sep 24 02:38:37 PM UTC 24
Peak memory 261764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736137550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1736137550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2059375951
Short name T237
Test name
Test status
Simulation time 13666734385 ps
CPU time 179.06 seconds
Started Sep 24 02:36:49 PM UTC 24
Finished Sep 24 02:39:52 PM UTC 24
Peak memory 277960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059375951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2059375951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3313208026
Short name T140
Test name
Test status
Simulation time 109670919 ps
CPU time 4.5 seconds
Started Sep 24 02:09:59 PM UTC 24
Finished Sep 24 02:10:05 PM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3313208026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.spi_device_csr_mem_rw_with_rand_reset.3313208026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.1405946881
Short name T47
Test name
Test status
Simulation time 18095268075 ps
CPU time 110.69 seconds
Started Sep 24 02:36:58 PM UTC 24
Finished Sep 24 02:38:51 PM UTC 24
Peak memory 277828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405946881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1405946881
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3438002130
Short name T269
Test name
Test status
Simulation time 85997836860 ps
CPU time 239.92 seconds
Started Sep 24 02:39:02 PM UTC 24
Finished Sep 24 02:43:06 PM UTC 24
Peak memory 267964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438002130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.3438002130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.2767045241
Short name T21
Test name
Test status
Simulation time 226801753 ps
CPU time 6.73 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:36:51 PM UTC 24
Peak memory 234684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767045241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2767045241
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.812937053
Short name T3
Test name
Test status
Simulation time 19521552 ps
CPU time 1.19 seconds
Started Sep 24 02:36:40 PM UTC 24
Finished Sep 24 02:36:43 PM UTC 24
Peak memory 226928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812937053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.812937053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.1661297508
Short name T41
Test name
Test status
Simulation time 9295456937 ps
CPU time 29.47 seconds
Started Sep 24 02:36:40 PM UTC 24
Finished Sep 24 02:37:11 PM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661297508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1661297508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2178357665
Short name T9
Test name
Test status
Simulation time 277060707 ps
CPU time 1.72 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:36:46 PM UTC 24
Peak memory 256992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178357665 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2178357665
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2326625705
Short name T207
Test name
Test status
Simulation time 77407405070 ps
CPU time 170.51 seconds
Started Sep 24 02:37:40 PM UTC 24
Finished Sep 24 02:40:33 PM UTC 24
Peak memory 261568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326625705 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2326625705
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1173557257
Short name T82
Test name
Test status
Simulation time 45950090062 ps
CPU time 550.31 seconds
Started Sep 24 02:37:14 PM UTC 24
Finished Sep 24 02:46:32 PM UTC 24
Peak memory 300540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173557257 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.1173557257
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3993152290
Short name T253
Test name
Test status
Simulation time 17455897817 ps
CPU time 115.62 seconds
Started Sep 24 02:42:14 PM UTC 24
Finished Sep 24 02:44:12 PM UTC 24
Peak memory 261564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993152290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.3993152290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.4133610143
Short name T19
Test name
Test status
Simulation time 2477869989 ps
CPU time 8.46 seconds
Started Sep 24 02:36:40 PM UTC 24
Finished Sep 24 02:36:50 PM UTC 24
Peak memory 227716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133610143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4133610143
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.763980545
Short name T51
Test name
Test status
Simulation time 27371663292 ps
CPU time 25.76 seconds
Started Sep 24 02:37:06 PM UTC 24
Finished Sep 24 02:37:34 PM UTC 24
Peak memory 251204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763980545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.763980545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.329286619
Short name T321
Test name
Test status
Simulation time 21086809125 ps
CPU time 166.21 seconds
Started Sep 24 02:42:03 PM UTC 24
Finished Sep 24 02:44:52 PM UTC 24
Peak memory 284092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329286619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.329286619
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2019934028
Short name T243
Test name
Test status
Simulation time 93516574198 ps
CPU time 110.38 seconds
Started Sep 24 02:37:57 PM UTC 24
Finished Sep 24 02:39:50 PM UTC 24
Peak memory 263868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019934028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.2019934028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.794050126
Short name T233
Test name
Test status
Simulation time 9633673483 ps
CPU time 137.6 seconds
Started Sep 24 02:41:01 PM UTC 24
Finished Sep 24 02:43:21 PM UTC 24
Peak memory 265600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794050126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.794050126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2249930676
Short name T352
Test name
Test status
Simulation time 11741593603 ps
CPU time 33.44 seconds
Started Sep 24 02:11:00 PM UTC 24
Finished Sep 24 02:11:35 PM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249930676 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.2249930676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.306772871
Short name T224
Test name
Test status
Simulation time 55879157624 ps
CPU time 170.48 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:39:37 PM UTC 24
Peak memory 261828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306772871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.306772871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.300383915
Short name T320
Test name
Test status
Simulation time 5103165744 ps
CPU time 86.72 seconds
Started Sep 24 02:42:45 PM UTC 24
Finished Sep 24 02:44:14 PM UTC 24
Peak memory 267660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300383915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.300383915
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1316754190
Short name T139
Test name
Test status
Simulation time 291939934 ps
CPU time 8.01 seconds
Started Sep 24 02:09:47 PM UTC 24
Finished Sep 24 02:09:57 PM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316754190 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1316754190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.1915466968
Short name T162
Test name
Test status
Simulation time 39043830 ps
CPU time 1.88 seconds
Started Sep 24 02:09:37 PM UTC 24
Finished Sep 24 02:09:40 PM UTC 24
Peak memory 216168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915466968 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1915466968
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.1742354326
Short name T68
Test name
Test status
Simulation time 16469322462 ps
CPU time 112.59 seconds
Started Sep 24 02:37:27 PM UTC 24
Finished Sep 24 02:39:22 PM UTC 24
Peak memory 273732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742354326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1742354326
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.2045600797
Short name T280
Test name
Test status
Simulation time 14486793035 ps
CPU time 54.54 seconds
Started Sep 24 02:40:35 PM UTC 24
Finished Sep 24 02:41:32 PM UTC 24
Peak memory 261628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045600797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.2045600797
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2514936309
Short name T219
Test name
Test status
Simulation time 20620395357 ps
CPU time 108.25 seconds
Started Sep 24 02:37:40 PM UTC 24
Finished Sep 24 02:39:30 PM UTC 24
Peak memory 261840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514936309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.2514936309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1328208079
Short name T315
Test name
Test status
Simulation time 3432336876 ps
CPU time 98.61 seconds
Started Sep 24 02:44:18 PM UTC 24
Finished Sep 24 02:45:58 PM UTC 24
Peak memory 276028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328208079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.1328208079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1532269479
Short name T313
Test name
Test status
Simulation time 154349002133 ps
CPU time 414.81 seconds
Started Sep 24 02:36:49 PM UTC 24
Finished Sep 24 02:43:50 PM UTC 24
Peak memory 277948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532269479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.1532269479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2706475778
Short name T347
Test name
Test status
Simulation time 90676003072 ps
CPU time 399.12 seconds
Started Sep 24 02:43:21 PM UTC 24
Finished Sep 24 02:50:06 PM UTC 24
Peak memory 261452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706475778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2706475778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.2331695101
Short name T45
Test name
Test status
Simulation time 4193361073 ps
CPU time 45.26 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:37:30 PM UTC 24
Peak memory 265484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331695101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2331695101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1381836294
Short name T406
Test name
Test status
Simulation time 6261283957 ps
CPU time 104.97 seconds
Started Sep 24 02:45:29 PM UTC 24
Finished Sep 24 02:47:16 PM UTC 24
Peak memory 263500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381836294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1381836294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1058119798
Short name T7
Test name
Test status
Simulation time 16959608 ps
CPU time 1.17 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:36:46 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058119798 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1058119798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2845527380
Short name T371
Test name
Test status
Simulation time 6593863436 ps
CPU time 108.46 seconds
Started Sep 24 02:39:02 PM UTC 24
Finished Sep 24 02:40:53 PM UTC 24
Peak memory 265992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845527380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2845527380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.806879276
Short name T360
Test name
Test status
Simulation time 3031680899 ps
CPU time 63.32 seconds
Started Sep 24 02:40:54 PM UTC 24
Finished Sep 24 02:41:59 PM UTC 24
Peak memory 267704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806879276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.806879276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3796253443
Short name T64
Test name
Test status
Simulation time 1721729632 ps
CPU time 10.48 seconds
Started Sep 24 02:37:35 PM UTC 24
Finished Sep 24 02:37:46 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796253443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.3796253443
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3337439283
Short name T83
Test name
Test status
Simulation time 343427617466 ps
CPU time 154.24 seconds
Started Sep 24 02:45:47 PM UTC 24
Finished Sep 24 02:48:24 PM UTC 24
Peak memory 268032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337439283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3337439283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2451871268
Short name T424
Test name
Test status
Simulation time 7975605103 ps
CPU time 31.17 seconds
Started Sep 24 02:48:55 PM UTC 24
Finished Sep 24 02:49:28 PM UTC 24
Peak memory 234816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451871268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2451871268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1820761616
Short name T110
Test name
Test status
Simulation time 6759576051 ps
CPU time 30.03 seconds
Started Sep 24 02:37:48 PM UTC 24
Finished Sep 24 02:38:20 PM UTC 24
Peak memory 251200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820761616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1820761616
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2343831892
Short name T306
Test name
Test status
Simulation time 776707776552 ps
CPU time 805.67 seconds
Started Sep 24 02:38:09 PM UTC 24
Finished Sep 24 02:51:46 PM UTC 24
Peak memory 283956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343831892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.2343831892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.3411370573
Short name T100
Test name
Test status
Simulation time 196646731199 ps
CPU time 132.56 seconds
Started Sep 24 02:36:57 PM UTC 24
Finished Sep 24 02:39:12 PM UTC 24
Peak memory 261696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411370573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.3411370573
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.560879457
Short name T153
Test name
Test status
Simulation time 218834224 ps
CPU time 6.78 seconds
Started Sep 24 02:10:50 PM UTC 24
Finished Sep 24 02:10:58 PM UTC 24
Peak memory 225608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560879457 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.560879457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3873356022
Short name T108
Test name
Test status
Simulation time 314223434 ps
CPU time 29.12 seconds
Started Sep 24 02:09:21 PM UTC 24
Finished Sep 24 02:09:51 PM UTC 24
Peak memory 225440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873356022 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.3873356022
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.191011434
Short name T48
Test name
Test status
Simulation time 4571888159 ps
CPU time 69.7 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:37:55 PM UTC 24
Peak memory 265556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191011434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.191011434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3721421719
Short name T354
Test name
Test status
Simulation time 255808639 ps
CPU time 4.36 seconds
Started Sep 24 02:43:30 PM UTC 24
Finished Sep 24 02:43:35 PM UTC 24
Peak memory 244880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721421719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3721421719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.561699383
Short name T311
Test name
Test status
Simulation time 52805431391 ps
CPU time 97.95 seconds
Started Sep 24 02:43:52 PM UTC 24
Finished Sep 24 02:45:32 PM UTC 24
Peak memory 265664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561699383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.561699383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.664601675
Short name T339
Test name
Test status
Simulation time 11443247556 ps
CPU time 114.74 seconds
Started Sep 24 02:44:33 PM UTC 24
Finished Sep 24 02:46:30 PM UTC 24
Peak memory 280124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664601675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.664601675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.510697928
Short name T147
Test name
Test status
Simulation time 356360601 ps
CPU time 6.66 seconds
Started Sep 24 02:37:48 PM UTC 24
Finished Sep 24 02:37:56 PM UTC 24
Peak memory 234664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510697928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.510697928
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3093652706
Short name T262
Test name
Test status
Simulation time 5171331748 ps
CPU time 16.32 seconds
Started Sep 24 02:41:13 PM UTC 24
Finished Sep 24 02:41:31 PM UTC 24
Peak memory 245264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093652706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3093652706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3949116417
Short name T1005
Test name
Test status
Simulation time 45373484525 ps
CPU time 443.4 seconds
Started Sep 24 02:47:09 PM UTC 24
Finished Sep 24 02:54:40 PM UTC 24
Peak memory 265664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949116417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3949116417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2948587533
Short name T141
Test name
Test status
Simulation time 1123950475 ps
CPU time 19.74 seconds
Started Sep 24 02:09:49 PM UTC 24
Finished Sep 24 02:10:10 PM UTC 24
Peak memory 227484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948587533 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.2948587533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1491862286
Short name T54
Test name
Test status
Simulation time 2450908976 ps
CPU time 10.62 seconds
Started Sep 24 02:36:48 PM UTC 24
Finished Sep 24 02:37:00 PM UTC 24
Peak memory 245120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491862286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1491862286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3989657181
Short name T22
Test name
Test status
Simulation time 1188005690 ps
CPU time 6.41 seconds
Started Sep 24 02:36:46 PM UTC 24
Finished Sep 24 02:36:53 PM UTC 24
Peak memory 244996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989657181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3989657181
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3242923578
Short name T137
Test name
Test status
Simulation time 24598051113 ps
CPU time 25.89 seconds
Started Sep 24 02:36:47 PM UTC 24
Finished Sep 24 02:37:14 PM UTC 24
Peak memory 234812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242923578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3242923578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.318049927
Short name T217
Test name
Test status
Simulation time 2958399523 ps
CPU time 88.35 seconds
Started Sep 24 02:39:23 PM UTC 24
Finished Sep 24 02:40:54 PM UTC 24
Peak memory 267712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318049927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.318049927
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.3977489021
Short name T267
Test name
Test status
Simulation time 30484300479 ps
CPU time 114.17 seconds
Started Sep 24 02:39:36 PM UTC 24
Finished Sep 24 02:41:33 PM UTC 24
Peak memory 261756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977489021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.3977489021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.459130519
Short name T418
Test name
Test status
Simulation time 569354126 ps
CPU time 16.61 seconds
Started Sep 24 02:39:46 PM UTC 24
Finished Sep 24 02:40:04 PM UTC 24
Peak memory 261528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459130519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.459130519
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2909474427
Short name T294
Test name
Test status
Simulation time 1268398523 ps
CPU time 6.56 seconds
Started Sep 24 02:39:44 PM UTC 24
Finished Sep 24 02:39:52 PM UTC 24
Peak memory 234808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909474427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.2909474427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.2242498041
Short name T329
Test name
Test status
Simulation time 15348797148 ps
CPU time 226.92 seconds
Started Sep 24 02:41:24 PM UTC 24
Finished Sep 24 02:45:15 PM UTC 24
Peak memory 267716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242498041 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.2242498041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3955457030
Short name T331
Test name
Test status
Simulation time 404031533045 ps
CPU time 679.02 seconds
Started Sep 24 02:45:46 PM UTC 24
Finished Sep 24 02:57:15 PM UTC 24
Peak memory 275788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955457030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3955457030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3007971600
Short name T333
Test name
Test status
Simulation time 140374410598 ps
CPU time 401.19 seconds
Started Sep 24 02:45:48 PM UTC 24
Finished Sep 24 02:52:35 PM UTC 24
Peak memory 273852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007971600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.3007971600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1741752492
Short name T1
Test name
Test status
Simulation time 138190198 ps
CPU time 1.13 seconds
Started Sep 24 02:36:39 PM UTC 24
Finished Sep 24 02:36:41 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741752492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1741752492
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.812063061
Short name T132
Test name
Test status
Simulation time 17477648274 ps
CPU time 46.09 seconds
Started Sep 24 02:40:09 PM UTC 24
Finished Sep 24 02:40:56 PM UTC 24
Peak memory 263488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812063061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.812063061
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1555173361
Short name T115
Test name
Test status
Simulation time 106953303 ps
CPU time 1.88 seconds
Started Sep 24 02:09:36 PM UTC 24
Finished Sep 24 02:09:39 PM UTC 24
Peak memory 214288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555173361 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.1555173361
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.326684180
Short name T1052
Test name
Test status
Simulation time 99528269 ps
CPU time 6.94 seconds
Started Sep 24 02:11:14 PM UTC 24
Finished Sep 24 02:11:22 PM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326684180 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.326684180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2087470803
Short name T163
Test name
Test status
Simulation time 2331682432 ps
CPU time 15.36 seconds
Started Sep 24 02:09:37 PM UTC 24
Finished Sep 24 02:09:54 PM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087470803 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.2087470803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4031010710
Short name T1015
Test name
Test status
Simulation time 2527031481 ps
CPU time 19.98 seconds
Started Sep 24 02:09:37 PM UTC 24
Finished Sep 24 02:09:58 PM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031010710 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.4031010710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1018966804
Short name T107
Test name
Test status
Simulation time 257589692 ps
CPU time 5.7 seconds
Started Sep 24 02:09:41 PM UTC 24
Finished Sep 24 02:09:48 PM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1018966804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.spi_device_csr_mem_rw_with_rand_reset.1018966804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.400517513
Short name T1011
Test name
Test status
Simulation time 46124226 ps
CPU time 1.21 seconds
Started Sep 24 02:09:26 PM UTC 24
Finished Sep 24 02:09:28 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400517513 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.400517513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2833995282
Short name T161
Test name
Test status
Simulation time 113237743 ps
CPU time 2.72 seconds
Started Sep 24 02:09:32 PM UTC 24
Finished Sep 24 02:09:36 PM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833995282 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.2833995282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1377673583
Short name T1012
Test name
Test status
Simulation time 24903466 ps
CPU time 1.12 seconds
Started Sep 24 02:09:29 PM UTC 24
Finished Sep 24 02:09:31 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377673583 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.1377673583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3997137064
Short name T188
Test name
Test status
Simulation time 209230663 ps
CPU time 5.58 seconds
Started Sep 24 02:09:40 PM UTC 24
Finished Sep 24 02:09:47 PM UTC 24
Peak memory 225508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997137064 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstand
ing.3997137064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3633589193
Short name T106
Test name
Test status
Simulation time 101051899 ps
CPU time 2.42 seconds
Started Sep 24 02:09:17 PM UTC 24
Finished Sep 24 02:09:20 PM UTC 24
Peak memory 225736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633589193 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3633589193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2862707857
Short name T167
Test name
Test status
Simulation time 2192875563 ps
CPU time 15.63 seconds
Started Sep 24 02:09:59 PM UTC 24
Finished Sep 24 02:10:16 PM UTC 24
Peak memory 225364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862707857 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.2862707857
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1379037565
Short name T1019
Test name
Test status
Simulation time 188147519 ps
CPU time 16.92 seconds
Started Sep 24 02:09:58 PM UTC 24
Finished Sep 24 02:10:16 PM UTC 24
Peak memory 225292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379037565 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.1379037565
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3421432102
Short name T116
Test name
Test status
Simulation time 58726448 ps
CPU time 1.81 seconds
Started Sep 24 02:09:56 PM UTC 24
Finished Sep 24 02:09:59 PM UTC 24
Peak memory 214188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421432102 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.3421432102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1531213662
Short name T165
Test name
Test status
Simulation time 1685846808 ps
CPU time 2.84 seconds
Started Sep 24 02:09:58 PM UTC 24
Finished Sep 24 02:10:02 PM UTC 24
Peak memory 225244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531213662 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1531213662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3088043256
Short name T1013
Test name
Test status
Simulation time 33912998 ps
CPU time 1.12 seconds
Started Sep 24 02:09:52 PM UTC 24
Finished Sep 24 02:09:54 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088043256 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3088043256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1386537025
Short name T164
Test name
Test status
Simulation time 46984215 ps
CPU time 2.65 seconds
Started Sep 24 02:09:55 PM UTC 24
Finished Sep 24 02:09:58 PM UTC 24
Peak memory 225508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386537025 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.1386537025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2230033336
Short name T1014
Test name
Test status
Simulation time 39269016 ps
CPU time 1.07 seconds
Started Sep 24 02:09:55 PM UTC 24
Finished Sep 24 02:09:57 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230033336 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.2230033336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2564526935
Short name T189
Test name
Test status
Simulation time 101855264 ps
CPU time 5.83 seconds
Started Sep 24 02:09:59 PM UTC 24
Finished Sep 24 02:10:06 PM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564526935 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand
ing.2564526935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1716942402
Short name T197
Test name
Test status
Simulation time 405469355 ps
CPU time 4.1 seconds
Started Sep 24 02:11:15 PM UTC 24
Finished Sep 24 02:11:21 PM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1716942402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.spi_device_csr_mem_rw_with_rand_reset.1716942402
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2141445519
Short name T1050
Test name
Test status
Simulation time 154624433 ps
CPU time 3.87 seconds
Started Sep 24 02:11:14 PM UTC 24
Finished Sep 24 02:11:19 PM UTC 24
Peak memory 225304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141445519 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.2141445519
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1784542678
Short name T1048
Test name
Test status
Simulation time 12725563 ps
CPU time 1.21 seconds
Started Sep 24 02:11:14 PM UTC 24
Finished Sep 24 02:11:16 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784542678 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.1784542678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.931454879
Short name T196
Test name
Test status
Simulation time 291571248 ps
CPU time 2.96 seconds
Started Sep 24 02:11:15 PM UTC 24
Finished Sep 24 02:11:20 PM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931454879 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstand
ing.931454879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.729974950
Short name T1074
Test name
Test status
Simulation time 1794936885 ps
CPU time 28.69 seconds
Started Sep 24 02:11:14 PM UTC 24
Finished Sep 24 02:11:44 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729974950 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.729974950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2511356560
Short name T1055
Test name
Test status
Simulation time 61983774 ps
CPU time 5.51 seconds
Started Sep 24 02:11:22 PM UTC 24
Finished Sep 24 02:11:28 PM UTC 24
Peak memory 229728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2511356560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.spi_device_csr_mem_rw_with_rand_reset.2511356560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.28403871
Short name T200
Test name
Test status
Simulation time 304321549 ps
CPU time 2.9 seconds
Started Sep 24 02:11:20 PM UTC 24
Finished Sep 24 02:11:24 PM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28403871 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.28403871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.172340277
Short name T1051
Test name
Test status
Simulation time 19873201 ps
CPU time 1.15 seconds
Started Sep 24 02:11:19 PM UTC 24
Finished Sep 24 02:11:21 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172340277 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.172340277
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1833324550
Short name T1053
Test name
Test status
Simulation time 651025825 ps
CPU time 2.77 seconds
Started Sep 24 02:11:21 PM UTC 24
Finished Sep 24 02:11:25 PM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833324550 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstan
ding.1833324550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2554982627
Short name T155
Test name
Test status
Simulation time 1745742680 ps
CPU time 6.91 seconds
Started Sep 24 02:11:16 PM UTC 24
Finished Sep 24 02:11:25 PM UTC 24
Peak memory 227664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554982627 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.2554982627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3512076397
Short name T1077
Test name
Test status
Simulation time 309915331 ps
CPU time 26.4 seconds
Started Sep 24 02:11:17 PM UTC 24
Finished Sep 24 02:11:45 PM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512076397 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.3512076397
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3665511228
Short name T1057
Test name
Test status
Simulation time 104061237 ps
CPU time 2.69 seconds
Started Sep 24 02:11:25 PM UTC 24
Finished Sep 24 02:11:29 PM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3665511228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.spi_device_csr_mem_rw_with_rand_reset.3665511228
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1877199084
Short name T1056
Test name
Test status
Simulation time 39229955 ps
CPU time 3.65 seconds
Started Sep 24 02:11:24 PM UTC 24
Finished Sep 24 02:11:29 PM UTC 24
Peak memory 225300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877199084 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.1877199084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2151434666
Short name T1054
Test name
Test status
Simulation time 47126655 ps
CPU time 1.22 seconds
Started Sep 24 02:11:23 PM UTC 24
Finished Sep 24 02:11:25 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151434666 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2151434666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2180957490
Short name T1060
Test name
Test status
Simulation time 163833292 ps
CPU time 6.53 seconds
Started Sep 24 02:11:25 PM UTC 24
Finished Sep 24 02:11:33 PM UTC 24
Peak memory 225488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180957490 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan
ding.2180957490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.3265148709
Short name T157
Test name
Test status
Simulation time 1174207075 ps
CPU time 7.49 seconds
Started Sep 24 02:11:22 PM UTC 24
Finished Sep 24 02:11:30 PM UTC 24
Peak memory 225564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265148709 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.3265148709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.137268047
Short name T1083
Test name
Test status
Simulation time 1200725526 ps
CPU time 24.96 seconds
Started Sep 24 02:11:23 PM UTC 24
Finished Sep 24 02:11:49 PM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137268047 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.137268047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.969674890
Short name T1062
Test name
Test status
Simulation time 89240611 ps
CPU time 2.92 seconds
Started Sep 24 02:11:32 PM UTC 24
Finished Sep 24 02:11:36 PM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=969674890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 13.spi_device_csr_mem_rw_with_rand_reset.969674890
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.201107380
Short name T1059
Test name
Test status
Simulation time 54724406 ps
CPU time 1.93 seconds
Started Sep 24 02:11:30 PM UTC 24
Finished Sep 24 02:11:33 PM UTC 24
Peak memory 226380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201107380 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.201107380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.150092539
Short name T1058
Test name
Test status
Simulation time 47210205 ps
CPU time 1.19 seconds
Started Sep 24 02:11:29 PM UTC 24
Finished Sep 24 02:11:32 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150092539 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.150092539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3949104429
Short name T198
Test name
Test status
Simulation time 161349381 ps
CPU time 2.34 seconds
Started Sep 24 02:11:31 PM UTC 24
Finished Sep 24 02:11:34 PM UTC 24
Peak memory 225376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949104429 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstan
ding.3949104429
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2616247309
Short name T1061
Test name
Test status
Simulation time 74547913 ps
CPU time 6.45 seconds
Started Sep 24 02:11:26 PM UTC 24
Finished Sep 24 02:11:34 PM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616247309 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.2616247309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2994240145
Short name T1070
Test name
Test status
Simulation time 265563600 ps
CPU time 9.74 seconds
Started Sep 24 02:11:29 PM UTC 24
Finished Sep 24 02:11:40 PM UTC 24
Peak memory 227400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994240145 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.2994240145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3854827987
Short name T1067
Test name
Test status
Simulation time 100786218 ps
CPU time 3.4 seconds
Started Sep 24 02:11:35 PM UTC 24
Finished Sep 24 02:11:40 PM UTC 24
Peak memory 227532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3854827987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.spi_device_csr_mem_rw_with_rand_reset.3854827987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3703216511
Short name T1066
Test name
Test status
Simulation time 68713984 ps
CPU time 2.75 seconds
Started Sep 24 02:11:35 PM UTC 24
Finished Sep 24 02:11:39 PM UTC 24
Peak memory 225316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703216511 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.3703216511
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.578681547
Short name T1063
Test name
Test status
Simulation time 16156299 ps
CPU time 1.27 seconds
Started Sep 24 02:11:34 PM UTC 24
Finished Sep 24 02:11:36 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578681547 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.578681547
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.842455831
Short name T1071
Test name
Test status
Simulation time 157839510 ps
CPU time 5.61 seconds
Started Sep 24 02:11:35 PM UTC 24
Finished Sep 24 02:11:42 PM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842455831 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstand
ing.842455831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3971580263
Short name T1065
Test name
Test status
Simulation time 467040485 ps
CPU time 4.63 seconds
Started Sep 24 02:11:33 PM UTC 24
Finished Sep 24 02:11:39 PM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971580263 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.3971580263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2327655095
Short name T1089
Test name
Test status
Simulation time 1619800299 ps
CPU time 18.14 seconds
Started Sep 24 02:11:34 PM UTC 24
Finished Sep 24 02:11:53 PM UTC 24
Peak memory 227540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327655095 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.2327655095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.563185566
Short name T1075
Test name
Test status
Simulation time 73774176 ps
CPU time 3.8 seconds
Started Sep 24 02:11:40 PM UTC 24
Finished Sep 24 02:11:45 PM UTC 24
Peak memory 227608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=563185566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.spi_device_csr_mem_rw_with_rand_reset.563185566
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4069145473
Short name T1073
Test name
Test status
Simulation time 31066540 ps
CPU time 2.7 seconds
Started Sep 24 02:11:40 PM UTC 24
Finished Sep 24 02:11:43 PM UTC 24
Peak memory 225448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069145473 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.4069145473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2362408462
Short name T1068
Test name
Test status
Simulation time 15476107 ps
CPU time 1.21 seconds
Started Sep 24 02:11:38 PM UTC 24
Finished Sep 24 02:11:40 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362408462 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2362408462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3039611799
Short name T199
Test name
Test status
Simulation time 317016956 ps
CPU time 3.2 seconds
Started Sep 24 02:11:40 PM UTC 24
Finished Sep 24 02:11:44 PM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039611799 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstan
ding.3039611799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2633362674
Short name T1069
Test name
Test status
Simulation time 88157694 ps
CPU time 2.97 seconds
Started Sep 24 02:11:36 PM UTC 24
Finished Sep 24 02:11:40 PM UTC 24
Peak memory 227612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633362674 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.2633362674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.113301136
Short name T1114
Test name
Test status
Simulation time 1120807577 ps
CPU time 24.74 seconds
Started Sep 24 02:11:38 PM UTC 24
Finished Sep 24 02:12:04 PM UTC 24
Peak memory 225428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113301136 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.113301136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.430287355
Short name T1085
Test name
Test status
Simulation time 666590275 ps
CPU time 5.27 seconds
Started Sep 24 02:11:44 PM UTC 24
Finished Sep 24 02:11:51 PM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=430287355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 16.spi_device_csr_mem_rw_with_rand_reset.430287355
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.395024267
Short name T1076
Test name
Test status
Simulation time 101734347 ps
CPU time 2.92 seconds
Started Sep 24 02:11:41 PM UTC 24
Finished Sep 24 02:11:45 PM UTC 24
Peak memory 215056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395024267 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.395024267
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3302008232
Short name T1072
Test name
Test status
Simulation time 11403149 ps
CPU time 1.19 seconds
Started Sep 24 02:11:41 PM UTC 24
Finished Sep 24 02:11:43 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302008232 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.3302008232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1198002339
Short name T1079
Test name
Test status
Simulation time 91486372 ps
CPU time 2.68 seconds
Started Sep 24 02:11:43 PM UTC 24
Finished Sep 24 02:11:47 PM UTC 24
Peak memory 225416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198002339 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstan
ding.1198002339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.1360822166
Short name T1078
Test name
Test status
Simulation time 84261424 ps
CPU time 3.59 seconds
Started Sep 24 02:11:41 PM UTC 24
Finished Sep 24 02:11:46 PM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360822166 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.1360822166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2614006068
Short name T1108
Test name
Test status
Simulation time 652437073 ps
CPU time 19.06 seconds
Started Sep 24 02:11:41 PM UTC 24
Finished Sep 24 02:12:01 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614006068 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.2614006068
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3621216189
Short name T1088
Test name
Test status
Simulation time 53270987 ps
CPU time 4.96 seconds
Started Sep 24 02:11:47 PM UTC 24
Finished Sep 24 02:11:53 PM UTC 24
Peak memory 227544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3621216189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.spi_device_csr_mem_rw_with_rand_reset.3621216189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.4221623728
Short name T1084
Test name
Test status
Simulation time 85471162 ps
CPU time 3.32 seconds
Started Sep 24 02:11:45 PM UTC 24
Finished Sep 24 02:11:50 PM UTC 24
Peak memory 225240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221623728 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.4221623728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3849744086
Short name T1080
Test name
Test status
Simulation time 119138616 ps
CPU time 1.18 seconds
Started Sep 24 02:11:45 PM UTC 24
Finished Sep 24 02:11:48 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849744086 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.3849744086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.503893038
Short name T1082
Test name
Test status
Simulation time 109226754 ps
CPU time 2.79 seconds
Started Sep 24 02:11:45 PM UTC 24
Finished Sep 24 02:11:49 PM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503893038 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstand
ing.503893038
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.708788864
Short name T1081
Test name
Test status
Simulation time 57443191 ps
CPU time 2.81 seconds
Started Sep 24 02:11:44 PM UTC 24
Finished Sep 24 02:11:48 PM UTC 24
Peak memory 227664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708788864 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.708788864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2644722208
Short name T1099
Test name
Test status
Simulation time 317565993 ps
CPU time 11.78 seconds
Started Sep 24 02:11:45 PM UTC 24
Finished Sep 24 02:11:58 PM UTC 24
Peak memory 225380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644722208 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2644722208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3632045282
Short name T1093
Test name
Test status
Simulation time 221961848 ps
CPU time 4.22 seconds
Started Sep 24 02:11:50 PM UTC 24
Finished Sep 24 02:11:55 PM UTC 24
Peak memory 229668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3632045282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.spi_device_csr_mem_rw_with_rand_reset.3632045282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.1480995032
Short name T201
Test name
Test status
Simulation time 39521696 ps
CPU time 1.93 seconds
Started Sep 24 02:11:49 PM UTC 24
Finished Sep 24 02:11:52 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480995032 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.1480995032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1951534272
Short name T1086
Test name
Test status
Simulation time 41887800 ps
CPU time 1.02 seconds
Started Sep 24 02:11:49 PM UTC 24
Finished Sep 24 02:11:51 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951534272 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.1951534272
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3588619455
Short name T1092
Test name
Test status
Simulation time 155051348 ps
CPU time 3.79 seconds
Started Sep 24 02:11:50 PM UTC 24
Finished Sep 24 02:11:55 PM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588619455 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan
ding.3588619455
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3957781697
Short name T1090
Test name
Test status
Simulation time 124629668 ps
CPU time 6.57 seconds
Started Sep 24 02:11:47 PM UTC 24
Finished Sep 24 02:11:54 PM UTC 24
Peak memory 227744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957781697 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3957781697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.4215327818
Short name T1128
Test name
Test status
Simulation time 235178554 ps
CPU time 18.42 seconds
Started Sep 24 02:11:48 PM UTC 24
Finished Sep 24 02:12:07 PM UTC 24
Peak memory 227596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215327818 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.4215327818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3143453910
Short name T1102
Test name
Test status
Simulation time 328093474 ps
CPU time 4.16 seconds
Started Sep 24 02:11:54 PM UTC 24
Finished Sep 24 02:12:00 PM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3143453910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.spi_device_csr_mem_rw_with_rand_reset.3143453910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3663150597
Short name T1094
Test name
Test status
Simulation time 27852906 ps
CPU time 2.58 seconds
Started Sep 24 02:11:52 PM UTC 24
Finished Sep 24 02:11:56 PM UTC 24
Peak memory 225304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663150597 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.3663150597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.4138685942
Short name T1091
Test name
Test status
Simulation time 14252352 ps
CPU time 1.18 seconds
Started Sep 24 02:11:52 PM UTC 24
Finished Sep 24 02:11:54 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138685942 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.4138685942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2327945926
Short name T1095
Test name
Test status
Simulation time 305990318 ps
CPU time 2.75 seconds
Started Sep 24 02:11:53 PM UTC 24
Finished Sep 24 02:11:57 PM UTC 24
Peak memory 225424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327945926 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstan
ding.2327945926
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3551771624
Short name T1104
Test name
Test status
Simulation time 492687811 ps
CPU time 8.25 seconds
Started Sep 24 02:11:51 PM UTC 24
Finished Sep 24 02:12:00 PM UTC 24
Peak memory 227656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551771624 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.3551771624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.1483138627
Short name T1131
Test name
Test status
Simulation time 4208759235 ps
CPU time 32.03 seconds
Started Sep 24 02:11:51 PM UTC 24
Finished Sep 24 02:12:25 PM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483138627 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.1483138627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.3466958116
Short name T171
Test name
Test status
Simulation time 6060802396 ps
CPU time 30.57 seconds
Started Sep 24 02:10:14 PM UTC 24
Finished Sep 24 02:10:46 PM UTC 24
Peak memory 215184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466958116 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.3466958116
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1823301421
Short name T170
Test name
Test status
Simulation time 191405491 ps
CPU time 16.62 seconds
Started Sep 24 02:10:13 PM UTC 24
Finished Sep 24 02:10:31 PM UTC 24
Peak memory 215008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823301421 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.1823301421
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1635405501
Short name T117
Test name
Test status
Simulation time 99012398 ps
CPU time 1.78 seconds
Started Sep 24 02:10:11 PM UTC 24
Finished Sep 24 02:10:13 PM UTC 24
Peak memory 214480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635405501 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.1635405501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1737708330
Short name T154
Test name
Test status
Simulation time 50645936 ps
CPU time 3.87 seconds
Started Sep 24 02:10:15 PM UTC 24
Finished Sep 24 02:10:20 PM UTC 24
Peak memory 229528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1737708330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.spi_device_csr_mem_rw_with_rand_reset.1737708330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.571021823
Short name T1018
Test name
Test status
Simulation time 988125407 ps
CPU time 2.89 seconds
Started Sep 24 02:10:11 PM UTC 24
Finished Sep 24 02:10:15 PM UTC 24
Peak memory 225356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571021823 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.571021823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2636680051
Short name T1016
Test name
Test status
Simulation time 111911801 ps
CPU time 1.18 seconds
Started Sep 24 02:10:06 PM UTC 24
Finished Sep 24 02:10:09 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636680051 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2636680051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1722750032
Short name T166
Test name
Test status
Simulation time 17153656 ps
CPU time 1.78 seconds
Started Sep 24 02:10:10 PM UTC 24
Finished Sep 24 02:10:12 PM UTC 24
Peak memory 224396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722750032 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.1722750032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2942516836
Short name T1017
Test name
Test status
Simulation time 14079756 ps
CPU time 1.1 seconds
Started Sep 24 02:10:08 PM UTC 24
Finished Sep 24 02:10:10 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942516836 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.2942516836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.352454687
Short name T1020
Test name
Test status
Simulation time 41433860 ps
CPU time 4.28 seconds
Started Sep 24 02:10:14 PM UTC 24
Finished Sep 24 02:10:19 PM UTC 24
Peak memory 225480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352454687 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.352454687
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.1589938304
Short name T149
Test name
Test status
Simulation time 30590231 ps
CPU time 2.92 seconds
Started Sep 24 02:10:02 PM UTC 24
Finished Sep 24 02:10:06 PM UTC 24
Peak memory 225668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589938304 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1589938304
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.3462847696
Short name T143
Test name
Test status
Simulation time 3397337590 ps
CPU time 29.02 seconds
Started Sep 24 02:10:05 PM UTC 24
Finished Sep 24 02:10:36 PM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462847696 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.3462847696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.596011516
Short name T1097
Test name
Test status
Simulation time 46169293 ps
CPU time 1.24 seconds
Started Sep 24 02:11:55 PM UTC 24
Finished Sep 24 02:11:58 PM UTC 24
Peak memory 212100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596011516 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.596011516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3643477841
Short name T1096
Test name
Test status
Simulation time 27059176 ps
CPU time 1.15 seconds
Started Sep 24 02:11:56 PM UTC 24
Finished Sep 24 02:11:58 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643477841 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.3643477841
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.645027854
Short name T1098
Test name
Test status
Simulation time 11971013 ps
CPU time 1.18 seconds
Started Sep 24 02:11:56 PM UTC 24
Finished Sep 24 02:11:58 PM UTC 24
Peak memory 212100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645027854 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.645027854
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.2797465497
Short name T1100
Test name
Test status
Simulation time 15875748 ps
CPU time 1.14 seconds
Started Sep 24 02:11:57 PM UTC 24
Finished Sep 24 02:11:59 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797465497 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.2797465497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2599145196
Short name T1101
Test name
Test status
Simulation time 32550980 ps
CPU time 1.18 seconds
Started Sep 24 02:11:57 PM UTC 24
Finished Sep 24 02:11:59 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599145196 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.2599145196
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.1244145397
Short name T1103
Test name
Test status
Simulation time 20150401 ps
CPU time 1.23 seconds
Started Sep 24 02:11:58 PM UTC 24
Finished Sep 24 02:12:00 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244145397 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.1244145397
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.4251449737
Short name T1105
Test name
Test status
Simulation time 30622978 ps
CPU time 1.17 seconds
Started Sep 24 02:11:59 PM UTC 24
Finished Sep 24 02:12:01 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251449737 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.4251449737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1977904962
Short name T1107
Test name
Test status
Simulation time 42496871 ps
CPU time 1.16 seconds
Started Sep 24 02:11:59 PM UTC 24
Finished Sep 24 02:12:01 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977904962 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.1977904962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3111164877
Short name T1106
Test name
Test status
Simulation time 11719680 ps
CPU time 1.11 seconds
Started Sep 24 02:11:59 PM UTC 24
Finished Sep 24 02:12:01 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111164877 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.3111164877
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.603409373
Short name T1109
Test name
Test status
Simulation time 95447771 ps
CPU time 1.22 seconds
Started Sep 24 02:11:59 PM UTC 24
Finished Sep 24 02:12:01 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603409373 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.603409373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3503988245
Short name T1025
Test name
Test status
Simulation time 1228671726 ps
CPU time 11.72 seconds
Started Sep 24 02:10:28 PM UTC 24
Finished Sep 24 02:10:41 PM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503988245 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.3503988245
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4237038796
Short name T1028
Test name
Test status
Simulation time 532044990 ps
CPU time 17.65 seconds
Started Sep 24 02:10:26 PM UTC 24
Finished Sep 24 02:10:45 PM UTC 24
Peak memory 215064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237038796 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.4237038796
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2741311902
Short name T169
Test name
Test status
Simulation time 45253980 ps
CPU time 2.11 seconds
Started Sep 24 02:10:23 PM UTC 24
Finished Sep 24 02:10:27 PM UTC 24
Peak memory 215036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741311902 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.2741311902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2818864701
Short name T159
Test name
Test status
Simulation time 93573180 ps
CPU time 2.66 seconds
Started Sep 24 02:10:32 PM UTC 24
Finished Sep 24 02:10:36 PM UTC 24
Peak memory 227544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2818864701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.spi_device_csr_mem_rw_with_rand_reset.2818864701
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2210642860
Short name T193
Test name
Test status
Simulation time 208677720 ps
CPU time 2.23 seconds
Started Sep 24 02:10:25 PM UTC 24
Finished Sep 24 02:10:28 PM UTC 24
Peak memory 215064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210642860 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2210642860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1464202781
Short name T1021
Test name
Test status
Simulation time 35191182 ps
CPU time 1.13 seconds
Started Sep 24 02:10:20 PM UTC 24
Finished Sep 24 02:10:22 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464202781 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1464202781
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1154516843
Short name T168
Test name
Test status
Simulation time 23788036 ps
CPU time 2.19 seconds
Started Sep 24 02:10:21 PM UTC 24
Finished Sep 24 02:10:25 PM UTC 24
Peak memory 225356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154516843 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.1154516843
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1696802393
Short name T1022
Test name
Test status
Simulation time 14497514 ps
CPU time 1.08 seconds
Started Sep 24 02:10:21 PM UTC 24
Finished Sep 24 02:10:23 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696802393 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.1696802393
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2869135193
Short name T1023
Test name
Test status
Simulation time 60507443 ps
CPU time 5.57 seconds
Started Sep 24 02:10:29 PM UTC 24
Finished Sep 24 02:10:36 PM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869135193 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstand
ing.2869135193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.3360072564
Short name T150
Test name
Test status
Simulation time 123325281 ps
CPU time 2.28 seconds
Started Sep 24 02:10:17 PM UTC 24
Finished Sep 24 02:10:20 PM UTC 24
Peak memory 227660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360072564 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3360072564
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1402578745
Short name T351
Test name
Test status
Simulation time 2178066029 ps
CPU time 21.12 seconds
Started Sep 24 02:10:17 PM UTC 24
Finished Sep 24 02:10:40 PM UTC 24
Peak memory 227596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402578745 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1402578745
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.3111580500
Short name T1110
Test name
Test status
Simulation time 41451768 ps
CPU time 1.11 seconds
Started Sep 24 02:12:00 PM UTC 24
Finished Sep 24 02:12:02 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111580500 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.3111580500
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2631617676
Short name T1087
Test name
Test status
Simulation time 15375646 ps
CPU time 1.19 seconds
Started Sep 24 02:12:00 PM UTC 24
Finished Sep 24 02:12:02 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631617676 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.2631617676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2953176005
Short name T1111
Test name
Test status
Simulation time 22551654 ps
CPU time 1.19 seconds
Started Sep 24 02:12:00 PM UTC 24
Finished Sep 24 02:12:02 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953176005 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.2953176005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1877967944
Short name T1112
Test name
Test status
Simulation time 61614537 ps
CPU time 1 seconds
Started Sep 24 02:12:01 PM UTC 24
Finished Sep 24 02:12:03 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877967944 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.1877967944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3538996955
Short name T1113
Test name
Test status
Simulation time 22220155 ps
CPU time 1.13 seconds
Started Sep 24 02:12:01 PM UTC 24
Finished Sep 24 02:12:04 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538996955 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.3538996955
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3390151696
Short name T1115
Test name
Test status
Simulation time 134755350 ps
CPU time 1.08 seconds
Started Sep 24 02:12:01 PM UTC 24
Finished Sep 24 02:12:04 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390151696 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.3390151696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3197098643
Short name T1116
Test name
Test status
Simulation time 20936469 ps
CPU time 1.01 seconds
Started Sep 24 02:12:03 PM UTC 24
Finished Sep 24 02:12:05 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197098643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.3197098643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3662970193
Short name T1117
Test name
Test status
Simulation time 163306116 ps
CPU time 1.17 seconds
Started Sep 24 02:12:03 PM UTC 24
Finished Sep 24 02:12:05 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662970193 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3662970193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.58369308
Short name T1119
Test name
Test status
Simulation time 18299526 ps
CPU time 1.19 seconds
Started Sep 24 02:12:03 PM UTC 24
Finished Sep 24 02:12:05 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58369308 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.58369308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3896757305
Short name T1118
Test name
Test status
Simulation time 38041600 ps
CPU time 1.09 seconds
Started Sep 24 02:12:03 PM UTC 24
Finished Sep 24 02:12:05 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896757305 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.3896757305
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.1952274925
Short name T1039
Test name
Test status
Simulation time 2416518108 ps
CPU time 21.05 seconds
Started Sep 24 02:10:44 PM UTC 24
Finished Sep 24 02:11:06 PM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952274925 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.1952274925
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4218296403
Short name T1035
Test name
Test status
Simulation time 1103976980 ps
CPU time 17.14 seconds
Started Sep 24 02:10:43 PM UTC 24
Finished Sep 24 02:11:02 PM UTC 24
Peak memory 225368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218296403 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.4218296403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3771273473
Short name T118
Test name
Test status
Simulation time 80050263 ps
CPU time 1.98 seconds
Started Sep 24 02:10:41 PM UTC 24
Finished Sep 24 02:10:44 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771273473 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.3771273473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.864819536
Short name T1031
Test name
Test status
Simulation time 121782386 ps
CPU time 5.32 seconds
Started Sep 24 02:10:45 PM UTC 24
Finished Sep 24 02:10:51 PM UTC 24
Peak memory 229596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=864819536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.spi_device_csr_mem_rw_with_rand_reset.864819536
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1932611420
Short name T1027
Test name
Test status
Simulation time 42786143 ps
CPU time 2.27 seconds
Started Sep 24 02:10:41 PM UTC 24
Finished Sep 24 02:10:45 PM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932611420 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1932611420
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.4097613496
Short name T1024
Test name
Test status
Simulation time 26937877 ps
CPU time 1.24 seconds
Started Sep 24 02:10:37 PM UTC 24
Finished Sep 24 02:10:39 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097613496 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4097613496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2448388547
Short name T173
Test name
Test status
Simulation time 20650538 ps
CPU time 2.01 seconds
Started Sep 24 02:10:40 PM UTC 24
Finished Sep 24 02:10:43 PM UTC 24
Peak memory 224396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448388547 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.2448388547
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.701202729
Short name T1026
Test name
Test status
Simulation time 13591262 ps
CPU time 1.08 seconds
Started Sep 24 02:10:40 PM UTC 24
Finished Sep 24 02:10:42 PM UTC 24
Peak memory 212100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701202729 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.701202729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.715455011
Short name T1029
Test name
Test status
Simulation time 31341414 ps
CPU time 2.58 seconds
Started Sep 24 02:10:44 PM UTC 24
Finished Sep 24 02:10:47 PM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715455011 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.715455011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.1897234080
Short name T144
Test name
Test status
Simulation time 30225701 ps
CPU time 2.89 seconds
Started Sep 24 02:10:36 PM UTC 24
Finished Sep 24 02:10:40 PM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897234080 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1897234080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.1803433859
Short name T195
Test name
Test status
Simulation time 1092814437 ps
CPU time 34.13 seconds
Started Sep 24 02:10:37 PM UTC 24
Finished Sep 24 02:11:13 PM UTC 24
Peak memory 227564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803433859 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.1803433859
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2189308537
Short name T1121
Test name
Test status
Simulation time 13109027 ps
CPU time 1.12 seconds
Started Sep 24 02:12:04 PM UTC 24
Finished Sep 24 02:12:06 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189308537 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.2189308537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2138726186
Short name T1122
Test name
Test status
Simulation time 70235208 ps
CPU time 1.16 seconds
Started Sep 24 02:12:04 PM UTC 24
Finished Sep 24 02:12:06 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138726186 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.2138726186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.269475011
Short name T1120
Test name
Test status
Simulation time 12737284 ps
CPU time 1.03 seconds
Started Sep 24 02:12:04 PM UTC 24
Finished Sep 24 02:12:06 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269475011 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.269475011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1833735957
Short name T1123
Test name
Test status
Simulation time 36866007 ps
CPU time 1.08 seconds
Started Sep 24 02:12:04 PM UTC 24
Finished Sep 24 02:12:06 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833735957 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1833735957
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2161931252
Short name T1124
Test name
Test status
Simulation time 15424876 ps
CPU time 1.12 seconds
Started Sep 24 02:12:04 PM UTC 24
Finished Sep 24 02:12:06 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161931252 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.2161931252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.4009847944
Short name T1126
Test name
Test status
Simulation time 17388967 ps
CPU time 1.12 seconds
Started Sep 24 02:12:04 PM UTC 24
Finished Sep 24 02:12:06 PM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009847944 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.4009847944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1359293012
Short name T1125
Test name
Test status
Simulation time 33477306 ps
CPU time 1.11 seconds
Started Sep 24 02:12:04 PM UTC 24
Finished Sep 24 02:12:06 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359293012 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.1359293012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.454565693
Short name T1127
Test name
Test status
Simulation time 17805860 ps
CPU time 1.16 seconds
Started Sep 24 02:12:04 PM UTC 24
Finished Sep 24 02:12:07 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454565693 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.454565693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2867905864
Short name T1129
Test name
Test status
Simulation time 124932323 ps
CPU time 1.1 seconds
Started Sep 24 02:12:05 PM UTC 24
Finished Sep 24 02:12:08 PM UTC 24
Peak memory 211764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867905864 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.2867905864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2014302545
Short name T1130
Test name
Test status
Simulation time 30626682 ps
CPU time 1.19 seconds
Started Sep 24 02:12:06 PM UTC 24
Finished Sep 24 02:12:08 PM UTC 24
Peak memory 211784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014302545 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2014302545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2817478552
Short name T158
Test name
Test status
Simulation time 1000765581 ps
CPU time 5.76 seconds
Started Sep 24 02:10:49 PM UTC 24
Finished Sep 24 02:10:56 PM UTC 24
Peak memory 229724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2817478552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.spi_device_csr_mem_rw_with_rand_reset.2817478552
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3606693032
Short name T172
Test name
Test status
Simulation time 73759986 ps
CPU time 1.91 seconds
Started Sep 24 02:10:47 PM UTC 24
Finished Sep 24 02:10:50 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606693032 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3606693032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.467703637
Short name T1030
Test name
Test status
Simulation time 26810632 ps
CPU time 1.18 seconds
Started Sep 24 02:10:46 PM UTC 24
Finished Sep 24 02:10:48 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467703637 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.467703637
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3508588357
Short name T1032
Test name
Test status
Simulation time 45089587 ps
CPU time 4.28 seconds
Started Sep 24 02:10:48 PM UTC 24
Finished Sep 24 02:10:53 PM UTC 24
Peak memory 225512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508588357 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstand
ing.3508588357
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3634688889
Short name T202
Test name
Test status
Simulation time 105638675 ps
CPU time 3.16 seconds
Started Sep 24 02:10:45 PM UTC 24
Finished Sep 24 02:10:49 PM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634688889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3634688889
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.353525936
Short name T350
Test name
Test status
Simulation time 560220726 ps
CPU time 21.73 seconds
Started Sep 24 02:10:46 PM UTC 24
Finished Sep 24 02:11:09 PM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353525936 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.353525936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2151749516
Short name T1036
Test name
Test status
Simulation time 166320955 ps
CPU time 3.94 seconds
Started Sep 24 02:10:57 PM UTC 24
Finished Sep 24 02:11:02 PM UTC 24
Peak memory 227608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2151749516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.spi_device_csr_mem_rw_with_rand_reset.2151749516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3760761424
Short name T174
Test name
Test status
Simulation time 40100411 ps
CPU time 3.69 seconds
Started Sep 24 02:10:54 PM UTC 24
Finished Sep 24 02:10:59 PM UTC 24
Peak memory 225300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760761424 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3760761424
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.291500969
Short name T1033
Test name
Test status
Simulation time 108701865 ps
CPU time 1.2 seconds
Started Sep 24 02:10:52 PM UTC 24
Finished Sep 24 02:10:55 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291500969 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.291500969
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2486747317
Short name T1034
Test name
Test status
Simulation time 93992957 ps
CPU time 2.84 seconds
Started Sep 24 02:10:55 PM UTC 24
Finished Sep 24 02:11:00 PM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486747317 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstand
ing.2486747317
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1210051441
Short name T349
Test name
Test status
Simulation time 108576461 ps
CPU time 8.52 seconds
Started Sep 24 02:10:51 PM UTC 24
Finished Sep 24 02:11:01 PM UTC 24
Peak memory 227428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210051441 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.1210051441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3080543407
Short name T1041
Test name
Test status
Simulation time 185772871 ps
CPU time 4.98 seconds
Started Sep 24 02:11:03 PM UTC 24
Finished Sep 24 02:11:09 PM UTC 24
Peak memory 227672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3080543407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.spi_device_csr_mem_rw_with_rand_reset.3080543407
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3968491549
Short name T1038
Test name
Test status
Simulation time 150679172 ps
CPU time 1.96 seconds
Started Sep 24 02:11:02 PM UTC 24
Finished Sep 24 02:11:05 PM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968491549 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3968491549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.4193675083
Short name T1037
Test name
Test status
Simulation time 19417125 ps
CPU time 1.22 seconds
Started Sep 24 02:11:01 PM UTC 24
Finished Sep 24 02:11:03 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193675083 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4193675083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1427568504
Short name T194
Test name
Test status
Simulation time 68121920 ps
CPU time 2.11 seconds
Started Sep 24 02:11:03 PM UTC 24
Finished Sep 24 02:11:06 PM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427568504 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand
ing.1427568504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.144283423
Short name T152
Test name
Test status
Simulation time 203879691 ps
CPU time 4.31 seconds
Started Sep 24 02:10:59 PM UTC 24
Finished Sep 24 02:11:04 PM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144283423 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.144283423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3276209664
Short name T1044
Test name
Test status
Simulation time 159075219 ps
CPU time 4.01 seconds
Started Sep 24 02:11:07 PM UTC 24
Finished Sep 24 02:11:13 PM UTC 24
Peak memory 227540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3276209664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.spi_device_csr_mem_rw_with_rand_reset.3276209664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3717255430
Short name T1042
Test name
Test status
Simulation time 42225531 ps
CPU time 3.66 seconds
Started Sep 24 02:11:06 PM UTC 24
Finished Sep 24 02:11:11 PM UTC 24
Peak memory 225224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717255430 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3717255430
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2448137207
Short name T1040
Test name
Test status
Simulation time 15659566 ps
CPU time 1.12 seconds
Started Sep 24 02:11:06 PM UTC 24
Finished Sep 24 02:11:09 PM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448137207 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2448137207
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3669992500
Short name T1045
Test name
Test status
Simulation time 80669675 ps
CPU time 4.2 seconds
Started Sep 24 02:11:07 PM UTC 24
Finished Sep 24 02:11:13 PM UTC 24
Peak memory 225364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669992500 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand
ing.3669992500
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2679582813
Short name T156
Test name
Test status
Simulation time 38178700 ps
CPU time 3.79 seconds
Started Sep 24 02:11:04 PM UTC 24
Finished Sep 24 02:11:09 PM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679582813 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2679582813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.1435249552
Short name T353
Test name
Test status
Simulation time 215882185 ps
CPU time 7.39 seconds
Started Sep 24 02:11:05 PM UTC 24
Finished Sep 24 02:11:14 PM UTC 24
Peak memory 225436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435249552 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.1435249552
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.5222179
Short name T1049
Test name
Test status
Simulation time 179755805 ps
CPU time 3.56 seconds
Started Sep 24 02:11:13 PM UTC 24
Finished Sep 24 02:11:18 PM UTC 24
Peak memory 227472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=5222179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_csr_mem_rw_with_rand_reset.5222179
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.2133021594
Short name T1046
Test name
Test status
Simulation time 38818238 ps
CPU time 2.13 seconds
Started Sep 24 02:11:10 PM UTC 24
Finished Sep 24 02:11:13 PM UTC 24
Peak memory 225376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133021594 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2133021594
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3192245156
Short name T1043
Test name
Test status
Simulation time 13487332 ps
CPU time 1.14 seconds
Started Sep 24 02:11:10 PM UTC 24
Finished Sep 24 02:11:12 PM UTC 24
Peak memory 211940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192245156 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3192245156
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1980617621
Short name T1047
Test name
Test status
Simulation time 110380258 ps
CPU time 2.73 seconds
Started Sep 24 02:11:12 PM UTC 24
Finished Sep 24 02:11:16 PM UTC 24
Peak memory 225472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980617621 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand
ing.1980617621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1567881415
Short name T151
Test name
Test status
Simulation time 67830168 ps
CPU time 3.36 seconds
Started Sep 24 02:11:10 PM UTC 24
Finished Sep 24 02:11:14 PM UTC 24
Peak memory 225740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567881415 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1567881415
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.472222373
Short name T1064
Test name
Test status
Simulation time 5942180084 ps
CPU time 27.1 seconds
Started Sep 24 02:11:10 PM UTC 24
Finished Sep 24 02:11:38 PM UTC 24
Peak memory 227660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472222373 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.472222373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1429952117
Short name T14
Test name
Test status
Simulation time 126459344 ps
CPU time 3.51 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:36:47 PM UTC 24
Peak memory 245144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429952117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1429952117
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3801142970
Short name T62
Test name
Test status
Simulation time 9540478162 ps
CPU time 45.72 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:37:31 PM UTC 24
Peak memory 251328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801142970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.3801142970
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2358818134
Short name T57
Test name
Test status
Simulation time 2718451194 ps
CPU time 20.84 seconds
Started Sep 24 02:36:42 PM UTC 24
Finished Sep 24 02:37:04 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358818134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2358818134
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3363671610
Short name T15
Test name
Test status
Simulation time 152236954 ps
CPU time 5.01 seconds
Started Sep 24 02:36:42 PM UTC 24
Finished Sep 24 02:36:48 PM UTC 24
Peak memory 251072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363671610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3363671610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.863836446
Short name T6
Test name
Test status
Simulation time 32058197 ps
CPU time 2.71 seconds
Started Sep 24 02:36:42 PM UTC 24
Finished Sep 24 02:36:45 PM UTC 24
Peak memory 244628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863836446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.863836446
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3253819907
Short name T18
Test name
Test status
Simulation time 715403900 ps
CPU time 6.57 seconds
Started Sep 24 02:36:42 PM UTC 24
Finished Sep 24 02:36:49 PM UTC 24
Peak memory 234676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253819907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3253819907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3997887212
Short name T16
Test name
Test status
Simulation time 701959798 ps
CPU time 4.22 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:36:48 PM UTC 24
Peak memory 231228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997887212 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.3997887212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.1565822432
Short name T8
Test name
Test status
Simulation time 417278187 ps
CPU time 1.28 seconds
Started Sep 24 02:36:43 PM UTC 24
Finished Sep 24 02:36:46 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565822432 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.1565822432
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.1062483287
Short name T5
Test name
Test status
Simulation time 175798788 ps
CPU time 1.27 seconds
Started Sep 24 02:36:42 PM UTC 24
Finished Sep 24 02:36:44 PM UTC 24
Peak memory 216332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062483287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1062483287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1478951093
Short name T4
Test name
Test status
Simulation time 33356148 ps
CPU time 1.25 seconds
Started Sep 24 02:36:41 PM UTC 24
Finished Sep 24 02:36:43 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478951093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1478951093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.649033525
Short name T104
Test name
Test status
Simulation time 11377065 ps
CPU time 1.19 seconds
Started Sep 24 02:36:50 PM UTC 24
Finished Sep 24 02:36:52 PM UTC 24
Peak memory 213652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649033525 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.649033525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1159005272
Short name T12
Test name
Test status
Simulation time 51683394 ps
CPU time 0.97 seconds
Started Sep 24 02:36:44 PM UTC 24
Finished Sep 24 02:36:46 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159005272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1159005272
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.2092772785
Short name T160
Test name
Test status
Simulation time 34285066 ps
CPU time 1.29 seconds
Started Sep 24 02:36:48 PM UTC 24
Finished Sep 24 02:36:51 PM UTC 24
Peak memory 226808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092772785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2092772785
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.3754790805
Short name T23
Test name
Test status
Simulation time 118060293 ps
CPU time 3.86 seconds
Started Sep 24 02:36:48 PM UTC 24
Finished Sep 24 02:36:54 PM UTC 24
Peak memory 235008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754790805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3754790805
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3336428363
Short name T61
Test name
Test status
Simulation time 23348549084 ps
CPU time 47.82 seconds
Started Sep 24 02:36:48 PM UTC 24
Finished Sep 24 02:37:38 PM UTC 24
Peak memory 261488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336428363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.3336428363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.2338919981
Short name T50
Test name
Test status
Simulation time 1521078697 ps
CPU time 14.44 seconds
Started Sep 24 02:36:46 PM UTC 24
Finished Sep 24 02:37:02 PM UTC 24
Peak memory 234692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338919981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2338919981
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.486011383
Short name T25
Test name
Test status
Simulation time 708965773 ps
CPU time 9.65 seconds
Started Sep 24 02:36:46 PM UTC 24
Finished Sep 24 02:36:57 PM UTC 24
Peak memory 234796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486011383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.486011383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.272094363
Short name T136
Test name
Test status
Simulation time 6681327529 ps
CPU time 9.96 seconds
Started Sep 24 02:36:46 PM UTC 24
Finished Sep 24 02:36:57 PM UTC 24
Peak memory 234820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272094363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.272094363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1605899940
Short name T24
Test name
Test status
Simulation time 86978299 ps
CPU time 3.91 seconds
Started Sep 24 02:36:48 PM UTC 24
Finished Sep 24 02:36:54 PM UTC 24
Peak memory 233312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605899940 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.1605899940
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.3352438826
Short name T32
Test name
Test status
Simulation time 280678447 ps
CPU time 1.85 seconds
Started Sep 24 02:36:50 PM UTC 24
Finished Sep 24 02:36:53 PM UTC 24
Peak memory 256924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352438826 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3352438826
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.4258343323
Short name T26
Test name
Test status
Simulation time 124177606 ps
CPU time 1.62 seconds
Started Sep 24 02:36:50 PM UTC 24
Finished Sep 24 02:36:52 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258343323 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.4258343323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1730087724
Short name T29
Test name
Test status
Simulation time 4423291932 ps
CPU time 13.49 seconds
Started Sep 24 02:36:44 PM UTC 24
Finished Sep 24 02:36:59 PM UTC 24
Peak memory 227532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730087724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1730087724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.1881279037
Short name T17
Test name
Test status
Simulation time 604109238 ps
CPU time 3.03 seconds
Started Sep 24 02:36:45 PM UTC 24
Finished Sep 24 02:36:49 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881279037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1881279037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3528369239
Short name T13
Test name
Test status
Simulation time 73793455 ps
CPU time 1.57 seconds
Started Sep 24 02:36:45 PM UTC 24
Finished Sep 24 02:36:47 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528369239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3528369239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.3128387308
Short name T480
Test name
Test status
Simulation time 45164056 ps
CPU time 1.15 seconds
Started Sep 24 02:39:04 PM UTC 24
Finished Sep 24 02:39:07 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128387308 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.3128387308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1380645823
Short name T285
Test name
Test status
Simulation time 35285089 ps
CPU time 3.59 seconds
Started Sep 24 02:38:58 PM UTC 24
Finished Sep 24 02:39:02 PM UTC 24
Peak memory 244880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380645823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1380645823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.2965747932
Short name T475
Test name
Test status
Simulation time 17854076 ps
CPU time 1.27 seconds
Started Sep 24 02:38:50 PM UTC 24
Finished Sep 24 02:38:52 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965747932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2965747932
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.3309603999
Short name T270
Test name
Test status
Simulation time 45742932363 ps
CPU time 249.93 seconds
Started Sep 24 02:39:00 PM UTC 24
Finished Sep 24 02:43:14 PM UTC 24
Peak memory 265740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309603999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3309603999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.2245110380
Short name T504
Test name
Test status
Simulation time 3711504068 ps
CPU time 63.49 seconds
Started Sep 24 02:38:58 PM UTC 24
Finished Sep 24 02:40:03 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245110380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2245110380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3886991123
Short name T479
Test name
Test status
Simulation time 37918967 ps
CPU time 1.32 seconds
Started Sep 24 02:38:59 PM UTC 24
Finished Sep 24 02:39:01 PM UTC 24
Peak memory 226860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886991123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.3886991123
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.4172089211
Short name T283
Test name
Test status
Simulation time 1831192660 ps
CPU time 21.01 seconds
Started Sep 24 02:38:56 PM UTC 24
Finished Sep 24 02:39:19 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172089211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4172089211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.3399515861
Short name T369
Test name
Test status
Simulation time 10731156545 ps
CPU time 102.98 seconds
Started Sep 24 02:38:56 PM UTC 24
Finished Sep 24 02:40:42 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399515861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3399515861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3332348242
Short name T218
Test name
Test status
Simulation time 24679971647 ps
CPU time 27.94 seconds
Started Sep 24 02:38:56 PM UTC 24
Finished Sep 24 02:39:26 PM UTC 24
Peak memory 249208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332348242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.3332348242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3673249250
Short name T220
Test name
Test status
Simulation time 9930718339 ps
CPU time 15.19 seconds
Started Sep 24 02:38:54 PM UTC 24
Finished Sep 24 02:39:10 PM UTC 24
Peak memory 234812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673249250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3673249250
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1538919610
Short name T482
Test name
Test status
Simulation time 875664072 ps
CPU time 6.82 seconds
Started Sep 24 02:39:00 PM UTC 24
Finished Sep 24 02:39:08 PM UTC 24
Peak memory 231420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538919610 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1538919610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.2847795685
Short name T205
Test name
Test status
Simulation time 16213357914 ps
CPU time 76.08 seconds
Started Sep 24 02:39:04 PM UTC 24
Finished Sep 24 02:40:23 PM UTC 24
Peak memory 263932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847795685 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.2847795685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.3625511129
Short name T434
Test name
Test status
Simulation time 14916678774 ps
CPU time 25.9 seconds
Started Sep 24 02:38:53 PM UTC 24
Finished Sep 24 02:39:20 PM UTC 24
Peak memory 227736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625511129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3625511129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3690804515
Short name T483
Test name
Test status
Simulation time 5903990329 ps
CPU time 14.18 seconds
Started Sep 24 02:38:53 PM UTC 24
Finished Sep 24 02:39:08 PM UTC 24
Peak memory 227720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690804515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3690804515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2212362414
Short name T477
Test name
Test status
Simulation time 140853843 ps
CPU time 2.15 seconds
Started Sep 24 02:38:54 PM UTC 24
Finished Sep 24 02:38:57 PM UTC 24
Peak memory 227264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212362414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2212362414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1071775032
Short name T476
Test name
Test status
Simulation time 32683713 ps
CPU time 1.11 seconds
Started Sep 24 02:38:53 PM UTC 24
Finished Sep 24 02:38:55 PM UTC 24
Peak memory 215952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071775032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1071775032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3159399878
Short name T274
Test name
Test status
Simulation time 30658769775 ps
CPU time 43.25 seconds
Started Sep 24 02:38:58 PM UTC 24
Finished Sep 24 02:39:42 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159399878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3159399878
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.508093798
Short name T487
Test name
Test status
Simulation time 38257625 ps
CPU time 1.19 seconds
Started Sep 24 02:39:24 PM UTC 24
Finished Sep 24 02:39:26 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508093798 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.508093798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2733376625
Short name T288
Test name
Test status
Simulation time 5314612827 ps
CPU time 20.81 seconds
Started Sep 24 02:39:15 PM UTC 24
Finished Sep 24 02:39:37 PM UTC 24
Peak memory 234812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733376625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2733376625
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.1576896105
Short name T481
Test name
Test status
Simulation time 53007268 ps
CPU time 1.24 seconds
Started Sep 24 02:39:05 PM UTC 24
Finished Sep 24 02:39:07 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576896105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1576896105
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1659291520
Short name T387
Test name
Test status
Simulation time 15683185034 ps
CPU time 103.86 seconds
Started Sep 24 02:39:19 PM UTC 24
Finished Sep 24 02:41:05 PM UTC 24
Peak memory 234840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659291520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1659291520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2843842888
Short name T266
Test name
Test status
Simulation time 25174305787 ps
CPU time 223.18 seconds
Started Sep 24 02:39:20 PM UTC 24
Finished Sep 24 02:43:07 PM UTC 24
Peak memory 263548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843842888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2843842888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.117646380
Short name T486
Test name
Test status
Simulation time 62389626 ps
CPU time 4.66 seconds
Started Sep 24 02:39:17 PM UTC 24
Finished Sep 24 02:39:23 PM UTC 24
Peak memory 244952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117646380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.117646380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.583330490
Short name T275
Test name
Test status
Simulation time 120107901119 ps
CPU time 244.56 seconds
Started Sep 24 02:39:18 PM UTC 24
Finished Sep 24 02:43:26 PM UTC 24
Peak memory 263800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583330490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.583330490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3904364921
Short name T130
Test name
Test status
Simulation time 109859023 ps
CPU time 3.87 seconds
Started Sep 24 02:39:12 PM UTC 24
Finished Sep 24 02:39:16 PM UTC 24
Peak memory 234644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904364921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3904364921
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2215156473
Short name T247
Test name
Test status
Simulation time 4322494470 ps
CPU time 40.41 seconds
Started Sep 24 02:39:13 PM UTC 24
Finished Sep 24 02:39:55 PM UTC 24
Peak memory 245372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215156473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2215156473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3136919570
Short name T69
Test name
Test status
Simulation time 1561162570 ps
CPU time 9.9 seconds
Started Sep 24 02:39:12 PM UTC 24
Finished Sep 24 02:39:23 PM UTC 24
Peak memory 234704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136919570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.3136919570
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2230687562
Short name T293
Test name
Test status
Simulation time 4618011701 ps
CPU time 17.05 seconds
Started Sep 24 02:39:10 PM UTC 24
Finished Sep 24 02:39:29 PM UTC 24
Peak memory 247164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230687562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2230687562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.565800929
Short name T498
Test name
Test status
Simulation time 2157276117 ps
CPU time 25.06 seconds
Started Sep 24 02:39:19 PM UTC 24
Finished Sep 24 02:39:46 PM UTC 24
Peak memory 233584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565800929 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.565800929
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.738479317
Short name T204
Test name
Test status
Simulation time 206133235 ps
CPU time 1.6 seconds
Started Sep 24 02:39:23 PM UTC 24
Finished Sep 24 02:39:26 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738479317 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.738479317
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2557920820
Short name T427
Test name
Test status
Simulation time 7058365215 ps
CPU time 51.95 seconds
Started Sep 24 02:39:08 PM UTC 24
Finished Sep 24 02:40:02 PM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557920820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2557920820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2243415646
Short name T485
Test name
Test status
Simulation time 10323561518 ps
CPU time 9.01 seconds
Started Sep 24 02:39:08 PM UTC 24
Finished Sep 24 02:39:18 PM UTC 24
Peak memory 227784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243415646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2243415646
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.4042194114
Short name T444
Test name
Test status
Simulation time 1077182345 ps
CPU time 3.7 seconds
Started Sep 24 02:39:09 PM UTC 24
Finished Sep 24 02:39:14 PM UTC 24
Peak memory 227392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042194114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4042194114
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.553189715
Short name T484
Test name
Test status
Simulation time 76826807 ps
CPU time 1.26 seconds
Started Sep 24 02:39:09 PM UTC 24
Finished Sep 24 02:39:12 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553189715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.553189715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.2230691533
Short name T234
Test name
Test status
Simulation time 4799711239 ps
CPU time 10.57 seconds
Started Sep 24 02:39:13 PM UTC 24
Finished Sep 24 02:39:24 PM UTC 24
Peak memory 235140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230691533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2230691533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.221075955
Short name T492
Test name
Test status
Simulation time 42594256 ps
CPU time 1.11 seconds
Started Sep 24 02:39:39 PM UTC 24
Finished Sep 24 02:39:41 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221075955 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.221075955
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2643744459
Short name T495
Test name
Test status
Simulation time 905019254 ps
CPU time 10.44 seconds
Started Sep 24 02:39:32 PM UTC 24
Finished Sep 24 02:39:43 PM UTC 24
Peak memory 251132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643744459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2643744459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1174281873
Short name T488
Test name
Test status
Simulation time 35199984 ps
CPU time 1.24 seconds
Started Sep 24 02:39:24 PM UTC 24
Finished Sep 24 02:39:26 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174281873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1174281873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.2849771179
Short name T111
Test name
Test status
Simulation time 14452150128 ps
CPU time 88.09 seconds
Started Sep 24 02:39:37 PM UTC 24
Finished Sep 24 02:41:07 PM UTC 24
Peak memory 261760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849771179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2849771179
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.4044588624
Short name T393
Test name
Test status
Simulation time 4979252091 ps
CPU time 84.16 seconds
Started Sep 24 02:39:37 PM UTC 24
Finished Sep 24 02:41:03 PM UTC 24
Peak memory 261760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044588624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4044588624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2157700725
Short name T299
Test name
Test status
Simulation time 36250870066 ps
CPU time 336.52 seconds
Started Sep 24 02:39:39 PM UTC 24
Finished Sep 24 02:45:20 PM UTC 24
Peak memory 251296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157700725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.2157700725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.4040095264
Short name T389
Test name
Test status
Simulation time 167208785 ps
CPU time 6.77 seconds
Started Sep 24 02:39:34 PM UTC 24
Finished Sep 24 02:39:42 PM UTC 24
Peak memory 234684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040095264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4040095264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2341038569
Short name T490
Test name
Test status
Simulation time 105020617 ps
CPU time 3.42 seconds
Started Sep 24 02:39:30 PM UTC 24
Finished Sep 24 02:39:35 PM UTC 24
Peak memory 229392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341038569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2341038569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.1888529184
Short name T514
Test name
Test status
Simulation time 7049323337 ps
CPU time 62.57 seconds
Started Sep 24 02:39:30 PM UTC 24
Finished Sep 24 02:40:35 PM UTC 24
Peak memory 261628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888529184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1888529184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3680195687
Short name T284
Test name
Test status
Simulation time 302791545 ps
CPU time 5.58 seconds
Started Sep 24 02:39:29 PM UTC 24
Finished Sep 24 02:39:36 PM UTC 24
Peak memory 245196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680195687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3680195687
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3199877788
Short name T261
Test name
Test status
Simulation time 335988458 ps
CPU time 10.34 seconds
Started Sep 24 02:39:28 PM UTC 24
Finished Sep 24 02:39:40 PM UTC 24
Peak memory 234696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199877788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3199877788
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.176661353
Short name T501
Test name
Test status
Simulation time 2015976784 ps
CPU time 18.77 seconds
Started Sep 24 02:39:36 PM UTC 24
Finished Sep 24 02:39:56 PM UTC 24
Peak memory 233280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176661353 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.176661353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.1950225218
Short name T493
Test name
Test status
Simulation time 203592657 ps
CPU time 1.76 seconds
Started Sep 24 02:39:39 PM UTC 24
Finished Sep 24 02:39:42 PM UTC 24
Peak memory 215616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950225218 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.1950225218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1450924425
Short name T432
Test name
Test status
Simulation time 525149966 ps
CPU time 7.09 seconds
Started Sep 24 02:39:27 PM UTC 24
Finished Sep 24 02:39:35 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450924425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1450924425
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2518833559
Short name T491
Test name
Test status
Simulation time 818976492 ps
CPU time 8.81 seconds
Started Sep 24 02:39:27 PM UTC 24
Finished Sep 24 02:39:37 PM UTC 24
Peak memory 227384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518833559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2518833559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.3551792847
Short name T437
Test name
Test status
Simulation time 50626123 ps
CPU time 1.89 seconds
Started Sep 24 02:39:27 PM UTC 24
Finished Sep 24 02:39:30 PM UTC 24
Peak memory 226508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551792847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3551792847
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3739926972
Short name T489
Test name
Test status
Simulation time 16218116 ps
CPU time 1.19 seconds
Started Sep 24 02:39:27 PM UTC 24
Finished Sep 24 02:39:29 PM UTC 24
Peak memory 215892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739926972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3739926972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.1293556104
Short name T222
Test name
Test status
Simulation time 1089298635 ps
CPU time 8.94 seconds
Started Sep 24 02:39:30 PM UTC 24
Finished Sep 24 02:39:41 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293556104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1293556104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3647392087
Short name T502
Test name
Test status
Simulation time 15803939 ps
CPU time 1.22 seconds
Started Sep 24 02:39:53 PM UTC 24
Finished Sep 24 02:39:56 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647392087 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.3647392087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.2912352654
Short name T271
Test name
Test status
Simulation time 130662297 ps
CPU time 3.2 seconds
Started Sep 24 02:39:45 PM UTC 24
Finished Sep 24 02:39:49 PM UTC 24
Peak memory 245160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912352654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2912352654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3654940525
Short name T494
Test name
Test status
Simulation time 226980389 ps
CPU time 1.24 seconds
Started Sep 24 02:39:41 PM UTC 24
Finished Sep 24 02:39:43 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654940525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3654940525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.1279854745
Short name T383
Test name
Test status
Simulation time 5632530504 ps
CPU time 28.16 seconds
Started Sep 24 02:39:51 PM UTC 24
Finished Sep 24 02:40:20 PM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279854745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1279854745
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1919033265
Short name T292
Test name
Test status
Simulation time 27975882740 ps
CPU time 76.92 seconds
Started Sep 24 02:39:51 PM UTC 24
Finished Sep 24 02:41:09 PM UTC 24
Peak memory 265920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919033265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1919033265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.3950223032
Short name T216
Test name
Test status
Simulation time 11964368099 ps
CPU time 50.95 seconds
Started Sep 24 02:39:53 PM UTC 24
Finished Sep 24 02:40:46 PM UTC 24
Peak memory 249272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950223032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.3950223032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.3023426350
Short name T226
Test name
Test status
Simulation time 9791056133 ps
CPU time 65.49 seconds
Started Sep 24 02:39:46 PM UTC 24
Finished Sep 24 02:40:54 PM UTC 24
Peak memory 251516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023426350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.3023426350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.258160664
Short name T361
Test name
Test status
Simulation time 683851446 ps
CPU time 7.13 seconds
Started Sep 24 02:39:44 PM UTC 24
Finished Sep 24 02:39:52 PM UTC 24
Peak memory 245252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258160664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.258160664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.976578090
Short name T249
Test name
Test status
Simulation time 10181664743 ps
CPU time 75.62 seconds
Started Sep 24 02:39:44 PM UTC 24
Finished Sep 24 02:41:01 PM UTC 24
Peak memory 234876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976578090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.976578090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.3254972870
Short name T257
Test name
Test status
Simulation time 47785954840 ps
CPU time 59.13 seconds
Started Sep 24 02:39:44 PM UTC 24
Finished Sep 24 02:40:45 PM UTC 24
Peak memory 249144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254972870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3254972870
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2908770013
Short name T506
Test name
Test status
Simulation time 1315831309 ps
CPU time 25.39 seconds
Started Sep 24 02:39:47 PM UTC 24
Finished Sep 24 02:40:14 PM UTC 24
Peak memory 229372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908770013 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.2908770013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.1838277188
Short name T206
Test name
Test status
Simulation time 1318628670 ps
CPU time 30.3 seconds
Started Sep 24 02:39:53 PM UTC 24
Finished Sep 24 02:40:26 PM UTC 24
Peak memory 235012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838277188 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.1838277188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.3926476498
Short name T441
Test name
Test status
Simulation time 176295647100 ps
CPU time 76.23 seconds
Started Sep 24 02:39:42 PM UTC 24
Finished Sep 24 02:41:01 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926476498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3926476498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.591917196
Short name T496
Test name
Test status
Simulation time 27051819 ps
CPU time 1.01 seconds
Started Sep 24 02:39:42 PM UTC 24
Finished Sep 24 02:39:44 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591917196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.591917196
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.566529211
Short name T500
Test name
Test status
Simulation time 198437969 ps
CPU time 9.81 seconds
Started Sep 24 02:39:44 PM UTC 24
Finished Sep 24 02:39:55 PM UTC 24
Peak memory 227328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566529211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.566529211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2097399873
Short name T497
Test name
Test status
Simulation time 151845930 ps
CPU time 1.6 seconds
Started Sep 24 02:39:42 PM UTC 24
Finished Sep 24 02:39:45 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097399873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2097399873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.3392470183
Short name T402
Test name
Test status
Simulation time 7152843320 ps
CPU time 20.23 seconds
Started Sep 24 02:39:45 PM UTC 24
Finished Sep 24 02:40:07 PM UTC 24
Peak memory 235120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392470183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3392470183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.3991002109
Short name T509
Test name
Test status
Simulation time 14867229 ps
CPU time 1.11 seconds
Started Sep 24 02:40:21 PM UTC 24
Finished Sep 24 02:40:23 PM UTC 24
Peak memory 215696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991002109 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.3991002109
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3347292942
Short name T290
Test name
Test status
Simulation time 1267797048 ps
CPU time 5.6 seconds
Started Sep 24 02:40:05 PM UTC 24
Finished Sep 24 02:40:12 PM UTC 24
Peak memory 234768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347292942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3347292942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.1450289593
Short name T499
Test name
Test status
Simulation time 20871701 ps
CPU time 1.21 seconds
Started Sep 24 02:39:53 PM UTC 24
Finished Sep 24 02:39:56 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450289593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1450289593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.3702018598
Short name T391
Test name
Test status
Simulation time 2300581932 ps
CPU time 58.37 seconds
Started Sep 24 02:40:13 PM UTC 24
Finished Sep 24 02:41:13 PM UTC 24
Peak memory 261440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702018598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3702018598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2152961939
Short name T38
Test name
Test status
Simulation time 6078689524 ps
CPU time 93.04 seconds
Started Sep 24 02:40:15 PM UTC 24
Finished Sep 24 02:41:50 PM UTC 24
Peak memory 263872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152961939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2152961939
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.3323379062
Short name T390
Test name
Test status
Simulation time 8150937956 ps
CPU time 40.62 seconds
Started Sep 24 02:40:15 PM UTC 24
Finished Sep 24 02:40:57 PM UTC 24
Peak memory 265588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323379062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.3323379062
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.472328425
Short name T421
Test name
Test status
Simulation time 2770536639 ps
CPU time 43.45 seconds
Started Sep 24 02:40:08 PM UTC 24
Finished Sep 24 02:40:53 PM UTC 24
Peak memory 245184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472328425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.472328425
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3414479685
Short name T286
Test name
Test status
Simulation time 809001891 ps
CPU time 4.89 seconds
Started Sep 24 02:40:02 PM UTC 24
Finished Sep 24 02:40:08 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414479685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3414479685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.151022524
Short name T505
Test name
Test status
Simulation time 29137390 ps
CPU time 3.4 seconds
Started Sep 24 02:40:03 PM UTC 24
Finished Sep 24 02:40:08 PM UTC 24
Peak memory 244608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151022524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.151022524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2571940706
Short name T414
Test name
Test status
Simulation time 3495252238 ps
CPU time 22.73 seconds
Started Sep 24 02:40:00 PM UTC 24
Finished Sep 24 02:40:24 PM UTC 24
Peak memory 251260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571940706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.2571940706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.916067985
Short name T258
Test name
Test status
Simulation time 29565325985 ps
CPU time 27.71 seconds
Started Sep 24 02:39:59 PM UTC 24
Finished Sep 24 02:40:28 PM UTC 24
Peak memory 245012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916067985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.916067985
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.2268553929
Short name T507
Test name
Test status
Simulation time 488605265 ps
CPU time 8.04 seconds
Started Sep 24 02:40:09 PM UTC 24
Finished Sep 24 02:40:18 PM UTC 24
Peak memory 233676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268553929 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.2268553929
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.2425011170
Short name T337
Test name
Test status
Simulation time 30100564573 ps
CPU time 241.92 seconds
Started Sep 24 02:40:19 PM UTC 24
Finished Sep 24 02:44:25 PM UTC 24
Peak memory 261892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425011170 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.2425011170
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.4169672408
Short name T443
Test name
Test status
Simulation time 21899393544 ps
CPU time 37.49 seconds
Started Sep 24 02:39:57 PM UTC 24
Finished Sep 24 02:40:36 PM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169672408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4169672408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.4008704844
Short name T508
Test name
Test status
Simulation time 7457398583 ps
CPU time 25.1 seconds
Started Sep 24 02:39:55 PM UTC 24
Finished Sep 24 02:40:22 PM UTC 24
Peak memory 227492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008704844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4008704844
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.1500662474
Short name T440
Test name
Test status
Simulation time 87941377 ps
CPU time 2.46 seconds
Started Sep 24 02:39:57 PM UTC 24
Finished Sep 24 02:40:01 PM UTC 24
Peak memory 227588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500662474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1500662474
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.3110290520
Short name T503
Test name
Test status
Simulation time 20647184 ps
CPU time 1.16 seconds
Started Sep 24 02:39:57 PM UTC 24
Finished Sep 24 02:39:59 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110290520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3110290520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.255118839
Short name T260
Test name
Test status
Simulation time 18230667263 ps
CPU time 26.53 seconds
Started Sep 24 02:40:04 PM UTC 24
Finished Sep 24 02:40:32 PM UTC 24
Peak memory 251460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255118839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.255118839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.2113852262
Short name T515
Test name
Test status
Simulation time 49146208 ps
CPU time 1.05 seconds
Started Sep 24 02:40:37 PM UTC 24
Finished Sep 24 02:40:39 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113852262 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.2113852262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.4286758252
Short name T238
Test name
Test status
Simulation time 12252263222 ps
CPU time 40.6 seconds
Started Sep 24 02:40:33 PM UTC 24
Finished Sep 24 02:41:15 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286758252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4286758252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.622583686
Short name T510
Test name
Test status
Simulation time 14743509 ps
CPU time 1.18 seconds
Started Sep 24 02:40:23 PM UTC 24
Finished Sep 24 02:40:26 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622583686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.622583686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.3596869566
Short name T394
Test name
Test status
Simulation time 630364910 ps
CPU time 13.06 seconds
Started Sep 24 02:40:34 PM UTC 24
Finished Sep 24 02:40:49 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596869566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3596869566
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1774612692
Short name T175
Test name
Test status
Simulation time 11298729876 ps
CPU time 111.82 seconds
Started Sep 24 02:40:35 PM UTC 24
Finished Sep 24 02:42:30 PM UTC 24
Peak memory 265860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774612692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1774612692
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.2749204663
Short name T372
Test name
Test status
Simulation time 159286715 ps
CPU time 6.55 seconds
Started Sep 24 02:40:33 PM UTC 24
Finished Sep 24 02:40:41 PM UTC 24
Peak memory 244916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749204663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2749204663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3732037390
Short name T596
Test name
Test status
Simulation time 32113263140 ps
CPU time 144.98 seconds
Started Sep 24 02:40:34 PM UTC 24
Finished Sep 24 02:43:02 PM UTC 24
Peak memory 263168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732037390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.3732037390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.1585961169
Short name T403
Test name
Test status
Simulation time 86407909 ps
CPU time 5.8 seconds
Started Sep 24 02:40:29 PM UTC 24
Finished Sep 24 02:40:37 PM UTC 24
Peak memory 235076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585961169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1585961169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.158272991
Short name T513
Test name
Test status
Simulation time 59478966 ps
CPU time 3.16 seconds
Started Sep 24 02:40:31 PM UTC 24
Finished Sep 24 02:40:35 PM UTC 24
Peak memory 233320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158272991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.158272991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3510470410
Short name T310
Test name
Test status
Simulation time 871636944 ps
CPU time 4.62 seconds
Started Sep 24 02:40:27 PM UTC 24
Finished Sep 24 02:40:33 PM UTC 24
Peak memory 245192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510470410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.3510470410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.2104664802
Short name T236
Test name
Test status
Simulation time 642135873 ps
CPU time 7.02 seconds
Started Sep 24 02:40:27 PM UTC 24
Finished Sep 24 02:40:35 PM UTC 24
Peak memory 234444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104664802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2104664802
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3710255472
Short name T517
Test name
Test status
Simulation time 194642752 ps
CPU time 5.65 seconds
Started Sep 24 02:40:34 PM UTC 24
Finished Sep 24 02:40:41 PM UTC 24
Peak memory 231160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710255472 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.3710255472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.3703254963
Short name T265
Test name
Test status
Simulation time 59466073983 ps
CPU time 56.72 seconds
Started Sep 24 02:40:37 PM UTC 24
Finished Sep 24 02:41:35 PM UTC 24
Peak memory 234944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703254963 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.3703254963
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.3337096282
Short name T528
Test name
Test status
Simulation time 10080260577 ps
CPU time 30.99 seconds
Started Sep 24 02:40:26 PM UTC 24
Finished Sep 24 02:40:58 PM UTC 24
Peak memory 231616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337096282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3337096282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.564179563
Short name T520
Test name
Test status
Simulation time 5773833987 ps
CPU time 20.87 seconds
Started Sep 24 02:40:25 PM UTC 24
Finished Sep 24 02:40:47 PM UTC 24
Peak memory 227576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564179563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.564179563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1075921676
Short name T512
Test name
Test status
Simulation time 79899825 ps
CPU time 1.93 seconds
Started Sep 24 02:40:27 PM UTC 24
Finished Sep 24 02:40:30 PM UTC 24
Peak memory 227008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075921676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1075921676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.2568992998
Short name T511
Test name
Test status
Simulation time 71598199 ps
CPU time 1.27 seconds
Started Sep 24 02:40:27 PM UTC 24
Finished Sep 24 02:40:29 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568992998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2568992998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.3137288348
Short name T404
Test name
Test status
Simulation time 26570563768 ps
CPU time 18.11 seconds
Started Sep 24 02:40:31 PM UTC 24
Finished Sep 24 02:40:50 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137288348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3137288348
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.304856675
Short name T525
Test name
Test status
Simulation time 24019149 ps
CPU time 1.2 seconds
Started Sep 24 02:40:54 PM UTC 24
Finished Sep 24 02:40:56 PM UTC 24
Peak memory 213652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304856675 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.304856675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.2849121135
Short name T523
Test name
Test status
Simulation time 527016220 ps
CPU time 4.18 seconds
Started Sep 24 02:40:48 PM UTC 24
Finished Sep 24 02:40:53 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849121135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2849121135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.2133155254
Short name T516
Test name
Test status
Simulation time 18348329 ps
CPU time 1.3 seconds
Started Sep 24 02:40:38 PM UTC 24
Finished Sep 24 02:40:40 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133155254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2133155254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.2488340115
Short name T635
Test name
Test status
Simulation time 184679253440 ps
CPU time 164.75 seconds
Started Sep 24 02:40:50 PM UTC 24
Finished Sep 24 02:43:38 PM UTC 24
Peak memory 261452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488340115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2488340115
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.4218383865
Short name T430
Test name
Test status
Simulation time 11824006469 ps
CPU time 151.78 seconds
Started Sep 24 02:40:51 PM UTC 24
Finished Sep 24 02:43:26 PM UTC 24
Peak memory 261628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218383865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4218383865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1628888437
Short name T422
Test name
Test status
Simulation time 12085255004 ps
CPU time 33.09 seconds
Started Sep 24 02:40:49 PM UTC 24
Finished Sep 24 02:41:24 PM UTC 24
Peak memory 251264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628888437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1628888437
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3691936097
Short name T658
Test name
Test status
Simulation time 20011143343 ps
CPU time 178.34 seconds
Started Sep 24 02:40:49 PM UTC 24
Finished Sep 24 02:43:51 PM UTC 24
Peak memory 267840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691936097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.3691936097
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.1746484665
Short name T373
Test name
Test status
Simulation time 838863497 ps
CPU time 7.04 seconds
Started Sep 24 02:40:46 PM UTC 24
Finished Sep 24 02:40:54 PM UTC 24
Peak memory 245128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746484665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1746484665
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.1520756966
Short name T405
Test name
Test status
Simulation time 72341905552 ps
CPU time 166.56 seconds
Started Sep 24 02:40:47 PM UTC 24
Finished Sep 24 02:43:36 PM UTC 24
Peak memory 245096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520756966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1520756966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1867511928
Short name T235
Test name
Test status
Simulation time 1477404769 ps
CPU time 6.21 seconds
Started Sep 24 02:40:46 PM UTC 24
Finished Sep 24 02:40:53 PM UTC 24
Peak memory 234696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867511928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.1867511928
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2295661425
Short name T521
Test name
Test status
Simulation time 60804985 ps
CPU time 3.27 seconds
Started Sep 24 02:40:43 PM UTC 24
Finished Sep 24 02:40:48 PM UTC 24
Peak memory 244660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295661425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2295661425
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.3732383703
Short name T533
Test name
Test status
Simulation time 919270967 ps
CPU time 16.98 seconds
Started Sep 24 02:40:50 PM UTC 24
Finished Sep 24 02:41:09 PM UTC 24
Peak memory 233272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732383703 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.3732383703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.2921221494
Short name T526
Test name
Test status
Simulation time 37991927 ps
CPU time 1.43 seconds
Started Sep 24 02:40:54 PM UTC 24
Finished Sep 24 02:40:56 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921221494 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.2921221494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.3456981199
Short name T428
Test name
Test status
Simulation time 292686623 ps
CPU time 6.72 seconds
Started Sep 24 02:40:41 PM UTC 24
Finished Sep 24 02:40:49 PM UTC 24
Peak memory 227632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456981199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3456981199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.1878917005
Short name T522
Test name
Test status
Simulation time 1396142126 ps
CPU time 7.49 seconds
Started Sep 24 02:40:41 PM UTC 24
Finished Sep 24 02:40:50 PM UTC 24
Peak memory 227380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878917005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1878917005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.542930903
Short name T519
Test name
Test status
Simulation time 233921288 ps
CPU time 2.42 seconds
Started Sep 24 02:40:42 PM UTC 24
Finished Sep 24 02:40:46 PM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542930903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.542930903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3569360761
Short name T518
Test name
Test status
Simulation time 47273167 ps
CPU time 1.17 seconds
Started Sep 24 02:40:42 PM UTC 24
Finished Sep 24 02:40:44 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569360761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3569360761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.1409554153
Short name T268
Test name
Test status
Simulation time 6867732902 ps
CPU time 21.71 seconds
Started Sep 24 02:40:48 PM UTC 24
Finished Sep 24 02:41:11 PM UTC 24
Peak memory 261648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409554153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1409554153
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.538733720
Short name T531
Test name
Test status
Simulation time 13146053 ps
CPU time 1.14 seconds
Started Sep 24 02:41:06 PM UTC 24
Finished Sep 24 02:41:08 PM UTC 24
Peak memory 213592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538733720 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.538733720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.685287303
Short name T245
Test name
Test status
Simulation time 134065126 ps
CPU time 3.51 seconds
Started Sep 24 02:40:59 PM UTC 24
Finished Sep 24 02:41:03 PM UTC 24
Peak memory 244924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685287303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.685287303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.2714130840
Short name T524
Test name
Test status
Simulation time 16739896 ps
CPU time 1.1 seconds
Started Sep 24 02:40:54 PM UTC 24
Finished Sep 24 02:40:56 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714130840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2714130840
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.3854812964
Short name T296
Test name
Test status
Simulation time 21534855626 ps
CPU time 61.98 seconds
Started Sep 24 02:41:02 PM UTC 24
Finished Sep 24 02:42:06 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854812964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3854812964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.381293232
Short name T988
Test name
Test status
Simulation time 45753359039 ps
CPU time 552.07 seconds
Started Sep 24 02:41:03 PM UTC 24
Finished Sep 24 02:50:22 PM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381293232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.381293232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.1088575486
Short name T591
Test name
Test status
Simulation time 22241125680 ps
CPU time 97.25 seconds
Started Sep 24 02:41:05 PM UTC 24
Finished Sep 24 02:42:44 PM UTC 24
Peak memory 261752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088575486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.1088575486
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.3127086473
Short name T581
Test name
Test status
Simulation time 5713437448 ps
CPU time 83.01 seconds
Started Sep 24 02:41:01 PM UTC 24
Finished Sep 24 02:42:26 PM UTC 24
Peak memory 251120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127086473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3127086473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.622448635
Short name T241
Test name
Test status
Simulation time 140340959 ps
CPU time 5.54 seconds
Started Sep 24 02:40:59 PM UTC 24
Finished Sep 24 02:41:05 PM UTC 24
Peak memory 244948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622448635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.622448635
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.4023783703
Short name T297
Test name
Test status
Simulation time 1499336469 ps
CPU time 23.41 seconds
Started Sep 24 02:40:59 PM UTC 24
Finished Sep 24 02:41:23 PM UTC 24
Peak memory 249036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023783703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4023783703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1409627231
Short name T278
Test name
Test status
Simulation time 4632451580 ps
CPU time 23.42 seconds
Started Sep 24 02:40:57 PM UTC 24
Finished Sep 24 02:41:22 PM UTC 24
Peak memory 234768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409627231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.1409627231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1867514509
Short name T240
Test name
Test status
Simulation time 1446686308 ps
CPU time 9.13 seconds
Started Sep 24 02:40:57 PM UTC 24
Finished Sep 24 02:41:08 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867514509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1867514509
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.3571488864
Short name T538
Test name
Test status
Simulation time 5066889017 ps
CPU time 21.07 seconds
Started Sep 24 02:41:02 PM UTC 24
Finished Sep 24 02:41:25 PM UTC 24
Peak memory 233700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571488864 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.3571488864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.3582818303
Short name T209
Test name
Test status
Simulation time 40109678441 ps
CPU time 149.51 seconds
Started Sep 24 02:41:05 PM UTC 24
Finished Sep 24 02:43:37 PM UTC 24
Peak memory 263680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582818303 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.3582818303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.2465081275
Short name T442
Test name
Test status
Simulation time 115052436187 ps
CPU time 47.87 seconds
Started Sep 24 02:40:55 PM UTC 24
Finished Sep 24 02:41:44 PM UTC 24
Peak memory 227716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465081275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2465081275
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2184503722
Short name T527
Test name
Test status
Simulation time 32159390 ps
CPU time 1.01 seconds
Started Sep 24 02:40:55 PM UTC 24
Finished Sep 24 02:40:57 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184503722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2184503722
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.2254817674
Short name T530
Test name
Test status
Simulation time 150797848 ps
CPU time 1.41 seconds
Started Sep 24 02:40:57 PM UTC 24
Finished Sep 24 02:41:00 PM UTC 24
Peak memory 215816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254817674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2254817674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.3845762962
Short name T529
Test name
Test status
Simulation time 62756296 ps
CPU time 1.21 seconds
Started Sep 24 02:40:57 PM UTC 24
Finished Sep 24 02:41:00 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845762962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3845762962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.3149729162
Short name T542
Test name
Test status
Simulation time 17862317151 ps
CPU time 28.8 seconds
Started Sep 24 02:40:59 PM UTC 24
Finished Sep 24 02:41:29 PM UTC 24
Peak memory 251204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149729162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3149729162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.2786849281
Short name T539
Test name
Test status
Simulation time 34319634 ps
CPU time 1.13 seconds
Started Sep 24 02:41:24 PM UTC 24
Finished Sep 24 02:41:26 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786849281 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.2786849281
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.1009779615
Short name T532
Test name
Test status
Simulation time 14990945 ps
CPU time 1.19 seconds
Started Sep 24 02:41:06 PM UTC 24
Finished Sep 24 02:41:08 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009779615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1009779615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1106672662
Short name T570
Test name
Test status
Simulation time 63432271607 ps
CPU time 52.91 seconds
Started Sep 24 02:41:18 PM UTC 24
Finished Sep 24 02:42:13 PM UTC 24
Peak memory 234776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106672662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1106672662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.1187999844
Short name T889
Test name
Test status
Simulation time 37694902842 ps
CPU time 368.58 seconds
Started Sep 24 02:41:20 PM UTC 24
Finished Sep 24 02:47:33 PM UTC 24
Peak memory 267708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187999844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1187999844
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1023715264
Short name T252
Test name
Test status
Simulation time 27827099818 ps
CPU time 142.48 seconds
Started Sep 24 02:41:21 PM UTC 24
Finished Sep 24 02:43:46 PM UTC 24
Peak memory 261880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023715264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.1023715264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.590906641
Short name T426
Test name
Test status
Simulation time 88753483 ps
CPU time 3.79 seconds
Started Sep 24 02:41:14 PM UTC 24
Finished Sep 24 02:41:19 PM UTC 24
Peak memory 234696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590906641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.590906641
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3070334397
Short name T327
Test name
Test status
Simulation time 944875049 ps
CPU time 16.8 seconds
Started Sep 24 02:41:16 PM UTC 24
Finished Sep 24 02:41:35 PM UTC 24
Peak memory 244976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070334397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.3070334397
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.3081982287
Short name T264
Test name
Test status
Simulation time 349825249 ps
CPU time 5.5 seconds
Started Sep 24 02:41:11 PM UTC 24
Finished Sep 24 02:41:17 PM UTC 24
Peak memory 234680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081982287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3081982287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.164176522
Short name T535
Test name
Test status
Simulation time 106208949 ps
CPU time 3.95 seconds
Started Sep 24 02:41:12 PM UTC 24
Finished Sep 24 02:41:17 PM UTC 24
Peak memory 244924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164176522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.164176522
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.2482604138
Short name T295
Test name
Test status
Simulation time 18577275190 ps
CPU time 15.99 seconds
Started Sep 24 02:41:11 PM UTC 24
Finished Sep 24 02:41:28 PM UTC 24
Peak memory 234768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482604138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.2482604138
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.951811418
Short name T357
Test name
Test status
Simulation time 3535290557 ps
CPU time 23.65 seconds
Started Sep 24 02:41:11 PM UTC 24
Finished Sep 24 02:41:36 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951811418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.951811418
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3017639448
Short name T549
Test name
Test status
Simulation time 4927795282 ps
CPU time 22.67 seconds
Started Sep 24 02:41:17 PM UTC 24
Finished Sep 24 02:41:41 PM UTC 24
Peak memory 231352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017639448 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.3017639448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.680339069
Short name T537
Test name
Test status
Simulation time 1610817096 ps
CPU time 13.05 seconds
Started Sep 24 02:41:09 PM UTC 24
Finished Sep 24 02:41:24 PM UTC 24
Peak memory 227760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680339069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.680339069
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2260286126
Short name T536
Test name
Test status
Simulation time 1365967115 ps
CPU time 10.09 seconds
Started Sep 24 02:41:08 PM UTC 24
Finished Sep 24 02:41:19 PM UTC 24
Peak memory 227328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260286126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2260286126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.1790765794
Short name T439
Test name
Test status
Simulation time 151362472 ps
CPU time 1.67 seconds
Started Sep 24 02:41:09 PM UTC 24
Finished Sep 24 02:41:12 PM UTC 24
Peak memory 226076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790765794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1790765794
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3920737353
Short name T534
Test name
Test status
Simulation time 126189970 ps
CPU time 1.19 seconds
Started Sep 24 02:41:09 PM UTC 24
Finished Sep 24 02:41:12 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920737353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3920737353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3233367622
Short name T396
Test name
Test status
Simulation time 17745036975 ps
CPU time 48.29 seconds
Started Sep 24 02:41:13 PM UTC 24
Finished Sep 24 02:42:03 PM UTC 24
Peak memory 245012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233367622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3233367622
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.2139568561
Short name T546
Test name
Test status
Simulation time 33570744 ps
CPU time 1.09 seconds
Started Sep 24 02:41:37 PM UTC 24
Finished Sep 24 02:41:39 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139568561 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.2139568561
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1382739492
Short name T85
Test name
Test status
Simulation time 5437359639 ps
CPU time 20.21 seconds
Started Sep 24 02:41:30 PM UTC 24
Finished Sep 24 02:41:51 PM UTC 24
Peak memory 245312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382739492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1382739492
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.2999682338
Short name T540
Test name
Test status
Simulation time 20936296 ps
CPU time 1.1 seconds
Started Sep 24 02:41:24 PM UTC 24
Finished Sep 24 02:41:26 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999682338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2999682338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.2065552629
Short name T183
Test name
Test status
Simulation time 30949671189 ps
CPU time 62.98 seconds
Started Sep 24 02:41:33 PM UTC 24
Finished Sep 24 02:42:38 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065552629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2065552629
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.3912812453
Short name T308
Test name
Test status
Simulation time 5687821465 ps
CPU time 112.32 seconds
Started Sep 24 02:41:33 PM UTC 24
Finished Sep 24 02:43:28 PM UTC 24
Peak memory 267968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912812453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3912812453
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1652882732
Short name T346
Test name
Test status
Simulation time 39422340630 ps
CPU time 442.86 seconds
Started Sep 24 02:41:33 PM UTC 24
Finished Sep 24 02:49:03 PM UTC 24
Peak memory 277944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652882732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.1652882732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.758489590
Short name T423
Test name
Test status
Simulation time 374431514 ps
CPU time 14.16 seconds
Started Sep 24 02:41:31 PM UTC 24
Finished Sep 24 02:41:46 PM UTC 24
Peak memory 261312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758489590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.758489590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.495716307
Short name T89
Test name
Test status
Simulation time 3046342910 ps
CPU time 19.05 seconds
Started Sep 24 02:41:32 PM UTC 24
Finished Sep 24 02:41:52 PM UTC 24
Peak memory 249276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495716307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.495716307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2605182325
Short name T279
Test name
Test status
Simulation time 143832275 ps
CPU time 6.17 seconds
Started Sep 24 02:41:28 PM UTC 24
Finished Sep 24 02:41:36 PM UTC 24
Peak memory 244952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605182325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2605182325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.3910744064
Short name T548
Test name
Test status
Simulation time 1159628408 ps
CPU time 9.69 seconds
Started Sep 24 02:41:30 PM UTC 24
Finished Sep 24 02:41:41 PM UTC 24
Peak memory 261312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910744064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3910744064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.582518504
Short name T250
Test name
Test status
Simulation time 1665765805 ps
CPU time 7.94 seconds
Started Sep 24 02:41:28 PM UTC 24
Finished Sep 24 02:41:38 PM UTC 24
Peak memory 245188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582518504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.582518504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.849032876
Short name T366
Test name
Test status
Simulation time 488215547 ps
CPU time 3.96 seconds
Started Sep 24 02:41:27 PM UTC 24
Finished Sep 24 02:41:33 PM UTC 24
Peak memory 234700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849032876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.849032876
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2487452803
Short name T558
Test name
Test status
Simulation time 5365515340 ps
CPU time 23.24 seconds
Started Sep 24 02:41:33 PM UTC 24
Finished Sep 24 02:41:58 PM UTC 24
Peak memory 231284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487452803 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.2487452803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.1453140778
Short name T545
Test name
Test status
Simulation time 43833199 ps
CPU time 1.64 seconds
Started Sep 24 02:41:36 PM UTC 24
Finished Sep 24 02:41:38 PM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453140778 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.1453140778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.1849235094
Short name T553
Test name
Test status
Simulation time 2477107669 ps
CPU time 21.08 seconds
Started Sep 24 02:41:25 PM UTC 24
Finished Sep 24 02:41:48 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849235094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1849235094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1478716662
Short name T543
Test name
Test status
Simulation time 2890173965 ps
CPU time 3.6 seconds
Started Sep 24 02:41:25 PM UTC 24
Finished Sep 24 02:41:30 PM UTC 24
Peak memory 216288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478716662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1478716662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.2686475927
Short name T544
Test name
Test status
Simulation time 98707845 ps
CPU time 3.81 seconds
Started Sep 24 02:41:27 PM UTC 24
Finished Sep 24 02:41:32 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686475927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2686475927
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.2594114521
Short name T541
Test name
Test status
Simulation time 337219639 ps
CPU time 1.44 seconds
Started Sep 24 02:41:26 PM UTC 24
Finished Sep 24 02:41:29 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594114521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2594114521
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.1498539057
Short name T88
Test name
Test status
Simulation time 8152438162 ps
CPU time 20.94 seconds
Started Sep 24 02:41:30 PM UTC 24
Finished Sep 24 02:41:52 PM UTC 24
Peak memory 245320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498539057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1498539057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1096585755
Short name T105
Test name
Test status
Simulation time 64570297 ps
CPU time 1.1 seconds
Started Sep 24 02:37:00 PM UTC 24
Finished Sep 24 02:37:03 PM UTC 24
Peak memory 213588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096585755 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1096585755
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.255535157
Short name T120
Test name
Test status
Simulation time 2224506012 ps
CPU time 5.97 seconds
Started Sep 24 02:36:55 PM UTC 24
Finished Sep 24 02:37:02 PM UTC 24
Peak memory 234772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255535157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.255535157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.4020894921
Short name T146
Test name
Test status
Simulation time 72221483 ps
CPU time 1.06 seconds
Started Sep 24 02:36:52 PM UTC 24
Finished Sep 24 02:36:54 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020894921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4020894921
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2623811217
Short name T225
Test name
Test status
Simulation time 17487419247 ps
CPU time 142.19 seconds
Started Sep 24 02:36:58 PM UTC 24
Finished Sep 24 02:39:23 PM UTC 24
Peak memory 249668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623811217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2623811217
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4250363709
Short name T49
Test name
Test status
Simulation time 2517517352 ps
CPU time 23.82 seconds
Started Sep 24 02:36:56 PM UTC 24
Finished Sep 24 02:37:21 PM UTC 24
Peak memory 247428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250363709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4250363709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.3050772040
Short name T103
Test name
Test status
Simulation time 2333848065 ps
CPU time 14.57 seconds
Started Sep 24 02:36:54 PM UTC 24
Finished Sep 24 02:37:11 PM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050772040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3050772040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3390181174
Short name T99
Test name
Test status
Simulation time 2112900055 ps
CPU time 9.35 seconds
Started Sep 24 02:36:54 PM UTC 24
Finished Sep 24 02:37:05 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390181174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3390181174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.4094072899
Short name T59
Test name
Test status
Simulation time 34295806939 ps
CPU time 18.11 seconds
Started Sep 24 02:36:54 PM UTC 24
Finished Sep 24 02:37:14 PM UTC 24
Peak memory 234828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094072899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.4094072899
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3746775987
Short name T101
Test name
Test status
Simulation time 1337310324 ps
CPU time 13.79 seconds
Started Sep 24 02:36:53 PM UTC 24
Finished Sep 24 02:37:09 PM UTC 24
Peak memory 245012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746775987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3746775987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2653358814
Short name T102
Test name
Test status
Simulation time 1710493989 ps
CPU time 11.06 seconds
Started Sep 24 02:36:57 PM UTC 24
Finished Sep 24 02:37:09 PM UTC 24
Peak memory 233296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653358814 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.2653358814
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.2265954525
Short name T33
Test name
Test status
Simulation time 85166839 ps
CPU time 1.44 seconds
Started Sep 24 02:37:00 PM UTC 24
Finished Sep 24 02:37:03 PM UTC 24
Peak memory 256992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265954525 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2265954525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2834025636
Short name T915
Test name
Test status
Simulation time 62536544596 ps
CPU time 659.71 seconds
Started Sep 24 02:37:00 PM UTC 24
Finished Sep 24 02:48:09 PM UTC 24
Peak memory 261564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834025636 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.2834025636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3348953451
Short name T121
Test name
Test status
Simulation time 12056944 ps
CPU time 1.21 seconds
Started Sep 24 02:36:53 PM UTC 24
Finished Sep 24 02:36:56 PM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348953451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3348953451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3682661104
Short name T127
Test name
Test status
Simulation time 3167308695 ps
CPU time 18.64 seconds
Started Sep 24 02:36:53 PM UTC 24
Finished Sep 24 02:37:14 PM UTC 24
Peak memory 227492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682661104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3682661104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.2524209039
Short name T28
Test name
Test status
Simulation time 160758917 ps
CPU time 1.64 seconds
Started Sep 24 02:36:53 PM UTC 24
Finished Sep 24 02:36:57 PM UTC 24
Peak memory 217008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524209039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2524209039
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1629874219
Short name T27
Test name
Test status
Simulation time 46651840 ps
CPU time 1.43 seconds
Started Sep 24 02:36:53 PM UTC 24
Finished Sep 24 02:36:56 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629874219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1629874219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.2843918171
Short name T119
Test name
Test status
Simulation time 3089870610 ps
CPU time 3.49 seconds
Started Sep 24 02:36:54 PM UTC 24
Finished Sep 24 02:36:59 PM UTC 24
Peak memory 235092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843918171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2843918171
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.915860725
Short name T86
Test name
Test status
Simulation time 42204663 ps
CPU time 1.17 seconds
Started Sep 24 02:41:50 PM UTC 24
Finished Sep 24 02:41:52 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915860725 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.915860725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.562370556
Short name T556
Test name
Test status
Simulation time 139072078 ps
CPU time 4.12 seconds
Started Sep 24 02:41:43 PM UTC 24
Finished Sep 24 02:41:49 PM UTC 24
Peak memory 235004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562370556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.562370556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2096389248
Short name T547
Test name
Test status
Simulation time 43996973 ps
CPU time 1.21 seconds
Started Sep 24 02:41:37 PM UTC 24
Finished Sep 24 02:41:39 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096389248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2096389248
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.3232092612
Short name T392
Test name
Test status
Simulation time 1372945789 ps
CPU time 21.72 seconds
Started Sep 24 02:41:49 PM UTC 24
Finished Sep 24 02:42:12 PM UTC 24
Peak memory 261316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232092612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3232092612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.121814550
Short name T433
Test name
Test status
Simulation time 3143478849 ps
CPU time 31.77 seconds
Started Sep 24 02:41:49 PM UTC 24
Finished Sep 24 02:42:22 PM UTC 24
Peak memory 234900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121814550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.121814550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2282368504
Short name T302
Test name
Test status
Simulation time 101056694786 ps
CPU time 264.13 seconds
Started Sep 24 02:41:49 PM UTC 24
Finished Sep 24 02:46:18 PM UTC 24
Peak memory 261564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282368504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.2282368504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.1481333092
Short name T573
Test name
Test status
Simulation time 10341036130 ps
CPU time 33.35 seconds
Started Sep 24 02:41:43 PM UTC 24
Finished Sep 24 02:42:18 PM UTC 24
Peak memory 245064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481333092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1481333092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.3688518024
Short name T554
Test name
Test status
Simulation time 12323381 ps
CPU time 1.22 seconds
Started Sep 24 02:41:45 PM UTC 24
Finished Sep 24 02:41:48 PM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688518024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.3688518024
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.1116019986
Short name T87
Test name
Test status
Simulation time 3804977466 ps
CPU time 8.55 seconds
Started Sep 24 02:41:42 PM UTC 24
Finished Sep 24 02:41:52 PM UTC 24
Peak memory 245336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116019986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1116019986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.150471262
Short name T376
Test name
Test status
Simulation time 8920302597 ps
CPU time 21.42 seconds
Started Sep 24 02:41:42 PM UTC 24
Finished Sep 24 02:42:05 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150471262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.150471262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.3855662741
Short name T408
Test name
Test status
Simulation time 2064980668 ps
CPU time 8.11 seconds
Started Sep 24 02:41:40 PM UTC 24
Finished Sep 24 02:41:49 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855662741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.3855662741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.245046180
Short name T92
Test name
Test status
Simulation time 4522608829 ps
CPU time 15.59 seconds
Started Sep 24 02:41:40 PM UTC 24
Finished Sep 24 02:41:57 PM UTC 24
Peak memory 245004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245046180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.245046180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.1670574323
Short name T560
Test name
Test status
Simulation time 5408651470 ps
CPU time 15.33 seconds
Started Sep 24 02:41:45 PM UTC 24
Finished Sep 24 02:42:02 PM UTC 24
Peak memory 231292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670574323 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.1670574323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2773798296
Short name T693
Test name
Test status
Simulation time 153847435385 ps
CPU time 149.63 seconds
Started Sep 24 02:41:49 PM UTC 24
Finished Sep 24 02:44:22 PM UTC 24
Peak memory 261616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773798296 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.2773798296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.1160081921
Short name T555
Test name
Test status
Simulation time 1459571047 ps
CPU time 8.37 seconds
Started Sep 24 02:41:38 PM UTC 24
Finished Sep 24 02:41:48 PM UTC 24
Peak memory 227588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160081921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1160081921
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.2863149222
Short name T557
Test name
Test status
Simulation time 6753426140 ps
CPU time 11.43 seconds
Started Sep 24 02:41:37 PM UTC 24
Finished Sep 24 02:41:50 PM UTC 24
Peak memory 227464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863149222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2863149222
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.4286929843
Short name T550
Test name
Test status
Simulation time 32065918 ps
CPU time 1.01 seconds
Started Sep 24 02:41:40 PM UTC 24
Finished Sep 24 02:41:42 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286929843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4286929843
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.3322723350
Short name T551
Test name
Test status
Simulation time 135277020 ps
CPU time 1.64 seconds
Started Sep 24 02:41:40 PM UTC 24
Finished Sep 24 02:41:43 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322723350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3322723350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.876568939
Short name T282
Test name
Test status
Simulation time 3864263913 ps
CPU time 24.41 seconds
Started Sep 24 02:41:42 PM UTC 24
Finished Sep 24 02:42:08 PM UTC 24
Peak memory 251220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876568939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.876568939
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.1220438269
Short name T562
Test name
Test status
Simulation time 13741502 ps
CPU time 1.18 seconds
Started Sep 24 02:42:05 PM UTC 24
Finished Sep 24 02:42:08 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220438269 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1220438269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2937592132
Short name T566
Test name
Test status
Simulation time 1276221221 ps
CPU time 10.58 seconds
Started Sep 24 02:41:59 PM UTC 24
Finished Sep 24 02:42:10 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937592132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2937592132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.854248495
Short name T90
Test name
Test status
Simulation time 69440850 ps
CPU time 1.29 seconds
Started Sep 24 02:41:52 PM UTC 24
Finished Sep 24 02:41:54 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854248495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.854248495
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.2123044656
Short name T112
Test name
Test status
Simulation time 40117788369 ps
CPU time 294.78 seconds
Started Sep 24 02:42:03 PM UTC 24
Finished Sep 24 02:47:02 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123044656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2123044656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1776278661
Short name T300
Test name
Test status
Simulation time 29634271924 ps
CPU time 273.58 seconds
Started Sep 24 02:42:03 PM UTC 24
Finished Sep 24 02:46:41 PM UTC 24
Peak memory 267776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776278661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1776278661
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.1555695256
Short name T419
Test name
Test status
Simulation time 731955128 ps
CPU time 6.59 seconds
Started Sep 24 02:41:59 PM UTC 24
Finished Sep 24 02:42:06 PM UTC 24
Peak memory 245004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555695256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1555695256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3146979126
Short name T323
Test name
Test status
Simulation time 5937816472 ps
CPU time 46.04 seconds
Started Sep 24 02:41:59 PM UTC 24
Finished Sep 24 02:42:46 PM UTC 24
Peak memory 249140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146979126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.3146979126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.4240134407
Short name T281
Test name
Test status
Simulation time 1123824741 ps
CPU time 9.07 seconds
Started Sep 24 02:41:54 PM UTC 24
Finished Sep 24 02:42:04 PM UTC 24
Peak memory 234908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240134407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4240134407
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.2114152929
Short name T592
Test name
Test status
Simulation time 11589437523 ps
CPU time 51.33 seconds
Started Sep 24 02:41:56 PM UTC 24
Finished Sep 24 02:42:49 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114152929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2114152929
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.4151396681
Short name T561
Test name
Test status
Simulation time 23051056970 ps
CPU time 11.98 seconds
Started Sep 24 02:41:54 PM UTC 24
Finished Sep 24 02:42:07 PM UTC 24
Peak memory 245376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151396681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.4151396681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.863644698
Short name T272
Test name
Test status
Simulation time 5283599935 ps
CPU time 10.71 seconds
Started Sep 24 02:41:54 PM UTC 24
Finished Sep 24 02:42:06 PM UTC 24
Peak memory 235020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863644698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.863644698
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3043624925
Short name T568
Test name
Test status
Simulation time 2351155061 ps
CPU time 9.17 seconds
Started Sep 24 02:42:01 PM UTC 24
Finished Sep 24 02:42:11 PM UTC 24
Peak memory 229500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043624925 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.3043624925
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.148733000
Short name T277
Test name
Test status
Simulation time 5611972704 ps
CPU time 74.61 seconds
Started Sep 24 02:42:05 PM UTC 24
Finished Sep 24 02:43:22 PM UTC 24
Peak memory 267968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148733000 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.148733000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2879505106
Short name T565
Test name
Test status
Simulation time 2704619746 ps
CPU time 16.4 seconds
Started Sep 24 02:41:52 PM UTC 24
Finished Sep 24 02:42:09 PM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879505106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2879505106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.1705180315
Short name T559
Test name
Test status
Simulation time 9958196089 ps
CPU time 8.48 seconds
Started Sep 24 02:41:52 PM UTC 24
Finished Sep 24 02:42:01 PM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705180315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1705180315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.2031008754
Short name T93
Test name
Test status
Simulation time 58391958 ps
CPU time 2.16 seconds
Started Sep 24 02:41:54 PM UTC 24
Finished Sep 24 02:41:57 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031008754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2031008754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.2715816488
Short name T91
Test name
Test status
Simulation time 759460709 ps
CPU time 1.57 seconds
Started Sep 24 02:41:54 PM UTC 24
Finished Sep 24 02:41:57 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715816488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2715816488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.1666842264
Short name T564
Test name
Test status
Simulation time 4740511034 ps
CPU time 9.33 seconds
Started Sep 24 02:41:59 PM UTC 24
Finished Sep 24 02:42:09 PM UTC 24
Peak memory 245128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666842264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1666842264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.2477756795
Short name T574
Test name
Test status
Simulation time 15051462 ps
CPU time 1.23 seconds
Started Sep 24 02:42:17 PM UTC 24
Finished Sep 24 02:42:19 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477756795 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.2477756795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2027568513
Short name T572
Test name
Test status
Simulation time 189762277 ps
CPU time 3.88 seconds
Started Sep 24 02:42:11 PM UTC 24
Finished Sep 24 02:42:16 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027568513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2027568513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.2367374544
Short name T563
Test name
Test status
Simulation time 14974871 ps
CPU time 1.2 seconds
Started Sep 24 02:42:05 PM UTC 24
Finished Sep 24 02:42:08 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367374544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2367374544
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.896235918
Short name T182
Test name
Test status
Simulation time 931931675 ps
CPU time 23.33 seconds
Started Sep 24 02:42:13 PM UTC 24
Finished Sep 24 02:42:37 PM UTC 24
Peak memory 261316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896235918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.896235918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2073804221
Short name T647
Test name
Test status
Simulation time 13536733555 ps
CPU time 90.17 seconds
Started Sep 24 02:42:14 PM UTC 24
Finished Sep 24 02:43:46 PM UTC 24
Peak memory 245188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073804221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2073804221
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.3248025486
Short name T579
Test name
Test status
Simulation time 450819862 ps
CPU time 10.72 seconds
Started Sep 24 02:42:12 PM UTC 24
Finished Sep 24 02:42:24 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248025486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3248025486
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.276329882
Short name T381
Test name
Test status
Simulation time 1976022001 ps
CPU time 37.97 seconds
Started Sep 24 02:42:12 PM UTC 24
Finished Sep 24 02:42:52 PM UTC 24
Peak memory 261364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276329882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.276329882
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.629143059
Short name T582
Test name
Test status
Simulation time 8998015200 ps
CPU time 17.33 seconds
Started Sep 24 02:42:09 PM UTC 24
Finished Sep 24 02:42:27 PM UTC 24
Peak memory 235032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629143059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.629143059
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.928605456
Short name T184
Test name
Test status
Simulation time 1832849741 ps
CPU time 26.27 seconds
Started Sep 24 02:42:11 PM UTC 24
Finished Sep 24 02:42:39 PM UTC 24
Peak memory 229388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928605456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.928605456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1663686533
Short name T370
Test name
Test status
Simulation time 934358153 ps
CPU time 14.38 seconds
Started Sep 24 02:42:09 PM UTC 24
Finished Sep 24 02:42:24 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663686533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.1663686533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.4222704481
Short name T571
Test name
Test status
Simulation time 135639595 ps
CPU time 3.53 seconds
Started Sep 24 02:42:09 PM UTC 24
Finished Sep 24 02:42:13 PM UTC 24
Peak memory 234684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222704481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4222704481
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1409680112
Short name T575
Test name
Test status
Simulation time 956166480 ps
CPU time 7.16 seconds
Started Sep 24 02:42:13 PM UTC 24
Finished Sep 24 02:42:21 PM UTC 24
Peak memory 233312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409680112 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.1409680112
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.909912378
Short name T80
Test name
Test status
Simulation time 1942312818 ps
CPU time 39.46 seconds
Started Sep 24 02:42:15 PM UTC 24
Finished Sep 24 02:42:56 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909912378 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.909912378
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1017743339
Short name T180
Test name
Test status
Simulation time 2830590096 ps
CPU time 26.3 seconds
Started Sep 24 02:42:09 PM UTC 24
Finished Sep 24 02:42:36 PM UTC 24
Peak memory 227716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017743339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1017743339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1324628790
Short name T577
Test name
Test status
Simulation time 3157586894 ps
CPU time 12.94 seconds
Started Sep 24 02:42:08 PM UTC 24
Finished Sep 24 02:42:22 PM UTC 24
Peak memory 227768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324628790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1324628790
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.739949546
Short name T569
Test name
Test status
Simulation time 164204206 ps
CPU time 1.98 seconds
Started Sep 24 02:42:09 PM UTC 24
Finished Sep 24 02:42:12 PM UTC 24
Peak memory 227132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739949546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.739949546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.1415680653
Short name T567
Test name
Test status
Simulation time 27862805 ps
CPU time 1.29 seconds
Started Sep 24 02:42:09 PM UTC 24
Finished Sep 24 02:42:11 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415680653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1415680653
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.3649673430
Short name T578
Test name
Test status
Simulation time 1522606529 ps
CPU time 10.18 seconds
Started Sep 24 02:42:11 PM UTC 24
Finished Sep 24 02:42:22 PM UTC 24
Peak memory 235008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649673430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3649673430
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.282538243
Short name T584
Test name
Test status
Simulation time 87603823 ps
CPU time 1.08 seconds
Started Sep 24 02:42:37 PM UTC 24
Finished Sep 24 02:42:39 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282538243 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.282538243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.1783106775
Short name T589
Test name
Test status
Simulation time 1904599189 ps
CPU time 13.14 seconds
Started Sep 24 02:42:27 PM UTC 24
Finished Sep 24 02:42:41 PM UTC 24
Peak memory 245136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783106775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1783106775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.4123459260
Short name T576
Test name
Test status
Simulation time 52582955 ps
CPU time 1.25 seconds
Started Sep 24 02:42:19 PM UTC 24
Finished Sep 24 02:42:21 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123459260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4123459260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.4047537523
Short name T608
Test name
Test status
Simulation time 1820140212 ps
CPU time 38.27 seconds
Started Sep 24 02:42:32 PM UTC 24
Finished Sep 24 02:43:12 PM UTC 24
Peak memory 261576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047537523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4047537523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1173118129
Short name T666
Test name
Test status
Simulation time 19323361653 ps
CPU time 80.72 seconds
Started Sep 24 02:42:34 PM UTC 24
Finished Sep 24 02:43:56 PM UTC 24
Peak memory 261696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173118129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1173118129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3651106763
Short name T305
Test name
Test status
Simulation time 27315617980 ps
CPU time 133.53 seconds
Started Sep 24 02:42:34 PM UTC 24
Finished Sep 24 02:44:50 PM UTC 24
Peak memory 261560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651106763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.3651106763
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.2158080524
Short name T177
Test name
Test status
Simulation time 125729058 ps
CPU time 3.31 seconds
Started Sep 24 02:42:28 PM UTC 24
Finished Sep 24 02:42:33 PM UTC 24
Peak memory 234636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158080524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2158080524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3641756836
Short name T677
Test name
Test status
Simulation time 10257378138 ps
CPU time 99.21 seconds
Started Sep 24 02:42:29 PM UTC 24
Finished Sep 24 02:44:11 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641756836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.3641756836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2906607023
Short name T388
Test name
Test status
Simulation time 2898315971 ps
CPU time 17.55 seconds
Started Sep 24 02:42:25 PM UTC 24
Finished Sep 24 02:42:44 PM UTC 24
Peak memory 242116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906607023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2906607023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.3002855327
Short name T684
Test name
Test status
Simulation time 38213308556 ps
CPU time 107.51 seconds
Started Sep 24 02:42:26 PM UTC 24
Finished Sep 24 02:44:16 PM UTC 24
Peak memory 249144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002855327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3002855327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.153230462
Short name T287
Test name
Test status
Simulation time 35923919555 ps
CPU time 33.53 seconds
Started Sep 24 02:42:24 PM UTC 24
Finished Sep 24 02:42:59 PM UTC 24
Peak memory 235068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153230462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.153230462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.227079048
Short name T362
Test name
Test status
Simulation time 4985277177 ps
CPU time 34.88 seconds
Started Sep 24 02:42:24 PM UTC 24
Finished Sep 24 02:43:00 PM UTC 24
Peak memory 245268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227079048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.227079048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3424071607
Short name T585
Test name
Test status
Simulation time 394373166 ps
CPU time 7.32 seconds
Started Sep 24 02:42:30 PM UTC 24
Finished Sep 24 02:42:39 PM UTC 24
Peak memory 231164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424071607 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.3424071607
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.802094605
Short name T181
Test name
Test status
Simulation time 211514837 ps
CPU time 1.59 seconds
Started Sep 24 02:42:34 PM UTC 24
Finished Sep 24 02:42:36 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802094605 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.802094605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.2185360767
Short name T176
Test name
Test status
Simulation time 580228867 ps
CPU time 9.43 seconds
Started Sep 24 02:42:21 PM UTC 24
Finished Sep 24 02:42:32 PM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185360767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2185360767
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.74027576
Short name T178
Test name
Test status
Simulation time 9457918043 ps
CPU time 11.39 seconds
Started Sep 24 02:42:20 PM UTC 24
Finished Sep 24 02:42:33 PM UTC 24
Peak memory 227468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74027576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.74027576
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.3215067822
Short name T583
Test name
Test status
Simulation time 152038473 ps
CPU time 4.8 seconds
Started Sep 24 02:42:22 PM UTC 24
Finished Sep 24 02:42:28 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215067822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3215067822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3877200004
Short name T580
Test name
Test status
Simulation time 21058128 ps
CPU time 1.14 seconds
Started Sep 24 02:42:22 PM UTC 24
Finished Sep 24 02:42:25 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877200004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3877200004
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.496161014
Short name T291
Test name
Test status
Simulation time 5864713342 ps
CPU time 16.52 seconds
Started Sep 24 02:42:26 PM UTC 24
Finished Sep 24 02:42:44 PM UTC 24
Peak memory 245064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496161014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.496161014
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.3974331288
Short name T593
Test name
Test status
Simulation time 12615782 ps
CPU time 1.18 seconds
Started Sep 24 02:42:56 PM UTC 24
Finished Sep 24 02:42:58 PM UTC 24
Peak memory 213588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974331288 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.3974331288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.754043738
Short name T400
Test name
Test status
Simulation time 3426373701 ps
CPU time 4.58 seconds
Started Sep 24 02:42:44 PM UTC 24
Finished Sep 24 02:42:50 PM UTC 24
Peak memory 234816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754043738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.754043738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.1555907286
Short name T586
Test name
Test status
Simulation time 13104597 ps
CPU time 1.22 seconds
Started Sep 24 02:42:37 PM UTC 24
Finished Sep 24 02:42:39 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555907286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1555907286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.3949422604
Short name T303
Test name
Test status
Simulation time 17789153317 ps
CPU time 85.56 seconds
Started Sep 24 02:42:47 PM UTC 24
Finished Sep 24 02:44:15 PM UTC 24
Peak memory 251204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949422604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3949422604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.973569020
Short name T605
Test name
Test status
Simulation time 562777847 ps
CPU time 19.43 seconds
Started Sep 24 02:42:51 PM UTC 24
Finished Sep 24 02:43:11 PM UTC 24
Peak memory 243896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973569020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.973569020
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2589306139
Short name T81
Test name
Test status
Simulation time 11940708021 ps
CPU time 167.66 seconds
Started Sep 24 02:42:51 PM UTC 24
Finished Sep 24 02:45:41 PM UTC 24
Peak memory 261888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589306139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.2589306139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.1504625606
Short name T420
Test name
Test status
Simulation time 5303354220 ps
CPU time 26.64 seconds
Started Sep 24 02:42:45 PM UTC 24
Finished Sep 24 02:43:13 PM UTC 24
Peak memory 234764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504625606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1504625606
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3717917192
Short name T363
Test name
Test status
Simulation time 1467209720 ps
CPU time 19.08 seconds
Started Sep 24 02:42:42 PM UTC 24
Finished Sep 24 02:43:02 PM UTC 24
Peak memory 244944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717917192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3717917192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1737879731
Short name T401
Test name
Test status
Simulation time 4664367070 ps
CPU time 14.41 seconds
Started Sep 24 02:42:43 PM UTC 24
Finished Sep 24 02:42:58 PM UTC 24
Peak memory 247008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737879731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1737879731
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.2342847773
Short name T309
Test name
Test status
Simulation time 16961888927 ps
CPU time 16.18 seconds
Started Sep 24 02:42:40 PM UTC 24
Finished Sep 24 02:42:58 PM UTC 24
Peak memory 251448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342847773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.2342847773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2609854139
Short name T273
Test name
Test status
Simulation time 9148374748 ps
CPU time 13.51 seconds
Started Sep 24 02:42:40 PM UTC 24
Finished Sep 24 02:42:55 PM UTC 24
Peak memory 251516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609854139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2609854139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3443460804
Short name T598
Test name
Test status
Simulation time 2258578487 ps
CPU time 16.89 seconds
Started Sep 24 02:42:45 PM UTC 24
Finished Sep 24 02:43:03 PM UTC 24
Peak memory 233612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443460804 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.3443460804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.786106491
Short name T959
Test name
Test status
Simulation time 100716580462 ps
CPU time 466.55 seconds
Started Sep 24 02:42:53 PM UTC 24
Finished Sep 24 02:50:46 PM UTC 24
Peak memory 261568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786106491 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.786106491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.2696867690
Short name T587
Test name
Test status
Simulation time 10935437 ps
CPU time 1.12 seconds
Started Sep 24 02:42:39 PM UTC 24
Finished Sep 24 02:42:41 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696867690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2696867690
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1388645184
Short name T604
Test name
Test status
Simulation time 7148941208 ps
CPU time 30.68 seconds
Started Sep 24 02:42:38 PM UTC 24
Finished Sep 24 02:43:10 PM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388645184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1388645184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.4230929184
Short name T590
Test name
Test status
Simulation time 241589052 ps
CPU time 2.04 seconds
Started Sep 24 02:42:40 PM UTC 24
Finished Sep 24 02:42:43 PM UTC 24
Peak memory 227352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230929184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4230929184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.2432646693
Short name T588
Test name
Test status
Simulation time 81513314 ps
CPU time 1.26 seconds
Started Sep 24 02:42:39 PM UTC 24
Finished Sep 24 02:42:41 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432646693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2432646693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.56419834
Short name T276
Test name
Test status
Simulation time 6719309783 ps
CPU time 20.03 seconds
Started Sep 24 02:42:43 PM UTC 24
Finished Sep 24 02:43:04 PM UTC 24
Peak memory 234380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56419834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.56419834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.411399215
Short name T607
Test name
Test status
Simulation time 57144342 ps
CPU time 1.14 seconds
Started Sep 24 02:43:10 PM UTC 24
Finished Sep 24 02:43:12 PM UTC 24
Peak memory 215696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411399215 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.411399215
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3569742832
Short name T602
Test name
Test status
Simulation time 286665559 ps
CPU time 3.6 seconds
Started Sep 24 02:43:04 PM UTC 24
Finished Sep 24 02:43:09 PM UTC 24
Peak memory 234696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569742832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3569742832
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.3323158830
Short name T594
Test name
Test status
Simulation time 23295028 ps
CPU time 1.24 seconds
Started Sep 24 02:42:57 PM UTC 24
Finished Sep 24 02:42:59 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323158830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3323158830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.3286085001
Short name T603
Test name
Test status
Simulation time 33699095 ps
CPU time 1.26 seconds
Started Sep 24 02:43:06 PM UTC 24
Finished Sep 24 02:43:09 PM UTC 24
Peak memory 226808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286085001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3286085001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.2756052512
Short name T615
Test name
Test status
Simulation time 570997847 ps
CPU time 12.14 seconds
Started Sep 24 02:43:07 PM UTC 24
Finished Sep 24 02:43:21 PM UTC 24
Peak memory 233660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756052512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2756052512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1566565220
Short name T251
Test name
Test status
Simulation time 7099105638 ps
CPU time 32.2 seconds
Started Sep 24 02:43:08 PM UTC 24
Finished Sep 24 02:43:42 PM UTC 24
Peak memory 251324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566565220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.1566565220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.1107347287
Short name T612
Test name
Test status
Simulation time 1847272274 ps
CPU time 10 seconds
Started Sep 24 02:43:05 PM UTC 24
Finished Sep 24 02:43:16 PM UTC 24
Peak memory 234680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107347287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1107347287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.3080892524
Short name T652
Test name
Test status
Simulation time 11756403492 ps
CPU time 41.88 seconds
Started Sep 24 02:43:05 PM UTC 24
Finished Sep 24 02:43:49 PM UTC 24
Peak memory 261416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080892524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.3080892524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.85777064
Short name T620
Test name
Test status
Simulation time 2171246466 ps
CPU time 22.49 seconds
Started Sep 24 02:43:03 PM UTC 24
Finished Sep 24 02:43:26 PM UTC 24
Peak memory 245072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85777064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.85777064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2976666626
Short name T606
Test name
Test status
Simulation time 205261551 ps
CPU time 7.5 seconds
Started Sep 24 02:43:03 PM UTC 24
Finished Sep 24 02:43:11 PM UTC 24
Peak memory 244924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976666626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2976666626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.2250943712
Short name T646
Test name
Test status
Simulation time 17616696478 ps
CPU time 42.53 seconds
Started Sep 24 02:43:01 PM UTC 24
Finished Sep 24 02:43:46 PM UTC 24
Peak memory 251260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250943712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.2250943712
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2388968101
Short name T601
Test name
Test status
Simulation time 196086364 ps
CPU time 5.37 seconds
Started Sep 24 02:43:00 PM UTC 24
Finished Sep 24 02:43:07 PM UTC 24
Peak memory 234816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388968101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2388968101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.1123921254
Short name T614
Test name
Test status
Simulation time 4658882043 ps
CPU time 13.71 seconds
Started Sep 24 02:43:05 PM UTC 24
Finished Sep 24 02:43:20 PM UTC 24
Peak memory 231320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123921254 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.1123921254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1337961372
Short name T208
Test name
Test status
Simulation time 229194379 ps
CPU time 1.71 seconds
Started Sep 24 02:43:10 PM UTC 24
Finished Sep 24 02:43:13 PM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337961372 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1337961372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.1182512304
Short name T609
Test name
Test status
Simulation time 5486458726 ps
CPU time 12.49 seconds
Started Sep 24 02:42:59 PM UTC 24
Finished Sep 24 02:43:13 PM UTC 24
Peak memory 227568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182512304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1182512304
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.2049270130
Short name T597
Test name
Test status
Simulation time 238334120 ps
CPU time 2.03 seconds
Started Sep 24 02:42:59 PM UTC 24
Finished Sep 24 02:43:02 PM UTC 24
Peak memory 217132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049270130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2049270130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.678079982
Short name T599
Test name
Test status
Simulation time 81821181 ps
CPU time 2.31 seconds
Started Sep 24 02:43:00 PM UTC 24
Finished Sep 24 02:43:04 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678079982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.678079982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3477069475
Short name T595
Test name
Test status
Simulation time 38692422 ps
CPU time 1.31 seconds
Started Sep 24 02:42:59 PM UTC 24
Finished Sep 24 02:43:02 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477069475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3477069475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.951342646
Short name T631
Test name
Test status
Simulation time 15386955534 ps
CPU time 31.43 seconds
Started Sep 24 02:43:03 PM UTC 24
Finished Sep 24 02:43:36 PM UTC 24
Peak memory 261448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951342646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.951342646
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3272546996
Short name T618
Test name
Test status
Simulation time 19509273 ps
CPU time 1.11 seconds
Started Sep 24 02:43:22 PM UTC 24
Finished Sep 24 02:43:24 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272546996 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3272546996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3853448084
Short name T600
Test name
Test status
Simulation time 767881582 ps
CPU time 3.37 seconds
Started Sep 24 02:43:17 PM UTC 24
Finished Sep 24 02:43:21 PM UTC 24
Peak memory 234688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853448084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3853448084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.2160273262
Short name T610
Test name
Test status
Simulation time 15088842 ps
CPU time 1.23 seconds
Started Sep 24 02:43:11 PM UTC 24
Finished Sep 24 02:43:13 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160273262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2160273262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.363661642
Short name T431
Test name
Test status
Simulation time 17141233420 ps
CPU time 45.06 seconds
Started Sep 24 02:43:22 PM UTC 24
Finished Sep 24 02:44:09 PM UTC 24
Peak memory 229880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363661642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.363661642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.1118300589
Short name T754
Test name
Test status
Simulation time 51047469422 ps
CPU time 107.82 seconds
Started Sep 24 02:43:22 PM UTC 24
Finished Sep 24 02:45:12 PM UTC 24
Peak memory 251192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118300589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.1118300589
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.912381409
Short name T636
Test name
Test status
Simulation time 1005752105 ps
CPU time 19.92 seconds
Started Sep 24 02:43:17 PM UTC 24
Finished Sep 24 02:43:38 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912381409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.912381409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.2899903239
Short name T922
Test name
Test status
Simulation time 116408146126 ps
CPU time 296.79 seconds
Started Sep 24 02:43:18 PM UTC 24
Finished Sep 24 02:48:19 PM UTC 24
Peak memory 265788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899903239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.2899903239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.3908754252
Short name T617
Test name
Test status
Simulation time 353303245 ps
CPU time 5.85 seconds
Started Sep 24 02:43:14 PM UTC 24
Finished Sep 24 02:43:21 PM UTC 24
Peak memory 244784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908754252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3908754252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.3782644418
Short name T616
Test name
Test status
Simulation time 412997568 ps
CPU time 5.37 seconds
Started Sep 24 02:43:14 PM UTC 24
Finished Sep 24 02:43:21 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782644418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3782644418
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.3281919030
Short name T613
Test name
Test status
Simulation time 736688659 ps
CPU time 3.18 seconds
Started Sep 24 02:43:14 PM UTC 24
Finished Sep 24 02:43:19 PM UTC 24
Peak memory 234592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281919030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.3281919030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1776317449
Short name T623
Test name
Test status
Simulation time 10321513507 ps
CPU time 14.41 seconds
Started Sep 24 02:43:13 PM UTC 24
Finished Sep 24 02:43:29 PM UTC 24
Peak memory 245112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776317449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1776317449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.3879405205
Short name T625
Test name
Test status
Simulation time 2710541885 ps
CPU time 9.25 seconds
Started Sep 24 02:43:20 PM UTC 24
Finished Sep 24 02:43:30 PM UTC 24
Peak memory 231292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879405205 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.3879405205
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2378250608
Short name T84
Test name
Test status
Simulation time 45689427436 ps
CPU time 645.19 seconds
Started Sep 24 02:43:22 PM UTC 24
Finished Sep 24 02:54:16 PM UTC 24
Peak memory 294392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378250608 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2378250608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.3834779102
Short name T621
Test name
Test status
Simulation time 2631369280 ps
CPU time 15.27 seconds
Started Sep 24 02:43:12 PM UTC 24
Finished Sep 24 02:43:29 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834779102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3834779102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.689889022
Short name T641
Test name
Test status
Simulation time 10104190555 ps
CPU time 28.22 seconds
Started Sep 24 02:43:12 PM UTC 24
Finished Sep 24 02:43:42 PM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689889022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.689889022
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.9457651
Short name T473
Test name
Test status
Simulation time 715162297 ps
CPU time 2.31 seconds
Started Sep 24 02:43:13 PM UTC 24
Finished Sep 24 02:43:17 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9457651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_dev
ice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.9457651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.1700206211
Short name T611
Test name
Test status
Simulation time 31782854 ps
CPU time 1.35 seconds
Started Sep 24 02:43:13 PM UTC 24
Finished Sep 24 02:43:16 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700206211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1700206211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.1713208947
Short name T358
Test name
Test status
Simulation time 544109698 ps
CPU time 19.01 seconds
Started Sep 24 02:43:15 PM UTC 24
Finished Sep 24 02:43:35 PM UTC 24
Peak memory 257536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713208947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1713208947
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.1647109945
Short name T630
Test name
Test status
Simulation time 48835349 ps
CPU time 1.12 seconds
Started Sep 24 02:43:33 PM UTC 24
Finished Sep 24 02:43:36 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647109945 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.1647109945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.721752095
Short name T619
Test name
Test status
Simulation time 73122161 ps
CPU time 1.18 seconds
Started Sep 24 02:43:22 PM UTC 24
Finished Sep 24 02:43:25 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721752095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.721752095
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.1165853931
Short name T761
Test name
Test status
Simulation time 11197863361 ps
CPU time 106.79 seconds
Started Sep 24 02:43:31 PM UTC 24
Finished Sep 24 02:45:20 PM UTC 24
Peak memory 261500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165853931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1165853931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1977631519
Short name T336
Test name
Test status
Simulation time 86089246068 ps
CPU time 218.22 seconds
Started Sep 24 02:43:32 PM UTC 24
Finished Sep 24 02:47:14 PM UTC 24
Peak memory 264008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977631519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1977631519
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3016101506
Short name T667
Test name
Test status
Simulation time 11845734292 ps
CPU time 24.64 seconds
Started Sep 24 02:43:32 PM UTC 24
Finished Sep 24 02:43:58 PM UTC 24
Peak memory 229636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016101506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.3016101506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.2952455306
Short name T659
Test name
Test status
Simulation time 5285128493 ps
CPU time 21.05 seconds
Started Sep 24 02:43:30 PM UTC 24
Finished Sep 24 02:43:52 PM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952455306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2952455306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2783186789
Short name T703
Test name
Test status
Simulation time 7565564941 ps
CPU time 55.76 seconds
Started Sep 24 02:43:30 PM UTC 24
Finished Sep 24 02:44:28 PM UTC 24
Peak memory 251196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783186789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.2783186789
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.209472666
Short name T628
Test name
Test status
Simulation time 723130631 ps
CPU time 3.8 seconds
Started Sep 24 02:43:27 PM UTC 24
Finished Sep 24 02:43:32 PM UTC 24
Peak memory 245192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209472666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.209472666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.3423525998
Short name T655
Test name
Test status
Simulation time 7817040178 ps
CPU time 21.5 seconds
Started Sep 24 02:43:27 PM UTC 24
Finished Sep 24 02:43:50 PM UTC 24
Peak memory 243908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423525998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3423525998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3110901216
Short name T626
Test name
Test status
Simulation time 271869541 ps
CPU time 3.03 seconds
Started Sep 24 02:43:27 PM UTC 24
Finished Sep 24 02:43:31 PM UTC 24
Peak memory 244672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110901216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.3110901216
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.4122099338
Short name T629
Test name
Test status
Simulation time 816523795 ps
CPU time 5.52 seconds
Started Sep 24 02:43:26 PM UTC 24
Finished Sep 24 02:43:33 PM UTC 24
Peak memory 245304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122099338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4122099338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1196951604
Short name T640
Test name
Test status
Simulation time 619982808 ps
CPU time 8.81 seconds
Started Sep 24 02:43:30 PM UTC 24
Finished Sep 24 02:43:40 PM UTC 24
Peak memory 233316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196951604 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.1196951604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.853299157
Short name T632
Test name
Test status
Simulation time 166263436 ps
CPU time 1.4 seconds
Started Sep 24 02:43:33 PM UTC 24
Finished Sep 24 02:43:36 PM UTC 24
Peak memory 215232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853299157 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.853299157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.965578330
Short name T627
Test name
Test status
Simulation time 1917042859 ps
CPU time 4.48 seconds
Started Sep 24 02:43:26 PM UTC 24
Finished Sep 24 02:43:32 PM UTC 24
Peak memory 229700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965578330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.965578330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.2069433363
Short name T633
Test name
Test status
Simulation time 10410142768 ps
CPU time 11.54 seconds
Started Sep 24 02:43:23 PM UTC 24
Finished Sep 24 02:43:36 PM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069433363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2069433363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1746593111
Short name T624
Test name
Test status
Simulation time 281331165 ps
CPU time 1.8 seconds
Started Sep 24 02:43:26 PM UTC 24
Finished Sep 24 02:43:29 PM UTC 24
Peak memory 217128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746593111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1746593111
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.4254423669
Short name T622
Test name
Test status
Simulation time 53185149 ps
CPU time 1.41 seconds
Started Sep 24 02:43:26 PM UTC 24
Finished Sep 24 02:43:29 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254423669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4254423669
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.85090749
Short name T399
Test name
Test status
Simulation time 576747976 ps
CPU time 7.75 seconds
Started Sep 24 02:43:28 PM UTC 24
Finished Sep 24 02:43:37 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85090749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.85090749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.143309512
Short name T645
Test name
Test status
Simulation time 33041529 ps
CPU time 1.16 seconds
Started Sep 24 02:43:43 PM UTC 24
Finished Sep 24 02:43:45 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143309512 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.143309512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.598662000
Short name T644
Test name
Test status
Simulation time 145230786 ps
CPU time 4.16 seconds
Started Sep 24 02:43:38 PM UTC 24
Finished Sep 24 02:43:44 PM UTC 24
Peak memory 244996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598662000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.598662000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.1969959094
Short name T634
Test name
Test status
Simulation time 18363895 ps
CPU time 1.22 seconds
Started Sep 24 02:43:36 PM UTC 24
Finished Sep 24 02:43:38 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969959094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1969959094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.725980092
Short name T642
Test name
Test status
Simulation time 24332298 ps
CPU time 1.03 seconds
Started Sep 24 02:43:41 PM UTC 24
Finished Sep 24 02:43:43 PM UTC 24
Peak memory 226740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725980092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.725980092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1290561759
Short name T409
Test name
Test status
Simulation time 1287797288 ps
CPU time 24.84 seconds
Started Sep 24 02:43:41 PM UTC 24
Finished Sep 24 02:44:07 PM UTC 24
Peak memory 251268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290561759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1290561759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1096479895
Short name T1000
Test name
Test status
Simulation time 150836046460 ps
CPU time 553.18 seconds
Started Sep 24 02:43:43 PM UTC 24
Finished Sep 24 02:53:04 PM UTC 24
Peak memory 278204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096479895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.1096479895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.3364254906
Short name T425
Test name
Test status
Simulation time 5188895593 ps
CPU time 29.36 seconds
Started Sep 24 02:43:39 PM UTC 24
Finished Sep 24 02:44:10 PM UTC 24
Peak memory 245064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364254906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3364254906
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.2380857324
Short name T673
Test name
Test status
Simulation time 7098059796 ps
CPU time 22.62 seconds
Started Sep 24 02:43:40 PM UTC 24
Finished Sep 24 02:44:03 PM UTC 24
Peak memory 261820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380857324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.2380857324
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.1429285387
Short name T672
Test name
Test status
Simulation time 1891226221 ps
CPU time 22.86 seconds
Started Sep 24 02:43:38 PM UTC 24
Finished Sep 24 02:44:02 PM UTC 24
Peak memory 235076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429285387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1429285387
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.2668486255
Short name T133
Test name
Test status
Simulation time 33338253 ps
CPU time 2.8 seconds
Started Sep 24 02:43:38 PM UTC 24
Finished Sep 24 02:43:42 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668486255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2668486255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.1629139236
Short name T411
Test name
Test status
Simulation time 455354702 ps
CPU time 10.16 seconds
Started Sep 24 02:43:37 PM UTC 24
Finished Sep 24 02:43:48 PM UTC 24
Peak memory 234952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629139236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.1629139236
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.3525122314
Short name T654
Test name
Test status
Simulation time 6513088485 ps
CPU time 11.67 seconds
Started Sep 24 02:43:37 PM UTC 24
Finished Sep 24 02:43:50 PM UTC 24
Peak memory 235024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525122314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3525122314
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1050048311
Short name T649
Test name
Test status
Simulation time 139518412 ps
CPU time 5.2 seconds
Started Sep 24 02:43:41 PM UTC 24
Finished Sep 24 02:43:47 PM UTC 24
Peak memory 233320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050048311 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.1050048311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.1903934087
Short name T1010
Test name
Test status
Simulation time 1185659155752 ps
CPU time 1086.85 seconds
Started Sep 24 02:43:43 PM UTC 24
Finished Sep 24 03:02:04 PM UTC 24
Peak memory 284096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903934087 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.1903934087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.3231579184
Short name T724
Test name
Test status
Simulation time 29581724010 ps
CPU time 66.57 seconds
Started Sep 24 02:43:37 PM UTC 24
Finished Sep 24 02:44:45 PM UTC 24
Peak memory 227516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231579184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3231579184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.1128946461
Short name T643
Test name
Test status
Simulation time 2597101058 ps
CPU time 5.17 seconds
Started Sep 24 02:43:37 PM UTC 24
Finished Sep 24 02:43:43 PM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128946461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1128946461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.3397738557
Short name T638
Test name
Test status
Simulation time 77107249 ps
CPU time 1.64 seconds
Started Sep 24 02:43:37 PM UTC 24
Finished Sep 24 02:43:40 PM UTC 24
Peak memory 227044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397738557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3397738557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.692603271
Short name T637
Test name
Test status
Simulation time 232387604 ps
CPU time 1.29 seconds
Started Sep 24 02:43:37 PM UTC 24
Finished Sep 24 02:43:39 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692603271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.692603271
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.2729770037
Short name T674
Test name
Test status
Simulation time 35920793375 ps
CPU time 25.88 seconds
Started Sep 24 02:43:38 PM UTC 24
Finished Sep 24 02:44:05 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729770037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2729770037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.2484282426
Short name T661
Test name
Test status
Simulation time 20958357 ps
CPU time 1.13 seconds
Started Sep 24 02:43:52 PM UTC 24
Finished Sep 24 02:43:54 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484282426 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.2484282426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.2505961599
Short name T660
Test name
Test status
Simulation time 162666890 ps
CPU time 3.22 seconds
Started Sep 24 02:43:49 PM UTC 24
Finished Sep 24 02:43:53 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505961599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2505961599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.1607646782
Short name T648
Test name
Test status
Simulation time 43639449 ps
CPU time 1.13 seconds
Started Sep 24 02:43:44 PM UTC 24
Finished Sep 24 02:43:46 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607646782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1607646782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.2749831207
Short name T704
Test name
Test status
Simulation time 3171615803 ps
CPU time 35.46 seconds
Started Sep 24 02:43:51 PM UTC 24
Finished Sep 24 02:44:28 PM UTC 24
Peak memory 245064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749831207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2749831207
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.618467289
Short name T374
Test name
Test status
Simulation time 71459072763 ps
CPU time 183.59 seconds
Started Sep 24 02:43:51 PM UTC 24
Finished Sep 24 02:46:58 PM UTC 24
Peak memory 265724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618467289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.618467289
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.1187806552
Short name T662
Test name
Test status
Simulation time 203651193 ps
CPU time 3.9 seconds
Started Sep 24 02:43:50 PM UTC 24
Finished Sep 24 02:43:55 PM UTC 24
Peak memory 244916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187806552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1187806552
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.4095272692
Short name T670
Test name
Test status
Simulation time 362676257 ps
CPU time 8.65 seconds
Started Sep 24 02:43:50 PM UTC 24
Finished Sep 24 02:44:00 PM UTC 24
Peak memory 234688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095272692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.4095272692
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.2815851498
Short name T384
Test name
Test status
Simulation time 2636083990 ps
CPU time 19.47 seconds
Started Sep 24 02:43:48 PM UTC 24
Finished Sep 24 02:44:09 PM UTC 24
Peak memory 234820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815851498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2815851498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.1583447234
Short name T676
Test name
Test status
Simulation time 1495954462 ps
CPU time 20.95 seconds
Started Sep 24 02:43:48 PM UTC 24
Finished Sep 24 02:44:10 PM UTC 24
Peak memory 245176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583447234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1583447234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.47256757
Short name T657
Test name
Test status
Simulation time 44766669 ps
CPU time 3.02 seconds
Started Sep 24 02:43:47 PM UTC 24
Finished Sep 24 02:43:51 PM UTC 24
Peak memory 233200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47256757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.47256757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2500720751
Short name T664
Test name
Test status
Simulation time 36676233558 ps
CPU time 8.1 seconds
Started Sep 24 02:43:47 PM UTC 24
Finished Sep 24 02:43:56 PM UTC 24
Peak memory 234832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500720751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2500720751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.1736833749
Short name T669
Test name
Test status
Simulation time 1007092816 ps
CPU time 6.55 seconds
Started Sep 24 02:43:51 PM UTC 24
Finished Sep 24 02:43:59 PM UTC 24
Peak memory 233136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736833749 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.1736833749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.2456842160
Short name T950
Test name
Test status
Simulation time 27049922292 ps
CPU time 297.97 seconds
Started Sep 24 02:43:52 PM UTC 24
Finished Sep 24 02:48:54 PM UTC 24
Peak memory 278212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456842160 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.2456842160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.717111464
Short name T429
Test name
Test status
Simulation time 27661507765 ps
CPU time 35.17 seconds
Started Sep 24 02:43:44 PM UTC 24
Finished Sep 24 02:44:21 PM UTC 24
Peak memory 227508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717111464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.717111464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3767076964
Short name T651
Test name
Test status
Simulation time 231029924 ps
CPU time 3.14 seconds
Started Sep 24 02:43:44 PM UTC 24
Finished Sep 24 02:43:48 PM UTC 24
Peak memory 216876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767076964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3767076964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.2279827698
Short name T656
Test name
Test status
Simulation time 36878831 ps
CPU time 2.81 seconds
Started Sep 24 02:43:47 PM UTC 24
Finished Sep 24 02:43:50 PM UTC 24
Peak memory 227588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279827698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2279827698
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.649376048
Short name T653
Test name
Test status
Simulation time 83649482 ps
CPU time 1.38 seconds
Started Sep 24 02:43:47 PM UTC 24
Finished Sep 24 02:43:49 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649376048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.649376048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.662679798
Short name T688
Test name
Test status
Simulation time 14468035907 ps
CPU time 28.29 seconds
Started Sep 24 02:43:49 PM UTC 24
Finished Sep 24 02:44:19 PM UTC 24
Peak memory 261704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662679798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.662679798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.342735647
Short name T447
Test name
Test status
Simulation time 20572902 ps
CPU time 1.14 seconds
Started Sep 24 02:37:15 PM UTC 24
Finished Sep 24 02:37:18 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342735647 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.342735647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1327560766
Short name T58
Test name
Test status
Simulation time 351342874 ps
CPU time 5.04 seconds
Started Sep 24 02:37:07 PM UTC 24
Finished Sep 24 02:37:14 PM UTC 24
Peak memory 245140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327560766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1327560766
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.860821509
Short name T445
Test name
Test status
Simulation time 16267864 ps
CPU time 1.3 seconds
Started Sep 24 02:37:02 PM UTC 24
Finished Sep 24 02:37:04 PM UTC 24
Peak memory 215652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860821509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.860821509
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3717103832
Short name T223
Test name
Test status
Simulation time 17294336419 ps
CPU time 102.32 seconds
Started Sep 24 02:37:12 PM UTC 24
Finished Sep 24 02:38:57 PM UTC 24
Peak memory 261528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717103832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3717103832
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1441645903
Short name T316
Test name
Test status
Simulation time 253650086380 ps
CPU time 426.94 seconds
Started Sep 24 02:37:12 PM UTC 24
Finished Sep 24 02:44:25 PM UTC 24
Peak memory 284320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441645903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.1441645903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.941676739
Short name T215
Test name
Test status
Simulation time 264783844 ps
CPU time 5.85 seconds
Started Sep 24 02:37:08 PM UTC 24
Finished Sep 24 02:37:14 PM UTC 24
Peak memory 234696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941676739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.941676739
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2190118560
Short name T44
Test name
Test status
Simulation time 906507634 ps
CPU time 13.59 seconds
Started Sep 24 02:37:10 PM UTC 24
Finished Sep 24 02:37:25 PM UTC 24
Peak memory 249088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190118560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.2190118560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.2870619208
Short name T77
Test name
Test status
Simulation time 3725540705 ps
CPU time 19.54 seconds
Started Sep 24 02:37:05 PM UTC 24
Finished Sep 24 02:37:26 PM UTC 24
Peak memory 235080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870619208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2870619208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1636102667
Short name T60
Test name
Test status
Simulation time 7212506912 ps
CPU time 30.02 seconds
Started Sep 24 02:37:05 PM UTC 24
Finished Sep 24 02:37:37 PM UTC 24
Peak memory 245320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636102667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.1636102667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1967457581
Short name T55
Test name
Test status
Simulation time 1271749465 ps
CPU time 11 seconds
Started Sep 24 02:37:05 PM UTC 24
Finished Sep 24 02:37:17 PM UTC 24
Peak memory 234680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967457581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1967457581
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2082501427
Short name T145
Test name
Test status
Simulation time 1251180325 ps
CPU time 10.82 seconds
Started Sep 24 02:37:10 PM UTC 24
Finished Sep 24 02:37:22 PM UTC 24
Peak memory 229232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082501427 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.2082501427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.4075342498
Short name T34
Test name
Test status
Simulation time 223524239 ps
CPU time 1.67 seconds
Started Sep 24 02:37:15 PM UTC 24
Finished Sep 24 02:37:18 PM UTC 24
Peak memory 256992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075342498 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4075342498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2412511818
Short name T123
Test name
Test status
Simulation time 2422713903 ps
CPU time 43.87 seconds
Started Sep 24 02:37:03 PM UTC 24
Finished Sep 24 02:37:48 PM UTC 24
Peak memory 231560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412511818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2412511818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3595529273
Short name T122
Test name
Test status
Simulation time 1632439151 ps
CPU time 6.86 seconds
Started Sep 24 02:37:03 PM UTC 24
Finished Sep 24 02:37:11 PM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595529273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3595529273
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1686326363
Short name T31
Test name
Test status
Simulation time 97209881 ps
CPU time 1.6 seconds
Started Sep 24 02:37:04 PM UTC 24
Finished Sep 24 02:37:07 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686326363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1686326363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3692509189
Short name T126
Test name
Test status
Simulation time 382817097 ps
CPU time 1.59 seconds
Started Sep 24 02:37:04 PM UTC 24
Finished Sep 24 02:37:07 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692509189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3692509189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.3448062864
Short name T678
Test name
Test status
Simulation time 15045907 ps
CPU time 1.15 seconds
Started Sep 24 02:44:10 PM UTC 24
Finished Sep 24 02:44:12 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448062864 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.3448062864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.1057732453
Short name T683
Test name
Test status
Simulation time 1000077764 ps
CPU time 13.59 seconds
Started Sep 24 02:44:01 PM UTC 24
Finished Sep 24 02:44:16 PM UTC 24
Peak memory 234748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057732453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1057732453
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.753349068
Short name T665
Test name
Test status
Simulation time 92960489 ps
CPU time 1.21 seconds
Started Sep 24 02:43:54 PM UTC 24
Finished Sep 24 02:43:56 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753349068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.753349068
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.2019516834
Short name T304
Test name
Test status
Simulation time 44991062529 ps
CPU time 158.93 seconds
Started Sep 24 02:44:04 PM UTC 24
Finished Sep 24 02:46:46 PM UTC 24
Peak memory 282120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019516834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2019516834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.4137752757
Short name T798
Test name
Test status
Simulation time 17183099945 ps
CPU time 103.97 seconds
Started Sep 24 02:44:06 PM UTC 24
Finished Sep 24 02:45:53 PM UTC 24
Peak memory 261568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137752757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4137752757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.4185230021
Short name T747
Test name
Test status
Simulation time 10847360080 ps
CPU time 59.01 seconds
Started Sep 24 02:44:08 PM UTC 24
Finished Sep 24 02:45:08 PM UTC 24
Peak memory 251576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185230021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.4185230021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.3112762994
Short name T675
Test name
Test status
Simulation time 356044054 ps
CPU time 4.69 seconds
Started Sep 24 02:44:01 PM UTC 24
Finished Sep 24 02:44:07 PM UTC 24
Peak memory 244924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112762994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3112762994
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.4184530833
Short name T742
Test name
Test status
Simulation time 20097382545 ps
CPU time 59.7 seconds
Started Sep 24 02:44:02 PM UTC 24
Finished Sep 24 02:45:04 PM UTC 24
Peak memory 261440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184530833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.4184530833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.1826415505
Short name T289
Test name
Test status
Simulation time 2436203783 ps
CPU time 10.51 seconds
Started Sep 24 02:44:00 PM UTC 24
Finished Sep 24 02:44:11 PM UTC 24
Peak memory 245032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826415505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1826415505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.2024339864
Short name T356
Test name
Test status
Simulation time 32972296830 ps
CPU time 98.3 seconds
Started Sep 24 02:44:00 PM UTC 24
Finished Sep 24 02:45:40 PM UTC 24
Peak memory 261452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024339864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2024339864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3760101561
Short name T386
Test name
Test status
Simulation time 12914697183 ps
CPU time 26.05 seconds
Started Sep 24 02:43:58 PM UTC 24
Finished Sep 24 02:44:25 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760101561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.3760101561
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2011126139
Short name T380
Test name
Test status
Simulation time 499556135 ps
CPU time 3.21 seconds
Started Sep 24 02:43:57 PM UTC 24
Finished Sep 24 02:44:02 PM UTC 24
Peak memory 234936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011126139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2011126139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.749815028
Short name T680
Test name
Test status
Simulation time 302882265 ps
CPU time 7.92 seconds
Started Sep 24 02:44:03 PM UTC 24
Finished Sep 24 02:44:12 PM UTC 24
Peak memory 229128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749815028 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.749815028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.3724553119
Short name T749
Test name
Test status
Simulation time 13398648942 ps
CPU time 61.46 seconds
Started Sep 24 02:44:08 PM UTC 24
Finished Sep 24 02:45:11 PM UTC 24
Peak memory 263684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724553119 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.3724553119
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3043279036
Short name T723
Test name
Test status
Simulation time 34976857783 ps
CPU time 47.86 seconds
Started Sep 24 02:43:55 PM UTC 24
Finished Sep 24 02:44:45 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043279036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3043279036
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.2779802965
Short name T687
Test name
Test status
Simulation time 40416438507 ps
CPU time 22.14 seconds
Started Sep 24 02:43:54 PM UTC 24
Finished Sep 24 02:44:17 PM UTC 24
Peak memory 227768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779802965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2779802965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.1304334002
Short name T671
Test name
Test status
Simulation time 90873902 ps
CPU time 3.17 seconds
Started Sep 24 02:43:56 PM UTC 24
Finished Sep 24 02:44:00 PM UTC 24
Peak memory 227248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304334002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1304334002
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1833267011
Short name T668
Test name
Test status
Simulation time 20009837 ps
CPU time 1.14 seconds
Started Sep 24 02:43:56 PM UTC 24
Finished Sep 24 02:43:58 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833267011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1833267011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.3491948634
Short name T397
Test name
Test status
Simulation time 489927432 ps
CPU time 8.27 seconds
Started Sep 24 02:44:00 PM UTC 24
Finished Sep 24 02:44:09 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491948634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3491948634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.3857372750
Short name T691
Test name
Test status
Simulation time 31186600 ps
CPU time 1.16 seconds
Started Sep 24 02:44:19 PM UTC 24
Finished Sep 24 02:44:21 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857372750 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.3857372750
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4117542120
Short name T355
Test name
Test status
Simulation time 1814861946 ps
CPU time 6.68 seconds
Started Sep 24 02:44:14 PM UTC 24
Finished Sep 24 02:44:22 PM UTC 24
Peak memory 245184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117542120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4117542120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.2252995913
Short name T679
Test name
Test status
Simulation time 28053000 ps
CPU time 1.18 seconds
Started Sep 24 02:44:10 PM UTC 24
Finished Sep 24 02:44:12 PM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252995913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2252995913
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.2191329370
Short name T338
Test name
Test status
Simulation time 4489212729 ps
CPU time 47.82 seconds
Started Sep 24 02:44:16 PM UTC 24
Finished Sep 24 02:45:06 PM UTC 24
Peak memory 261708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191329370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2191329370
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3457124124
Short name T325
Test name
Test status
Simulation time 11339675304 ps
CPU time 145.12 seconds
Started Sep 24 02:44:16 PM UTC 24
Finished Sep 24 02:46:44 PM UTC 24
Peak memory 280004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457124124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3457124124
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.1694523689
Short name T692
Test name
Test status
Simulation time 468617010 ps
CPU time 6.03 seconds
Started Sep 24 02:44:14 PM UTC 24
Finished Sep 24 02:44:21 PM UTC 24
Peak memory 244924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694523689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1694523689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.921439286
Short name T326
Test name
Test status
Simulation time 123121110879 ps
CPU time 150.71 seconds
Started Sep 24 02:44:15 PM UTC 24
Finished Sep 24 02:46:49 PM UTC 24
Peak memory 261688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921439286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.921439286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.3377733856
Short name T685
Test name
Test status
Simulation time 49971549 ps
CPU time 2.27 seconds
Started Sep 24 02:44:13 PM UTC 24
Finished Sep 24 02:44:16 PM UTC 24
Peak memory 233308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377733856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3377733856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.2772813533
Short name T702
Test name
Test status
Simulation time 5467675162 ps
CPU time 13.33 seconds
Started Sep 24 02:44:13 PM UTC 24
Finished Sep 24 02:44:27 PM UTC 24
Peak memory 251200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772813533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2772813533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.149604962
Short name T686
Test name
Test status
Simulation time 106865577 ps
CPU time 2.45 seconds
Started Sep 24 02:44:13 PM UTC 24
Finished Sep 24 02:44:16 PM UTC 24
Peak memory 233920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149604962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.149604962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.1970473557
Short name T689
Test name
Test status
Simulation time 2812318689 ps
CPU time 6.19 seconds
Started Sep 24 02:44:13 PM UTC 24
Finished Sep 24 02:44:20 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970473557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1970473557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1149119261
Short name T695
Test name
Test status
Simulation time 203091644 ps
CPU time 4.88 seconds
Started Sep 24 02:44:16 PM UTC 24
Finished Sep 24 02:44:22 PM UTC 24
Peak memory 231404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149119261 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.1149119261
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.1977841969
Short name T690
Test name
Test status
Simulation time 35021414 ps
CPU time 1.43 seconds
Started Sep 24 02:44:18 PM UTC 24
Finished Sep 24 02:44:20 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977841969 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.1977841969
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.590879965
Short name T681
Test name
Test status
Simulation time 40991448 ps
CPU time 0.91 seconds
Started Sep 24 02:44:11 PM UTC 24
Finished Sep 24 02:44:13 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590879965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.590879965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.3667553980
Short name T709
Test name
Test status
Simulation time 15011729805 ps
CPU time 19.99 seconds
Started Sep 24 02:44:10 PM UTC 24
Finished Sep 24 02:44:31 PM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667553980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3667553980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.3963794932
Short name T696
Test name
Test status
Simulation time 194713546 ps
CPU time 9.2 seconds
Started Sep 24 02:44:13 PM UTC 24
Finished Sep 24 02:44:23 PM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963794932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3963794932
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.3438887734
Short name T682
Test name
Test status
Simulation time 16231906 ps
CPU time 1.16 seconds
Started Sep 24 02:44:11 PM UTC 24
Finished Sep 24 02:44:13 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438887734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3438887734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.3475419663
Short name T710
Test name
Test status
Simulation time 4156431098 ps
CPU time 16.34 seconds
Started Sep 24 02:44:14 PM UTC 24
Finished Sep 24 02:44:31 PM UTC 24
Peak memory 251196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475419663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3475419663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.4260600330
Short name T707
Test name
Test status
Simulation time 43278034 ps
CPU time 1.18 seconds
Started Sep 24 02:44:28 PM UTC 24
Finished Sep 24 02:44:30 PM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260600330 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.4260600330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3281697129
Short name T701
Test name
Test status
Simulation time 71081942 ps
CPU time 2.19 seconds
Started Sep 24 02:44:24 PM UTC 24
Finished Sep 24 02:44:27 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281697129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3281697129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.4025096465
Short name T694
Test name
Test status
Simulation time 14835495 ps
CPU time 1.15 seconds
Started Sep 24 02:44:20 PM UTC 24
Finished Sep 24 02:44:22 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025096465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4025096465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.646596881
Short name T301
Test name
Test status
Simulation time 97981649432 ps
CPU time 154.91 seconds
Started Sep 24 02:44:26 PM UTC 24
Finished Sep 24 02:47:04 PM UTC 24
Peak memory 261444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646596881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.646596881
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3591828826
Short name T328
Test name
Test status
Simulation time 203883586076 ps
CPU time 500.05 seconds
Started Sep 24 02:44:26 PM UTC 24
Finished Sep 24 02:52:54 PM UTC 24
Peak memory 267668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591828826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3591828826
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.4164916094
Short name T185
Test name
Test status
Simulation time 11460123745 ps
CPU time 85.34 seconds
Started Sep 24 02:44:27 PM UTC 24
Finished Sep 24 02:45:54 PM UTC 24
Peak memory 267640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164916094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.4164916094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.4255788098
Short name T713
Test name
Test status
Simulation time 453499372 ps
CPU time 7.79 seconds
Started Sep 24 02:44:25 PM UTC 24
Finished Sep 24 02:44:34 PM UTC 24
Peak memory 234880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255788098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4255788098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1618969085
Short name T341
Test name
Test status
Simulation time 3693133902 ps
CPU time 91.57 seconds
Started Sep 24 02:44:26 PM UTC 24
Finished Sep 24 02:46:00 PM UTC 24
Peak memory 263616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618969085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.1618969085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.2912778567
Short name T714
Test name
Test status
Simulation time 2259128250 ps
CPU time 9.02 seconds
Started Sep 24 02:44:24 PM UTC 24
Finished Sep 24 02:44:34 PM UTC 24
Peak memory 245080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912778567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2912778567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.1470665047
Short name T385
Test name
Test status
Simulation time 1802695680 ps
CPU time 6.92 seconds
Started Sep 24 02:44:24 PM UTC 24
Finished Sep 24 02:44:32 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470665047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1470665047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3371247617
Short name T412
Test name
Test status
Simulation time 907800835 ps
CPU time 6.07 seconds
Started Sep 24 02:44:22 PM UTC 24
Finished Sep 24 02:44:30 PM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371247617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.3371247617
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2133303888
Short name T298
Test name
Test status
Simulation time 116483245 ps
CPU time 2.94 seconds
Started Sep 24 02:44:22 PM UTC 24
Finished Sep 24 02:44:26 PM UTC 24
Peak memory 234708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133303888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2133303888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3646931070
Short name T716
Test name
Test status
Simulation time 837993253 ps
CPU time 9.46 seconds
Started Sep 24 02:44:26 PM UTC 24
Finished Sep 24 02:44:37 PM UTC 24
Peak memory 231156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646931070 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.3646931070
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.410382526
Short name T789
Test name
Test status
Simulation time 27409360943 ps
CPU time 75.81 seconds
Started Sep 24 02:44:27 PM UTC 24
Finished Sep 24 02:45:44 PM UTC 24
Peak memory 251584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410382526 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.410382526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.1487477075
Short name T700
Test name
Test status
Simulation time 158040672 ps
CPU time 3.39 seconds
Started Sep 24 02:44:21 PM UTC 24
Finished Sep 24 02:44:25 PM UTC 24
Peak memory 227648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487477075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1487477075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.87282448
Short name T698
Test name
Test status
Simulation time 1461681232 ps
CPU time 2.95 seconds
Started Sep 24 02:44:21 PM UTC 24
Finished Sep 24 02:44:25 PM UTC 24
Peak memory 216420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87282448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.87282448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.2248554515
Short name T699
Test name
Test status
Simulation time 294620012 ps
CPU time 1.91 seconds
Started Sep 24 02:44:22 PM UTC 24
Finished Sep 24 02:44:25 PM UTC 24
Peak memory 226564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248554515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2248554515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2862406278
Short name T697
Test name
Test status
Simulation time 85460680 ps
CPU time 1.33 seconds
Started Sep 24 02:44:22 PM UTC 24
Finished Sep 24 02:44:25 PM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862406278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2862406278
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.1938524837
Short name T705
Test name
Test status
Simulation time 259730082 ps
CPU time 3.71 seconds
Started Sep 24 02:44:24 PM UTC 24
Finished Sep 24 02:44:29 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938524837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1938524837
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.3431326232
Short name T717
Test name
Test status
Simulation time 11478832 ps
CPU time 1.12 seconds
Started Sep 24 02:44:38 PM UTC 24
Finished Sep 24 02:44:40 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431326232 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.3431326232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1830956063
Short name T715
Test name
Test status
Simulation time 121329370 ps
CPU time 2.65 seconds
Started Sep 24 02:44:33 PM UTC 24
Finished Sep 24 02:44:37 PM UTC 24
Peak memory 245200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830956063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1830956063
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.27546687
Short name T706
Test name
Test status
Simulation time 97528315 ps
CPU time 1.19 seconds
Started Sep 24 02:44:28 PM UTC 24
Finished Sep 24 02:44:30 PM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27546687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.27546687
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.3056836902
Short name T762
Test name
Test status
Simulation time 4332354427 ps
CPU time 42.63 seconds
Started Sep 24 02:44:35 PM UTC 24
Finished Sep 24 02:45:20 PM UTC 24
Peak memory 247176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056836902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3056836902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1468598139
Short name T334
Test name
Test status
Simulation time 4218952368 ps
CPU time 63.96 seconds
Started Sep 24 02:44:35 PM UTC 24
Finished Sep 24 02:45:41 PM UTC 24
Peak memory 251392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468598139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1468598139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2061487528
Short name T858
Test name
Test status
Simulation time 19269248274 ps
CPU time 138.23 seconds
Started Sep 24 02:44:36 PM UTC 24
Finished Sep 24 02:46:57 PM UTC 24
Peak memory 261624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061487528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.2061487528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.1655487162
Short name T720
Test name
Test status
Simulation time 1400373185 ps
CPU time 8.88 seconds
Started Sep 24 02:44:33 PM UTC 24
Finished Sep 24 02:44:43 PM UTC 24
Peak memory 234644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655487162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1655487162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.589745667
Short name T745
Test name
Test status
Simulation time 2801559625 ps
CPU time 33.41 seconds
Started Sep 24 02:44:32 PM UTC 24
Finished Sep 24 02:45:06 PM UTC 24
Peak memory 234880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589745667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.589745667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.367268979
Short name T744
Test name
Test status
Simulation time 9407999803 ps
CPU time 32.31 seconds
Started Sep 24 02:44:32 PM UTC 24
Finished Sep 24 02:45:05 PM UTC 24
Peak memory 249412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367268979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.367268979
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.1782314915
Short name T407
Test name
Test status
Simulation time 960813649 ps
CPU time 3.7 seconds
Started Sep 24 02:44:30 PM UTC 24
Finished Sep 24 02:44:35 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782314915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.1782314915
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3744966840
Short name T719
Test name
Test status
Simulation time 2641705647 ps
CPU time 9.41 seconds
Started Sep 24 02:44:29 PM UTC 24
Finished Sep 24 02:44:40 PM UTC 24
Peak memory 251204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744966840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3744966840
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.1671440843
Short name T718
Test name
Test status
Simulation time 319966617 ps
CPU time 5.75 seconds
Started Sep 24 02:44:33 PM UTC 24
Finished Sep 24 02:44:40 PM UTC 24
Peak memory 233364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671440843 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.1671440843
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.871470569
Short name T740
Test name
Test status
Simulation time 1389236560 ps
CPU time 22.74 seconds
Started Sep 24 02:44:38 PM UTC 24
Finished Sep 24 02:45:02 PM UTC 24
Peak memory 234880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871470569 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.871470569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.2181510700
Short name T725
Test name
Test status
Simulation time 9069338276 ps
CPU time 17.11 seconds
Started Sep 24 02:44:28 PM UTC 24
Finished Sep 24 02:44:46 PM UTC 24
Peak memory 227456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181510700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2181510700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2697993743
Short name T721
Test name
Test status
Simulation time 3544463157 ps
CPU time 13.81 seconds
Started Sep 24 02:44:28 PM UTC 24
Finished Sep 24 02:44:43 PM UTC 24
Peak memory 227572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697993743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2697993743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.418747350
Short name T712
Test name
Test status
Simulation time 66316023 ps
CPU time 1.72 seconds
Started Sep 24 02:44:29 PM UTC 24
Finished Sep 24 02:44:32 PM UTC 24
Peak memory 227232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418747350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.418747350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.1935504263
Short name T711
Test name
Test status
Simulation time 90512279 ps
CPU time 1.16 seconds
Started Sep 24 02:44:29 PM UTC 24
Finished Sep 24 02:44:32 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935504263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1935504263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.830047401
Short name T730
Test name
Test status
Simulation time 6920843203 ps
CPU time 16.8 seconds
Started Sep 24 02:44:33 PM UTC 24
Finished Sep 24 02:44:51 PM UTC 24
Peak memory 251208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830047401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.830047401
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.2605184759
Short name T735
Test name
Test status
Simulation time 21370962 ps
CPU time 1.22 seconds
Started Sep 24 02:44:56 PM UTC 24
Finished Sep 24 02:44:58 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605184759 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2605184759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.1805594562
Short name T732
Test name
Test status
Simulation time 241771649 ps
CPU time 7.2 seconds
Started Sep 24 02:44:48 PM UTC 24
Finished Sep 24 02:44:56 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805594562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1805594562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.105700700
Short name T722
Test name
Test status
Simulation time 32716360 ps
CPU time 1.16 seconds
Started Sep 24 02:44:41 PM UTC 24
Finished Sep 24 02:44:43 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105700700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.105700700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.2183853292
Short name T639
Test name
Test status
Simulation time 18392769 ps
CPU time 1.22 seconds
Started Sep 24 02:44:52 PM UTC 24
Finished Sep 24 02:44:55 PM UTC 24
Peak memory 216704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183853292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2183853292
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1223036653
Short name T788
Test name
Test status
Simulation time 4277667370 ps
CPU time 49.29 seconds
Started Sep 24 02:44:53 PM UTC 24
Finished Sep 24 02:45:44 PM UTC 24
Peak memory 251336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223036653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1223036653
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1538023395
Short name T803
Test name
Test status
Simulation time 4937933621 ps
CPU time 63.13 seconds
Started Sep 24 02:44:54 PM UTC 24
Finished Sep 24 02:45:58 PM UTC 24
Peak memory 261500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538023395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.1538023395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.1346932978
Short name T650
Test name
Test status
Simulation time 317937694 ps
CPU time 4.42 seconds
Started Sep 24 02:44:49 PM UTC 24
Finished Sep 24 02:44:54 PM UTC 24
Peak memory 244880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346932978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1346932978
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2736523677
Short name T743
Test name
Test status
Simulation time 1049680835 ps
CPU time 12.29 seconds
Started Sep 24 02:44:51 PM UTC 24
Finished Sep 24 02:45:05 PM UTC 24
Peak memory 244884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736523677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.2736523677
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.2360148365
Short name T746
Test name
Test status
Simulation time 1369139456 ps
CPU time 19.68 seconds
Started Sep 24 02:44:47 PM UTC 24
Finished Sep 24 02:45:07 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360148365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2360148365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.2727799780
Short name T663
Test name
Test status
Simulation time 351200804 ps
CPU time 7.07 seconds
Started Sep 24 02:44:48 PM UTC 24
Finished Sep 24 02:44:56 PM UTC 24
Peak memory 244880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727799780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2727799780
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.2595215515
Short name T731
Test name
Test status
Simulation time 846068987 ps
CPU time 5.74 seconds
Started Sep 24 02:44:45 PM UTC 24
Finished Sep 24 02:44:52 PM UTC 24
Peak memory 234644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595215515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.2595215515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.73334436
Short name T708
Test name
Test status
Simulation time 1205269522 ps
CPU time 7.26 seconds
Started Sep 24 02:44:44 PM UTC 24
Finished Sep 24 02:44:53 PM UTC 24
Peak memory 245068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73334436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.73334436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.121087656
Short name T734
Test name
Test status
Simulation time 314768790 ps
CPU time 4.3 seconds
Started Sep 24 02:44:51 PM UTC 24
Finished Sep 24 02:44:57 PM UTC 24
Peak memory 233348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121087656 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.121087656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.3098061055
Short name T999
Test name
Test status
Simulation time 176454782584 ps
CPU time 459.71 seconds
Started Sep 24 02:44:54 PM UTC 24
Finished Sep 24 02:52:40 PM UTC 24
Peak memory 267764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098061055 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.3098061055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.2869169852
Short name T728
Test name
Test status
Simulation time 504374230 ps
CPU time 6.47 seconds
Started Sep 24 02:44:41 PM UTC 24
Finished Sep 24 02:44:49 PM UTC 24
Peak memory 227396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869169852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2869169852
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.66865207
Short name T729
Test name
Test status
Simulation time 480597361 ps
CPU time 7.86 seconds
Started Sep 24 02:44:41 PM UTC 24
Finished Sep 24 02:44:50 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66865207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.66865207
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.3525869956
Short name T727
Test name
Test status
Simulation time 138655013 ps
CPU time 1.3 seconds
Started Sep 24 02:44:44 PM UTC 24
Finished Sep 24 02:44:47 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525869956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3525869956
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.3834776281
Short name T726
Test name
Test status
Simulation time 48675617 ps
CPU time 1.31 seconds
Started Sep 24 02:44:44 PM UTC 24
Finished Sep 24 02:44:47 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834776281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3834776281
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.1164244566
Short name T733
Test name
Test status
Simulation time 1036010936 ps
CPU time 7.52 seconds
Started Sep 24 02:44:48 PM UTC 24
Finished Sep 24 02:44:56 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164244566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1164244566
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.4059050305
Short name T752
Test name
Test status
Simulation time 14488942 ps
CPU time 1.17 seconds
Started Sep 24 02:45:10 PM UTC 24
Finished Sep 24 02:45:12 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059050305 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.4059050305
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2011240046
Short name T758
Test name
Test status
Simulation time 1910104714 ps
CPU time 12.23 seconds
Started Sep 24 02:45:03 PM UTC 24
Finished Sep 24 02:45:17 PM UTC 24
Peak memory 245184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011240046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2011240046
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.2536472350
Short name T736
Test name
Test status
Simulation time 18239022 ps
CPU time 1.17 seconds
Started Sep 24 02:44:56 PM UTC 24
Finished Sep 24 02:44:58 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536472350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2536472350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.3419602296
Short name T877
Test name
Test status
Simulation time 31279744501 ps
CPU time 129.3 seconds
Started Sep 24 02:45:06 PM UTC 24
Finished Sep 24 02:47:19 PM UTC 24
Peak memory 261704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419602296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3419602296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.650683637
Short name T838
Test name
Test status
Simulation time 71120440065 ps
CPU time 96.8 seconds
Started Sep 24 02:45:06 PM UTC 24
Finished Sep 24 02:46:45 PM UTC 24
Peak memory 244572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650683637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.650683637
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.968584502
Short name T924
Test name
Test status
Simulation time 46651823186 ps
CPU time 189.44 seconds
Started Sep 24 02:45:08 PM UTC 24
Finished Sep 24 02:48:20 PM UTC 24
Peak memory 267968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968584502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.968584502
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.2085843434
Short name T751
Test name
Test status
Simulation time 384613372 ps
CPU time 7.15 seconds
Started Sep 24 02:45:03 PM UTC 24
Finished Sep 24 02:45:11 PM UTC 24
Peak memory 251132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085843434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2085843434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.1021754725
Short name T874
Test name
Test status
Simulation time 16806520063 ps
CPU time 128.18 seconds
Started Sep 24 02:45:04 PM UTC 24
Finished Sep 24 02:47:15 PM UTC 24
Peak memory 261504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021754725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.1021754725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3024538515
Short name T748
Test name
Test status
Simulation time 554437358 ps
CPU time 7.73 seconds
Started Sep 24 02:45:01 PM UTC 24
Finished Sep 24 02:45:10 PM UTC 24
Peak memory 234628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024538515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3024538515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.4091916349
Short name T771
Test name
Test status
Simulation time 1103908990 ps
CPU time 21.98 seconds
Started Sep 24 02:45:01 PM UTC 24
Finished Sep 24 02:45:24 PM UTC 24
Peak memory 244924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091916349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4091916349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2174900492
Short name T760
Test name
Test status
Simulation time 12934643189 ps
CPU time 15.53 seconds
Started Sep 24 02:44:59 PM UTC 24
Finished Sep 24 02:45:17 PM UTC 24
Peak memory 234756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174900492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2174900492
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2303749425
Short name T364
Test name
Test status
Simulation time 924350180 ps
CPU time 8.46 seconds
Started Sep 24 02:44:59 PM UTC 24
Finished Sep 24 02:45:09 PM UTC 24
Peak memory 249084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303749425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2303749425
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.2481348991
Short name T750
Test name
Test status
Simulation time 363235001 ps
CPU time 5.09 seconds
Started Sep 24 02:45:05 PM UTC 24
Finished Sep 24 02:45:11 PM UTC 24
Peak memory 233500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481348991 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.2481348991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.1967385377
Short name T882
Test name
Test status
Simulation time 62253451414 ps
CPU time 131.71 seconds
Started Sep 24 02:45:09 PM UTC 24
Finished Sep 24 02:47:23 PM UTC 24
Peak memory 251652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967385377 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.1967385377
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.3137389283
Short name T741
Test name
Test status
Simulation time 387435112 ps
CPU time 3.46 seconds
Started Sep 24 02:44:57 PM UTC 24
Finished Sep 24 02:45:02 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137389283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3137389283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.2804798511
Short name T737
Test name
Test status
Simulation time 37009608 ps
CPU time 1.14 seconds
Started Sep 24 02:44:57 PM UTC 24
Finished Sep 24 02:44:59 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804798511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2804798511
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.3937115452
Short name T739
Test name
Test status
Simulation time 467162010 ps
CPU time 1.97 seconds
Started Sep 24 02:44:57 PM UTC 24
Finished Sep 24 02:45:00 PM UTC 24
Peak memory 227064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937115452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3937115452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.1550588880
Short name T738
Test name
Test status
Simulation time 95186721 ps
CPU time 1.77 seconds
Started Sep 24 02:44:57 PM UTC 24
Finished Sep 24 02:45:00 PM UTC 24
Peak memory 215660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550588880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1550588880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.102528247
Short name T755
Test name
Test status
Simulation time 633332046 ps
CPU time 11.72 seconds
Started Sep 24 02:45:01 PM UTC 24
Finished Sep 24 02:45:14 PM UTC 24
Peak memory 249284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102528247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.102528247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.10824272
Short name T769
Test name
Test status
Simulation time 41944547 ps
CPU time 1.19 seconds
Started Sep 24 02:45:22 PM UTC 24
Finished Sep 24 02:45:24 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10824272 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.10824272
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.158458097
Short name T766
Test name
Test status
Simulation time 2147619759 ps
CPU time 5.18 seconds
Started Sep 24 02:45:16 PM UTC 24
Finished Sep 24 02:45:23 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158458097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.158458097
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.3656601571
Short name T753
Test name
Test status
Simulation time 16607969 ps
CPU time 1.29 seconds
Started Sep 24 02:45:10 PM UTC 24
Finished Sep 24 02:45:12 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656601571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3656601571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2797047726
Short name T843
Test name
Test status
Simulation time 9778262201 ps
CPU time 86.92 seconds
Started Sep 24 02:45:18 PM UTC 24
Finished Sep 24 02:46:48 PM UTC 24
Peak memory 261508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797047726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2797047726
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3660542531
Short name T113
Test name
Test status
Simulation time 25230168023 ps
CPU time 116.33 seconds
Started Sep 24 02:45:22 PM UTC 24
Finished Sep 24 02:47:21 PM UTC 24
Peak memory 268028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660542531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3660542531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2637088239
Short name T941
Test name
Test status
Simulation time 19576253886 ps
CPU time 199.74 seconds
Started Sep 24 02:45:22 PM UTC 24
Finished Sep 24 02:48:45 PM UTC 24
Peak memory 263868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637088239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.2637088239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.2568118984
Short name T417
Test name
Test status
Simulation time 3612006740 ps
CPU time 8.4 seconds
Started Sep 24 02:45:17 PM UTC 24
Finished Sep 24 02:45:27 PM UTC 24
Peak memory 234812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568118984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2568118984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.125715494
Short name T805
Test name
Test status
Simulation time 7026551788 ps
CPU time 44.58 seconds
Started Sep 24 02:45:17 PM UTC 24
Finished Sep 24 02:46:04 PM UTC 24
Peak memory 261404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125715494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.125715494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.2371614299
Short name T763
Test name
Test status
Simulation time 132831575 ps
CPU time 5.64 seconds
Started Sep 24 02:45:14 PM UTC 24
Finished Sep 24 02:45:21 PM UTC 24
Peak memory 245132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371614299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2371614299
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.1817238330
Short name T415
Test name
Test status
Simulation time 27761957019 ps
CPU time 19.21 seconds
Started Sep 24 02:45:15 PM UTC 24
Finished Sep 24 02:45:36 PM UTC 24
Peak memory 251404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817238330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1817238330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.3792394899
Short name T773
Test name
Test status
Simulation time 706350480 ps
CPU time 10.39 seconds
Started Sep 24 02:45:14 PM UTC 24
Finished Sep 24 02:45:26 PM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792394899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.3792394899
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.3455464345
Short name T767
Test name
Test status
Simulation time 243795357 ps
CPU time 7.8 seconds
Started Sep 24 02:45:14 PM UTC 24
Finished Sep 24 02:45:23 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455464345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3455464345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1908613647
Short name T768
Test name
Test status
Simulation time 2973793366 ps
CPU time 4.36 seconds
Started Sep 24 02:45:17 PM UTC 24
Finished Sep 24 02:45:23 PM UTC 24
Peak memory 231168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908613647 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.1908613647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.2728311458
Short name T317
Test name
Test status
Simulation time 56492968812 ps
CPU time 251.79 seconds
Started Sep 24 02:45:22 PM UTC 24
Finished Sep 24 02:49:38 PM UTC 24
Peak memory 282052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728311458 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.2728311458
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.766760952
Short name T764
Test name
Test status
Simulation time 1913309150 ps
CPU time 7.88 seconds
Started Sep 24 02:45:12 PM UTC 24
Finished Sep 24 02:45:21 PM UTC 24
Peak memory 231744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766760952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.766760952
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2698699823
Short name T759
Test name
Test status
Simulation time 2274688188 ps
CPU time 4.48 seconds
Started Sep 24 02:45:11 PM UTC 24
Finished Sep 24 02:45:17 PM UTC 24
Peak memory 217260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698699823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2698699823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.1111337667
Short name T757
Test name
Test status
Simulation time 121586713 ps
CPU time 2.84 seconds
Started Sep 24 02:45:12 PM UTC 24
Finished Sep 24 02:45:16 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111337667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1111337667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.1182313581
Short name T756
Test name
Test status
Simulation time 103676365 ps
CPU time 1.43 seconds
Started Sep 24 02:45:12 PM UTC 24
Finished Sep 24 02:45:15 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182313581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1182313581
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.556318645
Short name T765
Test name
Test status
Simulation time 699829943 ps
CPU time 3.82 seconds
Started Sep 24 02:45:16 PM UTC 24
Finished Sep 24 02:45:21 PM UTC 24
Peak memory 234756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556318645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.556318645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.1745699482
Short name T780
Test name
Test status
Simulation time 21614229 ps
CPU time 1.15 seconds
Started Sep 24 02:45:34 PM UTC 24
Finished Sep 24 02:45:36 PM UTC 24
Peak memory 213648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745699482 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.1745699482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.1064229740
Short name T778
Test name
Test status
Simulation time 74936459 ps
CPU time 3.39 seconds
Started Sep 24 02:45:27 PM UTC 24
Finished Sep 24 02:45:32 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064229740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1064229740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.3290972120
Short name T770
Test name
Test status
Simulation time 13814144 ps
CPU time 1.17 seconds
Started Sep 24 02:45:22 PM UTC 24
Finished Sep 24 02:45:24 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290972120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3290972120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2452062940
Short name T1001
Test name
Test status
Simulation time 38162461682 ps
CPU time 477.73 seconds
Started Sep 24 02:45:31 PM UTC 24
Finished Sep 24 02:53:36 PM UTC 24
Peak memory 267840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452062940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2452062940
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1134167345
Short name T916
Test name
Test status
Simulation time 82709102530 ps
CPU time 154.8 seconds
Started Sep 24 02:45:33 PM UTC 24
Finished Sep 24 02:48:11 PM UTC 24
Peak memory 265660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134167345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1134167345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.1523090950
Short name T795
Test name
Test status
Simulation time 1913908509 ps
CPU time 20.87 seconds
Started Sep 24 02:45:27 PM UTC 24
Finished Sep 24 02:45:49 PM UTC 24
Peak memory 249088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523090950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1523090950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1628996083
Short name T822
Test name
Test status
Simulation time 3138373603 ps
CPU time 54.69 seconds
Started Sep 24 02:45:28 PM UTC 24
Finished Sep 24 02:46:25 PM UTC 24
Peak memory 267584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628996083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.1628996083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.4291303549
Short name T781
Test name
Test status
Simulation time 423579029 ps
CPU time 9.8 seconds
Started Sep 24 02:45:26 PM UTC 24
Finished Sep 24 02:45:37 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291303549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4291303549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.2200858916
Short name T784
Test name
Test status
Simulation time 550937354 ps
CPU time 12.96 seconds
Started Sep 24 02:45:26 PM UTC 24
Finished Sep 24 02:45:40 PM UTC 24
Peak memory 251340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200858916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2200858916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.771591350
Short name T335
Test name
Test status
Simulation time 18516896769 ps
CPU time 22.5 seconds
Started Sep 24 02:45:26 PM UTC 24
Finished Sep 24 02:45:50 PM UTC 24
Peak memory 234764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771591350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.771591350
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.166924056
Short name T777
Test name
Test status
Simulation time 274763183 ps
CPU time 3.15 seconds
Started Sep 24 02:45:26 PM UTC 24
Finished Sep 24 02:45:30 PM UTC 24
Peak memory 244656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166924056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.166924056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1162237946
Short name T779
Test name
Test status
Simulation time 423045761 ps
CPU time 4.1 seconds
Started Sep 24 02:45:28 PM UTC 24
Finished Sep 24 02:45:34 PM UTC 24
Peak memory 233572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162237946 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1162237946
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.567755319
Short name T813
Test name
Test status
Simulation time 14885250566 ps
CPU time 40.05 seconds
Started Sep 24 02:45:33 PM UTC 24
Finished Sep 24 02:46:15 PM UTC 24
Peak memory 251324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567755319 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.567755319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.4049623449
Short name T772
Test name
Test status
Simulation time 15316603 ps
CPU time 1.2 seconds
Started Sep 24 02:45:23 PM UTC 24
Finished Sep 24 02:45:25 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049623449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4049623449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3473576100
Short name T774
Test name
Test status
Simulation time 652632436 ps
CPU time 2.64 seconds
Started Sep 24 02:45:22 PM UTC 24
Finished Sep 24 02:45:26 PM UTC 24
Peak memory 216872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473576100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3473576100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.799136770
Short name T776
Test name
Test status
Simulation time 66741273 ps
CPU time 1.5 seconds
Started Sep 24 02:45:24 PM UTC 24
Finished Sep 24 02:45:27 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799136770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.799136770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.3798406180
Short name T775
Test name
Test status
Simulation time 151811016 ps
CPU time 1.35 seconds
Started Sep 24 02:45:24 PM UTC 24
Finished Sep 24 02:45:27 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798406180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3798406180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.3265415252
Short name T791
Test name
Test status
Simulation time 708715856 ps
CPU time 16.88 seconds
Started Sep 24 02:45:27 PM UTC 24
Finished Sep 24 02:45:45 PM UTC 24
Peak memory 251072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265415252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3265415252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.1228143040
Short name T796
Test name
Test status
Simulation time 12522579 ps
CPU time 1.21 seconds
Started Sep 24 02:45:50 PM UTC 24
Finished Sep 24 02:45:52 PM UTC 24
Peak memory 213528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228143040 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.1228143040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.3933529740
Short name T792
Test name
Test status
Simulation time 82329675 ps
CPU time 3 seconds
Started Sep 24 02:45:43 PM UTC 24
Finished Sep 24 02:45:47 PM UTC 24
Peak memory 234148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933529740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3933529740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.1608583128
Short name T782
Test name
Test status
Simulation time 13951952 ps
CPU time 1.17 seconds
Started Sep 24 02:45:36 PM UTC 24
Finished Sep 24 02:45:39 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608583128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1608583128
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.913894071
Short name T794
Test name
Test status
Simulation time 121661030 ps
CPU time 3.76 seconds
Started Sep 24 02:45:44 PM UTC 24
Finished Sep 24 02:45:49 PM UTC 24
Peak memory 234684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913894071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.913894071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.711414560
Short name T378
Test name
Test status
Simulation time 4676168101 ps
CPU time 27.56 seconds
Started Sep 24 02:45:46 PM UTC 24
Finished Sep 24 02:46:15 PM UTC 24
Peak memory 261756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711414560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.711414560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.3973911854
Short name T793
Test name
Test status
Simulation time 405894378 ps
CPU time 4.85 seconds
Started Sep 24 02:45:42 PM UTC 24
Finished Sep 24 02:45:48 PM UTC 24
Peak memory 229396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973911854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3973911854
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.1395371445
Short name T919
Test name
Test status
Simulation time 91291839816 ps
CPU time 150.59 seconds
Started Sep 24 02:45:42 PM UTC 24
Finished Sep 24 02:48:15 PM UTC 24
Peak memory 245112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395371445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1395371445
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.2945937215
Short name T410
Test name
Test status
Simulation time 3578036738 ps
CPU time 20.51 seconds
Started Sep 24 02:45:42 PM UTC 24
Finished Sep 24 02:46:04 PM UTC 24
Peak memory 251256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945937215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.2945937215
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3840329298
Short name T790
Test name
Test status
Simulation time 65224547 ps
CPU time 3.21 seconds
Started Sep 24 02:45:41 PM UTC 24
Finished Sep 24 02:45:45 PM UTC 24
Peak memory 244676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840329298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3840329298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2310871878
Short name T799
Test name
Test status
Simulation time 167697071 ps
CPU time 6.44 seconds
Started Sep 24 02:45:46 PM UTC 24
Finished Sep 24 02:45:53 PM UTC 24
Peak memory 231420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310871878 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2310871878
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.204255989
Short name T348
Test name
Test status
Simulation time 23511370858 ps
CPU time 314.39 seconds
Started Sep 24 02:45:49 PM UTC 24
Finished Sep 24 02:51:09 PM UTC 24
Peak memory 275904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204255989 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.204255989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.928853119
Short name T786
Test name
Test status
Simulation time 460480893 ps
CPU time 3.79 seconds
Started Sep 24 02:45:37 PM UTC 24
Finished Sep 24 02:45:42 PM UTC 24
Peak memory 227440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928853119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.928853119
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.4105917988
Short name T783
Test name
Test status
Simulation time 11992053 ps
CPU time 1.18 seconds
Started Sep 24 02:45:37 PM UTC 24
Finished Sep 24 02:45:40 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105917988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4105917988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.3582009258
Short name T787
Test name
Test status
Simulation time 104072467 ps
CPU time 2.13 seconds
Started Sep 24 02:45:41 PM UTC 24
Finished Sep 24 02:45:44 PM UTC 24
Peak memory 227392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582009258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3582009258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.4160928253
Short name T785
Test name
Test status
Simulation time 711365901 ps
CPU time 1.51 seconds
Started Sep 24 02:45:39 PM UTC 24
Finished Sep 24 02:45:42 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160928253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4160928253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.2988048587
Short name T807
Test name
Test status
Simulation time 12993368454 ps
CPU time 22.84 seconds
Started Sep 24 02:45:43 PM UTC 24
Finished Sep 24 02:46:07 PM UTC 24
Peak memory 261456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988048587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2988048587
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.2596816487
Short name T809
Test name
Test status
Simulation time 43793909 ps
CPU time 1.15 seconds
Started Sep 24 02:46:08 PM UTC 24
Finished Sep 24 02:46:10 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596816487 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.2596816487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.2307974091
Short name T820
Test name
Test status
Simulation time 3007421376 ps
CPU time 22.05 seconds
Started Sep 24 02:45:59 PM UTC 24
Finished Sep 24 02:46:23 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307974091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2307974091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.2948086596
Short name T797
Test name
Test status
Simulation time 114309299 ps
CPU time 1.33 seconds
Started Sep 24 02:45:50 PM UTC 24
Finished Sep 24 02:45:53 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948086596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2948086596
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.1444957064
Short name T812
Test name
Test status
Simulation time 316594770 ps
CPU time 8.57 seconds
Started Sep 24 02:46:04 PM UTC 24
Finished Sep 24 02:46:14 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444957064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1444957064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.818128937
Short name T979
Test name
Test status
Simulation time 18009988470 ps
CPU time 220.82 seconds
Started Sep 24 02:46:05 PM UTC 24
Finished Sep 24 02:49:50 PM UTC 24
Peak memory 265732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818128937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.818128937
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.2001807960
Short name T342
Test name
Test status
Simulation time 3885056214 ps
CPU time 94.14 seconds
Started Sep 24 02:46:05 PM UTC 24
Finished Sep 24 02:47:41 PM UTC 24
Peak memory 267572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001807960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.2001807960
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.3931669229
Short name T814
Test name
Test status
Simulation time 596372316 ps
CPU time 14.21 seconds
Started Sep 24 02:45:59 PM UTC 24
Finished Sep 24 02:46:15 PM UTC 24
Peak memory 245312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931669229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3931669229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.4270103508
Short name T991
Test name
Test status
Simulation time 103417107258 ps
CPU time 287.6 seconds
Started Sep 24 02:46:01 PM UTC 24
Finished Sep 24 02:50:53 PM UTC 24
Peak memory 265600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270103508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.4270103508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.2737690683
Short name T817
Test name
Test status
Simulation time 8093196700 ps
CPU time 19 seconds
Started Sep 24 02:45:57 PM UTC 24
Finished Sep 24 02:46:17 PM UTC 24
Peak memory 234780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737690683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2737690683
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.656178059
Short name T806
Test name
Test status
Simulation time 183370320 ps
CPU time 6.54 seconds
Started Sep 24 02:45:57 PM UTC 24
Finished Sep 24 02:46:05 PM UTC 24
Peak memory 234892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656178059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.656178059
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.149978501
Short name T344
Test name
Test status
Simulation time 114803425 ps
CPU time 4.04 seconds
Started Sep 24 02:45:55 PM UTC 24
Finished Sep 24 02:46:00 PM UTC 24
Peak memory 244300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149978501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.149978501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.4199393539
Short name T377
Test name
Test status
Simulation time 1236024692 ps
CPU time 13.07 seconds
Started Sep 24 02:45:55 PM UTC 24
Finished Sep 24 02:46:09 PM UTC 24
Peak memory 244276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199393539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4199393539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.3771606531
Short name T808
Test name
Test status
Simulation time 1285886086 ps
CPU time 6.79 seconds
Started Sep 24 02:46:01 PM UTC 24
Finished Sep 24 02:46:09 PM UTC 24
Peak memory 231164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771606531 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.3771606531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.3924837338
Short name T833
Test name
Test status
Simulation time 12741320407 ps
CPU time 30.12 seconds
Started Sep 24 02:46:05 PM UTC 24
Finished Sep 24 02:46:37 PM UTC 24
Peak memory 234044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924837338 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.3924837338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.2322363839
Short name T800
Test name
Test status
Simulation time 43271806 ps
CPU time 1.13 seconds
Started Sep 24 02:45:54 PM UTC 24
Finished Sep 24 02:45:56 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322363839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2322363839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1536726410
Short name T804
Test name
Test status
Simulation time 6260510086 ps
CPU time 11.37 seconds
Started Sep 24 02:45:50 PM UTC 24
Finished Sep 24 02:46:03 PM UTC 24
Peak memory 227508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536726410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1536726410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.2028231255
Short name T802
Test name
Test status
Simulation time 74240155 ps
CPU time 2.08 seconds
Started Sep 24 02:45:54 PM UTC 24
Finished Sep 24 02:45:57 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028231255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2028231255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3224295660
Short name T801
Test name
Test status
Simulation time 15446413 ps
CPU time 1.18 seconds
Started Sep 24 02:45:54 PM UTC 24
Finished Sep 24 02:45:56 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224295660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3224295660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.3389975967
Short name T848
Test name
Test status
Simulation time 17098795960 ps
CPU time 50.58 seconds
Started Sep 24 02:45:58 PM UTC 24
Finished Sep 24 02:46:50 PM UTC 24
Peak memory 261568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389975967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3389975967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2085959820
Short name T449
Test name
Test status
Simulation time 16772011 ps
CPU time 1.2 seconds
Started Sep 24 02:37:31 PM UTC 24
Finished Sep 24 02:37:33 PM UTC 24
Peak memory 212560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085959820 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2085959820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3754893093
Short name T97
Test name
Test status
Simulation time 836842869 ps
CPU time 7.74 seconds
Started Sep 24 02:37:23 PM UTC 24
Finished Sep 24 02:37:32 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754893093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3754893093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.4244331382
Short name T446
Test name
Test status
Simulation time 49426452 ps
CPU time 0.98 seconds
Started Sep 24 02:37:15 PM UTC 24
Finished Sep 24 02:37:17 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244331382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4244331382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.975652674
Short name T359
Test name
Test status
Simulation time 24284576808 ps
CPU time 236.76 seconds
Started Sep 24 02:37:28 PM UTC 24
Finished Sep 24 02:41:28 PM UTC 24
Peak memory 267708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975652674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.975652674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.2677737791
Short name T63
Test name
Test status
Simulation time 1948564571 ps
CPU time 34.86 seconds
Started Sep 24 02:37:29 PM UTC 24
Finished Sep 24 02:38:05 PM UTC 24
Peak memory 261312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677737791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.2677737791
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3256805907
Short name T96
Test name
Test status
Simulation time 42428244 ps
CPU time 4.05 seconds
Started Sep 24 02:37:24 PM UTC 24
Finished Sep 24 02:37:30 PM UTC 24
Peak memory 234660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256805907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3256805907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1871852164
Short name T552
Test name
Test status
Simulation time 420069409076 ps
CPU time 254.66 seconds
Started Sep 24 02:37:26 PM UTC 24
Finished Sep 24 02:41:45 PM UTC 24
Peak memory 261436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871852164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.1871852164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1991177886
Short name T78
Test name
Test status
Simulation time 71270070 ps
CPU time 4.29 seconds
Started Sep 24 02:37:22 PM UTC 24
Finished Sep 24 02:37:27 PM UTC 24
Peak memory 245256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991177886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1991177886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.445942384
Short name T398
Test name
Test status
Simulation time 10220650777 ps
CPU time 94.25 seconds
Started Sep 24 02:37:22 PM UTC 24
Finished Sep 24 02:38:59 PM UTC 24
Peak memory 251396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445942384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.445942384
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3513793833
Short name T70
Test name
Test status
Simulation time 15524334511 ps
CPU time 15.72 seconds
Started Sep 24 02:37:19 PM UTC 24
Finished Sep 24 02:37:36 PM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513793833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.3513793833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1940166999
Short name T52
Test name
Test status
Simulation time 11074346414 ps
CPU time 9.71 seconds
Started Sep 24 02:37:19 PM UTC 24
Finished Sep 24 02:37:30 PM UTC 24
Peak memory 235192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940166999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1940166999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3750384672
Short name T72
Test name
Test status
Simulation time 500899899 ps
CPU time 11.78 seconds
Started Sep 24 02:37:26 PM UTC 24
Finished Sep 24 02:37:39 PM UTC 24
Peak memory 233324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750384672 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.3750384672
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3499812351
Short name T20
Test name
Test status
Simulation time 113974539 ps
CPU time 1.77 seconds
Started Sep 24 02:37:30 PM UTC 24
Finished Sep 24 02:37:33 PM UTC 24
Peak memory 256992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499812351 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3499812351
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.3481147598
Short name T42
Test name
Test status
Simulation time 1797074876 ps
CPU time 4.99 seconds
Started Sep 24 02:37:18 PM UTC 24
Finished Sep 24 02:37:24 PM UTC 24
Peak memory 227336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481147598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3481147598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.3718200189
Short name T79
Test name
Test status
Simulation time 1725851389 ps
CPU time 9.57 seconds
Started Sep 24 02:37:18 PM UTC 24
Finished Sep 24 02:37:28 PM UTC 24
Peak memory 227616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718200189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3718200189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.4199959074
Short name T43
Test name
Test status
Simulation time 228526041 ps
CPU time 2.35 seconds
Started Sep 24 02:37:19 PM UTC 24
Finished Sep 24 02:37:22 PM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199959074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4199959074
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2266034320
Short name T448
Test name
Test status
Simulation time 298930123 ps
CPU time 1.47 seconds
Started Sep 24 02:37:19 PM UTC 24
Finished Sep 24 02:37:21 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266034320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2266034320
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.2453635407
Short name T56
Test name
Test status
Simulation time 960881747 ps
CPU time 4.67 seconds
Started Sep 24 02:37:22 PM UTC 24
Finished Sep 24 02:37:28 PM UTC 24
Peak memory 234744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453635407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2453635407
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.888241981
Short name T828
Test name
Test status
Simulation time 23251799 ps
CPU time 1.19 seconds
Started Sep 24 02:46:27 PM UTC 24
Finished Sep 24 02:46:30 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888241981 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.888241981
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.562659938
Short name T819
Test name
Test status
Simulation time 76992708 ps
CPU time 3.68 seconds
Started Sep 24 02:46:17 PM UTC 24
Finished Sep 24 02:46:22 PM UTC 24
Peak memory 244880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562659938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.562659938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.3510672354
Short name T810
Test name
Test status
Simulation time 45042913 ps
CPU time 1.28 seconds
Started Sep 24 02:46:09 PM UTC 24
Finished Sep 24 02:46:12 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510672354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3510672354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.670152094
Short name T821
Test name
Test status
Simulation time 56650324650 ps
CPU time 117.27 seconds
Started Sep 24 02:46:23 PM UTC 24
Finished Sep 24 02:48:22 PM UTC 24
Peak memory 277872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670152094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.670152094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3480684156
Short name T992
Test name
Test status
Simulation time 33453728984 ps
CPU time 284.29 seconds
Started Sep 24 02:46:24 PM UTC 24
Finished Sep 24 02:51:13 PM UTC 24
Peak memory 267712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480684156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3480684156
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2201236682
Short name T853
Test name
Test status
Simulation time 873756848 ps
CPU time 24.32 seconds
Started Sep 24 02:46:26 PM UTC 24
Finished Sep 24 02:46:52 PM UTC 24
Peak memory 245300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201236682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.2201236682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.606810000
Short name T823
Test name
Test status
Simulation time 105283428 ps
CPU time 5.94 seconds
Started Sep 24 02:46:19 PM UTC 24
Finished Sep 24 02:46:26 PM UTC 24
Peak memory 244932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606810000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.606810000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2837282716
Short name T981
Test name
Test status
Simulation time 22165169671 ps
CPU time 216.6 seconds
Started Sep 24 02:46:19 PM UTC 24
Finished Sep 24 02:49:59 PM UTC 24
Peak memory 263740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837282716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.2837282716
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1040449253
Short name T818
Test name
Test status
Simulation time 1498535588 ps
CPU time 4.43 seconds
Started Sep 24 02:46:16 PM UTC 24
Finished Sep 24 02:46:22 PM UTC 24
Peak memory 234696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040449253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1040449253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.3775019996
Short name T824
Test name
Test status
Simulation time 277843509 ps
CPU time 8.49 seconds
Started Sep 24 02:46:16 PM UTC 24
Finished Sep 24 02:46:26 PM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775019996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3775019996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2655516293
Short name T825
Test name
Test status
Simulation time 2847281246 ps
CPU time 8.99 seconds
Started Sep 24 02:46:16 PM UTC 24
Finished Sep 24 02:46:26 PM UTC 24
Peak memory 245120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655516293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.2655516293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4225923279
Short name T830
Test name
Test status
Simulation time 944736792 ps
CPU time 14.71 seconds
Started Sep 24 02:46:15 PM UTC 24
Finished Sep 24 02:46:31 PM UTC 24
Peak memory 251080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225923279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4225923279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.741135710
Short name T834
Test name
Test status
Simulation time 1801934489 ps
CPU time 14.19 seconds
Started Sep 24 02:46:23 PM UTC 24
Finished Sep 24 02:46:38 PM UTC 24
Peak memory 233392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741135710 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.741135710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.2074576528
Short name T186
Test name
Test status
Simulation time 71535893610 ps
CPU time 276.79 seconds
Started Sep 24 02:46:26 PM UTC 24
Finished Sep 24 02:51:08 PM UTC 24
Peak memory 277952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074576528 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.2074576528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.130736871
Short name T827
Test name
Test status
Simulation time 2767367129 ps
CPU time 15.99 seconds
Started Sep 24 02:46:11 PM UTC 24
Finished Sep 24 02:46:29 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130736871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.130736871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.666449608
Short name T811
Test name
Test status
Simulation time 19480535 ps
CPU time 1.18 seconds
Started Sep 24 02:46:10 PM UTC 24
Finished Sep 24 02:46:13 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666449608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.666449608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3545092488
Short name T816
Test name
Test status
Simulation time 181560831 ps
CPU time 2.01 seconds
Started Sep 24 02:46:14 PM UTC 24
Finished Sep 24 02:46:17 PM UTC 24
Peak memory 227048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545092488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3545092488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.4121549588
Short name T815
Test name
Test status
Simulation time 108045478 ps
CPU time 1.45 seconds
Started Sep 24 02:46:13 PM UTC 24
Finished Sep 24 02:46:15 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121549588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4121549588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.3662021579
Short name T826
Test name
Test status
Simulation time 601467130 ps
CPU time 9.54 seconds
Started Sep 24 02:46:16 PM UTC 24
Finished Sep 24 02:46:27 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662021579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3662021579
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2460834368
Short name T845
Test name
Test status
Simulation time 72083823 ps
CPU time 1.05 seconds
Started Sep 24 02:46:47 PM UTC 24
Finished Sep 24 02:46:49 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460834368 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.2460834368
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3625529040
Short name T837
Test name
Test status
Simulation time 71167451 ps
CPU time 3.91 seconds
Started Sep 24 02:46:38 PM UTC 24
Finished Sep 24 02:46:42 PM UTC 24
Peak memory 234740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625529040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3625529040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.348459757
Short name T829
Test name
Test status
Simulation time 70008769 ps
CPU time 1.24 seconds
Started Sep 24 02:46:28 PM UTC 24
Finished Sep 24 02:46:30 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348459757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.348459757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.2030174557
Short name T970
Test name
Test status
Simulation time 39364709779 ps
CPU time 152.52 seconds
Started Sep 24 02:46:42 PM UTC 24
Finished Sep 24 02:49:17 PM UTC 24
Peak memory 265668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030174557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2030174557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.4280750554
Short name T330
Test name
Test status
Simulation time 116186973977 ps
CPU time 233.74 seconds
Started Sep 24 02:46:43 PM UTC 24
Finished Sep 24 02:50:40 PM UTC 24
Peak memory 247236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280750554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4280750554
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3973434468
Short name T187
Test name
Test status
Simulation time 102251235614 ps
CPU time 264.13 seconds
Started Sep 24 02:46:45 PM UTC 24
Finished Sep 24 02:51:13 PM UTC 24
Peak memory 261568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973434468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.3973434468
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.2267708993
Short name T840
Test name
Test status
Simulation time 960059502 ps
CPU time 6.69 seconds
Started Sep 24 02:46:39 PM UTC 24
Finished Sep 24 02:46:46 PM UTC 24
Peak memory 234688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267708993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2267708993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2808735388
Short name T345
Test name
Test status
Simulation time 29987845915 ps
CPU time 263.81 seconds
Started Sep 24 02:46:40 PM UTC 24
Finished Sep 24 02:51:07 PM UTC 24
Peak memory 267796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808735388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2808735388
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.2473057572
Short name T839
Test name
Test status
Simulation time 4241492419 ps
CPU time 11.82 seconds
Started Sep 24 02:46:33 PM UTC 24
Finished Sep 24 02:46:46 PM UTC 24
Peak memory 235036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473057572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2473057572
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.2412952478
Short name T850
Test name
Test status
Simulation time 7025321245 ps
CPU time 15.81 seconds
Started Sep 24 02:46:34 PM UTC 24
Finished Sep 24 02:46:51 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412952478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2412952478
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.76543766
Short name T854
Test name
Test status
Simulation time 11464965899 ps
CPU time 19.53 seconds
Started Sep 24 02:46:32 PM UTC 24
Finished Sep 24 02:46:53 PM UTC 24
Peak memory 231596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76543766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.76543766
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1639466643
Short name T835
Test name
Test status
Simulation time 4178716449 ps
CPU time 6.8 seconds
Started Sep 24 02:46:31 PM UTC 24
Finished Sep 24 02:46:39 PM UTC 24
Peak memory 245072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639466643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1639466643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.734080916
Short name T841
Test name
Test status
Simulation time 158161040 ps
CPU time 3.87 seconds
Started Sep 24 02:46:42 PM UTC 24
Finished Sep 24 02:46:47 PM UTC 24
Peak memory 233284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734080916 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.734080916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1711731141
Short name T844
Test name
Test status
Simulation time 37486378 ps
CPU time 1.13 seconds
Started Sep 24 02:46:46 PM UTC 24
Finished Sep 24 02:46:48 PM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711731141 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.1711731141
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.3741866728
Short name T847
Test name
Test status
Simulation time 4597901028 ps
CPU time 18.47 seconds
Started Sep 24 02:46:30 PM UTC 24
Finished Sep 24 02:46:50 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741866728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3741866728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1000535170
Short name T836
Test name
Test status
Simulation time 2233871502 ps
CPU time 12.43 seconds
Started Sep 24 02:46:28 PM UTC 24
Finished Sep 24 02:46:41 PM UTC 24
Peak memory 227632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000535170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1000535170
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.3218892387
Short name T832
Test name
Test status
Simulation time 96937465 ps
CPU time 4.28 seconds
Started Sep 24 02:46:31 PM UTC 24
Finished Sep 24 02:46:36 PM UTC 24
Peak memory 227436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218892387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3218892387
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3120228170
Short name T831
Test name
Test status
Simulation time 293626670 ps
CPU time 1.41 seconds
Started Sep 24 02:46:31 PM UTC 24
Finished Sep 24 02:46:33 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120228170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3120228170
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.720772687
Short name T842
Test name
Test status
Simulation time 1928019515 ps
CPU time 8.91 seconds
Started Sep 24 02:46:37 PM UTC 24
Finished Sep 24 02:46:47 PM UTC 24
Peak memory 244888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720772687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.720772687
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1893508878
Short name T859
Test name
Test status
Simulation time 18387487 ps
CPU time 1.18 seconds
Started Sep 24 02:46:57 PM UTC 24
Finished Sep 24 02:47:00 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893508878 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.1893508878
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1150945035
Short name T856
Test name
Test status
Simulation time 181127423 ps
CPU time 3.09 seconds
Started Sep 24 02:46:51 PM UTC 24
Finished Sep 24 02:46:56 PM UTC 24
Peak memory 244880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150945035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1150945035
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2482302168
Short name T846
Test name
Test status
Simulation time 16086616 ps
CPU time 1.11 seconds
Started Sep 24 02:46:48 PM UTC 24
Finished Sep 24 02:46:50 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482302168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2482302168
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.764250929
Short name T324
Test name
Test status
Simulation time 27995804736 ps
CPU time 117.6 seconds
Started Sep 24 02:46:53 PM UTC 24
Finished Sep 24 02:48:53 PM UTC 24
Peak memory 277832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764250929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.764250929
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.318355497
Short name T998
Test name
Test status
Simulation time 148507496319 ps
CPU time 338.58 seconds
Started Sep 24 02:46:54 PM UTC 24
Finished Sep 24 02:52:37 PM UTC 24
Peak memory 263612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318355497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.318355497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.4268111020
Short name T928
Test name
Test status
Simulation time 4606165482 ps
CPU time 88.53 seconds
Started Sep 24 02:46:56 PM UTC 24
Finished Sep 24 02:48:27 PM UTC 24
Peak memory 267708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268111020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.4268111020
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.2171368893
Short name T868
Test name
Test status
Simulation time 6082042434 ps
CPU time 15.15 seconds
Started Sep 24 02:46:52 PM UTC 24
Finished Sep 24 02:47:08 PM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171368893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2171368893
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.4124381450
Short name T322
Test name
Test status
Simulation time 20555376876 ps
CPU time 239.66 seconds
Started Sep 24 02:46:53 PM UTC 24
Finished Sep 24 02:50:56 PM UTC 24
Peak memory 282172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124381450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.4124381450
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.3397917000
Short name T851
Test name
Test status
Simulation time 552432200 ps
CPU time 5.86 seconds
Started Sep 24 02:46:50 PM UTC 24
Finished Sep 24 02:46:57 PM UTC 24
Peak memory 234716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397917000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3397917000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1525485890
Short name T855
Test name
Test status
Simulation time 314342271 ps
CPU time 3.89 seconds
Started Sep 24 02:46:50 PM UTC 24
Finished Sep 24 02:46:55 PM UTC 24
Peak memory 244928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525485890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1525485890
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.4252055183
Short name T857
Test name
Test status
Simulation time 675429666 ps
CPU time 5.04 seconds
Started Sep 24 02:46:50 PM UTC 24
Finished Sep 24 02:46:56 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252055183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.4252055183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3678394110
Short name T862
Test name
Test status
Simulation time 2016194041 ps
CPU time 12.29 seconds
Started Sep 24 02:46:49 PM UTC 24
Finished Sep 24 02:47:02 PM UTC 24
Peak memory 245244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678394110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3678394110
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.4238306994
Short name T866
Test name
Test status
Simulation time 549304817 ps
CPU time 10.83 seconds
Started Sep 24 02:46:53 PM UTC 24
Finished Sep 24 02:47:05 PM UTC 24
Peak memory 233612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238306994 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.4238306994
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.1388108206
Short name T987
Test name
Test status
Simulation time 212372172344 ps
CPU time 201.7 seconds
Started Sep 24 02:46:56 PM UTC 24
Finished Sep 24 02:50:21 PM UTC 24
Peak memory 261572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388108206 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.1388108206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.286392705
Short name T881
Test name
Test status
Simulation time 16423024983 ps
CPU time 33.33 seconds
Started Sep 24 02:46:48 PM UTC 24
Finished Sep 24 02:47:22 PM UTC 24
Peak memory 231812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286392705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.286392705
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1812536902
Short name T864
Test name
Test status
Simulation time 12827725982 ps
CPU time 14.38 seconds
Started Sep 24 02:46:48 PM UTC 24
Finished Sep 24 02:47:03 PM UTC 24
Peak memory 227464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812536902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1812536902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.1687475917
Short name T852
Test name
Test status
Simulation time 64362131 ps
CPU time 2.07 seconds
Started Sep 24 02:46:49 PM UTC 24
Finished Sep 24 02:46:52 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687475917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1687475917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3807178056
Short name T849
Test name
Test status
Simulation time 22732817 ps
CPU time 1.19 seconds
Started Sep 24 02:46:49 PM UTC 24
Finished Sep 24 02:46:51 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807178056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3807178056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.4042294172
Short name T860
Test name
Test status
Simulation time 1316769179 ps
CPU time 7.35 seconds
Started Sep 24 02:46:51 PM UTC 24
Finished Sep 24 02:47:00 PM UTC 24
Peak memory 235012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042294172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4042294172
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.2870435177
Short name T876
Test name
Test status
Simulation time 23788678 ps
CPU time 1.22 seconds
Started Sep 24 02:47:14 PM UTC 24
Finished Sep 24 02:47:17 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870435177 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.2870435177
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1305125026
Short name T134
Test name
Test status
Simulation time 481649019 ps
CPU time 7.02 seconds
Started Sep 24 02:47:06 PM UTC 24
Finished Sep 24 02:47:14 PM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305125026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1305125026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.3917408
Short name T861
Test name
Test status
Simulation time 15175191 ps
CPU time 1.17 seconds
Started Sep 24 02:46:58 PM UTC 24
Finished Sep 24 02:47:01 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3917408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.2419424986
Short name T896
Test name
Test status
Simulation time 13764206085 ps
CPU time 31.2 seconds
Started Sep 24 02:47:09 PM UTC 24
Finished Sep 24 02:47:43 PM UTC 24
Peak memory 245388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419424986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2419424986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3505598075
Short name T936
Test name
Test status
Simulation time 9664327027 ps
CPU time 88.43 seconds
Started Sep 24 02:47:12 PM UTC 24
Finished Sep 24 02:48:42 PM UTC 24
Peak memory 261432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505598075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.3505598075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.3998679020
Short name T871
Test name
Test status
Simulation time 117902686 ps
CPU time 5.71 seconds
Started Sep 24 02:47:06 PM UTC 24
Finished Sep 24 02:47:13 PM UTC 24
Peak memory 235072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998679020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3998679020
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.999121864
Short name T869
Test name
Test status
Simulation time 13136819 ps
CPU time 1.25 seconds
Started Sep 24 02:47:06 PM UTC 24
Finished Sep 24 02:47:08 PM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999121864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.999121864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1310904084
Short name T883
Test name
Test status
Simulation time 4471155804 ps
CPU time 19.78 seconds
Started Sep 24 02:47:03 PM UTC 24
Finished Sep 24 02:47:24 PM UTC 24
Peak memory 245400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310904084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1310904084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2796660333
Short name T884
Test name
Test status
Simulation time 1068547636 ps
CPU time 19.82 seconds
Started Sep 24 02:47:04 PM UTC 24
Finished Sep 24 02:47:25 PM UTC 24
Peak memory 245184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796660333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2796660333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1691718197
Short name T875
Test name
Test status
Simulation time 1201561612 ps
CPU time 11.39 seconds
Started Sep 24 02:47:03 PM UTC 24
Finished Sep 24 02:47:16 PM UTC 24
Peak memory 251384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691718197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.1691718197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2020973021
Short name T902
Test name
Test status
Simulation time 14318595481 ps
CPU time 50.93 seconds
Started Sep 24 02:47:02 PM UTC 24
Finished Sep 24 02:47:55 PM UTC 24
Peak memory 245008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020973021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2020973021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4220340871
Short name T873
Test name
Test status
Simulation time 545745355 ps
CPU time 7.04 seconds
Started Sep 24 02:47:07 PM UTC 24
Finished Sep 24 02:47:15 PM UTC 24
Peak memory 231216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220340871 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.4220340871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3103521087
Short name T1006
Test name
Test status
Simulation time 69779885313 ps
CPU time 469.74 seconds
Started Sep 24 02:47:13 PM UTC 24
Finished Sep 24 02:55:09 PM UTC 24
Peak memory 298436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103521087 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.3103521087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.1668882877
Short name T870
Test name
Test status
Simulation time 2620080097 ps
CPU time 10.6 seconds
Started Sep 24 02:47:00 PM UTC 24
Finished Sep 24 02:47:11 PM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668882877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1668882877
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1806514531
Short name T867
Test name
Test status
Simulation time 3714925074 ps
CPU time 6.27 seconds
Started Sep 24 02:46:59 PM UTC 24
Finished Sep 24 02:47:06 PM UTC 24
Peak memory 227496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806514531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1806514531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.1607953174
Short name T865
Test name
Test status
Simulation time 103193380 ps
CPU time 2.75 seconds
Started Sep 24 02:47:01 PM UTC 24
Finished Sep 24 02:47:05 PM UTC 24
Peak memory 227276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607953174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1607953174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3214174778
Short name T863
Test name
Test status
Simulation time 87698197 ps
CPU time 1.22 seconds
Started Sep 24 02:47:01 PM UTC 24
Finished Sep 24 02:47:03 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214174778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3214174778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.877311989
Short name T872
Test name
Test status
Simulation time 3918011383 ps
CPU time 9.06 seconds
Started Sep 24 02:47:04 PM UTC 24
Finished Sep 24 02:47:14 PM UTC 24
Peak memory 234776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877311989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.877311989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.639805508
Short name T890
Test name
Test status
Simulation time 14145928 ps
CPU time 0.93 seconds
Started Sep 24 02:47:32 PM UTC 24
Finished Sep 24 02:47:34 PM UTC 24
Peak memory 213592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639805508 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.639805508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2926581471
Short name T885
Test name
Test status
Simulation time 333056594 ps
CPU time 4.06 seconds
Started Sep 24 02:47:21 PM UTC 24
Finished Sep 24 02:47:27 PM UTC 24
Peak memory 234636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926581471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2926581471
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2184573991
Short name T878
Test name
Test status
Simulation time 15790327 ps
CPU time 1.22 seconds
Started Sep 24 02:47:16 PM UTC 24
Finished Sep 24 02:47:19 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184573991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2184573991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.2668286012
Short name T318
Test name
Test status
Simulation time 7261348839 ps
CPU time 77.07 seconds
Started Sep 24 02:47:26 PM UTC 24
Finished Sep 24 02:48:45 PM UTC 24
Peak memory 265536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668286012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2668286012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2999021140
Short name T307
Test name
Test status
Simulation time 48032789132 ps
CPU time 441.32 seconds
Started Sep 24 02:47:26 PM UTC 24
Finished Sep 24 02:54:54 PM UTC 24
Peak memory 278008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999021140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2999021140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1644868891
Short name T1003
Test name
Test status
Simulation time 406707510852 ps
CPU time 397.29 seconds
Started Sep 24 02:47:28 PM UTC 24
Finished Sep 24 02:54:12 PM UTC 24
Peak memory 265712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644868891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1644868891
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.4201504621
Short name T887
Test name
Test status
Simulation time 300365143 ps
CPU time 7.39 seconds
Started Sep 24 02:47:23 PM UTC 24
Finished Sep 24 02:47:33 PM UTC 24
Peak memory 251124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201504621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4201504621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3017377887
Short name T312
Test name
Test status
Simulation time 91645448817 ps
CPU time 253.75 seconds
Started Sep 24 02:47:23 PM UTC 24
Finished Sep 24 02:51:42 PM UTC 24
Peak memory 261420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017377887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.3017377887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.3818995617
Short name T886
Test name
Test status
Simulation time 2658707735 ps
CPU time 9.78 seconds
Started Sep 24 02:47:19 PM UTC 24
Finished Sep 24 02:47:32 PM UTC 24
Peak memory 245064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818995617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3818995617
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2947909422
Short name T975
Test name
Test status
Simulation time 46216393478 ps
CPU time 123.16 seconds
Started Sep 24 02:47:19 PM UTC 24
Finished Sep 24 02:49:26 PM UTC 24
Peak memory 245180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947909422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2947909422
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2467674524
Short name T379
Test name
Test status
Simulation time 4392512359 ps
CPU time 23.35 seconds
Started Sep 24 02:47:18 PM UTC 24
Finished Sep 24 02:47:44 PM UTC 24
Peak memory 261704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467674524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.2467674524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1113767426
Short name T382
Test name
Test status
Simulation time 4107004564 ps
CPU time 12.07 seconds
Started Sep 24 02:47:17 PM UTC 24
Finished Sep 24 02:47:30 PM UTC 24
Peak memory 235032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113767426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1113767426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3457061783
Short name T894
Test name
Test status
Simulation time 1112895666 ps
CPU time 13.16 seconds
Started Sep 24 02:47:26 PM UTC 24
Finished Sep 24 02:47:41 PM UTC 24
Peak memory 233316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457061783 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.3457061783
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1111747685
Short name T1009
Test name
Test status
Simulation time 82049076937 ps
CPU time 683.02 seconds
Started Sep 24 02:47:31 PM UTC 24
Finished Sep 24 02:59:04 PM UTC 24
Peak memory 280008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111747685 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.1111747685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.3716297285
Short name T899
Test name
Test status
Simulation time 2092912228 ps
CPU time 31.39 seconds
Started Sep 24 02:47:16 PM UTC 24
Finished Sep 24 02:47:49 PM UTC 24
Peak memory 231428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716297285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3716297285
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2473430975
Short name T897
Test name
Test status
Simulation time 18962876235 ps
CPU time 29.58 seconds
Started Sep 24 02:47:16 PM UTC 24
Finished Sep 24 02:47:48 PM UTC 24
Peak memory 227544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473430975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2473430975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1156194635
Short name T880
Test name
Test status
Simulation time 14978156 ps
CPU time 1.42 seconds
Started Sep 24 02:47:17 PM UTC 24
Finished Sep 24 02:47:20 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156194635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1156194635
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.4057412134
Short name T879
Test name
Test status
Simulation time 59177390 ps
CPU time 1.18 seconds
Started Sep 24 02:47:16 PM UTC 24
Finished Sep 24 02:47:19 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057412134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4057412134
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.747048629
Short name T888
Test name
Test status
Simulation time 4822740767 ps
CPU time 10.59 seconds
Started Sep 24 02:47:21 PM UTC 24
Finished Sep 24 02:47:33 PM UTC 24
Peak memory 245016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747048629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.747048629
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3713436731
Short name T906
Test name
Test status
Simulation time 19736935 ps
CPU time 1.18 seconds
Started Sep 24 02:47:56 PM UTC 24
Finished Sep 24 02:47:58 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713436731 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.3713436731
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3330473007
Short name T898
Test name
Test status
Simulation time 225929669 ps
CPU time 3.35 seconds
Started Sep 24 02:47:44 PM UTC 24
Finished Sep 24 02:47:48 PM UTC 24
Peak memory 244924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330473007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3330473007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.2467606404
Short name T891
Test name
Test status
Simulation time 26676001 ps
CPU time 1.24 seconds
Started Sep 24 02:47:34 PM UTC 24
Finished Sep 24 02:47:36 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467606404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2467606404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.756487451
Short name T319
Test name
Test status
Simulation time 60758696582 ps
CPU time 449.17 seconds
Started Sep 24 02:47:50 PM UTC 24
Finished Sep 24 02:55:25 PM UTC 24
Peak memory 265536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756487451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.756487451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1705236725
Short name T989
Test name
Test status
Simulation time 20492462204 ps
CPU time 167.2 seconds
Started Sep 24 02:47:52 PM UTC 24
Finished Sep 24 02:50:42 PM UTC 24
Peak memory 263612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705236725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1705236725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2226651575
Short name T994
Test name
Test status
Simulation time 48429012519 ps
CPU time 222.06 seconds
Started Sep 24 02:47:56 PM UTC 24
Finished Sep 24 02:51:41 PM UTC 24
Peak memory 261628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226651575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.2226651575
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.22744322
Short name T911
Test name
Test status
Simulation time 1561111467 ps
CPU time 16.61 seconds
Started Sep 24 02:47:45 PM UTC 24
Finished Sep 24 02:48:03 PM UTC 24
Peak memory 245248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22744322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.22744322
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.625960494
Short name T955
Test name
Test status
Simulation time 3691879114 ps
CPU time 73.85 seconds
Started Sep 24 02:47:48 PM UTC 24
Finished Sep 24 02:49:04 PM UTC 24
Peak memory 261436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625960494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.625960494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.636820323
Short name T903
Test name
Test status
Simulation time 717670271 ps
CPU time 12.13 seconds
Started Sep 24 02:47:41 PM UTC 24
Finished Sep 24 02:47:55 PM UTC 24
Peak memory 245256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636820323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.636820323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.1681754855
Short name T901
Test name
Test status
Simulation time 1132563172 ps
CPU time 10.4 seconds
Started Sep 24 02:47:42 PM UTC 24
Finished Sep 24 02:47:54 PM UTC 24
Peak memory 244920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681754855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1681754855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2480047255
Short name T900
Test name
Test status
Simulation time 1697599331 ps
CPU time 9.53 seconds
Started Sep 24 02:47:40 PM UTC 24
Finished Sep 24 02:47:51 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480047255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.2480047255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.4284481192
Short name T895
Test name
Test status
Simulation time 965508934 ps
CPU time 3.09 seconds
Started Sep 24 02:47:38 PM UTC 24
Finished Sep 24 02:47:42 PM UTC 24
Peak memory 234080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284481192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4284481192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.665993950
Short name T905
Test name
Test status
Simulation time 293679988 ps
CPU time 6.72 seconds
Started Sep 24 02:47:49 PM UTC 24
Finished Sep 24 02:47:57 PM UTC 24
Peak memory 233524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665993950 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.665993950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1794563182
Short name T907
Test name
Test status
Simulation time 80778357 ps
CPU time 1.5 seconds
Started Sep 24 02:47:56 PM UTC 24
Finished Sep 24 02:47:58 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794563182 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.1794563182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.2277563863
Short name T908
Test name
Test status
Simulation time 1826984204 ps
CPU time 22.71 seconds
Started Sep 24 02:47:35 PM UTC 24
Finished Sep 24 02:47:59 PM UTC 24
Peak memory 231744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277563863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2277563863
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2403829313
Short name T914
Test name
Test status
Simulation time 28802410386 ps
CPU time 32.63 seconds
Started Sep 24 02:47:34 PM UTC 24
Finished Sep 24 02:48:08 PM UTC 24
Peak memory 227504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403829313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2403829313
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.545830007
Short name T893
Test name
Test status
Simulation time 67277613 ps
CPU time 1.45 seconds
Started Sep 24 02:47:37 PM UTC 24
Finished Sep 24 02:47:39 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545830007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.545830007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2326820501
Short name T892
Test name
Test status
Simulation time 12978553 ps
CPU time 1.14 seconds
Started Sep 24 02:47:35 PM UTC 24
Finished Sep 24 02:47:37 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326820501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2326820501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.2417049533
Short name T904
Test name
Test status
Simulation time 353390776 ps
CPU time 10.46 seconds
Started Sep 24 02:47:44 PM UTC 24
Finished Sep 24 02:47:55 PM UTC 24
Peak memory 250576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417049533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2417049533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3517891505
Short name T925
Test name
Test status
Simulation time 14997888 ps
CPU time 1.19 seconds
Started Sep 24 02:48:20 PM UTC 24
Finished Sep 24 02:48:22 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517891505 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3517891505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2904430535
Short name T918
Test name
Test status
Simulation time 113299250 ps
CPU time 3.01 seconds
Started Sep 24 02:48:09 PM UTC 24
Finished Sep 24 02:48:13 PM UTC 24
Peak memory 234636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904430535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2904430535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.2536563584
Short name T909
Test name
Test status
Simulation time 33996887 ps
CPU time 1.14 seconds
Started Sep 24 02:47:57 PM UTC 24
Finished Sep 24 02:47:59 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536563584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2536563584
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2533202482
Short name T949
Test name
Test status
Simulation time 2866485475 ps
CPU time 38.3 seconds
Started Sep 24 02:48:14 PM UTC 24
Finished Sep 24 02:48:53 PM UTC 24
Peak memory 267916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533202482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2533202482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2695888772
Short name T927
Test name
Test status
Simulation time 1192937478 ps
CPU time 9.66 seconds
Started Sep 24 02:48:16 PM UTC 24
Finished Sep 24 02:48:27 PM UTC 24
Peak memory 233716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695888772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2695888772
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.4220296415
Short name T996
Test name
Test status
Simulation time 17188954722 ps
CPU time 213.26 seconds
Started Sep 24 02:48:17 PM UTC 24
Finished Sep 24 02:51:54 PM UTC 24
Peak memory 263612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220296415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.4220296415
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.1580589588
Short name T939
Test name
Test status
Simulation time 9093030286 ps
CPU time 32.99 seconds
Started Sep 24 02:48:10 PM UTC 24
Finished Sep 24 02:48:44 PM UTC 24
Peak memory 245000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580589588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1580589588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2913259244
Short name T332
Test name
Test status
Simulation time 28109947250 ps
CPU time 230.2 seconds
Started Sep 24 02:48:11 PM UTC 24
Finished Sep 24 02:52:05 PM UTC 24
Peak memory 261692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913259244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.2913259244
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.3510680582
Short name T930
Test name
Test status
Simulation time 6861084697 ps
CPU time 23.47 seconds
Started Sep 24 02:48:04 PM UTC 24
Finished Sep 24 02:48:28 PM UTC 24
Peak memory 245060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510680582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3510680582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2255965325
Short name T920
Test name
Test status
Simulation time 1334115114 ps
CPU time 10.51 seconds
Started Sep 24 02:48:04 PM UTC 24
Finished Sep 24 02:48:15 PM UTC 24
Peak memory 245244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255965325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2255965325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3011958330
Short name T917
Test name
Test status
Simulation time 4429525699 ps
CPU time 7.16 seconds
Started Sep 24 02:48:02 PM UTC 24
Finished Sep 24 02:48:11 PM UTC 24
Peak memory 235056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011958330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.3011958330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3214639218
Short name T953
Test name
Test status
Simulation time 11327361393 ps
CPU time 56.1 seconds
Started Sep 24 02:48:00 PM UTC 24
Finished Sep 24 02:48:58 PM UTC 24
Peak memory 249468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214639218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3214639218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3102831288
Short name T921
Test name
Test status
Simulation time 306994859 ps
CPU time 4.9 seconds
Started Sep 24 02:48:11 PM UTC 24
Finished Sep 24 02:48:17 PM UTC 24
Peak memory 233316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102831288 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.3102831288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1374660048
Short name T960
Test name
Test status
Simulation time 2941580383 ps
CPU time 49.01 seconds
Started Sep 24 02:48:18 PM UTC 24
Finished Sep 24 02:49:09 PM UTC 24
Peak memory 263608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374660048 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.1374660048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.4208501716
Short name T935
Test name
Test status
Simulation time 4059413684 ps
CPU time 35.6 seconds
Started Sep 24 02:47:59 PM UTC 24
Finished Sep 24 02:48:37 PM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208501716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4208501716
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1144785249
Short name T913
Test name
Test status
Simulation time 983660218 ps
CPU time 4.49 seconds
Started Sep 24 02:47:58 PM UTC 24
Finished Sep 24 02:48:03 PM UTC 24
Peak memory 227316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144785249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1144785249
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3060725132
Short name T912
Test name
Test status
Simulation time 19379889 ps
CPU time 1.2 seconds
Started Sep 24 02:48:00 PM UTC 24
Finished Sep 24 02:48:03 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060725132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3060725132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2214101812
Short name T910
Test name
Test status
Simulation time 437415526 ps
CPU time 1.5 seconds
Started Sep 24 02:47:59 PM UTC 24
Finished Sep 24 02:48:02 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214101812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2214101812
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.2674365020
Short name T923
Test name
Test status
Simulation time 3012240710 ps
CPU time 13.93 seconds
Started Sep 24 02:48:05 PM UTC 24
Finished Sep 24 02:48:20 PM UTC 24
Peak memory 234880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674365020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2674365020
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.813778770
Short name T943
Test name
Test status
Simulation time 47554595 ps
CPU time 1.19 seconds
Started Sep 24 02:48:48 PM UTC 24
Finished Sep 24 02:48:50 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813778770 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.813778770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1303795616
Short name T934
Test name
Test status
Simulation time 120977766 ps
CPU time 4.38 seconds
Started Sep 24 02:48:30 PM UTC 24
Finished Sep 24 02:48:35 PM UTC 24
Peak memory 245072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303795616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1303795616
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2817174674
Short name T926
Test name
Test status
Simulation time 35036685 ps
CPU time 1.24 seconds
Started Sep 24 02:48:23 PM UTC 24
Finished Sep 24 02:48:25 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817174674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2817174674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.2503565925
Short name T984
Test name
Test status
Simulation time 10647489450 ps
CPU time 80.88 seconds
Started Sep 24 02:48:38 PM UTC 24
Finished Sep 24 02:50:01 PM UTC 24
Peak memory 265864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503565925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2503565925
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3169402757
Short name T990
Test name
Test status
Simulation time 5652417064 ps
CPU time 115.9 seconds
Started Sep 24 02:48:45 PM UTC 24
Finished Sep 24 02:50:43 PM UTC 24
Peak memory 251336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169402757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3169402757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1239833811
Short name T1008
Test name
Test status
Simulation time 1135238765251 ps
CPU time 580.49 seconds
Started Sep 24 02:48:45 PM UTC 24
Finished Sep 24 02:58:33 PM UTC 24
Peak memory 263868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239833811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.1239833811
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.2599322519
Short name T942
Test name
Test status
Simulation time 1126163100 ps
CPU time 12.75 seconds
Started Sep 24 02:48:32 PM UTC 24
Finished Sep 24 02:48:46 PM UTC 24
Peak memory 251076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599322519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2599322519
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1910607649
Short name T995
Test name
Test status
Simulation time 78313385149 ps
CPU time 188.17 seconds
Started Sep 24 02:48:36 PM UTC 24
Finished Sep 24 02:51:48 PM UTC 24
Peak memory 267824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910607649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.1910607649
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3494101279
Short name T940
Test name
Test status
Simulation time 567407509 ps
CPU time 13.65 seconds
Started Sep 24 02:48:30 PM UTC 24
Finished Sep 24 02:48:45 PM UTC 24
Peak memory 235016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494101279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3494101279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.3597252300
Short name T965
Test name
Test status
Simulation time 9614218426 ps
CPU time 41.2 seconds
Started Sep 24 02:48:30 PM UTC 24
Finished Sep 24 02:49:12 PM UTC 24
Peak memory 251196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597252300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3597252300
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1622769498
Short name T938
Test name
Test status
Simulation time 1123164177 ps
CPU time 11.8 seconds
Started Sep 24 02:48:30 PM UTC 24
Finished Sep 24 02:48:43 PM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622769498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.1622769498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.694636279
Short name T932
Test name
Test status
Simulation time 111053703 ps
CPU time 3.26 seconds
Started Sep 24 02:48:27 PM UTC 24
Finished Sep 24 02:48:31 PM UTC 24
Peak memory 234420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694636279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.694636279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.4064103520
Short name T937
Test name
Test status
Simulation time 294492232 ps
CPU time 5.29 seconds
Started Sep 24 02:48:36 PM UTC 24
Finished Sep 24 02:48:43 PM UTC 24
Peak memory 231164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064103520 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.4064103520
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.3346111279
Short name T993
Test name
Test status
Simulation time 11925728577 ps
CPU time 154.75 seconds
Started Sep 24 02:48:45 PM UTC 24
Finished Sep 24 02:51:23 PM UTC 24
Peak memory 263620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346111279 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.3346111279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.12038007
Short name T948
Test name
Test status
Simulation time 3315013609 ps
CPU time 26.43 seconds
Started Sep 24 02:48:25 PM UTC 24
Finished Sep 24 02:48:52 PM UTC 24
Peak memory 227464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12038007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.12038007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.3832473523
Short name T946
Test name
Test status
Simulation time 22735048120 ps
CPU time 25.82 seconds
Started Sep 24 02:48:23 PM UTC 24
Finished Sep 24 02:48:50 PM UTC 24
Peak memory 229816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832473523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3832473523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.2891845252
Short name T931
Test name
Test status
Simulation time 143243598 ps
CPU time 3.2 seconds
Started Sep 24 02:48:25 PM UTC 24
Finished Sep 24 02:48:29 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891845252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2891845252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.4144672203
Short name T929
Test name
Test status
Simulation time 68995974 ps
CPU time 1.31 seconds
Started Sep 24 02:48:25 PM UTC 24
Finished Sep 24 02:48:27 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144672203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4144672203
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.4162395174
Short name T933
Test name
Test status
Simulation time 56305090 ps
CPU time 3.49 seconds
Started Sep 24 02:48:30 PM UTC 24
Finished Sep 24 02:48:34 PM UTC 24
Peak memory 244656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162395174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4162395174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.295085897
Short name T961
Test name
Test status
Simulation time 13864326 ps
CPU time 1.24 seconds
Started Sep 24 02:49:07 PM UTC 24
Finished Sep 24 02:49:09 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295085897 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.295085897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2788065094
Short name T957
Test name
Test status
Simulation time 1621839768 ps
CPU time 9.09 seconds
Started Sep 24 02:48:55 PM UTC 24
Finished Sep 24 02:49:05 PM UTC 24
Peak memory 234752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788065094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2788065094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.2843861545
Short name T945
Test name
Test status
Simulation time 22205935 ps
CPU time 1.3 seconds
Started Sep 24 02:48:48 PM UTC 24
Finished Sep 24 02:48:50 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843861545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2843861545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.3728498537
Short name T980
Test name
Test status
Simulation time 3443698301 ps
CPU time 56.68 seconds
Started Sep 24 02:48:58 PM UTC 24
Finished Sep 24 02:49:56 PM UTC 24
Peak memory 261452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728498537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3728498537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2982749643
Short name T40
Test name
Test status
Simulation time 22014885955 ps
CPU time 111.89 seconds
Started Sep 24 02:49:00 PM UTC 24
Finished Sep 24 02:50:54 PM UTC 24
Peak memory 261632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982749643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2982749643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3382531071
Short name T978
Test name
Test status
Simulation time 6475046020 ps
CPU time 36.16 seconds
Started Sep 24 02:49:04 PM UTC 24
Finished Sep 24 02:49:42 PM UTC 24
Peak memory 251328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382531071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.3382531071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.769772258
Short name T343
Test name
Test status
Simulation time 1088297732 ps
CPU time 26.95 seconds
Started Sep 24 02:48:55 PM UTC 24
Finished Sep 24 02:49:24 PM UTC 24
Peak memory 267444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769772258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.769772258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1971144993
Short name T956
Test name
Test status
Simulation time 1259927152 ps
CPU time 10.91 seconds
Started Sep 24 02:48:52 PM UTC 24
Finished Sep 24 02:49:05 PM UTC 24
Peak memory 241988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971144993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1971144993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1121598275
Short name T964
Test name
Test status
Simulation time 2904814910 ps
CPU time 18.15 seconds
Started Sep 24 02:48:53 PM UTC 24
Finished Sep 24 02:49:12 PM UTC 24
Peak memory 245052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121598275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1121598275
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2146158174
Short name T969
Test name
Test status
Simulation time 69441390507 ps
CPU time 22.72 seconds
Started Sep 24 02:48:52 PM UTC 24
Finished Sep 24 02:49:17 PM UTC 24
Peak memory 245264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146158174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2146158174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.1982577629
Short name T954
Test name
Test status
Simulation time 245282104 ps
CPU time 8.93 seconds
Started Sep 24 02:48:52 PM UTC 24
Finished Sep 24 02:49:02 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982577629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1982577629
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1707563549
Short name T968
Test name
Test status
Simulation time 1439091408 ps
CPU time 15.37 seconds
Started Sep 24 02:48:58 PM UTC 24
Finished Sep 24 02:49:14 PM UTC 24
Peak memory 231420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707563549 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.1707563549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.4223241037
Short name T340
Test name
Test status
Simulation time 1906672877 ps
CPU time 45.59 seconds
Started Sep 24 02:49:04 PM UTC 24
Finished Sep 24 02:49:51 PM UTC 24
Peak memory 251264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223241037 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.4223241037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.2391054756
Short name T944
Test name
Test status
Simulation time 33643320 ps
CPU time 1.18 seconds
Started Sep 24 02:48:48 PM UTC 24
Finished Sep 24 02:48:50 PM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391054756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2391054756
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3703918913
Short name T952
Test name
Test status
Simulation time 1723582602 ps
CPU time 7.67 seconds
Started Sep 24 02:48:48 PM UTC 24
Finished Sep 24 02:48:56 PM UTC 24
Peak memory 227396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703918913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3703918913
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.2761397989
Short name T951
Test name
Test status
Simulation time 75643607 ps
CPU time 2.23 seconds
Started Sep 24 02:48:52 PM UTC 24
Finished Sep 24 02:48:56 PM UTC 24
Peak memory 227444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761397989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2761397989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2457287676
Short name T947
Test name
Test status
Simulation time 48082715 ps
CPU time 1.43 seconds
Started Sep 24 02:48:48 PM UTC 24
Finished Sep 24 02:48:51 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457287676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2457287676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3159468036
Short name T958
Test name
Test status
Simulation time 4415307269 ps
CPU time 9.75 seconds
Started Sep 24 02:48:55 PM UTC 24
Finished Sep 24 02:49:06 PM UTC 24
Peak memory 235136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159468036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3159468036
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.3597889345
Short name T976
Test name
Test status
Simulation time 13929398 ps
CPU time 1.17 seconds
Started Sep 24 02:49:25 PM UTC 24
Finished Sep 24 02:49:28 PM UTC 24
Peak memory 213588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597889345 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.3597889345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1976164719
Short name T973
Test name
Test status
Simulation time 2417549254 ps
CPU time 6.76 seconds
Started Sep 24 02:49:15 PM UTC 24
Finished Sep 24 02:49:23 PM UTC 24
Peak memory 234768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976164719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1976164719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3065643027
Short name T963
Test name
Test status
Simulation time 80058587 ps
CPU time 1.33 seconds
Started Sep 24 02:49:07 PM UTC 24
Finished Sep 24 02:49:09 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065643027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3065643027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.3440409475
Short name T1002
Test name
Test status
Simulation time 107212947039 ps
CPU time 264.3 seconds
Started Sep 24 02:49:20 PM UTC 24
Finished Sep 24 02:53:49 PM UTC 24
Peak memory 278148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440409475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3440409475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.353102782
Short name T985
Test name
Test status
Simulation time 50105055954 ps
CPU time 39.17 seconds
Started Sep 24 02:49:21 PM UTC 24
Finished Sep 24 02:50:02 PM UTC 24
Peak memory 234892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353102782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.353102782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3739586777
Short name T1004
Test name
Test status
Simulation time 191074018008 ps
CPU time 292.21 seconds
Started Sep 24 02:49:21 PM UTC 24
Finished Sep 24 02:54:18 PM UTC 24
Peak memory 261576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739586777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.3739586777
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.270148359
Short name T972
Test name
Test status
Simulation time 89116580 ps
CPU time 3.98 seconds
Started Sep 24 02:49:15 PM UTC 24
Finished Sep 24 02:49:21 PM UTC 24
Peak memory 234636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270148359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.270148359
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3122924096
Short name T997
Test name
Test status
Simulation time 27379310204 ps
CPU time 168.86 seconds
Started Sep 24 02:49:18 PM UTC 24
Finished Sep 24 02:52:10 PM UTC 24
Peak memory 261692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122924096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.3122924096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.4262448834
Short name T971
Test name
Test status
Simulation time 171659641 ps
CPU time 4.78 seconds
Started Sep 24 02:49:13 PM UTC 24
Finished Sep 24 02:49:19 PM UTC 24
Peak memory 234652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262448834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4262448834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2434138005
Short name T982
Test name
Test status
Simulation time 33579424294 ps
CPU time 43.6 seconds
Started Sep 24 02:49:15 PM UTC 24
Finished Sep 24 02:50:00 PM UTC 24
Peak memory 245008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434138005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2434138005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.310588174
Short name T413
Test name
Test status
Simulation time 697459613 ps
CPU time 15.07 seconds
Started Sep 24 02:49:12 PM UTC 24
Finished Sep 24 02:49:28 PM UTC 24
Peak memory 234896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310588174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.310588174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3142139736
Short name T983
Test name
Test status
Simulation time 34552921678 ps
CPU time 47.61 seconds
Started Sep 24 02:49:11 PM UTC 24
Finished Sep 24 02:50:01 PM UTC 24
Peak memory 251192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142139736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3142139736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.3027116545
Short name T974
Test name
Test status
Simulation time 323622974 ps
CPU time 6.24 seconds
Started Sep 24 02:49:18 PM UTC 24
Finished Sep 24 02:49:25 PM UTC 24
Peak memory 233352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027116545 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.3027116545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.4222471256
Short name T1007
Test name
Test status
Simulation time 140374930653 ps
CPU time 406.83 seconds
Started Sep 24 02:49:25 PM UTC 24
Finished Sep 24 02:56:19 PM UTC 24
Peak memory 263864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222471256 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.4222471256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.111533503
Short name T986
Test name
Test status
Simulation time 42166393199 ps
CPU time 67.76 seconds
Started Sep 24 02:49:07 PM UTC 24
Finished Sep 24 02:50:16 PM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111533503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.111533503
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1990483055
Short name T962
Test name
Test status
Simulation time 43016479 ps
CPU time 1.2 seconds
Started Sep 24 02:49:07 PM UTC 24
Finished Sep 24 02:49:09 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990483055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1990483055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.708855160
Short name T967
Test name
Test status
Simulation time 29464540 ps
CPU time 1.24 seconds
Started Sep 24 02:49:11 PM UTC 24
Finished Sep 24 02:49:14 PM UTC 24
Peak memory 215680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708855160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.708855160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2715596291
Short name T966
Test name
Test status
Simulation time 88969467 ps
CPU time 1.18 seconds
Started Sep 24 02:49:11 PM UTC 24
Finished Sep 24 02:49:14 PM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715596291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2715596291
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1335140486
Short name T977
Test name
Test status
Simulation time 5247704608 ps
CPU time 21.01 seconds
Started Sep 24 02:49:15 PM UTC 24
Finished Sep 24 02:49:38 PM UTC 24
Peak memory 251412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335140486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1335140486
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.449411336
Short name T450
Test name
Test status
Simulation time 13285566 ps
CPU time 1.22 seconds
Started Sep 24 02:37:41 PM UTC 24
Finished Sep 24 02:37:43 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449411336 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.449411336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2455633343
Short name T129
Test name
Test status
Simulation time 2302700930 ps
CPU time 25.36 seconds
Started Sep 24 02:37:37 PM UTC 24
Finished Sep 24 02:38:04 PM UTC 24
Peak memory 245056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455633343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2455633343
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.342899598
Short name T2
Test name
Test status
Simulation time 36820056 ps
CPU time 1.24 seconds
Started Sep 24 02:37:31 PM UTC 24
Finished Sep 24 02:37:33 PM UTC 24
Peak memory 214640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342899598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.342899598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.3009876028
Short name T67
Test name
Test status
Simulation time 11217852796 ps
CPU time 73.56 seconds
Started Sep 24 02:37:40 PM UTC 24
Finished Sep 24 02:38:55 PM UTC 24
Peak memory 251272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009876028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3009876028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2656920895
Short name T179
Test name
Test status
Simulation time 48581536793 ps
CPU time 288.34 seconds
Started Sep 24 02:37:40 PM UTC 24
Finished Sep 24 02:42:33 PM UTC 24
Peak memory 267776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656920895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2656920895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.1789071166
Short name T76
Test name
Test status
Simulation time 466122350 ps
CPU time 4.03 seconds
Started Sep 24 02:37:38 PM UTC 24
Finished Sep 24 02:37:43 PM UTC 24
Peak memory 234676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789071166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1789071166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2476948851
Short name T95
Test name
Test status
Simulation time 14297042212 ps
CPU time 30.02 seconds
Started Sep 24 02:37:38 PM UTC 24
Finished Sep 24 02:38:10 PM UTC 24
Peak memory 234816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476948851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.2476948851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.2321173563
Short name T231
Test name
Test status
Simulation time 1380613370 ps
CPU time 16.18 seconds
Started Sep 24 02:37:35 PM UTC 24
Finished Sep 24 02:37:52 PM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321173563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2321173563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.3363721157
Short name T74
Test name
Test status
Simulation time 773666024 ps
CPU time 4.85 seconds
Started Sep 24 02:37:35 PM UTC 24
Finished Sep 24 02:37:41 PM UTC 24
Peak memory 234880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363721157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3363721157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.609160767
Short name T135
Test name
Test status
Simulation time 7842267854 ps
CPU time 16.19 seconds
Started Sep 24 02:37:34 PM UTC 24
Finished Sep 24 02:37:52 PM UTC 24
Peak memory 234736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609160767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.609160767
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2913134480
Short name T190
Test name
Test status
Simulation time 3721888002 ps
CPU time 18.48 seconds
Started Sep 24 02:37:40 PM UTC 24
Finished Sep 24 02:38:00 PM UTC 24
Peak memory 231300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913134480 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.2913134480
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.4074051662
Short name T125
Test name
Test status
Simulation time 4665412628 ps
CPU time 27.7 seconds
Started Sep 24 02:37:33 PM UTC 24
Finished Sep 24 02:38:02 PM UTC 24
Peak memory 227564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074051662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4074051662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.480012005
Short name T73
Test name
Test status
Simulation time 4514480541 ps
CPU time 6.44 seconds
Started Sep 24 02:37:32 PM UTC 24
Finished Sep 24 02:37:40 PM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480012005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.480012005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2753416592
Short name T71
Test name
Test status
Simulation time 1598060530 ps
CPU time 3.24 seconds
Started Sep 24 02:37:34 PM UTC 24
Finished Sep 24 02:37:39 PM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753416592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2753416592
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2474577664
Short name T128
Test name
Test status
Simulation time 370898823 ps
CPU time 1.39 seconds
Started Sep 24 02:37:33 PM UTC 24
Finished Sep 24 02:37:36 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474577664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2474577664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.228324179
Short name T75
Test name
Test status
Simulation time 466747679 ps
CPU time 4.93 seconds
Started Sep 24 02:37:37 PM UTC 24
Finished Sep 24 02:37:43 PM UTC 24
Peak memory 234704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228324179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.228324179
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.3184420497
Short name T210
Test name
Test status
Simulation time 15288236 ps
CPU time 1.24 seconds
Started Sep 24 02:37:59 PM UTC 24
Finished Sep 24 02:38:01 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184420497 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3184420497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1930478101
Short name T259
Test name
Test status
Simulation time 92745801 ps
CPU time 5.27 seconds
Started Sep 24 02:37:50 PM UTC 24
Finished Sep 24 02:37:56 PM UTC 24
Peak memory 245188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930478101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1930478101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3909031938
Short name T451
Test name
Test status
Simulation time 24548154 ps
CPU time 1.38 seconds
Started Sep 24 02:37:41 PM UTC 24
Finished Sep 24 02:37:44 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909031938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3909031938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3587319587
Short name T455
Test name
Test status
Simulation time 19561607 ps
CPU time 1.22 seconds
Started Sep 24 02:37:56 PM UTC 24
Finished Sep 24 02:37:58 PM UTC 24
Peak memory 226808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587319587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3587319587
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.738678810
Short name T246
Test name
Test status
Simulation time 87825311099 ps
CPU time 190.69 seconds
Started Sep 24 02:37:56 PM UTC 24
Finished Sep 24 02:41:10 PM UTC 24
Peak memory 275772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738678810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.738678810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1999465582
Short name T458
Test name
Test status
Simulation time 2598905934 ps
CPU time 20.4 seconds
Started Sep 24 02:37:50 PM UTC 24
Finished Sep 24 02:38:11 PM UTC 24
Peak memory 251256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999465582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1999465582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2856024230
Short name T314
Test name
Test status
Simulation time 25890177653 ps
CPU time 224.58 seconds
Started Sep 24 02:37:53 PM UTC 24
Finished Sep 24 02:41:41 PM UTC 24
Peak memory 263536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856024230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.2856024230
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.2469997043
Short name T229
Test name
Test status
Simulation time 463980403 ps
CPU time 17.6 seconds
Started Sep 24 02:37:48 PM UTC 24
Finished Sep 24 02:38:07 PM UTC 24
Peak memory 249288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469997043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2469997043
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1920302888
Short name T242
Test name
Test status
Simulation time 13977525220 ps
CPU time 20.67 seconds
Started Sep 24 02:37:47 PM UTC 24
Finished Sep 24 02:38:09 PM UTC 24
Peak memory 234808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920302888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1920302888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.110944941
Short name T228
Test name
Test status
Simulation time 691500537 ps
CPU time 7.13 seconds
Started Sep 24 02:37:47 PM UTC 24
Finished Sep 24 02:37:55 PM UTC 24
Peak memory 234888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110944941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.110944941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1909282902
Short name T191
Test name
Test status
Simulation time 991409183 ps
CPU time 8.11 seconds
Started Sep 24 02:37:53 PM UTC 24
Finished Sep 24 02:38:02 PM UTC 24
Peak memory 231428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909282902 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.1909282902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.715571498
Short name T35
Test name
Test status
Simulation time 49024104 ps
CPU time 1.53 seconds
Started Sep 24 02:37:57 PM UTC 24
Finished Sep 24 02:38:00 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715571498 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.715571498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.574919760
Short name T438
Test name
Test status
Simulation time 1580063684 ps
CPU time 20.84 seconds
Started Sep 24 02:37:45 PM UTC 24
Finished Sep 24 02:38:07 PM UTC 24
Peak memory 227444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574919760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.574919760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.896354728
Short name T453
Test name
Test status
Simulation time 31956030 ps
CPU time 1.17 seconds
Started Sep 24 02:37:45 PM UTC 24
Finished Sep 24 02:37:47 PM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896354728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.896354728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.4127745873
Short name T436
Test name
Test status
Simulation time 1045162281 ps
CPU time 3.09 seconds
Started Sep 24 02:37:45 PM UTC 24
Finished Sep 24 02:37:49 PM UTC 24
Peak memory 227592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127745873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.4127745873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3836634764
Short name T454
Test name
Test status
Simulation time 29431080 ps
CPU time 1.24 seconds
Started Sep 24 02:37:45 PM UTC 24
Finished Sep 24 02:37:47 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836634764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3836634764
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2700704779
Short name T460
Test name
Test status
Simulation time 36603847 ps
CPU time 1.2 seconds
Started Sep 24 02:38:11 PM UTC 24
Finished Sep 24 02:38:13 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700704779 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2700704779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3885686442
Short name T457
Test name
Test status
Simulation time 27441358 ps
CPU time 3.12 seconds
Started Sep 24 02:38:05 PM UTC 24
Finished Sep 24 02:38:09 PM UTC 24
Peak memory 234308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885686442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3885686442
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2896595699
Short name T211
Test name
Test status
Simulation time 17616266 ps
CPU time 1.3 seconds
Started Sep 24 02:37:59 PM UTC 24
Finished Sep 24 02:38:01 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896595699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2896595699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.697536759
Short name T94
Test name
Test status
Simulation time 6234269106 ps
CPU time 33.98 seconds
Started Sep 24 02:38:08 PM UTC 24
Finished Sep 24 02:38:44 PM UTC 24
Peak memory 234856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697536759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.697536759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3898619360
Short name T98
Test name
Test status
Simulation time 5750608194 ps
CPU time 47.64 seconds
Started Sep 24 02:38:08 PM UTC 24
Finished Sep 24 02:38:58 PM UTC 24
Peak memory 261576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898619360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3898619360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.159884727
Short name T192
Test name
Test status
Simulation time 66457831 ps
CPU time 5.42 seconds
Started Sep 24 02:38:06 PM UTC 24
Finished Sep 24 02:38:12 PM UTC 24
Peak memory 245248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159884727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.159884727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.51121206
Short name T138
Test name
Test status
Simulation time 3828427866 ps
CPU time 51.52 seconds
Started Sep 24 02:38:06 PM UTC 24
Finished Sep 24 02:38:59 PM UTC 24
Peak memory 261440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51121206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.51121206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.1889586251
Short name T142
Test name
Test status
Simulation time 1472413105 ps
CPU time 18.26 seconds
Started Sep 24 02:38:04 PM UTC 24
Finished Sep 24 02:38:23 PM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889586251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1889586251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.975082509
Short name T255
Test name
Test status
Simulation time 416806029 ps
CPU time 9.94 seconds
Started Sep 24 02:38:04 PM UTC 24
Finished Sep 24 02:38:15 PM UTC 24
Peak memory 246980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975082509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.975082509
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1009472960
Short name T230
Test name
Test status
Simulation time 247414085 ps
CPU time 4.4 seconds
Started Sep 24 02:38:04 PM UTC 24
Finished Sep 24 02:38:09 PM UTC 24
Peak memory 235020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009472960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.1009472960
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3161741761
Short name T395
Test name
Test status
Simulation time 8026506283 ps
CPU time 14.76 seconds
Started Sep 24 02:38:02 PM UTC 24
Finished Sep 24 02:38:18 PM UTC 24
Peak memory 245068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161741761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3161741761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.336196856
Short name T459
Test name
Test status
Simulation time 116834106 ps
CPU time 5.31 seconds
Started Sep 24 02:38:06 PM UTC 24
Finished Sep 24 02:38:12 PM UTC 24
Peak memory 231432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336196856 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.336196856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.2986058248
Short name T365
Test name
Test status
Simulation time 132759472856 ps
CPU time 321.29 seconds
Started Sep 24 02:38:09 PM UTC 24
Finished Sep 24 02:43:36 PM UTC 24
Peak memory 265708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986058248 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.2986058248
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.436938268
Short name T212
Test name
Test status
Simulation time 14089655 ps
CPU time 1.11 seconds
Started Sep 24 02:38:02 PM UTC 24
Finished Sep 24 02:38:04 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436938268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.436938268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3376859521
Short name T456
Test name
Test status
Simulation time 707274283 ps
CPU time 6.78 seconds
Started Sep 24 02:38:01 PM UTC 24
Finished Sep 24 02:38:09 PM UTC 24
Peak memory 227360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376859521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3376859521
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.3985340888
Short name T214
Test name
Test status
Simulation time 11907694 ps
CPU time 1.17 seconds
Started Sep 24 02:38:02 PM UTC 24
Finished Sep 24 02:38:05 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985340888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3985340888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3240624744
Short name T213
Test name
Test status
Simulation time 27525711 ps
CPU time 1.21 seconds
Started Sep 24 02:38:02 PM UTC 24
Finished Sep 24 02:38:05 PM UTC 24
Peak memory 215828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240624744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3240624744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.949977477
Short name T109
Test name
Test status
Simulation time 1692790635 ps
CPU time 11.27 seconds
Started Sep 24 02:38:05 PM UTC 24
Finished Sep 24 02:38:17 PM UTC 24
Peak memory 244992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949977477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.949977477
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.353126718
Short name T467
Test name
Test status
Simulation time 99808802 ps
CPU time 1.26 seconds
Started Sep 24 02:38:27 PM UTC 24
Finished Sep 24 02:38:30 PM UTC 24
Peak memory 213592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353126718 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.353126718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1000192062
Short name T263
Test name
Test status
Simulation time 7894637053 ps
CPU time 10.61 seconds
Started Sep 24 02:38:20 PM UTC 24
Finished Sep 24 02:38:32 PM UTC 24
Peak memory 245248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000192062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1000192062
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1542305091
Short name T461
Test name
Test status
Simulation time 20990470 ps
CPU time 1.32 seconds
Started Sep 24 02:38:11 PM UTC 24
Finished Sep 24 02:38:13 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542305091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1542305091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.2284140946
Short name T465
Test name
Test status
Simulation time 35988095 ps
CPU time 1.37 seconds
Started Sep 24 02:38:24 PM UTC 24
Finished Sep 24 02:38:26 PM UTC 24
Peak memory 226812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284140946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2284140946
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2678069633
Short name T39
Test name
Test status
Simulation time 139238587341 ps
CPU time 214.95 seconds
Started Sep 24 02:38:24 PM UTC 24
Finished Sep 24 02:42:02 PM UTC 24
Peak memory 265932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678069633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2678069633
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2367379102
Short name T227
Test name
Test status
Simulation time 3074572990 ps
CPU time 49.82 seconds
Started Sep 24 02:38:25 PM UTC 24
Finished Sep 24 02:39:17 PM UTC 24
Peak memory 234892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367379102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.2367379102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.1001661709
Short name T375
Test name
Test status
Simulation time 110253496 ps
CPU time 3.21 seconds
Started Sep 24 02:38:20 PM UTC 24
Finished Sep 24 02:38:25 PM UTC 24
Peak memory 234684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001661709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1001661709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2963745457
Short name T368
Test name
Test status
Simulation time 17517707183 ps
CPU time 82.73 seconds
Started Sep 24 02:38:21 PM UTC 24
Finished Sep 24 02:39:46 PM UTC 24
Peak memory 251200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963745457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.2963745457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.3786693971
Short name T244
Test name
Test status
Simulation time 3492627991 ps
CPU time 12.84 seconds
Started Sep 24 02:38:15 PM UTC 24
Finished Sep 24 02:38:30 PM UTC 24
Peak memory 231764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786693971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3786693971
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.543174166
Short name T148
Test name
Test status
Simulation time 1983873728 ps
CPU time 26.81 seconds
Started Sep 24 02:38:16 PM UTC 24
Finished Sep 24 02:38:45 PM UTC 24
Peak memory 244888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543174166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.543174166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3503164235
Short name T65
Test name
Test status
Simulation time 6886354388 ps
CPU time 12.3 seconds
Started Sep 24 02:38:14 PM UTC 24
Finished Sep 24 02:38:28 PM UTC 24
Peak memory 235060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503164235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.3503164235
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.4140288550
Short name T256
Test name
Test status
Simulation time 3007081816 ps
CPU time 10.66 seconds
Started Sep 24 02:38:14 PM UTC 24
Finished Sep 24 02:38:26 PM UTC 24
Peak memory 234764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140288550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4140288550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1237366221
Short name T468
Test name
Test status
Simulation time 316094565 ps
CPU time 6.55 seconds
Started Sep 24 02:38:24 PM UTC 24
Finished Sep 24 02:38:32 PM UTC 24
Peak memory 229124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237366221 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.1237366221
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.3424810396
Short name T37
Test name
Test status
Simulation time 2456345204 ps
CPU time 7.14 seconds
Started Sep 24 02:38:25 PM UTC 24
Finished Sep 24 02:38:33 PM UTC 24
Peak memory 234872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424810396 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.3424810396
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2460296855
Short name T435
Test name
Test status
Simulation time 685852441 ps
CPU time 8.49 seconds
Started Sep 24 02:38:13 PM UTC 24
Finished Sep 24 02:38:23 PM UTC 24
Peak memory 227368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460296855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2460296855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2372702696
Short name T464
Test name
Test status
Simulation time 16825524585 ps
CPU time 10.87 seconds
Started Sep 24 02:38:12 PM UTC 24
Finished Sep 24 02:38:24 PM UTC 24
Peak memory 227468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372702696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2372702696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2266333683
Short name T463
Test name
Test status
Simulation time 123214651 ps
CPU time 3.12 seconds
Started Sep 24 02:38:14 PM UTC 24
Finished Sep 24 02:38:18 PM UTC 24
Peak memory 227592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266333683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2266333683
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.1175811038
Short name T462
Test name
Test status
Simulation time 89696214 ps
CPU time 1.59 seconds
Started Sep 24 02:38:13 PM UTC 24
Finished Sep 24 02:38:16 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175811038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1175811038
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.3233463969
Short name T239
Test name
Test status
Simulation time 144297614 ps
CPU time 3.5 seconds
Started Sep 24 02:38:18 PM UTC 24
Finished Sep 24 02:38:23 PM UTC 24
Peak memory 234752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233463969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3233463969
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3321761975
Short name T474
Test name
Test status
Simulation time 22535977 ps
CPU time 1.21 seconds
Started Sep 24 02:38:48 PM UTC 24
Finished Sep 24 02:38:50 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321761975 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3321761975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.924278226
Short name T452
Test name
Test status
Simulation time 307973221 ps
CPU time 3.63 seconds
Started Sep 24 02:38:38 PM UTC 24
Finished Sep 24 02:38:43 PM UTC 24
Peak memory 244560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924278226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.924278226
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.662119057
Short name T466
Test name
Test status
Simulation time 15226022 ps
CPU time 1.25 seconds
Started Sep 24 02:38:27 PM UTC 24
Finished Sep 24 02:38:30 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662119057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.662119057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.896714483
Short name T114
Test name
Test status
Simulation time 35759291037 ps
CPU time 105.67 seconds
Started Sep 24 02:38:43 PM UTC 24
Finished Sep 24 02:40:32 PM UTC 24
Peak memory 261464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896714483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.896714483
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2215499729
Short name T367
Test name
Test status
Simulation time 5070756700 ps
CPU time 87.15 seconds
Started Sep 24 02:38:45 PM UTC 24
Finished Sep 24 02:40:14 PM UTC 24
Peak memory 261580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215499729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2215499729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1630760399
Short name T221
Test name
Test status
Simulation time 10749823708 ps
CPU time 55.25 seconds
Started Sep 24 02:38:46 PM UTC 24
Finished Sep 24 02:39:43 PM UTC 24
Peak memory 263616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630760399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.1630760399
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.1549098601
Short name T416
Test name
Test status
Simulation time 91820187 ps
CPU time 7.55 seconds
Started Sep 24 02:38:38 PM UTC 24
Finished Sep 24 02:38:47 PM UTC 24
Peak memory 245188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549098601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1549098601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2111562734
Short name T131
Test name
Test status
Simulation time 1116944193 ps
CPU time 45.83 seconds
Started Sep 24 02:38:41 PM UTC 24
Finished Sep 24 02:39:29 PM UTC 24
Peak memory 261372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111562734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.2111562734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3641715760
Short name T232
Test name
Test status
Simulation time 66440616 ps
CPU time 4.89 seconds
Started Sep 24 02:38:34 PM UTC 24
Finished Sep 24 02:38:40 PM UTC 24
Peak memory 245000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641715760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3641715760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.10396916
Short name T254
Test name
Test status
Simulation time 668378088 ps
CPU time 16.89 seconds
Started Sep 24 02:38:34 PM UTC 24
Finished Sep 24 02:38:52 PM UTC 24
Peak memory 234692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10396916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.10396916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2459807674
Short name T66
Test name
Test status
Simulation time 6015234106 ps
CPU time 12.16 seconds
Started Sep 24 02:38:33 PM UTC 24
Finished Sep 24 02:38:46 PM UTC 24
Peak memory 245240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459807674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.2459807674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1867453915
Short name T471
Test name
Test status
Simulation time 283838394 ps
CPU time 3.41 seconds
Started Sep 24 02:38:33 PM UTC 24
Finished Sep 24 02:38:37 PM UTC 24
Peak memory 233988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867453915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1867453915
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2527167998
Short name T478
Test name
Test status
Simulation time 3669750270 ps
CPU time 16.08 seconds
Started Sep 24 02:38:43 PM UTC 24
Finished Sep 24 02:39:01 PM UTC 24
Peak memory 231320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527167998 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.2527167998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3722639828
Short name T203
Test name
Test status
Simulation time 208933392 ps
CPU time 1.8 seconds
Started Sep 24 02:38:47 PM UTC 24
Finished Sep 24 02:38:50 PM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722639828 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3722639828
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3078729348
Short name T124
Test name
Test status
Simulation time 5056522272 ps
CPU time 37.57 seconds
Started Sep 24 02:38:30 PM UTC 24
Finished Sep 24 02:39:10 PM UTC 24
Peak memory 227500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078729348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3078729348
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1199251537
Short name T472
Test name
Test status
Simulation time 1708407307 ps
CPU time 11.13 seconds
Started Sep 24 02:38:30 PM UTC 24
Finished Sep 24 02:38:43 PM UTC 24
Peak memory 227332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199251537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1199251537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1029736090
Short name T470
Test name
Test status
Simulation time 170122256 ps
CPU time 2.18 seconds
Started Sep 24 02:38:32 PM UTC 24
Finished Sep 24 02:38:35 PM UTC 24
Peak memory 227112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029736090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1029736090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2740907654
Short name T469
Test name
Test status
Simulation time 12516684 ps
CPU time 1.19 seconds
Started Sep 24 02:38:31 PM UTC 24
Finished Sep 24 02:38:33 PM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740907654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2740907654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.210189919
Short name T248
Test name
Test status
Simulation time 7491024385 ps
CPU time 18.88 seconds
Started Sep 24 02:38:36 PM UTC 24
Finished Sep 24 02:38:57 PM UTC 24
Peak memory 245008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210189919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.210189919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest
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