| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.2104421713 |
|
|
Oct 03 04:12:05 AM UTC 24 |
Oct 03 04:13:07 AM UTC 24 |
19520624444 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.2325210518 |
|
|
Oct 03 04:12:51 AM UTC 24 |
Oct 03 04:13:07 AM UTC 24 |
1972729635 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.918061053 |
|
|
Oct 03 04:13:00 AM UTC 24 |
Oct 03 04:13:08 AM UTC 24 |
782387942 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.341878364 |
|
|
Oct 03 04:13:02 AM UTC 24 |
Oct 03 04:13:10 AM UTC 24 |
1113175311 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3838237648 |
|
|
Oct 03 04:12:51 AM UTC 24 |
Oct 03 04:13:10 AM UTC 24 |
2371984310 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.1851599546 |
|
|
Oct 03 04:13:05 AM UTC 24 |
Oct 03 04:13:11 AM UTC 24 |
2093485303 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.887693606 |
|
|
Oct 03 04:12:53 AM UTC 24 |
Oct 03 04:13:12 AM UTC 24 |
671653654 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.1331425940 |
|
|
Oct 03 04:13:03 AM UTC 24 |
Oct 03 04:13:13 AM UTC 24 |
522597690 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.177034205 |
|
|
Oct 03 04:13:14 AM UTC 24 |
Oct 03 04:13:16 AM UTC 24 |
23460162 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.313278723 |
|
|
Oct 03 04:13:14 AM UTC 24 |
Oct 03 04:13:16 AM UTC 24 |
12383440 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1845727452 |
|
|
Oct 03 04:13:09 AM UTC 24 |
Oct 03 04:13:16 AM UTC 24 |
498365048 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1355612618 |
|
|
Oct 03 04:13:08 AM UTC 24 |
Oct 03 04:13:16 AM UTC 24 |
809454567 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.2130824919 |
|
|
Oct 03 04:13:01 AM UTC 24 |
Oct 03 04:13:19 AM UTC 24 |
3543029490 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.623000842 |
|
|
Oct 03 04:13:18 AM UTC 24 |
Oct 03 04:13:20 AM UTC 24 |
11997095 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2181960092 |
|
|
Oct 03 04:13:18 AM UTC 24 |
Oct 03 04:13:20 AM UTC 24 |
70298218 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.705183595 |
|
|
Oct 03 04:12:37 AM UTC 24 |
Oct 03 04:13:21 AM UTC 24 |
2232934076 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.63347156 |
|
|
Oct 03 04:13:18 AM UTC 24 |
Oct 03 04:13:22 AM UTC 24 |
111554436 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.638159036 |
|
|
Oct 03 04:12:22 AM UTC 24 |
Oct 03 04:13:25 AM UTC 24 |
3736146301 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3638837172 |
|
|
Oct 03 04:13:18 AM UTC 24 |
Oct 03 04:13:25 AM UTC 24 |
1240120745 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1539256567 |
|
|
Oct 03 04:13:01 AM UTC 24 |
Oct 03 04:13:27 AM UTC 24 |
4283227219 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.1436989238 |
|
|
Oct 03 04:12:41 AM UTC 24 |
Oct 03 04:13:28 AM UTC 24 |
9410891007 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.3961613846 |
|
|
Oct 03 04:13:23 AM UTC 24 |
Oct 03 04:13:30 AM UTC 24 |
299121907 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.41956126 |
|
|
Oct 03 04:09:54 AM UTC 24 |
Oct 03 04:13:32 AM UTC 24 |
91955982663 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3329444902 |
|
|
Oct 03 04:13:27 AM UTC 24 |
Oct 03 04:13:33 AM UTC 24 |
815635182 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.4166951730 |
|
|
Oct 03 04:13:22 AM UTC 24 |
Oct 03 04:13:34 AM UTC 24 |
387661342 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1259551994 |
|
|
Oct 03 04:13:22 AM UTC 24 |
Oct 03 04:13:37 AM UTC 24 |
856884242 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.566041977 |
|
|
Oct 03 04:13:27 AM UTC 24 |
Oct 03 04:13:37 AM UTC 24 |
486789517 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.3149771616 |
|
|
Oct 03 04:13:35 AM UTC 24 |
Oct 03 04:13:37 AM UTC 24 |
96685052 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.334853936 |
|
|
Oct 03 04:13:20 AM UTC 24 |
Oct 03 04:13:40 AM UTC 24 |
1288889464 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.612543935 |
|
|
Oct 03 04:13:38 AM UTC 24 |
Oct 03 04:13:40 AM UTC 24 |
25616426 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.405947618 |
|
|
Oct 03 04:13:41 AM UTC 24 |
Oct 03 04:13:43 AM UTC 24 |
41516362 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1721375072 |
|
|
Oct 03 04:13:41 AM UTC 24 |
Oct 03 04:13:43 AM UTC 24 |
17166911 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.807097482 |
|
|
Oct 03 04:13:05 AM UTC 24 |
Oct 03 04:13:45 AM UTC 24 |
36280134910 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.2456347733 |
|
|
Oct 03 04:11:37 AM UTC 24 |
Oct 03 04:13:52 AM UTC 24 |
78761043708 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.1386927839 |
|
|
Oct 03 04:13:29 AM UTC 24 |
Oct 03 04:13:46 AM UTC 24 |
917638885 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.4271001906 |
|
|
Oct 03 04:13:08 AM UTC 24 |
Oct 03 04:13:47 AM UTC 24 |
2980881488 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3792214836 |
|
|
Oct 03 04:13:39 AM UTC 24 |
Oct 03 04:13:49 AM UTC 24 |
495472431 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.1771318575 |
|
|
Oct 03 04:13:46 AM UTC 24 |
Oct 03 04:13:50 AM UTC 24 |
469568228 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.3889134077 |
|
|
Oct 03 04:12:53 AM UTC 24 |
Oct 03 04:13:52 AM UTC 24 |
118753085935 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3427584706 |
|
|
Oct 03 04:13:50 AM UTC 24 |
Oct 03 04:13:54 AM UTC 24 |
32757937 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.2786598929 |
|
|
Oct 03 04:13:38 AM UTC 24 |
Oct 03 04:13:54 AM UTC 24 |
13214514714 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2758772093 |
|
|
Oct 03 04:13:44 AM UTC 24 |
Oct 03 04:13:55 AM UTC 24 |
494914677 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.1631028062 |
|
|
Oct 03 04:13:52 AM UTC 24 |
Oct 03 04:13:57 AM UTC 24 |
316072714 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.1779562625 |
|
|
Oct 03 04:11:08 AM UTC 24 |
Oct 03 04:13:58 AM UTC 24 |
16319936587 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.3766956428 |
|
|
Oct 03 04:13:58 AM UTC 24 |
Oct 03 04:14:00 AM UTC 24 |
61131007 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.1513525559 |
|
|
Oct 03 04:11:27 AM UTC 24 |
Oct 03 04:14:03 AM UTC 24 |
63075980670 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.842150028 |
|
|
Oct 03 04:14:01 AM UTC 24 |
Oct 03 04:14:03 AM UTC 24 |
63704605 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.2924424182 |
|
|
Oct 03 04:13:48 AM UTC 24 |
Oct 03 04:14:07 AM UTC 24 |
1693978619 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.19328171 |
|
|
Oct 03 04:13:53 AM UTC 24 |
Oct 03 04:14:11 AM UTC 24 |
3710309985 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.4211865212 |
|
|
Oct 03 04:14:09 AM UTC 24 |
Oct 03 04:14:11 AM UTC 24 |
20554222 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.4160488440 |
|
|
Oct 03 04:11:22 AM UTC 24 |
Oct 03 04:14:14 AM UTC 24 |
63372533094 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.2663445206 |
|
|
Oct 03 04:14:12 AM UTC 24 |
Oct 03 04:14:15 AM UTC 24 |
249789969 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1113475799 |
|
|
Oct 03 04:13:09 AM UTC 24 |
Oct 03 04:14:15 AM UTC 24 |
9325172486 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.2190898968 |
|
|
Oct 03 04:13:47 AM UTC 24 |
Oct 03 04:14:16 AM UTC 24 |
4308841115 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.1643866598 |
|
|
Oct 03 04:12:41 AM UTC 24 |
Oct 03 04:14:17 AM UTC 24 |
10586522727 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.717813496 |
|
|
Oct 03 04:13:44 AM UTC 24 |
Oct 03 04:14:17 AM UTC 24 |
33448576679 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1455343359 |
|
|
Oct 03 04:05:24 AM UTC 24 |
Oct 03 04:14:17 AM UTC 24 |
110245141615 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.4235810660 |
|
|
Oct 03 04:14:03 AM UTC 24 |
Oct 03 04:14:18 AM UTC 24 |
17694116163 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2645325523 |
|
|
Oct 03 04:09:33 AM UTC 24 |
Oct 03 04:14:21 AM UTC 24 |
25058814684 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.3712847836 |
|
|
Oct 03 04:14:18 AM UTC 24 |
Oct 03 04:14:21 AM UTC 24 |
142545125 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.2114664174 |
|
|
Oct 03 04:14:17 AM UTC 24 |
Oct 03 04:14:23 AM UTC 24 |
957418464 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.2502922144 |
|
|
Oct 03 04:14:18 AM UTC 24 |
Oct 03 04:14:23 AM UTC 24 |
323512472 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.2248165859 |
|
|
Oct 03 04:14:21 AM UTC 24 |
Oct 03 04:14:23 AM UTC 24 |
41773105 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.4036140489 |
|
|
Oct 03 04:14:17 AM UTC 24 |
Oct 03 04:14:26 AM UTC 24 |
289570893 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.911851323 |
|
|
Oct 03 04:14:24 AM UTC 24 |
Oct 03 04:14:26 AM UTC 24 |
38931092 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.468570493 |
|
|
Oct 03 04:14:24 AM UTC 24 |
Oct 03 04:14:26 AM UTC 24 |
68772313 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2202405328 |
|
|
Oct 03 04:14:12 AM UTC 24 |
Oct 03 04:14:29 AM UTC 24 |
6337460126 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1073573393 |
|
|
Oct 03 04:13:12 AM UTC 24 |
Oct 03 04:14:29 AM UTC 24 |
5413737130 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1444829806 |
|
|
Oct 03 04:14:27 AM UTC 24 |
Oct 03 04:14:30 AM UTC 24 |
598664889 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.253907330 |
|
|
Oct 03 04:14:19 AM UTC 24 |
Oct 03 04:14:30 AM UTC 24 |
596071104 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.4017703112 |
|
|
Oct 03 04:12:37 AM UTC 24 |
Oct 03 04:14:30 AM UTC 24 |
13001060133 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.612785720 |
|
|
Oct 03 04:14:29 AM UTC 24 |
Oct 03 04:14:32 AM UTC 24 |
36315730 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.2450115545 |
|
|
Oct 03 04:14:15 AM UTC 24 |
Oct 03 04:14:34 AM UTC 24 |
1708696260 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2036709221 |
|
|
Oct 03 04:13:12 AM UTC 24 |
Oct 03 04:14:36 AM UTC 24 |
6115468712 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.578173226 |
|
|
Oct 03 04:14:22 AM UTC 24 |
Oct 03 04:14:38 AM UTC 24 |
1790025341 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.1614957177 |
|
|
Oct 03 04:11:29 AM UTC 24 |
Oct 03 04:14:39 AM UTC 24 |
6496150628 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.750598817 |
|
|
Oct 03 04:14:33 AM UTC 24 |
Oct 03 04:14:39 AM UTC 24 |
1584887913 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1469302209 |
|
|
Oct 03 04:14:31 AM UTC 24 |
Oct 03 04:14:41 AM UTC 24 |
5438914285 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.1259134596 |
|
|
Oct 03 04:14:32 AM UTC 24 |
Oct 03 04:14:41 AM UTC 24 |
291189089 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.773621927 |
|
|
Oct 03 04:14:36 AM UTC 24 |
Oct 03 04:14:42 AM UTC 24 |
48467833 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.3992605189 |
|
|
Oct 03 04:14:32 AM UTC 24 |
Oct 03 04:14:42 AM UTC 24 |
433004017 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.487817495 |
|
|
Oct 03 04:14:04 AM UTC 24 |
Oct 03 04:14:43 AM UTC 24 |
43866409956 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.385171865 |
|
|
Oct 03 04:14:30 AM UTC 24 |
Oct 03 04:14:43 AM UTC 24 |
7923570374 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.3629777475 |
|
|
Oct 03 04:12:22 AM UTC 24 |
Oct 03 04:14:44 AM UTC 24 |
28478308125 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.912199443 |
|
|
Oct 03 04:14:16 AM UTC 24 |
Oct 03 04:14:44 AM UTC 24 |
10029640346 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3518369053 |
|
|
Oct 03 04:14:35 AM UTC 24 |
Oct 03 04:14:45 AM UTC 24 |
1089617035 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1360085863 |
|
|
Oct 03 04:11:47 AM UTC 24 |
Oct 03 04:14:46 AM UTC 24 |
50489931145 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.4230046320 |
|
|
Oct 03 04:14:44 AM UTC 24 |
Oct 03 04:14:46 AM UTC 24 |
21530476 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.1779528428 |
|
|
Oct 03 04:14:44 AM UTC 24 |
Oct 03 04:14:46 AM UTC 24 |
45599734 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.93350585 |
|
|
Oct 03 04:14:45 AM UTC 24 |
Oct 03 04:14:47 AM UTC 24 |
23392088 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1782520663 |
|
|
Oct 03 04:14:42 AM UTC 24 |
Oct 03 04:14:48 AM UTC 24 |
683333301 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.607409952 |
|
|
Oct 03 04:14:46 AM UTC 24 |
Oct 03 04:14:49 AM UTC 24 |
119786547 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.87817672 |
|
|
Oct 03 04:14:45 AM UTC 24 |
Oct 03 04:14:50 AM UTC 24 |
276849451 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.819786265 |
|
|
Oct 03 04:14:47 AM UTC 24 |
Oct 03 04:14:51 AM UTC 24 |
32157858 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1628915761 |
|
|
Oct 03 04:13:32 AM UTC 24 |
Oct 03 04:14:52 AM UTC 24 |
24507072821 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3262168278 |
|
|
Oct 03 04:14:40 AM UTC 24 |
Oct 03 04:14:54 AM UTC 24 |
720049118 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.124505835 |
|
|
Oct 03 04:14:48 AM UTC 24 |
Oct 03 04:14:57 AM UTC 24 |
1214610590 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3675800488 |
|
|
Oct 03 04:14:49 AM UTC 24 |
Oct 03 04:14:57 AM UTC 24 |
639475948 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.2019009111 |
|
|
Oct 03 04:14:27 AM UTC 24 |
Oct 03 04:15:00 AM UTC 24 |
2044221415 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.60061138 |
|
|
Oct 03 04:14:51 AM UTC 24 |
Oct 03 04:15:02 AM UTC 24 |
338246659 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.136895100 |
|
|
Oct 03 04:14:53 AM UTC 24 |
Oct 03 04:15:05 AM UTC 24 |
3130045692 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.594166991 |
|
|
Oct 03 04:14:26 AM UTC 24 |
Oct 03 04:15:05 AM UTC 24 |
62607997463 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.2567219733 |
|
|
Oct 03 04:15:03 AM UTC 24 |
Oct 03 04:15:05 AM UTC 24 |
13069651 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.4520214 |
|
|
Oct 03 04:15:05 AM UTC 24 |
Oct 03 04:15:08 AM UTC 24 |
16525104 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3405261435 |
|
|
Oct 03 04:15:05 AM UTC 24 |
Oct 03 04:15:10 AM UTC 24 |
175200877 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.656432786 |
|
|
Oct 03 04:15:09 AM UTC 24 |
Oct 03 04:15:11 AM UTC 24 |
134150882 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3235215664 |
|
|
Oct 03 04:12:39 AM UTC 24 |
Oct 03 04:15:12 AM UTC 24 |
64608890377 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.2492169683 |
|
|
Oct 03 04:13:14 AM UTC 24 |
Oct 03 04:15:12 AM UTC 24 |
28088099443 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.1726282774 |
|
|
Oct 03 04:15:12 AM UTC 24 |
Oct 03 04:15:15 AM UTC 24 |
167807351 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.2977714067 |
|
|
Oct 03 04:12:22 AM UTC 24 |
Oct 03 04:15:15 AM UTC 24 |
51614224331 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.2556311504 |
|
|
Oct 03 04:15:12 AM UTC 24 |
Oct 03 04:15:16 AM UTC 24 |
551985697 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.169954136 |
|
|
Oct 03 04:15:06 AM UTC 24 |
Oct 03 04:15:17 AM UTC 24 |
3225814507 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.3705381345 |
|
|
Oct 03 04:15:16 AM UTC 24 |
Oct 03 04:15:20 AM UTC 24 |
34842807 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.2978775338 |
|
|
Oct 03 04:11:25 AM UTC 24 |
Oct 03 04:16:48 AM UTC 24 |
28256276419 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.2938307852 |
|
|
Oct 03 04:14:47 AM UTC 24 |
Oct 03 04:15:20 AM UTC 24 |
2642596298 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.480476945 |
|
|
Oct 03 04:15:17 AM UTC 24 |
Oct 03 04:15:22 AM UTC 24 |
307272150 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.1679647888 |
|
|
Oct 03 04:13:09 AM UTC 24 |
Oct 03 04:15:23 AM UTC 24 |
42700470100 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.877544915 |
|
|
Oct 03 04:15:17 AM UTC 24 |
Oct 03 04:15:24 AM UTC 24 |
300399572 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1424825116 |
|
|
Oct 03 04:14:22 AM UTC 24 |
Oct 03 04:15:25 AM UTC 24 |
6143272683 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.502931310 |
|
|
Oct 03 04:14:45 AM UTC 24 |
Oct 03 04:15:26 AM UTC 24 |
7311841774 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2905941665 |
|
|
Oct 03 04:15:20 AM UTC 24 |
Oct 03 04:15:27 AM UTC 24 |
111567470 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.51995980 |
|
|
Oct 03 04:15:25 AM UTC 24 |
Oct 03 04:15:27 AM UTC 24 |
14713492 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.3569225318 |
|
|
Oct 03 04:15:26 AM UTC 24 |
Oct 03 04:15:28 AM UTC 24 |
87105440 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1992302460 |
|
|
Oct 03 04:15:27 AM UTC 24 |
Oct 03 04:15:30 AM UTC 24 |
12441091 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.1793894485 |
|
|
Oct 03 04:15:28 AM UTC 24 |
Oct 03 04:15:31 AM UTC 24 |
126547747 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.1342466605 |
|
|
Oct 03 04:14:16 AM UTC 24 |
Oct 03 04:15:32 AM UTC 24 |
6803956869 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.2722956823 |
|
|
Oct 03 04:15:30 AM UTC 24 |
Oct 03 04:15:32 AM UTC 24 |
50134354 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.250432540 |
|
|
Oct 03 04:15:13 AM UTC 24 |
Oct 03 04:15:34 AM UTC 24 |
17134164158 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.2478944350 |
|
|
Oct 03 04:15:33 AM UTC 24 |
Oct 03 04:15:38 AM UTC 24 |
156716778 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.3302703295 |
|
|
Oct 03 04:14:47 AM UTC 24 |
Oct 03 04:15:38 AM UTC 24 |
3891437916 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.4043155778 |
|
|
Oct 03 04:15:27 AM UTC 24 |
Oct 03 04:15:41 AM UTC 24 |
1691197161 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3418066789 |
|
|
Oct 03 04:14:48 AM UTC 24 |
Oct 03 04:15:41 AM UTC 24 |
15800034478 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.389270878 |
|
|
Oct 03 04:13:32 AM UTC 24 |
Oct 03 04:15:44 AM UTC 24 |
25644917041 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2848171196 |
|
|
Oct 03 04:15:31 AM UTC 24 |
Oct 03 04:15:47 AM UTC 24 |
382728895 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.1484490046 |
|
|
Oct 03 04:10:15 AM UTC 24 |
Oct 03 04:15:48 AM UTC 24 |
103908618174 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.549188211 |
|
|
Oct 03 04:13:34 AM UTC 24 |
Oct 03 04:15:49 AM UTC 24 |
16935527871 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.3815234763 |
|
|
Oct 03 04:15:35 AM UTC 24 |
Oct 03 04:15:50 AM UTC 24 |
992431029 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2589341346 |
|
|
Oct 03 04:15:50 AM UTC 24 |
Oct 03 04:15:52 AM UTC 24 |
41243320 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.4049707202 |
|
|
Oct 03 04:15:51 AM UTC 24 |
Oct 03 04:15:53 AM UTC 24 |
19162480 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.702058023 |
|
|
Oct 03 04:15:13 AM UTC 24 |
Oct 03 04:15:54 AM UTC 24 |
16916669256 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2876727275 |
|
|
Oct 03 04:15:32 AM UTC 24 |
Oct 03 04:15:55 AM UTC 24 |
3438197959 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.2842900749 |
|
|
Oct 03 04:15:41 AM UTC 24 |
Oct 03 04:15:55 AM UTC 24 |
13358390358 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3404751287 |
|
|
Oct 03 04:12:06 AM UTC 24 |
Oct 03 04:15:56 AM UTC 24 |
43023756632 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.3306205726 |
|
|
Oct 03 04:15:53 AM UTC 24 |
Oct 03 04:15:56 AM UTC 24 |
551837235 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.1857584470 |
|
|
Oct 03 04:15:55 AM UTC 24 |
Oct 03 04:15:58 AM UTC 24 |
96525875 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.555446799 |
|
|
Oct 03 04:15:55 AM UTC 24 |
Oct 03 04:16:00 AM UTC 24 |
86040654 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.752229500 |
|
|
Oct 03 04:15:54 AM UTC 24 |
Oct 03 04:16:01 AM UTC 24 |
1433024048 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.1113701603 |
|
|
Oct 03 04:13:23 AM UTC 24 |
Oct 03 04:16:01 AM UTC 24 |
52737032857 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.1657107322 |
|
|
Oct 03 04:15:33 AM UTC 24 |
Oct 03 04:16:03 AM UTC 24 |
25995053921 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.3923599079 |
|
|
Oct 03 04:16:02 AM UTC 24 |
Oct 03 04:16:10 AM UTC 24 |
375417285 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.2694986389 |
|
|
Oct 03 04:15:39 AM UTC 24 |
Oct 03 04:16:12 AM UTC 24 |
3729634545 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1901632758 |
|
|
Oct 03 04:15:39 AM UTC 24 |
Oct 03 04:16:13 AM UTC 24 |
2239242694 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.551489019 |
|
|
Oct 03 04:15:56 AM UTC 24 |
Oct 03 04:16:14 AM UTC 24 |
2037885556 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.3448187117 |
|
|
Oct 03 04:15:21 AM UTC 24 |
Oct 03 04:16:15 AM UTC 24 |
13031655703 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.59816896 |
|
|
Oct 03 04:10:32 AM UTC 24 |
Oct 03 04:16:17 AM UTC 24 |
99892108012 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.39174062 |
|
|
Oct 03 04:16:02 AM UTC 24 |
Oct 03 04:16:17 AM UTC 24 |
5763634676 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.2096581791 |
|
|
Oct 03 04:16:18 AM UTC 24 |
Oct 03 04:16:20 AM UTC 24 |
28883342 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.38422867 |
|
|
Oct 03 04:16:18 AM UTC 24 |
Oct 03 04:16:20 AM UTC 24 |
60901786 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.1831431635 |
|
|
Oct 03 04:15:58 AM UTC 24 |
Oct 03 04:16:22 AM UTC 24 |
9612420477 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.871401183 |
|
|
Oct 03 04:14:39 AM UTC 24 |
Oct 03 04:16:23 AM UTC 24 |
5088658264 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.4238755115 |
|
|
Oct 03 04:13:53 AM UTC 24 |
Oct 03 04:16:23 AM UTC 24 |
28173492254 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.252762078 |
|
|
Oct 03 04:16:10 AM UTC 24 |
Oct 03 04:16:24 AM UTC 24 |
641701199 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.268318696 |
|
|
Oct 03 04:15:18 AM UTC 24 |
Oct 03 04:16:24 AM UTC 24 |
1777672816 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1342817300 |
|
|
Oct 03 04:16:22 AM UTC 24 |
Oct 03 04:16:24 AM UTC 24 |
76689446 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.3304953844 |
|
|
Oct 03 04:16:00 AM UTC 24 |
Oct 03 04:16:25 AM UTC 24 |
21986056179 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1879397314 |
|
|
Oct 03 04:15:01 AM UTC 24 |
Oct 03 04:16:25 AM UTC 24 |
10788775313 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.945100872 |
|
|
Oct 03 04:13:56 AM UTC 24 |
Oct 03 04:16:25 AM UTC 24 |
103975921072 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2277386433 |
|
|
Oct 03 04:15:57 AM UTC 24 |
Oct 03 04:16:25 AM UTC 24 |
22860305313 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.1538029552 |
|
|
Oct 03 04:13:55 AM UTC 24 |
Oct 03 04:16:27 AM UTC 24 |
28702670572 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2800198481 |
|
|
Oct 03 04:16:24 AM UTC 24 |
Oct 03 04:16:28 AM UTC 24 |
295756488 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.604380430 |
|
|
Oct 03 04:16:02 AM UTC 24 |
Oct 03 04:16:28 AM UTC 24 |
1064137215 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.3278166290 |
|
|
Oct 03 04:16:13 AM UTC 24 |
Oct 03 04:16:43 AM UTC 24 |
1850338896 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.431689324 |
|
|
Oct 03 04:15:48 AM UTC 24 |
Oct 03 04:16:31 AM UTC 24 |
3593803607 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.2482508308 |
|
|
Oct 03 04:16:24 AM UTC 24 |
Oct 03 04:16:31 AM UTC 24 |
67602635 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.348524746 |
|
|
Oct 03 04:16:25 AM UTC 24 |
Oct 03 04:16:32 AM UTC 24 |
358792241 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.970134 |
|
|
Oct 03 04:16:27 AM UTC 24 |
Oct 03 04:16:33 AM UTC 24 |
1212160798 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.621631986 |
|
|
Oct 03 04:10:30 AM UTC 24 |
Oct 03 04:16:34 AM UTC 24 |
90422431442 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.2095282411 |
|
|
Oct 03 04:16:21 AM UTC 24 |
Oct 03 04:16:34 AM UTC 24 |
8800913345 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.3250393156 |
|
|
Oct 03 04:15:15 AM UTC 24 |
Oct 03 04:16:34 AM UTC 24 |
6279633188 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.567135454 |
|
|
Oct 03 04:16:32 AM UTC 24 |
Oct 03 04:16:34 AM UTC 24 |
74628676 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.2134534690 |
|
|
Oct 03 04:16:27 AM UTC 24 |
Oct 03 04:16:34 AM UTC 24 |
495198759 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1739042187 |
|
|
Oct 03 04:16:32 AM UTC 24 |
Oct 03 04:16:35 AM UTC 24 |
162202119 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.2625726545 |
|
|
Oct 03 04:16:33 AM UTC 24 |
Oct 03 04:16:35 AM UTC 24 |
57113968 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.4123641307 |
|
|
Oct 03 04:16:35 AM UTC 24 |
Oct 03 04:16:37 AM UTC 24 |
395825401 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.3878595684 |
|
|
Oct 03 04:16:04 AM UTC 24 |
Oct 03 04:16:37 AM UTC 24 |
2817935442 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.1034237658 |
|
|
Oct 03 04:16:36 AM UTC 24 |
Oct 03 04:16:38 AM UTC 24 |
11462276 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1256046679 |
|
|
Oct 03 04:16:28 AM UTC 24 |
Oct 03 04:16:41 AM UTC 24 |
4623665964 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3683688434 |
|
|
Oct 03 04:11:29 AM UTC 24 |
Oct 03 04:16:42 AM UTC 24 |
28603783129 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1221375453 |
|
|
Oct 03 04:16:36 AM UTC 24 |
Oct 03 04:16:43 AM UTC 24 |
426846257 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.57206100 |
|
|
Oct 03 04:16:38 AM UTC 24 |
Oct 03 04:16:43 AM UTC 24 |
112470784 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1702161539 |
|
|
Oct 03 04:16:25 AM UTC 24 |
Oct 03 04:16:49 AM UTC 24 |
5284157777 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.4043875601 |
|
|
Oct 03 04:16:41 AM UTC 24 |
Oct 03 04:16:50 AM UTC 24 |
320553449 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.3401394169 |
|
|
Oct 03 04:14:53 AM UTC 24 |
Oct 03 04:16:51 AM UTC 24 |
54280104431 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.961448956 |
|
|
Oct 03 04:16:25 AM UTC 24 |
Oct 03 04:16:52 AM UTC 24 |
6577834570 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1405817969 |
|
|
Oct 03 04:16:34 AM UTC 24 |
Oct 03 04:16:52 AM UTC 24 |
6944560734 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1838752356 |
|
|
Oct 03 04:16:50 AM UTC 24 |
Oct 03 04:16:52 AM UTC 24 |
60143890 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.3044817990 |
|
|
Oct 03 04:16:51 AM UTC 24 |
Oct 03 04:16:53 AM UTC 24 |
23942616 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.703708662 |
|
|
Oct 03 04:16:37 AM UTC 24 |
Oct 03 04:16:54 AM UTC 24 |
3803936451 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.831863308 |
|
|
Oct 03 04:16:52 AM UTC 24 |
Oct 03 04:16:54 AM UTC 24 |
59078441 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2085834076 |
|
|
Oct 03 04:16:21 AM UTC 24 |
Oct 03 04:16:54 AM UTC 24 |
5053981040 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2094062915 |
|
|
Oct 03 04:16:53 AM UTC 24 |
Oct 03 04:16:55 AM UTC 24 |
46300277 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.4231176127 |
|
|
Oct 03 04:16:54 AM UTC 24 |
Oct 03 04:16:59 AM UTC 24 |
418699756 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.1274226350 |
|
|
Oct 03 04:16:38 AM UTC 24 |
Oct 03 04:17:00 AM UTC 24 |
1533067089 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.81167036 |
|
|
Oct 03 04:16:54 AM UTC 24 |
Oct 03 04:17:00 AM UTC 24 |
205138116 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2146389761 |
|
|
Oct 03 04:16:43 AM UTC 24 |
Oct 03 04:17:00 AM UTC 24 |
697733464 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.1611300070 |
|
|
Oct 03 04:16:26 AM UTC 24 |
Oct 03 04:17:00 AM UTC 24 |
112907816191 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.2348703196 |
|
|
Oct 03 04:16:56 AM UTC 24 |
Oct 03 04:17:02 AM UTC 24 |
164006158 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.3353698798 |
|
|
Oct 03 04:16:57 AM UTC 24 |
Oct 03 04:17:02 AM UTC 24 |
185001871 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3299298796 |
|
|
Oct 03 04:16:53 AM UTC 24 |
Oct 03 04:17:04 AM UTC 24 |
2651094959 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.3721925093 |
|
|
Oct 03 04:17:06 AM UTC 24 |
Oct 03 04:17:08 AM UTC 24 |
37108578 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.166418624 |
|
|
Oct 03 04:17:01 AM UTC 24 |
Oct 03 04:17:08 AM UTC 24 |
152823791 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.2540652371 |
|
|
Oct 03 04:14:40 AM UTC 24 |
Oct 03 04:17:09 AM UTC 24 |
15368146176 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.2572177182 |
|
|
Oct 03 04:17:09 AM UTC 24 |
Oct 03 04:17:11 AM UTC 24 |
20662937 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.3365754609 |
|
|
Oct 03 04:17:09 AM UTC 24 |
Oct 03 04:17:11 AM UTC 24 |
35586203 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2345671725 |
|
|
Oct 03 04:16:36 AM UTC 24 |
Oct 03 04:17:11 AM UTC 24 |
55038835347 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.1517793612 |
|
|
Oct 03 04:17:12 AM UTC 24 |
Oct 03 04:17:14 AM UTC 24 |
22770247 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.836710133 |
|
|
Oct 03 04:17:12 AM UTC 24 |
Oct 03 04:17:14 AM UTC 24 |
167314404 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.1338441068 |
|
|
Oct 03 04:17:01 AM UTC 24 |
Oct 03 04:17:19 AM UTC 24 |
1079137448 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.2330123704 |
|
|
Oct 03 04:17:10 AM UTC 24 |
Oct 03 04:17:20 AM UTC 24 |
13014897763 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.899426432 |
|
|
Oct 03 04:17:15 AM UTC 24 |
Oct 03 04:17:20 AM UTC 24 |
72024907 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1953569278 |
|
|
Oct 03 04:11:14 AM UTC 24 |
Oct 03 04:17:26 AM UTC 24 |
323580155451 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.781802544 |
|
|
Oct 03 04:17:15 AM UTC 24 |
Oct 03 04:17:27 AM UTC 24 |
2351537133 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.261148895 |
|
|
Oct 03 04:17:12 AM UTC 24 |
Oct 03 04:17:28 AM UTC 24 |
1193216825 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.472018708 |
|
|
Oct 03 04:16:59 AM UTC 24 |
Oct 03 04:17:28 AM UTC 24 |
7518854532 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3894419911 |
|
|
Oct 03 04:17:02 AM UTC 24 |
Oct 03 04:17:29 AM UTC 24 |
4895695497 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2212909938 |
|
|
Oct 03 04:16:56 AM UTC 24 |
Oct 03 04:17:30 AM UTC 24 |
32337279277 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.2222936728 |
|
|
Oct 03 04:16:34 AM UTC 24 |
Oct 03 04:17:31 AM UTC 24 |
37560822674 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.3436204655 |
|
|
Oct 03 04:16:38 AM UTC 24 |
Oct 03 04:17:31 AM UTC 24 |
21330160106 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2877601826 |
|
|
Oct 03 04:07:55 AM UTC 24 |
Oct 03 04:17:31 AM UTC 24 |
112990401351 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.2348623747 |
|
|
Oct 03 04:14:55 AM UTC 24 |
Oct 03 04:17:33 AM UTC 24 |
18923297587 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.31778932 |
|
|
Oct 03 04:16:56 AM UTC 24 |
Oct 03 04:17:33 AM UTC 24 |
15355631820 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.4011162192 |
|
|
Oct 03 04:16:53 AM UTC 24 |
Oct 03 04:17:34 AM UTC 24 |
6930255644 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.254758863 |
|
|
Oct 03 04:17:50 AM UTC 24 |
Oct 03 04:17:57 AM UTC 24 |
379303919 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.1309996068 |
|
|
Oct 03 04:17:21 AM UTC 24 |
Oct 03 04:17:34 AM UTC 24 |
1737642255 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.354493826 |
|
|
Oct 03 04:17:32 AM UTC 24 |
Oct 03 04:17:35 AM UTC 24 |
13662010 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.1553465457 |
|
|
Oct 03 04:17:32 AM UTC 24 |
Oct 03 04:17:35 AM UTC 24 |
361618819 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1196345138 |
|
|
Oct 03 04:15:45 AM UTC 24 |
Oct 03 04:17:35 AM UTC 24 |
60084542810 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1701279820 |
|
|
Oct 03 04:17:33 AM UTC 24 |
Oct 03 04:17:36 AM UTC 24 |
13598666 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.516331072 |
|
|
Oct 03 04:16:45 AM UTC 24 |
Oct 03 04:17:36 AM UTC 24 |
49054972524 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.2459019748 |
|
|
Oct 03 04:17:35 AM UTC 24 |
Oct 03 04:17:37 AM UTC 24 |
29081351 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1396617723 |
|
|
Oct 03 04:16:32 AM UTC 24 |
Oct 03 04:17:37 AM UTC 24 |
3223927296 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3229730716 |
|
|
Oct 03 04:16:42 AM UTC 24 |
Oct 03 04:17:37 AM UTC 24 |
2436401291 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3906474678 |
|
|
Oct 03 04:17:35 AM UTC 24 |
Oct 03 04:17:37 AM UTC 24 |
61934528 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.4136937751 |
|
|
Oct 03 04:17:29 AM UTC 24 |
Oct 03 04:17:38 AM UTC 24 |
1138554946 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.3833105365 |
|
|
Oct 03 04:17:28 AM UTC 24 |
Oct 03 04:17:42 AM UTC 24 |
9530777891 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.733190398 |
|
|
Oct 03 04:17:37 AM UTC 24 |
Oct 03 04:17:42 AM UTC 24 |
715742790 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3830893617 |
|
|
Oct 03 04:17:37 AM UTC 24 |
Oct 03 04:17:42 AM UTC 24 |
55276050 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.2161263591 |
|
|
Oct 03 04:17:36 AM UTC 24 |
Oct 03 04:17:43 AM UTC 24 |
419916461 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1071774525 |
|
|
Oct 03 04:17:36 AM UTC 24 |
Oct 03 04:17:44 AM UTC 24 |
4646461114 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.1975971286 |
|
|
Oct 03 04:17:37 AM UTC 24 |
Oct 03 04:17:44 AM UTC 24 |
373163901 ps |