| T820 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1953924554 |
|
|
Oct 03 04:16:29 AM UTC 24 |
Oct 03 04:17:44 AM UTC 24 |
6997942964 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.423116981 |
|
|
Oct 03 04:13:35 AM UTC 24 |
Oct 03 04:17:45 AM UTC 24 |
62570867758 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.3489595907 |
|
|
Oct 03 04:17:20 AM UTC 24 |
Oct 03 04:17:45 AM UTC 24 |
32045439650 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1169681388 |
|
|
Oct 03 04:17:19 AM UTC 24 |
Oct 03 04:17:46 AM UTC 24 |
6771813633 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.2004429074 |
|
|
Oct 03 04:17:44 AM UTC 24 |
Oct 03 04:17:46 AM UTC 24 |
136418723 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1389590448 |
|
|
Oct 03 04:17:35 AM UTC 24 |
Oct 03 04:17:47 AM UTC 24 |
3167685525 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1510174990 |
|
|
Oct 03 04:17:45 AM UTC 24 |
Oct 03 04:17:47 AM UTC 24 |
15920879 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.3397727159 |
|
|
Oct 03 04:17:45 AM UTC 24 |
Oct 03 04:17:47 AM UTC 24 |
14035779 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.683921054 |
|
|
Oct 03 04:17:02 AM UTC 24 |
Oct 03 04:17:47 AM UTC 24 |
2415533302 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2757850324 |
|
|
Oct 03 04:17:36 AM UTC 24 |
Oct 03 04:17:49 AM UTC 24 |
8300295247 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.882785030 |
|
|
Oct 03 04:17:46 AM UTC 24 |
Oct 03 04:17:49 AM UTC 24 |
127907794 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3019650645 |
|
|
Oct 03 04:17:46 AM UTC 24 |
Oct 03 04:17:50 AM UTC 24 |
344103100 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2400501711 |
|
|
Oct 03 04:17:27 AM UTC 24 |
Oct 03 04:17:51 AM UTC 24 |
4034856754 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2780056859 |
|
|
Oct 03 04:17:38 AM UTC 24 |
Oct 03 04:17:51 AM UTC 24 |
1576105662 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.4010636595 |
|
|
Oct 03 04:17:46 AM UTC 24 |
Oct 03 04:17:53 AM UTC 24 |
588765410 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.2025462323 |
|
|
Oct 03 04:17:37 AM UTC 24 |
Oct 03 04:17:54 AM UTC 24 |
1031554613 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.1435059942 |
|
|
Oct 03 04:17:46 AM UTC 24 |
Oct 03 04:17:55 AM UTC 24 |
323001822 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2658404760 |
|
|
Oct 03 04:19:01 AM UTC 24 |
Oct 03 04:19:08 AM UTC 24 |
816915569 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.716031861 |
|
|
Oct 03 04:17:52 AM UTC 24 |
Oct 03 04:17:58 AM UTC 24 |
157693372 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3797039433 |
|
|
Oct 03 04:17:56 AM UTC 24 |
Oct 03 04:17:59 AM UTC 24 |
546562436 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2924675150 |
|
|
Oct 03 04:15:39 AM UTC 24 |
Oct 03 04:17:59 AM UTC 24 |
15161348080 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3988307993 |
|
|
Oct 03 04:17:50 AM UTC 24 |
Oct 03 04:17:59 AM UTC 24 |
770153909 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1378629797 |
|
|
Oct 03 04:17:57 AM UTC 24 |
Oct 03 04:18:00 AM UTC 24 |
40023100 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2832451894 |
|
|
Oct 03 04:17:47 AM UTC 24 |
Oct 03 04:18:01 AM UTC 24 |
569824297 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.1693745299 |
|
|
Oct 03 04:17:48 AM UTC 24 |
Oct 03 04:18:01 AM UTC 24 |
3082518984 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2222082858 |
|
|
Oct 03 04:17:59 AM UTC 24 |
Oct 03 04:18:01 AM UTC 24 |
54934405 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.413499993 |
|
|
Oct 03 04:17:59 AM UTC 24 |
Oct 03 04:18:02 AM UTC 24 |
46451292 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3101203786 |
|
|
Oct 03 04:12:51 AM UTC 24 |
Oct 03 04:18:03 AM UTC 24 |
30189100752 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.630944486 |
|
|
Oct 03 04:18:01 AM UTC 24 |
Oct 03 04:18:03 AM UTC 24 |
29249890 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3446495204 |
|
|
Oct 03 04:18:01 AM UTC 24 |
Oct 03 04:18:03 AM UTC 24 |
61126416 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.2174630113 |
|
|
Oct 03 04:17:38 AM UTC 24 |
Oct 03 04:18:04 AM UTC 24 |
1829996640 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.83403458 |
|
|
Oct 03 04:17:48 AM UTC 24 |
Oct 03 04:18:04 AM UTC 24 |
6644129904 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1932927749 |
|
|
Oct 03 04:12:56 AM UTC 24 |
Oct 03 04:18:04 AM UTC 24 |
146046683027 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.4287017238 |
|
|
Oct 03 04:17:48 AM UTC 24 |
Oct 03 04:18:06 AM UTC 24 |
431911751 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2178482461 |
|
|
Oct 03 04:17:47 AM UTC 24 |
Oct 03 04:18:07 AM UTC 24 |
9080008303 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.4004863156 |
|
|
Oct 03 04:18:04 AM UTC 24 |
Oct 03 04:18:10 AM UTC 24 |
498744697 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.244512569 |
|
|
Oct 03 04:18:04 AM UTC 24 |
Oct 03 04:18:14 AM UTC 24 |
841330200 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1097682490 |
|
|
Oct 03 04:18:05 AM UTC 24 |
Oct 03 04:18:15 AM UTC 24 |
297072673 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.859491076 |
|
|
Oct 03 04:18:02 AM UTC 24 |
Oct 03 04:18:15 AM UTC 24 |
504265911 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.739663407 |
|
|
Oct 03 04:18:15 AM UTC 24 |
Oct 03 04:18:17 AM UTC 24 |
13437768 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2460354038 |
|
|
Oct 03 04:18:02 AM UTC 24 |
Oct 03 04:18:17 AM UTC 24 |
11103580286 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2579316568 |
|
|
Oct 03 04:18:16 AM UTC 24 |
Oct 03 04:18:18 AM UTC 24 |
15083533 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.1724666735 |
|
|
Oct 03 04:17:52 AM UTC 24 |
Oct 03 04:18:20 AM UTC 24 |
24574594547 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1452883356 |
|
|
Oct 03 04:18:18 AM UTC 24 |
Oct 03 04:18:20 AM UTC 24 |
353950433 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.3813391698 |
|
|
Oct 03 04:17:54 AM UTC 24 |
Oct 03 04:18:21 AM UTC 24 |
9961810994 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3000883552 |
|
|
Oct 03 04:13:29 AM UTC 24 |
Oct 03 04:18:23 AM UTC 24 |
38418743557 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2208369332 |
|
|
Oct 03 04:17:29 AM UTC 24 |
Oct 03 04:18:23 AM UTC 24 |
2464074048 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2349375900 |
|
|
Oct 03 04:18:21 AM UTC 24 |
Oct 03 04:18:28 AM UTC 24 |
170580851 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.3936843024 |
|
|
Oct 03 04:18:19 AM UTC 24 |
Oct 03 04:18:29 AM UTC 24 |
260346104 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.726857675 |
|
|
Oct 03 04:18:24 AM UTC 24 |
Oct 03 04:18:29 AM UTC 24 |
425257633 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.2970212243 |
|
|
Oct 03 04:17:43 AM UTC 24 |
Oct 03 04:18:31 AM UTC 24 |
5126513561 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.4277901145 |
|
|
Oct 03 04:18:21 AM UTC 24 |
Oct 03 04:18:32 AM UTC 24 |
2514971238 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2239682562 |
|
|
Oct 03 04:18:04 AM UTC 24 |
Oct 03 04:18:34 AM UTC 24 |
3000335299 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1468059849 |
|
|
Oct 03 04:18:16 AM UTC 24 |
Oct 03 04:18:34 AM UTC 24 |
6585690658 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.2321166645 |
|
|
Oct 03 04:17:31 AM UTC 24 |
Oct 03 04:18:39 AM UTC 24 |
4490737562 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.1449041937 |
|
|
Oct 03 04:15:43 AM UTC 24 |
Oct 03 04:18:40 AM UTC 24 |
263466523279 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1341439402 |
|
|
Oct 03 04:18:29 AM UTC 24 |
Oct 03 04:18:40 AM UTC 24 |
1136429875 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.1967610009 |
|
|
Oct 03 04:18:30 AM UTC 24 |
Oct 03 04:18:40 AM UTC 24 |
686636453 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.2418533 |
|
|
Oct 03 04:15:21 AM UTC 24 |
Oct 03 04:18:42 AM UTC 24 |
56363863045 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1966677449 |
|
|
Oct 03 04:11:14 AM UTC 24 |
Oct 03 04:18:43 AM UTC 24 |
72281991019 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.1365740891 |
|
|
Oct 03 04:18:41 AM UTC 24 |
Oct 03 04:18:43 AM UTC 24 |
13797194 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.1786898328 |
|
|
Oct 03 04:18:41 AM UTC 24 |
Oct 03 04:18:43 AM UTC 24 |
11941157 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.4284663311 |
|
|
Oct 03 04:08:50 AM UTC 24 |
Oct 03 04:18:45 AM UTC 24 |
62260238343 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.264855636 |
|
|
Oct 03 04:18:03 AM UTC 24 |
Oct 03 04:18:45 AM UTC 24 |
15501981236 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2292036297 |
|
|
Oct 03 04:18:43 AM UTC 24 |
Oct 03 04:18:45 AM UTC 24 |
117659763 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.1078420132 |
|
|
Oct 03 04:18:44 AM UTC 24 |
Oct 03 04:18:46 AM UTC 24 |
103361382 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.1798001088 |
|
|
Oct 03 04:18:18 AM UTC 24 |
Oct 03 04:18:47 AM UTC 24 |
4726668007 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.242250927 |
|
|
Oct 03 04:16:44 AM UTC 24 |
Oct 03 04:18:49 AM UTC 24 |
25131705421 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3836299386 |
|
|
Oct 03 04:18:32 AM UTC 24 |
Oct 03 04:18:50 AM UTC 24 |
15050512509 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.4266899569 |
|
|
Oct 03 04:18:01 AM UTC 24 |
Oct 03 04:18:50 AM UTC 24 |
5672137115 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.928204250 |
|
|
Oct 03 04:18:42 AM UTC 24 |
Oct 03 04:18:51 AM UTC 24 |
1672454689 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.112897892 |
|
|
Oct 03 04:18:44 AM UTC 24 |
Oct 03 04:18:52 AM UTC 24 |
227559555 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.2212801570 |
|
|
Oct 03 04:18:46 AM UTC 24 |
Oct 03 04:18:53 AM UTC 24 |
958992526 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.3671712056 |
|
|
Oct 03 04:18:45 AM UTC 24 |
Oct 03 04:18:53 AM UTC 24 |
131506900 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.629248247 |
|
|
Oct 03 04:12:39 AM UTC 24 |
Oct 03 04:18:53 AM UTC 24 |
125743366680 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3388568681 |
|
|
Oct 03 04:18:47 AM UTC 24 |
Oct 03 04:18:53 AM UTC 24 |
73132036 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.895806860 |
|
|
Oct 03 04:18:49 AM UTC 24 |
Oct 03 04:18:54 AM UTC 24 |
648265236 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.411304847 |
|
|
Oct 03 04:18:23 AM UTC 24 |
Oct 03 04:18:55 AM UTC 24 |
1928647986 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3009787023 |
|
|
Oct 03 04:18:54 AM UTC 24 |
Oct 03 04:18:56 AM UTC 24 |
51458007 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.645028647 |
|
|
Oct 03 04:18:54 AM UTC 24 |
Oct 03 04:18:56 AM UTC 24 |
40068620 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3695360210 |
|
|
Oct 03 04:18:42 AM UTC 24 |
Oct 03 04:18:57 AM UTC 24 |
3995171679 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3927527233 |
|
|
Oct 03 04:18:44 AM UTC 24 |
Oct 03 04:18:57 AM UTC 24 |
1770649583 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3456230202 |
|
|
Oct 03 04:18:57 AM UTC 24 |
Oct 03 04:18:59 AM UTC 24 |
45235330 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3408602295 |
|
|
Oct 03 04:18:46 AM UTC 24 |
Oct 03 04:18:59 AM UTC 24 |
864958520 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1685882617 |
|
|
Oct 03 04:18:58 AM UTC 24 |
Oct 03 04:19:00 AM UTC 24 |
39546970 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.358982159 |
|
|
Oct 03 04:18:21 AM UTC 24 |
Oct 03 04:19:02 AM UTC 24 |
43737541559 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1098707587 |
|
|
Oct 03 04:18:58 AM UTC 24 |
Oct 03 04:19:02 AM UTC 24 |
403182491 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1387330127 |
|
|
Oct 03 04:16:50 AM UTC 24 |
Oct 03 04:19:03 AM UTC 24 |
67610220423 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3881405336 |
|
|
Oct 03 04:18:58 AM UTC 24 |
Oct 03 04:19:06 AM UTC 24 |
1156015575 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.2069833777 |
|
|
Oct 03 04:15:24 AM UTC 24 |
Oct 03 04:19:06 AM UTC 24 |
16100490772 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.3231436264 |
|
|
Oct 03 04:18:58 AM UTC 24 |
Oct 03 04:19:06 AM UTC 24 |
1649761071 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.3521412488 |
|
|
Oct 03 04:10:32 AM UTC 24 |
Oct 03 04:19:07 AM UTC 24 |
51484744827 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.19220906 |
|
|
Oct 03 04:19:02 AM UTC 24 |
Oct 03 04:19:07 AM UTC 24 |
122679900 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2982227999 |
|
|
Oct 03 04:18:51 AM UTC 24 |
Oct 03 04:19:08 AM UTC 24 |
1154225701 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2727210262 |
|
|
Oct 03 04:18:50 AM UTC 24 |
Oct 03 04:19:09 AM UTC 24 |
559101945 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2745610120 |
|
|
Oct 03 04:18:54 AM UTC 24 |
Oct 03 04:19:10 AM UTC 24 |
4711489416 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1020852300 |
|
|
Oct 03 04:17:01 AM UTC 24 |
Oct 03 04:19:10 AM UTC 24 |
13509680088 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.812095245 |
|
|
Oct 03 04:19:09 AM UTC 24 |
Oct 03 04:19:11 AM UTC 24 |
88739302 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3304624219 |
|
|
Oct 03 04:19:09 AM UTC 24 |
Oct 03 04:19:11 AM UTC 24 |
33415932 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.3015230781 |
|
|
Oct 03 04:17:30 AM UTC 24 |
Oct 03 04:19:12 AM UTC 24 |
24310144265 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3811401028 |
|
|
Oct 03 04:19:11 AM UTC 24 |
Oct 03 04:19:14 AM UTC 24 |
1099377198 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.3472438386 |
|
|
Oct 03 04:19:11 AM UTC 24 |
Oct 03 04:19:14 AM UTC 24 |
37238142 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1020545019 |
|
|
Oct 03 04:19:09 AM UTC 24 |
Oct 03 04:19:15 AM UTC 24 |
910391483 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.4059694060 |
|
|
Oct 03 04:19:38 AM UTC 24 |
Oct 03 04:21:00 AM UTC 24 |
40098946580 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.444734972 |
|
|
Oct 03 04:14:24 AM UTC 24 |
Oct 03 04:19:16 AM UTC 24 |
23336276975 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1245591704 |
|
|
Oct 03 04:19:04 AM UTC 24 |
Oct 03 04:19:16 AM UTC 24 |
4158197940 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1352373358 |
|
|
Oct 03 04:14:58 AM UTC 24 |
Oct 03 04:19:19 AM UTC 24 |
46234993025 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3374569557 |
|
|
Oct 03 04:19:16 AM UTC 24 |
Oct 03 04:19:20 AM UTC 24 |
223733537 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3567700337 |
|
|
Oct 03 04:19:07 AM UTC 24 |
Oct 03 04:19:20 AM UTC 24 |
1870057664 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2600569241 |
|
|
Oct 03 04:17:43 AM UTC 24 |
Oct 03 04:19:21 AM UTC 24 |
6192120203 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1406702594 |
|
|
Oct 03 04:18:05 AM UTC 24 |
Oct 03 04:19:21 AM UTC 24 |
9844635763 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2444134313 |
|
|
Oct 03 04:19:12 AM UTC 24 |
Oct 03 04:19:21 AM UTC 24 |
778668016 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.626223813 |
|
|
Oct 03 04:18:11 AM UTC 24 |
Oct 03 04:19:24 AM UTC 24 |
18588059946 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.880533238 |
|
|
Oct 03 04:19:00 AM UTC 24 |
Oct 03 04:19:24 AM UTC 24 |
3475791656 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.3601095496 |
|
|
Oct 03 04:19:10 AM UTC 24 |
Oct 03 04:19:24 AM UTC 24 |
1254155152 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.568251389 |
|
|
Oct 03 04:19:22 AM UTC 24 |
Oct 03 04:19:25 AM UTC 24 |
98531908 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.407413239 |
|
|
Oct 03 04:19:24 AM UTC 24 |
Oct 03 04:19:27 AM UTC 24 |
56797915 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.3565943597 |
|
|
Oct 03 04:19:15 AM UTC 24 |
Oct 03 04:19:27 AM UTC 24 |
18732192043 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1289285723 |
|
|
Oct 03 04:19:26 AM UTC 24 |
Oct 03 04:19:28 AM UTC 24 |
53875375 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.1528215022 |
|
|
Oct 03 04:18:55 AM UTC 24 |
Oct 03 04:19:29 AM UTC 24 |
8626698290 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3418348252 |
|
|
Oct 03 04:19:24 AM UTC 24 |
Oct 03 04:19:29 AM UTC 24 |
2909190999 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.2912121365 |
|
|
Oct 03 04:19:28 AM UTC 24 |
Oct 03 04:19:30 AM UTC 24 |
416578072 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.982635121 |
|
|
Oct 03 04:19:12 AM UTC 24 |
Oct 03 04:19:31 AM UTC 24 |
1456407895 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3632294513 |
|
|
Oct 03 04:19:29 AM UTC 24 |
Oct 03 04:19:33 AM UTC 24 |
29884995 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1651439050 |
|
|
Oct 03 04:19:30 AM UTC 24 |
Oct 03 04:19:34 AM UTC 24 |
117696534 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.2731064601 |
|
|
Oct 03 04:18:08 AM UTC 24 |
Oct 03 04:19:34 AM UTC 24 |
2603752169 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.346387479 |
|
|
Oct 03 04:19:14 AM UTC 24 |
Oct 03 04:19:36 AM UTC 24 |
1032232158 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1264949452 |
|
|
Oct 03 04:19:35 AM UTC 24 |
Oct 03 04:19:37 AM UTC 24 |
38445350 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.3594340255 |
|
|
Oct 03 04:19:00 AM UTC 24 |
Oct 03 04:19:38 AM UTC 24 |
9866982645 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.2660230583 |
|
|
Oct 03 04:19:12 AM UTC 24 |
Oct 03 04:19:39 AM UTC 24 |
14950789259 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2186545058 |
|
|
Oct 03 04:19:32 AM UTC 24 |
Oct 03 04:19:40 AM UTC 24 |
2443715481 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3724479102 |
|
|
Oct 03 04:19:29 AM UTC 24 |
Oct 03 04:19:40 AM UTC 24 |
8132313177 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2324125911 |
|
|
Oct 03 04:19:35 AM UTC 24 |
Oct 03 04:19:41 AM UTC 24 |
148556532 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.1777988839 |
|
|
Oct 03 04:19:33 AM UTC 24 |
Oct 03 04:19:41 AM UTC 24 |
129558682 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3252186206 |
|
|
Oct 03 04:19:40 AM UTC 24 |
Oct 03 04:19:42 AM UTC 24 |
51224776 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1838095111 |
|
|
Oct 03 04:18:03 AM UTC 24 |
Oct 03 04:19:43 AM UTC 24 |
14942395926 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3749567290 |
|
|
Oct 03 04:19:41 AM UTC 24 |
Oct 03 04:19:44 AM UTC 24 |
18263178 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3806026431 |
|
|
Oct 03 04:18:53 AM UTC 24 |
Oct 03 04:19:44 AM UTC 24 |
8020031066 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.4022953100 |
|
|
Oct 03 04:19:24 AM UTC 24 |
Oct 03 04:19:45 AM UTC 24 |
2115353184 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2239404434 |
|
|
Oct 03 04:19:42 AM UTC 24 |
Oct 03 04:19:45 AM UTC 24 |
85116022 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.3705639878 |
|
|
Oct 03 04:19:20 AM UTC 24 |
Oct 03 04:19:45 AM UTC 24 |
3097663711 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.4046679787 |
|
|
Oct 03 04:18:04 AM UTC 24 |
Oct 03 04:19:46 AM UTC 24 |
26471970968 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.2758080354 |
|
|
Oct 03 04:19:31 AM UTC 24 |
Oct 03 04:19:46 AM UTC 24 |
2999985405 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.2402611892 |
|
|
Oct 03 04:19:43 AM UTC 24 |
Oct 03 04:19:47 AM UTC 24 |
66844342 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.3934168663 |
|
|
Oct 03 04:19:30 AM UTC 24 |
Oct 03 04:19:48 AM UTC 24 |
3485583334 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.373489013 |
|
|
Oct 03 04:12:07 AM UTC 24 |
Oct 03 04:19:49 AM UTC 24 |
81346874737 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.3799892785 |
|
|
Oct 03 04:19:46 AM UTC 24 |
Oct 03 04:19:51 AM UTC 24 |
616782943 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2727103700 |
|
|
Oct 03 04:19:44 AM UTC 24 |
Oct 03 04:19:52 AM UTC 24 |
1471196247 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.1651925175 |
|
|
Oct 03 04:19:47 AM UTC 24 |
Oct 03 04:19:52 AM UTC 24 |
98755959 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.680033743 |
|
|
Oct 03 04:19:48 AM UTC 24 |
Oct 03 04:19:53 AM UTC 24 |
418009428 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.2442062259 |
|
|
Oct 03 04:19:54 AM UTC 24 |
Oct 03 04:19:56 AM UTC 24 |
19508876 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3987737536 |
|
|
Oct 03 04:19:46 AM UTC 24 |
Oct 03 04:19:56 AM UTC 24 |
721626709 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.991787912 |
|
|
Oct 03 04:19:45 AM UTC 24 |
Oct 03 04:19:57 AM UTC 24 |
1372793516 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3731302295 |
|
|
Oct 03 04:19:41 AM UTC 24 |
Oct 03 04:20:01 AM UTC 24 |
4245156701 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2523620110 |
|
|
Oct 03 04:19:46 AM UTC 24 |
Oct 03 04:20:03 AM UTC 24 |
481251730 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.3796823886 |
|
|
Oct 03 04:18:35 AM UTC 24 |
Oct 03 04:20:03 AM UTC 24 |
5620737976 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.1905185759 |
|
|
Oct 03 04:19:45 AM UTC 24 |
Oct 03 04:20:06 AM UTC 24 |
8751689832 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1443434111 |
|
|
Oct 03 04:19:17 AM UTC 24 |
Oct 03 04:20:08 AM UTC 24 |
6666276779 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3545521421 |
|
|
Oct 03 04:19:39 AM UTC 24 |
Oct 03 04:20:12 AM UTC 24 |
14354806861 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3986612305 |
|
|
Oct 03 04:18:31 AM UTC 24 |
Oct 03 04:20:14 AM UTC 24 |
17042446760 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2784066370 |
|
|
Oct 03 04:16:16 AM UTC 24 |
Oct 03 04:20:23 AM UTC 24 |
249476516394 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.3631649941 |
|
|
Oct 03 04:14:43 AM UTC 24 |
Oct 03 04:20:27 AM UTC 24 |
188285612165 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3404488712 |
|
|
Oct 03 04:19:50 AM UTC 24 |
Oct 03 04:20:27 AM UTC 24 |
2297957903 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.4233724842 |
|
|
Oct 03 04:19:41 AM UTC 24 |
Oct 03 04:20:33 AM UTC 24 |
41308380154 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3476047620 |
|
|
Oct 03 04:16:14 AM UTC 24 |
Oct 03 04:20:36 AM UTC 24 |
209357846783 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2490161515 |
|
|
Oct 03 04:18:35 AM UTC 24 |
Oct 03 04:20:47 AM UTC 24 |
8604529101 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.4232370356 |
|
|
Oct 03 04:17:01 AM UTC 24 |
Oct 03 04:20:50 AM UTC 24 |
22923481657 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.521615135 |
|
|
Oct 03 04:19:06 AM UTC 24 |
Oct 03 04:20:50 AM UTC 24 |
31560878710 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.276273240 |
|
|
Oct 03 04:19:21 AM UTC 24 |
Oct 03 04:20:58 AM UTC 24 |
12101428617 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1965250501 |
|
|
Oct 03 04:19:51 AM UTC 24 |
Oct 03 04:21:02 AM UTC 24 |
6072592794 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1302442938 |
|
|
Oct 03 04:15:23 AM UTC 24 |
Oct 03 04:21:08 AM UTC 24 |
31880965477 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2338102977 |
|
|
Oct 03 04:19:17 AM UTC 24 |
Oct 03 04:21:13 AM UTC 24 |
17999192372 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.684652400 |
|
|
Oct 03 04:14:58 AM UTC 24 |
Oct 03 04:21:19 AM UTC 24 |
265098168248 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.151922364 |
|
|
Oct 03 04:18:33 AM UTC 24 |
Oct 03 04:21:26 AM UTC 24 |
21955316311 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.831741362 |
|
|
Oct 03 04:19:47 AM UTC 24 |
Oct 03 04:21:26 AM UTC 24 |
34077279343 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.978643916 |
|
|
Oct 03 04:19:21 AM UTC 24 |
Oct 03 04:21:27 AM UTC 24 |
16126164919 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1106887355 |
|
|
Oct 03 04:19:08 AM UTC 24 |
Oct 03 04:21:32 AM UTC 24 |
10461595611 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.112362679 |
|
|
Oct 03 04:09:14 AM UTC 24 |
Oct 03 04:21:40 AM UTC 24 |
63346358013 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2709959558 |
|
|
Oct 03 04:12:18 AM UTC 24 |
Oct 03 04:21:42 AM UTC 24 |
59489895295 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2142135143 |
|
|
Oct 03 04:19:39 AM UTC 24 |
Oct 03 04:21:45 AM UTC 24 |
33761417582 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3085606175 |
|
|
Oct 03 04:18:52 AM UTC 24 |
Oct 03 04:21:47 AM UTC 24 |
106434978321 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.861605013 |
|
|
Oct 03 04:18:06 AM UTC 24 |
Oct 03 04:21:48 AM UTC 24 |
25892240984 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.4277955050 |
|
|
Oct 03 04:09:13 AM UTC 24 |
Oct 03 04:22:38 AM UTC 24 |
377185995010 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.568844727 |
|
|
Oct 03 04:18:51 AM UTC 24 |
Oct 03 04:22:42 AM UTC 24 |
63033121018 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1854896653 |
|
|
Oct 03 04:17:43 AM UTC 24 |
Oct 03 04:22:47 AM UTC 24 |
43085446397 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.1402908973 |
|
|
Oct 03 04:17:51 AM UTC 24 |
Oct 03 04:23:07 AM UTC 24 |
32752063855 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2412342829 |
|
|
Oct 03 04:17:55 AM UTC 24 |
Oct 03 04:23:15 AM UTC 24 |
23875349726 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1008266927 |
|
|
Oct 03 04:16:29 AM UTC 24 |
Oct 03 04:23:15 AM UTC 24 |
32088775755 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.1218921212 |
|
|
Oct 03 04:19:49 AM UTC 24 |
Oct 03 04:23:19 AM UTC 24 |
23719659975 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.4121468535 |
|
|
Oct 03 04:13:55 AM UTC 24 |
Oct 03 04:23:22 AM UTC 24 |
118402677496 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.668953280 |
|
|
Oct 03 04:19:03 AM UTC 24 |
Oct 03 04:23:43 AM UTC 24 |
73132436937 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.3693409918 |
|
|
Oct 03 04:19:08 AM UTC 24 |
Oct 03 04:23:57 AM UTC 24 |
65225139935 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2870522404 |
|
|
Oct 03 04:19:22 AM UTC 24 |
Oct 03 04:24:03 AM UTC 24 |
81415114842 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2794390729 |
|
|
Oct 03 04:18:54 AM UTC 24 |
Oct 03 04:24:41 AM UTC 24 |
61225878134 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.3077134436 |
|
|
Oct 03 04:10:01 AM UTC 24 |
Oct 03 04:25:19 AM UTC 24 |
77483296530 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1556729569 |
|
|
Oct 03 04:18:39 AM UTC 24 |
Oct 03 04:25:32 AM UTC 24 |
32461467400 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.3381763071 |
|
|
Oct 03 04:19:22 AM UTC 24 |
Oct 03 04:25:43 AM UTC 24 |
54443090177 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.3313402726 |
|
|
Oct 03 04:13:57 AM UTC 24 |
Oct 03 04:25:56 AM UTC 24 |
64398221827 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3194664155 |
|
|
Oct 03 04:17:38 AM UTC 24 |
Oct 03 04:26:11 AM UTC 24 |
173920408503 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.107263699 |
|
|
Oct 03 04:17:32 AM UTC 24 |
Oct 03 04:27:13 AM UTC 24 |
116652900749 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.2791886994 |
|
|
Oct 03 04:19:40 AM UTC 24 |
Oct 03 04:28:34 AM UTC 24 |
187251549612 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.4096697445 |
|
|
Oct 03 04:14:42 AM UTC 24 |
Oct 03 04:29:06 AM UTC 24 |
1496172257193 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.501133455 |
|
|
Oct 03 04:16:16 AM UTC 24 |
Oct 03 04:29:30 AM UTC 24 |
720896723163 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.3142665370 |
|
|
Oct 03 04:15:49 AM UTC 24 |
Oct 03 04:30:18 AM UTC 24 |
716416349526 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1389925937 |
|
|
Oct 03 04:19:52 AM UTC 24 |
Oct 03 04:34:03 AM UTC 24 |
183345377962 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2599577093 |
|
|
Oct 03 04:19:54 AM UTC 24 |
Oct 03 04:19:58 AM UTC 24 |
338818648 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.664150296 |
|
|
Oct 03 04:19:58 AM UTC 24 |
Oct 03 04:20:00 AM UTC 24 |
211653642 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.380995252 |
|
|
Oct 03 04:19:58 AM UTC 24 |
Oct 03 04:20:00 AM UTC 24 |
12542133 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1488455684 |
|
|
Oct 03 04:19:59 AM UTC 24 |
Oct 03 04:20:02 AM UTC 24 |
32426353 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3249596355 |
|
|
Oct 03 04:20:01 AM UTC 24 |
Oct 03 04:20:04 AM UTC 24 |
40667972 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.327876244 |
|
|
Oct 03 04:20:01 AM UTC 24 |
Oct 03 04:20:06 AM UTC 24 |
153224004 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2485616046 |
|
|
Oct 03 04:20:07 AM UTC 24 |
Oct 03 04:20:09 AM UTC 24 |
41483148 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4258475478 |
|
|
Oct 03 04:20:05 AM UTC 24 |
Oct 03 04:20:10 AM UTC 24 |
183934126 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4182711757 |
|
|
Oct 03 04:20:03 AM UTC 24 |
Oct 03 04:20:10 AM UTC 24 |
164687666 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.4072222454 |
|
|
Oct 03 04:20:06 AM UTC 24 |
Oct 03 04:20:10 AM UTC 24 |
94123612 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.576125226 |
|
|
Oct 03 04:20:09 AM UTC 24 |
Oct 03 04:20:11 AM UTC 24 |
35405664 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1185280266 |
|
|
Oct 03 04:20:10 AM UTC 24 |
Oct 03 04:20:14 AM UTC 24 |
25104934 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1215320783 |
|
|
Oct 03 04:20:11 AM UTC 24 |
Oct 03 04:20:14 AM UTC 24 |
21067013 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2660411133 |
|
|
Oct 03 04:20:11 AM UTC 24 |
Oct 03 04:20:15 AM UTC 24 |
28839680 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3694893348 |
|
|
Oct 03 04:20:13 AM UTC 24 |
Oct 03 04:20:17 AM UTC 24 |
104656656 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1819841620 |
|
|
Oct 03 04:20:16 AM UTC 24 |
Oct 03 04:20:18 AM UTC 24 |
88152233 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2034662337 |
|
|
Oct 03 04:20:14 AM UTC 24 |
Oct 03 04:20:19 AM UTC 24 |
91165240 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3334662027 |
|
|
Oct 03 04:20:02 AM UTC 24 |
Oct 03 04:20:19 AM UTC 24 |
188140630 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1239610661 |
|
|
Oct 03 04:20:18 AM UTC 24 |
Oct 03 04:20:20 AM UTC 24 |
11448340 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.827381992 |
|
|
Oct 03 04:20:14 AM UTC 24 |
Oct 03 04:20:21 AM UTC 24 |
141034261 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1344456248 |
|
|
Oct 03 04:20:19 AM UTC 24 |
Oct 03 04:20:22 AM UTC 24 |
17300046 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1821120341 |
|
|
Oct 03 04:20:20 AM UTC 24 |
Oct 03 04:20:23 AM UTC 24 |
62623336 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2321884249 |
|
|
Oct 03 04:20:20 AM UTC 24 |
Oct 03 04:20:23 AM UTC 24 |
34803883 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4167392733 |
|
|
Oct 03 04:20:11 AM UTC 24 |
Oct 03 04:20:26 AM UTC 24 |
184905478 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.711366031 |
|
|
Oct 03 04:19:57 AM UTC 24 |
Oct 03 04:20:27 AM UTC 24 |
1691221707 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2966312166 |
|
|
Oct 03 04:20:07 AM UTC 24 |
Oct 03 04:20:28 AM UTC 24 |
4149163537 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3101930449 |
|
|
Oct 03 04:20:23 AM UTC 24 |
Oct 03 04:20:28 AM UTC 24 |
434253228 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.362303141 |
|
|
Oct 03 04:20:27 AM UTC 24 |
Oct 03 04:20:29 AM UTC 24 |
27506345 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2998790962 |
|
|
Oct 03 04:20:28 AM UTC 24 |
Oct 03 04:20:30 AM UTC 24 |
25542621 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4257850752 |
|
|
Oct 03 04:20:23 AM UTC 24 |
Oct 03 04:20:31 AM UTC 24 |
829374383 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2704861607 |
|
|
Oct 03 04:20:29 AM UTC 24 |
Oct 03 04:20:31 AM UTC 24 |
16878632 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.4122380618 |
|
|
Oct 03 04:20:28 AM UTC 24 |
Oct 03 04:20:32 AM UTC 24 |
94380511 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2876699624 |
|
|
Oct 03 04:20:24 AM UTC 24 |
Oct 03 04:20:33 AM UTC 24 |
818327835 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.116822762 |
|
|
Oct 03 04:20:29 AM UTC 24 |
Oct 03 04:20:33 AM UTC 24 |
121384995 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.865303404 |
|
|
Oct 03 04:20:16 AM UTC 24 |
Oct 03 04:20:35 AM UTC 24 |
3667675944 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.216353021 |
|
|
Oct 03 04:20:31 AM UTC 24 |
Oct 03 04:20:35 AM UTC 24 |
297406583 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.248172648 |
|
|
Oct 03 04:20:31 AM UTC 24 |
Oct 03 04:20:35 AM UTC 24 |
55383713 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2694216521 |
|
|
Oct 03 04:20:02 AM UTC 24 |
Oct 03 04:20:35 AM UTC 24 |
4450650562 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.1452635387 |
|
|
Oct 03 04:20:34 AM UTC 24 |
Oct 03 04:20:36 AM UTC 24 |
34394272 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3805130164 |
|
|
Oct 03 04:20:34 AM UTC 24 |
Oct 03 04:20:36 AM UTC 24 |
15136218 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2090708769 |
|
|
Oct 03 04:20:12 AM UTC 24 |
Oct 03 04:20:37 AM UTC 24 |
595920876 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3387492623 |
|
|
Oct 03 04:20:33 AM UTC 24 |
Oct 03 04:20:37 AM UTC 24 |
98883215 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1525104218 |
|
|
Oct 03 04:20:34 AM UTC 24 |
Oct 03 04:20:39 AM UTC 24 |
271279012 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3875267215 |
|
|
Oct 03 04:20:36 AM UTC 24 |
Oct 03 04:20:39 AM UTC 24 |
44765529 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2077025238 |
|
|
Oct 03 04:20:36 AM UTC 24 |
Oct 03 04:20:40 AM UTC 24 |
89019248 ps |