| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.06 | 98.38 | 94.01 | 98.62 | 89.36 | 97.19 | 95.57 | 99.26 |
| T1020 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1479318085 | Oct 03 04:20:39 AM UTC 24 | Oct 03 04:20:41 AM UTC 24 | 25159294 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3509041427 | Oct 03 04:20:37 AM UTC 24 | Oct 03 04:20:42 AM UTC 24 | 58853594 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.2264332149 | Oct 03 04:20:21 AM UTC 24 | Oct 03 04:20:42 AM UTC 24 | 636981873 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1326514401 | Oct 03 04:20:29 AM UTC 24 | Oct 03 04:20:43 AM UTC 24 | 903916222 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.4266873680 | Oct 03 04:20:38 AM UTC 24 | Oct 03 04:20:43 AM UTC 24 | 50876458 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.2424783755 | Oct 03 04:20:30 AM UTC 24 | Oct 03 04:20:44 AM UTC 24 | 1239096433 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.148440435 | Oct 03 04:20:38 AM UTC 24 | Oct 03 04:20:44 AM UTC 24 | 650214038 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3554939926 | Oct 03 04:20:40 AM UTC 24 | Oct 03 04:20:44 AM UTC 24 | 81188237 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1457731844 | Oct 03 04:20:41 AM UTC 24 | Oct 03 04:20:45 AM UTC 24 | 113373807 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.58769995 | Oct 03 04:20:44 AM UTC 24 | Oct 03 04:20:46 AM UTC 24 | 11007780 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2003981176 | Oct 03 04:20:40 AM UTC 24 | Oct 03 04:20:47 AM UTC 24 | 707154923 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.4289204731 | Oct 03 04:20:42 AM UTC 24 | Oct 03 04:20:47 AM UTC 24 | 39598879 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.799165121 | Oct 03 04:20:21 AM UTC 24 | Oct 03 04:20:48 AM UTC 24 | 720444076 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1727507006 | Oct 03 04:20:46 AM UTC 24 | Oct 03 04:20:48 AM UTC 24 | 15669572 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1478146859 | Oct 03 04:20:44 AM UTC 24 | Oct 03 04:20:48 AM UTC 24 | 104608830 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.515837870 | Oct 03 04:20:33 AM UTC 24 | Oct 03 04:20:49 AM UTC 24 | 1721342296 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3541925789 | Oct 03 04:20:45 AM UTC 24 | Oct 03 04:20:49 AM UTC 24 | 1412818731 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1653560999 | Oct 03 04:20:48 AM UTC 24 | Oct 03 04:20:50 AM UTC 24 | 559481571 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1065849240 | Oct 03 04:20:42 AM UTC 24 | Oct 03 04:20:51 AM UTC 24 | 108994483 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3731381394 | Oct 03 04:20:45 AM UTC 24 | Oct 03 04:20:51 AM UTC 24 | 212938891 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.1697326297 | Oct 03 04:20:47 AM UTC 24 | Oct 03 04:20:51 AM UTC 24 | 53608040 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.393742413 | Oct 03 04:20:45 AM UTC 24 | Oct 03 04:20:51 AM UTC 24 | 173581431 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2896080990 | Oct 03 04:20:49 AM UTC 24 | Oct 03 04:20:52 AM UTC 24 | 128950356 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.4063598448 | Oct 03 04:20:50 AM UTC 24 | Oct 03 04:20:52 AM UTC 24 | 33782697 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2195535761 | Oct 03 04:20:47 AM UTC 24 | Oct 03 04:20:52 AM UTC 24 | 2117987895 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1269740036 | Oct 03 04:20:25 AM UTC 24 | Oct 03 04:20:53 AM UTC 24 | 7565717015 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4268112285 | Oct 03 04:20:52 AM UTC 24 | Oct 03 04:20:54 AM UTC 24 | 13679365 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2005985973 | Oct 03 04:20:50 AM UTC 24 | Oct 03 04:20:54 AM UTC 24 | 153204708 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.3506225387 | Oct 03 04:20:51 AM UTC 24 | Oct 03 04:20:55 AM UTC 24 | 242168636 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3818260244 | Oct 03 04:20:50 AM UTC 24 | Oct 03 04:20:55 AM UTC 24 | 92043064 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.190425152 | Oct 03 04:20:52 AM UTC 24 | Oct 03 04:20:55 AM UTC 24 | 107923009 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3236165797 | Oct 03 04:20:53 AM UTC 24 | Oct 03 04:20:55 AM UTC 24 | 67285379 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1224338390 | Oct 03 04:20:50 AM UTC 24 | Oct 03 04:20:56 AM UTC 24 | 627351200 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2909008459 | Oct 03 04:20:38 AM UTC 24 | Oct 03 04:20:57 AM UTC 24 | 1052494367 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.1519094936 | Oct 03 04:20:49 AM UTC 24 | Oct 03 04:20:57 AM UTC 24 | 207496021 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2482713997 | Oct 03 04:20:53 AM UTC 24 | Oct 03 04:20:57 AM UTC 24 | 116087090 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1503702889 | Oct 03 04:20:53 AM UTC 24 | Oct 03 04:20:58 AM UTC 24 | 108461215 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3498727748 | Oct 03 04:20:56 AM UTC 24 | Oct 03 04:20:58 AM UTC 24 | 14472942 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.637737164 | Oct 03 04:20:53 AM UTC 24 | Oct 03 04:20:59 AM UTC 24 | 164641718 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.447843937 | Oct 03 04:20:55 AM UTC 24 | Oct 03 04:20:59 AM UTC 24 | 282991218 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.867058979 | Oct 03 04:20:56 AM UTC 24 | Oct 03 04:20:59 AM UTC 24 | 28467378 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3915162997 | Oct 03 04:20:55 AM UTC 24 | Oct 03 04:20:59 AM UTC 24 | 1905483313 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.382280199 | Oct 03 04:20:56 AM UTC 24 | Oct 03 04:20:59 AM UTC 24 | 149581848 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3209976623 | Oct 03 04:20:56 AM UTC 24 | Oct 03 04:21:00 AM UTC 24 | 70576996 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2137994072 | Oct 03 04:20:58 AM UTC 24 | Oct 03 04:21:00 AM UTC 24 | 23063830 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1155405187 | Oct 03 04:20:53 AM UTC 24 | Oct 03 04:21:00 AM UTC 24 | 109635226 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2187595474 | Oct 03 04:20:58 AM UTC 24 | Oct 03 04:21:02 AM UTC 24 | 509429426 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3193289413 | Oct 03 04:20:59 AM UTC 24 | Oct 03 04:21:02 AM UTC 24 | 374430476 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.3340092657 | Oct 03 04:20:58 AM UTC 24 | Oct 03 04:21:02 AM UTC 24 | 137250404 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2198109158 | Oct 03 04:21:01 AM UTC 24 | Oct 03 04:21:03 AM UTC 24 | 105481651 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3027594512 | Oct 03 04:20:59 AM UTC 24 | Oct 03 04:21:03 AM UTC 24 | 79144195 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.121568940 | Oct 03 04:21:01 AM UTC 24 | Oct 03 04:21:04 AM UTC 24 | 109710774 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1522961819 | Oct 03 04:21:01 AM UTC 24 | Oct 03 04:21:04 AM UTC 24 | 90482963 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.4173505859 | Oct 03 04:21:02 AM UTC 24 | Oct 03 04:21:05 AM UTC 24 | 15053893 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4160407218 | Oct 03 04:21:01 AM UTC 24 | Oct 03 04:21:05 AM UTC 24 | 244863696 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3943529935 | Oct 03 04:20:59 AM UTC 24 | Oct 03 04:21:06 AM UTC 24 | 152741314 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.3194143559 | Oct 03 04:20:52 AM UTC 24 | Oct 03 04:21:06 AM UTC 24 | 1128695325 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2342462540 | Oct 03 04:21:04 AM UTC 24 | Oct 03 04:21:06 AM UTC 24 | 259948020 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2238038 | Oct 03 04:20:45 AM UTC 24 | Oct 03 04:21:06 AM UTC 24 | 597103475 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3400579561 | Oct 03 04:21:04 AM UTC 24 | Oct 03 04:21:07 AM UTC 24 | 320992610 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2031233685 | Oct 03 04:21:01 AM UTC 24 | Oct 03 04:21:07 AM UTC 24 | 213020058 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3286802964 | Oct 03 04:21:01 AM UTC 24 | Oct 03 04:21:07 AM UTC 24 | 177852723 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4027185694 | Oct 03 04:20:36 AM UTC 24 | Oct 03 04:21:07 AM UTC 24 | 1246003083 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3029751103 | Oct 03 04:21:04 AM UTC 24 | Oct 03 04:21:08 AM UTC 24 | 331131870 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.3599998839 | Oct 03 04:21:04 AM UTC 24 | Oct 03 04:21:08 AM UTC 24 | 263545921 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.603583153 | Oct 03 04:21:06 AM UTC 24 | Oct 03 04:21:09 AM UTC 24 | 84096117 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2418072703 | Oct 03 04:21:07 AM UTC 24 | Oct 03 04:21:09 AM UTC 24 | 13075179 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2159273287 | Oct 03 04:21:06 AM UTC 24 | Oct 03 04:21:10 AM UTC 24 | 36317617 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.902989650 | Oct 03 04:21:04 AM UTC 24 | Oct 03 04:21:10 AM UTC 24 | 605975025 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2067701437 | Oct 03 04:21:06 AM UTC 24 | Oct 03 04:21:10 AM UTC 24 | 274493639 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4082697301 | Oct 03 04:21:06 AM UTC 24 | Oct 03 04:21:10 AM UTC 24 | 482261641 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2477423013 | Oct 03 04:21:08 AM UTC 24 | Oct 03 04:21:11 AM UTC 24 | 101355279 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.547044299 | Oct 03 04:21:09 AM UTC 24 | Oct 03 04:21:11 AM UTC 24 | 31336690 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3649583306 | Oct 03 04:20:36 AM UTC 24 | Oct 03 04:21:12 AM UTC 24 | 4957493649 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.64205813 | Oct 03 04:21:07 AM UTC 24 | Oct 03 04:21:12 AM UTC 24 | 88840455 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.304009542 | Oct 03 04:21:09 AM UTC 24 | Oct 03 04:21:12 AM UTC 24 | 28580938 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.655966329 | Oct 03 04:21:11 AM UTC 24 | Oct 03 04:21:13 AM UTC 24 | 40629359 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3075890883 | Oct 03 04:21:09 AM UTC 24 | Oct 03 04:21:13 AM UTC 24 | 950992951 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.155780924 | Oct 03 04:21:04 AM UTC 24 | Oct 03 04:21:14 AM UTC 24 | 414862555 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1935633000 | Oct 03 04:21:07 AM UTC 24 | Oct 03 04:21:14 AM UTC 24 | 64290487 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3563759949 | Oct 03 04:20:53 AM UTC 24 | Oct 03 04:21:14 AM UTC 24 | 8981021749 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2843603818 | Oct 03 04:21:09 AM UTC 24 | Oct 03 04:21:14 AM UTC 24 | 75091751 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2793361884 | Oct 03 04:21:09 AM UTC 24 | Oct 03 04:21:15 AM UTC 24 | 562526325 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.4083811900 | Oct 03 04:21:11 AM UTC 24 | Oct 03 04:21:15 AM UTC 24 | 94126151 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.1508040632 | Oct 03 04:21:12 AM UTC 24 | Oct 03 04:21:16 AM UTC 24 | 75699250 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.364533608 | Oct 03 04:20:58 AM UTC 24 | Oct 03 04:21:16 AM UTC 24 | 555539462 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.2660926508 | Oct 03 04:21:14 AM UTC 24 | Oct 03 04:21:16 AM UTC 24 | 72725127 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.738470872 | Oct 03 04:21:13 AM UTC 24 | Oct 03 04:21:17 AM UTC 24 | 173548052 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1878057339 | Oct 03 04:21:15 AM UTC 24 | Oct 03 04:21:17 AM UTC 24 | 27743333 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3507026450 | Oct 03 04:21:14 AM UTC 24 | Oct 03 04:21:17 AM UTC 24 | 38346566 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.2432077481 | Oct 03 04:21:14 AM UTC 24 | Oct 03 04:21:17 AM UTC 24 | 84777800 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1175703951 | Oct 03 04:20:56 AM UTC 24 | Oct 03 04:21:18 AM UTC 24 | 828648244 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2785648436 | Oct 03 04:21:13 AM UTC 24 | Oct 03 04:21:18 AM UTC 24 | 378902169 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2018179695 | Oct 03 04:21:12 AM UTC 24 | Oct 03 04:21:18 AM UTC 24 | 103961613 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.2712457844 | Oct 03 04:21:16 AM UTC 24 | Oct 03 04:21:18 AM UTC 24 | 122770700 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2476656756 | Oct 03 04:21:16 AM UTC 24 | Oct 03 04:21:18 AM UTC 24 | 47308780 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.429796571 | Oct 03 04:21:16 AM UTC 24 | Oct 03 04:21:18 AM UTC 24 | 12044095 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1629795580 | Oct 03 04:21:17 AM UTC 24 | Oct 03 04:21:19 AM UTC 24 | 67161066 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.1963053311 | Oct 03 04:21:16 AM UTC 24 | Oct 03 04:21:19 AM UTC 24 | 39308683 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3141074327 | Oct 03 04:21:17 AM UTC 24 | Oct 03 04:21:19 AM UTC 24 | 49023444 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2929260010 | Oct 03 04:21:17 AM UTC 24 | Oct 03 04:21:19 AM UTC 24 | 38562139 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2102454857 | Oct 03 04:21:14 AM UTC 24 | Oct 03 04:21:19 AM UTC 24 | 167219649 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.265796202 | Oct 03 04:21:14 AM UTC 24 | Oct 03 04:21:20 AM UTC 24 | 145761722 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1777921510 | Oct 03 04:21:01 AM UTC 24 | Oct 03 04:21:20 AM UTC 24 | 536999263 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.2023471344 | Oct 03 04:21:19 AM UTC 24 | Oct 03 04:21:21 AM UTC 24 | 16299092 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2672545286 | Oct 03 04:21:19 AM UTC 24 | Oct 03 04:21:21 AM UTC 24 | 19980073 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.492493084 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:21 AM UTC 24 | 61204972 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3027934348 | Oct 03 04:21:19 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 12902354 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.774502447 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 53957543 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.3865367732 | Oct 03 04:21:19 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 54047597 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1402653222 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 35867636 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.754008567 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 14070542 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.3856624340 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 33744427 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.735927301 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 11820017 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.4223288361 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 13417438 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.2217255571 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 48700476 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.762562156 | Oct 03 04:21:20 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 67842094 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1118579095 | Oct 03 04:21:02 AM UTC 24 | Oct 03 04:21:22 AM UTC 24 | 869073623 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1575121414 | Oct 03 04:21:11 AM UTC 24 | Oct 03 04:21:24 AM UTC 24 | 368483194 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3334514825 | Oct 03 04:21:23 AM UTC 24 | Oct 03 04:21:25 AM UTC 24 | 44230413 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3472451788 | Oct 03 04:21:23 AM UTC 24 | Oct 03 04:21:25 AM UTC 24 | 15892198 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2118935541 | Oct 03 04:21:23 AM UTC 24 | Oct 03 04:21:25 AM UTC 24 | 47819248 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1007319147 | Oct 03 04:21:23 AM UTC 24 | Oct 03 04:21:25 AM UTC 24 | 47554672 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.3083944895 | Oct 03 04:21:23 AM UTC 24 | Oct 03 04:21:25 AM UTC 24 | 11252218 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2004405863 | Oct 03 04:21:23 AM UTC 24 | Oct 03 04:21:25 AM UTC 24 | 73334475 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1268700320 | Oct 03 04:21:23 AM UTC 24 | Oct 03 04:21:25 AM UTC 24 | 15208901 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.579697769 | Oct 03 04:21:23 AM UTC 24 | Oct 03 04:21:25 AM UTC 24 | 36481273 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2986899492 | Oct 03 04:21:09 AM UTC 24 | Oct 03 04:21:33 AM UTC 24 | 1635644376 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.474988845 | Oct 03 04:21:07 AM UTC 24 | Oct 03 04:21:34 AM UTC 24 | 1071936970 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.3899187418 | Oct 03 04:21:13 AM UTC 24 | Oct 03 04:21:38 AM UTC 24 | 4094234149 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2746059100 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2341415792 ps |
| CPU time | 10 seconds |
| Started | Oct 03 03:54:47 AM UTC 24 |
| Finished | Oct 03 03:54:58 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746059100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2746059100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3729279299 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3684974914 ps |
| CPU time | 87.06 seconds |
| Started | Oct 03 03:55:43 AM UTC 24 |
| Finished | Oct 03 03:57:13 AM UTC 24 |
| Peak memory | 268096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729279299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.3729279299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2133302017 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5775693493 ps |
| CPU time | 151.01 seconds |
| Started | Oct 03 03:58:56 AM UTC 24 |
| Finished | Oct 03 04:01:30 AM UTC 24 |
| Peak memory | 277948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133302017 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.2133302017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.1410471423 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 11830534504 ps |
| CPU time | 60.66 seconds |
| Started | Oct 03 04:06:32 AM UTC 24 |
| Finished | Oct 03 04:07:34 AM UTC 24 |
| Peak memory | 268028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410471423 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.1410471423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3101930449 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 434253228 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 04:20:23 AM UTC 24 |
| Finished | Oct 03 04:20:28 AM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3101930449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.spi_device_csr_mem_rw_with_rand_reset.3101930449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2667278595 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 85145954840 ps |
| CPU time | 903.18 seconds |
| Started | Oct 03 03:55:58 AM UTC 24 |
| Finished | Oct 03 04:11:13 AM UTC 24 |
| Peak memory | 278208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667278595 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.2667278595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3316888656 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 41524342531 ps |
| CPU time | 136.53 seconds |
| Started | Oct 03 04:05:20 AM UTC 24 |
| Finished | Oct 03 04:07:39 AM UTC 24 |
| Peak memory | 265920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316888656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.3316888656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.3284714323 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 16919047 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 03:54:29 AM UTC 24 |
| Finished | Oct 03 03:54:32 AM UTC 24 |
| Peak memory | 226864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284714323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3284714323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3714167762 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 12533155517 ps |
| CPU time | 138.19 seconds |
| Started | Oct 03 04:02:54 AM UTC 24 |
| Finished | Oct 03 04:05:14 AM UTC 24 |
| Peak memory | 278016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714167762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3714167762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.793799751 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 12133934021 ps |
| CPU time | 196.66 seconds |
| Started | Oct 03 04:04:31 AM UTC 24 |
| Finished | Oct 03 04:07:51 AM UTC 24 |
| Peak memory | 277960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793799751 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.793799751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2917987464 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 424447272 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 03:56:37 AM UTC 24 |
| Finished | Oct 03 03:56:39 AM UTC 24 |
| Peak memory | 256992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917987464 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2917987464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3228129967 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5736839345 ps |
| CPU time | 125.79 seconds |
| Started | Oct 03 03:59:44 AM UTC 24 |
| Finished | Oct 03 04:01:53 AM UTC 24 |
| Peak memory | 265540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228129967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3228129967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1175684968 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 14027546587 ps |
| CPU time | 197.55 seconds |
| Started | Oct 03 04:05:18 AM UTC 24 |
| Finished | Oct 03 04:08:39 AM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175684968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1175684968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.3146807709 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2010764260 ps |
| CPU time | 34.82 seconds |
| Started | Oct 03 03:55:06 AM UTC 24 |
| Finished | Oct 03 03:55:42 AM UTC 24 |
| Peak memory | 251392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146807709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3146807709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.16614784 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3247614791 ps |
| CPU time | 39.87 seconds |
| Started | Oct 03 03:56:53 AM UTC 24 |
| Finished | Oct 03 03:57:35 AM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16614784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.16614784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1989592719 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 9101379800 ps |
| CPU time | 164.13 seconds |
| Started | Oct 03 04:02:49 AM UTC 24 |
| Finished | Oct 03 04:05:36 AM UTC 24 |
| Peak memory | 267648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989592719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.1989592719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.865303404 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3667675944 ps |
| CPU time | 18 seconds |
| Started | Oct 03 04:20:16 AM UTC 24 |
| Finished | Oct 03 04:20:35 AM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865303404 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.865303404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.2720353333 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 24483151651 ps |
| CPU time | 252.76 seconds |
| Started | Oct 03 04:07:33 AM UTC 24 |
| Finished | Oct 03 04:11:50 AM UTC 24 |
| Peak memory | 267708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720353333 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.2720353333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1498899859 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 52018752097 ps |
| CPU time | 225.52 seconds |
| Started | Oct 03 04:01:11 AM UTC 24 |
| Finished | Oct 03 04:05:00 AM UTC 24 |
| Peak memory | 267968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498899859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.1498899859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2876699624 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 818327835 ps |
| CPU time | 7.09 seconds |
| Started | Oct 03 04:20:24 AM UTC 24 |
| Finished | Oct 03 04:20:33 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876699624 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2876699624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2694216521 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 4450650562 ps |
| CPU time | 31.13 seconds |
| Started | Oct 03 04:20:02 AM UTC 24 |
| Finished | Oct 03 04:20:35 AM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694216521 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.2694216521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2031177663 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12621026615 ps |
| CPU time | 137.83 seconds |
| Started | Oct 03 03:57:30 AM UTC 24 |
| Finished | Oct 03 03:59:50 AM UTC 24 |
| Peak memory | 265588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031177663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.2031177663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.871401183 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 5088658264 ps |
| CPU time | 101.64 seconds |
| Started | Oct 03 04:14:39 AM UTC 24 |
| Finished | Oct 03 04:16:23 AM UTC 24 |
| Peak memory | 281920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871401183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.871401183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2877601826 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 112990401351 ps |
| CPU time | 568.9 seconds |
| Started | Oct 03 04:07:55 AM UTC 24 |
| Finished | Oct 03 04:17:31 AM UTC 24 |
| Peak memory | 267704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877601826 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.2877601826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1867608671 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 16737510381 ps |
| CPU time | 99.98 seconds |
| Started | Oct 03 04:01:00 AM UTC 24 |
| Finished | Oct 03 04:02:42 AM UTC 24 |
| Peak memory | 267584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867608671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.1867608671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3896748805 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 8942186937 ps |
| CPU time | 113.07 seconds |
| Started | Oct 03 04:10:01 AM UTC 24 |
| Finished | Oct 03 04:11:57 AM UTC 24 |
| Peak memory | 278272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896748805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.3896748805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3834402030 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 47120187435 ps |
| CPU time | 161.97 seconds |
| Started | Oct 03 04:02:09 AM UTC 24 |
| Finished | Oct 03 04:04:54 AM UTC 24 |
| Peak memory | 261568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834402030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.3834402030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.1674552518 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30189501827 ps |
| CPU time | 359.82 seconds |
| Started | Oct 03 03:57:34 AM UTC 24 |
| Finished | Oct 03 04:03:40 AM UTC 24 |
| Peak memory | 265612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674552518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1674552518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.596660267 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5472186722 ps |
| CPU time | 132.16 seconds |
| Started | Oct 03 04:10:17 AM UTC 24 |
| Finished | Oct 03 04:12:32 AM UTC 24 |
| Peak memory | 267708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596660267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.596660267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3185784797 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 14341007959 ps |
| CPU time | 78.43 seconds |
| Started | Oct 03 03:59:49 AM UTC 24 |
| Finished | Oct 03 04:01:10 AM UTC 24 |
| Peak memory | 261768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185784797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3185784797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.4059694060 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 40098946580 ps |
| CPU time | 80.79 seconds |
| Started | Oct 03 04:19:38 AM UTC 24 |
| Finished | Oct 03 04:21:00 AM UTC 24 |
| Peak memory | 282248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059694060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4059694060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1572494714 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 55251437 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 03:56:40 AM UTC 24 |
| Finished | Oct 03 03:56:42 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572494714 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1572494714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1564023790 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 143421297204 ps |
| CPU time | 304.8 seconds |
| Started | Oct 03 03:58:34 AM UTC 24 |
| Finished | Oct 03 04:03:44 AM UTC 24 |
| Peak memory | 267580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564023790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.1564023790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.2669634780 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 40083930451 ps |
| CPU time | 105.15 seconds |
| Started | Oct 03 04:10:49 AM UTC 24 |
| Finished | Oct 03 04:12:36 AM UTC 24 |
| Peak memory | 267592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669634780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2669634780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.4169434454 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 115531528179 ps |
| CPU time | 659.83 seconds |
| Started | Oct 03 04:01:09 AM UTC 24 |
| Finished | Oct 03 04:12:19 AM UTC 24 |
| Peak memory | 280008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169434454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4169434454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2918384899 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1599134350 ps |
| CPU time | 21.6 seconds |
| Started | Oct 03 03:54:52 AM UTC 24 |
| Finished | Oct 03 03:55:15 AM UTC 24 |
| Peak memory | 261316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918384899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2918384899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1269740036 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 7565717015 ps |
| CPU time | 26.98 seconds |
| Started | Oct 03 04:20:25 AM UTC 24 |
| Finished | Oct 03 04:20:53 AM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269740036 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1269740036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.979923812 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5862731657 ps |
| CPU time | 26.27 seconds |
| Started | Oct 03 04:01:24 AM UTC 24 |
| Finished | Oct 03 04:01:52 AM UTC 24 |
| Peak memory | 231560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979923812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.979923812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3776310170 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4161780911 ps |
| CPU time | 82.57 seconds |
| Started | Oct 03 04:09:56 AM UTC 24 |
| Finished | Oct 03 04:11:21 AM UTC 24 |
| Peak memory | 278076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776310170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3776310170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.35206638 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 18189847345 ps |
| CPU time | 25.35 seconds |
| Started | Oct 03 03:54:31 AM UTC 24 |
| Finished | Oct 03 03:54:57 AM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35206638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.35206638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.604904991 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4646434098 ps |
| CPU time | 34.39 seconds |
| Started | Oct 03 04:08:47 AM UTC 24 |
| Finished | Oct 03 04:09:22 AM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604904991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.604904991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3404751287 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 43023756632 ps |
| CPU time | 225.62 seconds |
| Started | Oct 03 04:12:06 AM UTC 24 |
| Finished | Oct 03 04:15:56 AM UTC 24 |
| Peak memory | 277968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404751287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3404751287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3194664155 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 173920408503 ps |
| CPU time | 506.01 seconds |
| Started | Oct 03 04:17:38 AM UTC 24 |
| Finished | Oct 03 04:26:11 AM UTC 24 |
| Peak memory | 265528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194664155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.3194664155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.3599998839 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 263545921 ps |
| CPU time | 3.13 seconds |
| Started | Oct 03 04:21:04 AM UTC 24 |
| Finished | Oct 03 04:21:08 AM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599998839 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.3599998839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1491086667 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 49031313944 ps |
| CPU time | 201.72 seconds |
| Started | Oct 03 03:57:34 AM UTC 24 |
| Finished | Oct 03 04:00:59 AM UTC 24 |
| Peak memory | 261832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491086667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1491086667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3739432679 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 16032178993 ps |
| CPU time | 73.21 seconds |
| Started | Oct 03 04:06:19 AM UTC 24 |
| Finished | Oct 03 04:07:34 AM UTC 24 |
| Peak memory | 249216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739432679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.3739432679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.3821521771 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 364284558 ps |
| CPU time | 8.6 seconds |
| Started | Oct 03 04:07:22 AM UTC 24 |
| Finished | Oct 03 04:07:32 AM UTC 24 |
| Peak memory | 251128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821521771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3821521771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.3914789646 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 38482744666 ps |
| CPU time | 91.98 seconds |
| Started | Oct 03 04:08:14 AM UTC 24 |
| Finished | Oct 03 04:09:48 AM UTC 24 |
| Peak memory | 267576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914789646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.3914789646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3679218793 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2111607880 ps |
| CPU time | 12.73 seconds |
| Started | Oct 03 04:08:57 AM UTC 24 |
| Finished | Oct 03 04:09:12 AM UTC 24 |
| Peak memory | 251068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679218793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.3679218793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.439924372 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4728305949 ps |
| CPU time | 35.33 seconds |
| Started | Oct 03 04:10:13 AM UTC 24 |
| Finished | Oct 03 04:10:50 AM UTC 24 |
| Peak memory | 261444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439924372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.439924372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2599577093 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 338818648 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 04:19:54 AM UTC 24 |
| Finished | Oct 03 04:19:58 AM UTC 24 |
| Peak memory | 227796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599577093 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2599577093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1215320783 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 21067013 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 04:20:11 AM UTC 24 |
| Finished | Oct 03 04:20:14 AM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215320783 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.1215320783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.2840345585 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14653607 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 03:54:26 AM UTC 24 |
| Finished | Oct 03 03:54:28 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840345585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2840345585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3334662027 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 188140630 ps |
| CPU time | 15.55 seconds |
| Started | Oct 03 04:20:02 AM UTC 24 |
| Finished | Oct 03 04:20:19 AM UTC 24 |
| Peak memory | 215000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334662027 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.3334662027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3249596355 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 40667972 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 04:20:01 AM UTC 24 |
| Finished | Oct 03 04:20:04 AM UTC 24 |
| Peak memory | 214996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249596355 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.3249596355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4258475478 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 183934126 ps |
| CPU time | 3.93 seconds |
| Started | Oct 03 04:20:05 AM UTC 24 |
| Finished | Oct 03 04:20:10 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4258475478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.spi_device_csr_mem_rw_with_rand_reset.4258475478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.327876244 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 153224004 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 04:20:01 AM UTC 24 |
| Finished | Oct 03 04:20:06 AM UTC 24 |
| Peak memory | 225368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327876244 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.327876244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.664150296 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 211653642 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 04:19:58 AM UTC 24 |
| Finished | Oct 03 04:20:00 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664150296 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.664150296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1488455684 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 32426353 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 04:19:59 AM UTC 24 |
| Finished | Oct 03 04:20:02 AM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488455684 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1488455684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.380995252 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 12542133 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 04:19:58 AM UTC 24 |
| Finished | Oct 03 04:20:00 AM UTC 24 |
| Peak memory | 212040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380995252 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.380995252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4182711757 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 164687666 ps |
| CPU time | 5.57 seconds |
| Started | Oct 03 04:20:03 AM UTC 24 |
| Finished | Oct 03 04:20:10 AM UTC 24 |
| Peak memory | 227428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182711757 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstand ing.4182711757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.711366031 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1691221707 ps |
| CPU time | 28.42 seconds |
| Started | Oct 03 04:19:57 AM UTC 24 |
| Finished | Oct 03 04:20:27 AM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711366031 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.711366031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2090708769 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 595920876 ps |
| CPU time | 23.32 seconds |
| Started | Oct 03 04:20:12 AM UTC 24 |
| Finished | Oct 03 04:20:37 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090708769 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.2090708769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4167392733 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 184905478 ps |
| CPU time | 13.48 seconds |
| Started | Oct 03 04:20:11 AM UTC 24 |
| Finished | Oct 03 04:20:26 AM UTC 24 |
| Peak memory | 227292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167392733 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.4167392733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2034662337 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 91165240 ps |
| CPU time | 3.75 seconds |
| Started | Oct 03 04:20:14 AM UTC 24 |
| Finished | Oct 03 04:20:19 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2034662337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.spi_device_csr_mem_rw_with_rand_reset.2034662337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2660411133 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 28839680 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 04:20:11 AM UTC 24 |
| Finished | Oct 03 04:20:15 AM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660411133 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2660411133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2485616046 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 41483148 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 04:20:07 AM UTC 24 |
| Finished | Oct 03 04:20:09 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485616046 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2485616046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1185280266 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 25104934 ps |
| CPU time | 2.95 seconds |
| Started | Oct 03 04:20:10 AM UTC 24 |
| Finished | Oct 03 04:20:14 AM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185280266 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.1185280266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.576125226 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 35405664 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 04:20:09 AM UTC 24 |
| Finished | Oct 03 04:20:11 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576125226 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.576125226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3694893348 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 104656656 ps |
| CPU time | 2.47 seconds |
| Started | Oct 03 04:20:13 AM UTC 24 |
| Finished | Oct 03 04:20:17 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694893348 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand ing.3694893348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.4072222454 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 94123612 ps |
| CPU time | 3.59 seconds |
| Started | Oct 03 04:20:06 AM UTC 24 |
| Finished | Oct 03 04:20:10 AM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072222454 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4072222454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2966312166 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 4149163537 ps |
| CPU time | 19.59 seconds |
| Started | Oct 03 04:20:07 AM UTC 24 |
| Finished | Oct 03 04:20:28 AM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966312166 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.2966312166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3915162997 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 1905483313 ps |
| CPU time | 3.79 seconds |
| Started | Oct 03 04:20:55 AM UTC 24 |
| Finished | Oct 03 04:20:59 AM UTC 24 |
| Peak memory | 229528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3915162997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.spi_device_csr_mem_rw_with_rand_reset.3915162997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1503702889 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 108461215 ps |
| CPU time | 3.42 seconds |
| Started | Oct 03 04:20:53 AM UTC 24 |
| Finished | Oct 03 04:20:58 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503702889 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.1503702889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3236165797 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 67285379 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 04:20:53 AM UTC 24 |
| Finished | Oct 03 04:20:55 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236165797 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.3236165797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.447843937 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 282991218 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 04:20:55 AM UTC 24 |
| Finished | Oct 03 04:20:59 AM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447843937 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstand ing.447843937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2482713997 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 116087090 ps |
| CPU time | 2.69 seconds |
| Started | Oct 03 04:20:53 AM UTC 24 |
| Finished | Oct 03 04:20:57 AM UTC 24 |
| Peak memory | 227700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482713997 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.2482713997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3563759949 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 8981021749 ps |
| CPU time | 19.76 seconds |
| Started | Oct 03 04:20:53 AM UTC 24 |
| Finished | Oct 03 04:21:14 AM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563759949 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.3563759949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2187595474 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 509429426 ps |
| CPU time | 3.44 seconds |
| Started | Oct 03 04:20:58 AM UTC 24 |
| Finished | Oct 03 04:21:02 AM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2187595474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.spi_device_csr_mem_rw_with_rand_reset.2187595474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.867058979 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 28467378 ps |
| CPU time | 2.09 seconds |
| Started | Oct 03 04:20:56 AM UTC 24 |
| Finished | Oct 03 04:20:59 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867058979 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.867058979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3498727748 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 14472942 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 04:20:56 AM UTC 24 |
| Finished | Oct 03 04:20:58 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498727748 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.3498727748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.382280199 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 149581848 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 04:20:56 AM UTC 24 |
| Finished | Oct 03 04:20:59 AM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382280199 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstand ing.382280199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3209976623 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 70576996 ps |
| CPU time | 2.75 seconds |
| Started | Oct 03 04:20:56 AM UTC 24 |
| Finished | Oct 03 04:21:00 AM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209976623 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.3209976623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1175703951 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 828648244 ps |
| CPU time | 20.36 seconds |
| Started | Oct 03 04:20:56 AM UTC 24 |
| Finished | Oct 03 04:21:18 AM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175703951 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.1175703951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3943529935 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 152741314 ps |
| CPU time | 5.36 seconds |
| Started | Oct 03 04:20:59 AM UTC 24 |
| Finished | Oct 03 04:21:06 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3943529935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.spi_device_csr_mem_rw_with_rand_reset.3943529935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3193289413 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 374430476 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 04:20:59 AM UTC 24 |
| Finished | Oct 03 04:21:02 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193289413 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.3193289413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2137994072 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 23063830 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:20:58 AM UTC 24 |
| Finished | Oct 03 04:21:00 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137994072 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2137994072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3027594512 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 79144195 ps |
| CPU time | 3.15 seconds |
| Started | Oct 03 04:20:59 AM UTC 24 |
| Finished | Oct 03 04:21:03 AM UTC 24 |
| Peak memory | 225408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027594512 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan ding.3027594512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.3340092657 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 137250404 ps |
| CPU time | 3.66 seconds |
| Started | Oct 03 04:20:58 AM UTC 24 |
| Finished | Oct 03 04:21:02 AM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340092657 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.3340092657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.364533608 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 555539462 ps |
| CPU time | 16.83 seconds |
| Started | Oct 03 04:20:58 AM UTC 24 |
| Finished | Oct 03 04:21:16 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364533608 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.364533608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.121568940 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 109710774 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 04:21:01 AM UTC 24 |
| Finished | Oct 03 04:21:04 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=121568940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.spi_device_csr_mem_rw_with_rand_reset.121568940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1522961819 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 90482963 ps |
| CPU time | 2.47 seconds |
| Started | Oct 03 04:21:01 AM UTC 24 |
| Finished | Oct 03 04:21:04 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522961819 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.1522961819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2198109158 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 105481651 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 04:21:01 AM UTC 24 |
| Finished | Oct 03 04:21:03 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198109158 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.2198109158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4160407218 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 244863696 ps |
| CPU time | 2.95 seconds |
| Started | Oct 03 04:21:01 AM UTC 24 |
| Finished | Oct 03 04:21:05 AM UTC 24 |
| Peak memory | 225408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160407218 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstan ding.4160407218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2031233685 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 213020058 ps |
| CPU time | 5.18 seconds |
| Started | Oct 03 04:21:01 AM UTC 24 |
| Finished | Oct 03 04:21:07 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031233685 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.2031233685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1777921510 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 536999263 ps |
| CPU time | 18.12 seconds |
| Started | Oct 03 04:21:01 AM UTC 24 |
| Finished | Oct 03 04:21:20 AM UTC 24 |
| Peak memory | 225148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777921510 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.1777921510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3400579561 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 320992610 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 04:21:04 AM UTC 24 |
| Finished | Oct 03 04:21:07 AM UTC 24 |
| Peak memory | 224536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3400579561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.spi_device_csr_mem_rw_with_rand_reset.3400579561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3029751103 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 331131870 ps |
| CPU time | 2.68 seconds |
| Started | Oct 03 04:21:04 AM UTC 24 |
| Finished | Oct 03 04:21:08 AM UTC 24 |
| Peak memory | 225304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029751103 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.3029751103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.4173505859 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 15053893 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:21:02 AM UTC 24 |
| Finished | Oct 03 04:21:05 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173505859 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.4173505859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.902989650 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 605975025 ps |
| CPU time | 5.22 seconds |
| Started | Oct 03 04:21:04 AM UTC 24 |
| Finished | Oct 03 04:21:10 AM UTC 24 |
| Peak memory | 225428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902989650 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstand ing.902989650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3286802964 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 177852723 ps |
| CPU time | 5.08 seconds |
| Started | Oct 03 04:21:01 AM UTC 24 |
| Finished | Oct 03 04:21:07 AM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286802964 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.3286802964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1118579095 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 869073623 ps |
| CPU time | 18.93 seconds |
| Started | Oct 03 04:21:02 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118579095 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.1118579095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.603583153 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 84096117 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 04:21:06 AM UTC 24 |
| Finished | Oct 03 04:21:09 AM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=603583153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.spi_device_csr_mem_rw_with_rand_reset.603583153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4082697301 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 482261641 ps |
| CPU time | 3.86 seconds |
| Started | Oct 03 04:21:06 AM UTC 24 |
| Finished | Oct 03 04:21:10 AM UTC 24 |
| Peak memory | 225240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082697301 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.4082697301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2342462540 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 259948020 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 04:21:04 AM UTC 24 |
| Finished | Oct 03 04:21:06 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342462540 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2342462540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2067701437 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 274493639 ps |
| CPU time | 3.69 seconds |
| Started | Oct 03 04:21:06 AM UTC 24 |
| Finished | Oct 03 04:21:10 AM UTC 24 |
| Peak memory | 225512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067701437 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstan ding.2067701437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.155780924 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 414862555 ps |
| CPU time | 8.4 seconds |
| Started | Oct 03 04:21:04 AM UTC 24 |
| Finished | Oct 03 04:21:14 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155780924 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.155780924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2477423013 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 101355279 ps |
| CPU time | 2.55 seconds |
| Started | Oct 03 04:21:08 AM UTC 24 |
| Finished | Oct 03 04:21:11 AM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2477423013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.spi_device_csr_mem_rw_with_rand_reset.2477423013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.64205813 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 88840455 ps |
| CPU time | 3.65 seconds |
| Started | Oct 03 04:21:07 AM UTC 24 |
| Finished | Oct 03 04:21:12 AM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64205813 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.64205813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2418072703 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 13075179 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 04:21:07 AM UTC 24 |
| Finished | Oct 03 04:21:09 AM UTC 24 |
| Peak memory | 211844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418072703 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.2418072703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1935633000 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 64290487 ps |
| CPU time | 5.22 seconds |
| Started | Oct 03 04:21:07 AM UTC 24 |
| Finished | Oct 03 04:21:14 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935633000 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstan ding.1935633000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2159273287 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 36317617 ps |
| CPU time | 2.88 seconds |
| Started | Oct 03 04:21:06 AM UTC 24 |
| Finished | Oct 03 04:21:10 AM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159273287 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.2159273287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.474988845 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 1071936970 ps |
| CPU time | 25.7 seconds |
| Started | Oct 03 04:21:07 AM UTC 24 |
| Finished | Oct 03 04:21:34 AM UTC 24 |
| Peak memory | 227344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474988845 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.474988845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.304009542 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 28580938 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 04:21:09 AM UTC 24 |
| Finished | Oct 03 04:21:12 AM UTC 24 |
| Peak memory | 226584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=304009542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.spi_device_csr_mem_rw_with_rand_reset.304009542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2843603818 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 75091751 ps |
| CPU time | 3.9 seconds |
| Started | Oct 03 04:21:09 AM UTC 24 |
| Finished | Oct 03 04:21:14 AM UTC 24 |
| Peak memory | 225376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843603818 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.2843603818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.547044299 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 31336690 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:21:09 AM UTC 24 |
| Finished | Oct 03 04:21:11 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547044299 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.547044299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2793361884 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 562526325 ps |
| CPU time | 5.02 seconds |
| Started | Oct 03 04:21:09 AM UTC 24 |
| Finished | Oct 03 04:21:15 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793361884 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan ding.2793361884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3075890883 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 950992951 ps |
| CPU time | 3.34 seconds |
| Started | Oct 03 04:21:09 AM UTC 24 |
| Finished | Oct 03 04:21:13 AM UTC 24 |
| Peak memory | 227728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075890883 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.3075890883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2986899492 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 1635644376 ps |
| CPU time | 23.04 seconds |
| Started | Oct 03 04:21:09 AM UTC 24 |
| Finished | Oct 03 04:21:33 AM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986899492 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2986899492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2785648436 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 378902169 ps |
| CPU time | 4.12 seconds |
| Started | Oct 03 04:21:13 AM UTC 24 |
| Finished | Oct 03 04:21:18 AM UTC 24 |
| Peak memory | 229600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2785648436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.spi_device_csr_mem_rw_with_rand_reset.2785648436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.1508040632 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 75699250 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 04:21:12 AM UTC 24 |
| Finished | Oct 03 04:21:16 AM UTC 24 |
| Peak memory | 215060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508040632 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.1508040632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.655966329 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 40629359 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 04:21:11 AM UTC 24 |
| Finished | Oct 03 04:21:13 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655966329 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.655966329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2018179695 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 103961613 ps |
| CPU time | 4.48 seconds |
| Started | Oct 03 04:21:12 AM UTC 24 |
| Finished | Oct 03 04:21:18 AM UTC 24 |
| Peak memory | 225476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018179695 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan ding.2018179695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.4083811900 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 94126151 ps |
| CPU time | 3.69 seconds |
| Started | Oct 03 04:21:11 AM UTC 24 |
| Finished | Oct 03 04:21:15 AM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083811900 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.4083811900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1575121414 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 368483194 ps |
| CPU time | 11.65 seconds |
| Started | Oct 03 04:21:11 AM UTC 24 |
| Finished | Oct 03 04:21:24 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575121414 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.1575121414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2102454857 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 167219649 ps |
| CPU time | 3.5 seconds |
| Started | Oct 03 04:21:14 AM UTC 24 |
| Finished | Oct 03 04:21:19 AM UTC 24 |
| Peak memory | 229592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2102454857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.spi_device_csr_mem_rw_with_rand_reset.2102454857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.2432077481 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 84777800 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 04:21:14 AM UTC 24 |
| Finished | Oct 03 04:21:17 AM UTC 24 |
| Peak memory | 224360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432077481 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.2432077481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.2660926508 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 72725127 ps |
| CPU time | 0.96 seconds |
| Started | Oct 03 04:21:14 AM UTC 24 |
| Finished | Oct 03 04:21:16 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660926508 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.2660926508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.265796202 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 145761722 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 04:21:14 AM UTC 24 |
| Finished | Oct 03 04:21:20 AM UTC 24 |
| Peak memory | 225412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265796202 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstand ing.265796202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.738470872 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 173548052 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 04:21:13 AM UTC 24 |
| Finished | Oct 03 04:21:17 AM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738470872 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.738470872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.3899187418 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 4094234149 ps |
| CPU time | 24.02 seconds |
| Started | Oct 03 04:21:13 AM UTC 24 |
| Finished | Oct 03 04:21:38 AM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899187418 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.3899187418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.2264332149 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 636981873 ps |
| CPU time | 19.49 seconds |
| Started | Oct 03 04:20:21 AM UTC 24 |
| Finished | Oct 03 04:20:42 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264332149 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.2264332149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.799165121 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 720444076 ps |
| CPU time | 25.69 seconds |
| Started | Oct 03 04:20:21 AM UTC 24 |
| Finished | Oct 03 04:20:48 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799165121 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.799165121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1821120341 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 62623336 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 04:20:20 AM UTC 24 |
| Finished | Oct 03 04:20:23 AM UTC 24 |
| Peak memory | 214324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821120341 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.1821120341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2321884249 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 34803883 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 04:20:20 AM UTC 24 |
| Finished | Oct 03 04:20:23 AM UTC 24 |
| Peak memory | 225284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321884249 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2321884249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1819841620 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 88152233 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 04:20:16 AM UTC 24 |
| Finished | Oct 03 04:20:18 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819841620 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1819841620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1344456248 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 17300046 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 04:20:19 AM UTC 24 |
| Finished | Oct 03 04:20:22 AM UTC 24 |
| Peak memory | 225364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344456248 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.1344456248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1239610661 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 11448340 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 04:20:18 AM UTC 24 |
| Finished | Oct 03 04:20:20 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239610661 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.1239610661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4257850752 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 829374383 ps |
| CPU time | 6.14 seconds |
| Started | Oct 03 04:20:23 AM UTC 24 |
| Finished | Oct 03 04:20:31 AM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257850752 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand ing.4257850752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.827381992 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 141034261 ps |
| CPU time | 5.08 seconds |
| Started | Oct 03 04:20:14 AM UTC 24 |
| Finished | Oct 03 04:20:21 AM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827381992 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.827381992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3507026450 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 38346566 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 04:21:14 AM UTC 24 |
| Finished | Oct 03 04:21:17 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507026450 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.3507026450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1878057339 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 27743333 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 04:21:15 AM UTC 24 |
| Finished | Oct 03 04:21:17 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878057339 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.1878057339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2476656756 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 47308780 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 04:21:16 AM UTC 24 |
| Finished | Oct 03 04:21:18 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476656756 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.2476656756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.429796571 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 12044095 ps |
| CPU time | 0.97 seconds |
| Started | Oct 03 04:21:16 AM UTC 24 |
| Finished | Oct 03 04:21:18 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429796571 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.429796571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.1963053311 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 39308683 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 04:21:16 AM UTC 24 |
| Finished | Oct 03 04:21:19 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963053311 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.1963053311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.2712457844 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 122770700 ps |
| CPU time | 0.95 seconds |
| Started | Oct 03 04:21:16 AM UTC 24 |
| Finished | Oct 03 04:21:18 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712457844 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.2712457844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3141074327 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 49023444 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 04:21:17 AM UTC 24 |
| Finished | Oct 03 04:21:19 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141074327 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.3141074327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1629795580 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 67161066 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 04:21:17 AM UTC 24 |
| Finished | Oct 03 04:21:19 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629795580 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.1629795580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2929260010 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 38562139 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 04:21:17 AM UTC 24 |
| Finished | Oct 03 04:21:19 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929260010 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.2929260010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.2023471344 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 16299092 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 04:21:19 AM UTC 24 |
| Finished | Oct 03 04:21:21 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023471344 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.2023471344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.2424783755 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 1239096433 ps |
| CPU time | 12.38 seconds |
| Started | Oct 03 04:20:30 AM UTC 24 |
| Finished | Oct 03 04:20:44 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424783755 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.2424783755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1326514401 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 903916222 ps |
| CPU time | 12.47 seconds |
| Started | Oct 03 04:20:29 AM UTC 24 |
| Finished | Oct 03 04:20:43 AM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326514401 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.1326514401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2704861607 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 16878632 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 04:20:29 AM UTC 24 |
| Finished | Oct 03 04:20:31 AM UTC 24 |
| Peak memory | 214292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704861607 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.2704861607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.248172648 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 55383713 ps |
| CPU time | 2.85 seconds |
| Started | Oct 03 04:20:31 AM UTC 24 |
| Finished | Oct 03 04:20:35 AM UTC 24 |
| Peak memory | 227724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=248172648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.spi_device_csr_mem_rw_with_rand_reset.248172648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.116822762 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 121384995 ps |
| CPU time | 3.03 seconds |
| Started | Oct 03 04:20:29 AM UTC 24 |
| Finished | Oct 03 04:20:33 AM UTC 24 |
| Peak memory | 225240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116822762 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.116822762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.362303141 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 27506345 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 04:20:27 AM UTC 24 |
| Finished | Oct 03 04:20:29 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362303141 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.362303141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.4122380618 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 94380511 ps |
| CPU time | 3.09 seconds |
| Started | Oct 03 04:20:28 AM UTC 24 |
| Finished | Oct 03 04:20:32 AM UTC 24 |
| Peak memory | 225360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122380618 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.4122380618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2998790962 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 25542621 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 04:20:28 AM UTC 24 |
| Finished | Oct 03 04:20:30 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998790962 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.2998790962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.216353021 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 297406583 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 04:20:31 AM UTC 24 |
| Finished | Oct 03 04:20:35 AM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216353021 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.216353021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.3865367732 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 54047597 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:21:19 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865367732 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.3865367732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2672545286 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 19980073 ps |
| CPU time | 0.98 seconds |
| Started | Oct 03 04:21:19 AM UTC 24 |
| Finished | Oct 03 04:21:21 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672545286 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.2672545286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3027934348 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 12902354 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 04:21:19 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027934348 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3027934348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.492493084 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 61204972 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:21 AM UTC 24 |
| Peak memory | 212100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492493084 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.492493084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1402653222 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 35867636 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402653222 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.1402653222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.774502447 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 53957543 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774502447 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.774502447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.735927301 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 11820017 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735927301 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.735927301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.2217255571 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 48700476 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217255571 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.2217255571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.762562156 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 67842094 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762562156 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.762562156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.4223288361 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 13417438 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223288361 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.4223288361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3649583306 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 4957493649 ps |
| CPU time | 34.32 seconds |
| Started | Oct 03 04:20:36 AM UTC 24 |
| Finished | Oct 03 04:21:12 AM UTC 24 |
| Peak memory | 225416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649583306 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.3649583306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4027185694 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 1246003083 ps |
| CPU time | 29.89 seconds |
| Started | Oct 03 04:20:36 AM UTC 24 |
| Finished | Oct 03 04:21:07 AM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027185694 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.4027185694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3875267215 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 44765529 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 04:20:36 AM UTC 24 |
| Finished | Oct 03 04:20:39 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875267215 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.3875267215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.148440435 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 650214038 ps |
| CPU time | 5.09 seconds |
| Started | Oct 03 04:20:38 AM UTC 24 |
| Finished | Oct 03 04:20:44 AM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=148440435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.spi_device_csr_mem_rw_with_rand_reset.148440435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2077025238 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 89019248 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 04:20:36 AM UTC 24 |
| Finished | Oct 03 04:20:40 AM UTC 24 |
| Peak memory | 227252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077025238 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2077025238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3805130164 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 15136218 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 04:20:34 AM UTC 24 |
| Finished | Oct 03 04:20:36 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805130164 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3805130164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1525104218 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 271279012 ps |
| CPU time | 3.85 seconds |
| Started | Oct 03 04:20:34 AM UTC 24 |
| Finished | Oct 03 04:20:39 AM UTC 24 |
| Peak memory | 225412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525104218 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.1525104218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.1452635387 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 34394272 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 04:20:34 AM UTC 24 |
| Finished | Oct 03 04:20:36 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452635387 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.1452635387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3509041427 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 58853594 ps |
| CPU time | 3.33 seconds |
| Started | Oct 03 04:20:37 AM UTC 24 |
| Finished | Oct 03 04:20:42 AM UTC 24 |
| Peak memory | 225376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509041427 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstand ing.3509041427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3387492623 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 98883215 ps |
| CPU time | 3.87 seconds |
| Started | Oct 03 04:20:33 AM UTC 24 |
| Finished | Oct 03 04:20:37 AM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387492623 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3387492623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.515837870 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1721342296 ps |
| CPU time | 14.9 seconds |
| Started | Oct 03 04:20:33 AM UTC 24 |
| Finished | Oct 03 04:20:49 AM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515837870 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.515837870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.754008567 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 14070542 ps |
| CPU time | 0.85 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754008567 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.754008567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.3856624340 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 33744427 ps |
| CPU time | 0.85 seconds |
| Started | Oct 03 04:21:20 AM UTC 24 |
| Finished | Oct 03 04:21:22 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856624340 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.3856624340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3472451788 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 15892198 ps |
| CPU time | 0.98 seconds |
| Started | Oct 03 04:21:23 AM UTC 24 |
| Finished | Oct 03 04:21:25 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472451788 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3472451788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3334514825 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 44230413 ps |
| CPU time | 0.82 seconds |
| Started | Oct 03 04:21:23 AM UTC 24 |
| Finished | Oct 03 04:21:25 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334514825 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.3334514825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1007319147 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 47554672 ps |
| CPU time | 0.92 seconds |
| Started | Oct 03 04:21:23 AM UTC 24 |
| Finished | Oct 03 04:21:25 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007319147 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.1007319147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1268700320 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 15208901 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 04:21:23 AM UTC 24 |
| Finished | Oct 03 04:21:25 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268700320 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.1268700320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.3083944895 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 11252218 ps |
| CPU time | 0.88 seconds |
| Started | Oct 03 04:21:23 AM UTC 24 |
| Finished | Oct 03 04:21:25 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083944895 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.3083944895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2118935541 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 47819248 ps |
| CPU time | 0.75 seconds |
| Started | Oct 03 04:21:23 AM UTC 24 |
| Finished | Oct 03 04:21:25 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118935541 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.2118935541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2004405863 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 73334475 ps |
| CPU time | 0.86 seconds |
| Started | Oct 03 04:21:23 AM UTC 24 |
| Finished | Oct 03 04:21:25 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004405863 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.2004405863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.579697769 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 36481273 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 04:21:23 AM UTC 24 |
| Finished | Oct 03 04:21:25 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579697769 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.579697769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1457731844 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 113373807 ps |
| CPU time | 3.12 seconds |
| Started | Oct 03 04:20:41 AM UTC 24 |
| Finished | Oct 03 04:20:45 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1457731844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.spi_device_csr_mem_rw_with_rand_reset.1457731844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3554939926 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 81188237 ps |
| CPU time | 3.26 seconds |
| Started | Oct 03 04:20:40 AM UTC 24 |
| Finished | Oct 03 04:20:44 AM UTC 24 |
| Peak memory | 225364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554939926 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3554939926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1479318085 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 25159294 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:20:39 AM UTC 24 |
| Finished | Oct 03 04:20:41 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479318085 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1479318085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2003981176 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 707154923 ps |
| CPU time | 5.58 seconds |
| Started | Oct 03 04:20:40 AM UTC 24 |
| Finished | Oct 03 04:20:47 AM UTC 24 |
| Peak memory | 225412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003981176 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstand ing.2003981176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.4266873680 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 50876458 ps |
| CPU time | 4.73 seconds |
| Started | Oct 03 04:20:38 AM UTC 24 |
| Finished | Oct 03 04:20:43 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266873680 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4266873680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2909008459 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 1052494367 ps |
| CPU time | 17.67 seconds |
| Started | Oct 03 04:20:38 AM UTC 24 |
| Finished | Oct 03 04:20:57 AM UTC 24 |
| Peak memory | 233488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909008459 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.2909008459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3541925789 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1412818731 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 04:20:45 AM UTC 24 |
| Finished | Oct 03 04:20:49 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3541925789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.spi_device_csr_mem_rw_with_rand_reset.3541925789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1478146859 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 104608830 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 04:20:44 AM UTC 24 |
| Finished | Oct 03 04:20:48 AM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478146859 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1478146859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.58769995 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 11007780 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 04:20:44 AM UTC 24 |
| Finished | Oct 03 04:20:46 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58769995 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.58769995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3731381394 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 212938891 ps |
| CPU time | 5.21 seconds |
| Started | Oct 03 04:20:45 AM UTC 24 |
| Finished | Oct 03 04:20:51 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731381394 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstand ing.3731381394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.4289204731 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 39598879 ps |
| CPU time | 3.94 seconds |
| Started | Oct 03 04:20:42 AM UTC 24 |
| Finished | Oct 03 04:20:47 AM UTC 24 |
| Peak memory | 225608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289204731 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4289204731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1065849240 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 108994483 ps |
| CPU time | 7.7 seconds |
| Started | Oct 03 04:20:42 AM UTC 24 |
| Finished | Oct 03 04:20:51 AM UTC 24 |
| Peak memory | 225428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065849240 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.1065849240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1653560999 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 559481571 ps |
| CPU time | 2.02 seconds |
| Started | Oct 03 04:20:48 AM UTC 24 |
| Finished | Oct 03 04:20:50 AM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1653560999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.spi_device_csr_mem_rw_with_rand_reset.1653560999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.1697326297 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 53608040 ps |
| CPU time | 2.86 seconds |
| Started | Oct 03 04:20:47 AM UTC 24 |
| Finished | Oct 03 04:20:51 AM UTC 24 |
| Peak memory | 225224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697326297 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1697326297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1727507006 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 15669572 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 04:20:46 AM UTC 24 |
| Finished | Oct 03 04:20:48 AM UTC 24 |
| Peak memory | 212092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727507006 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1727507006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2195535761 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 2117987895 ps |
| CPU time | 3.9 seconds |
| Started | Oct 03 04:20:47 AM UTC 24 |
| Finished | Oct 03 04:20:52 AM UTC 24 |
| Peak memory | 225384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195535761 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand ing.2195535761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.393742413 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 173581431 ps |
| CPU time | 5.49 seconds |
| Started | Oct 03 04:20:45 AM UTC 24 |
| Finished | Oct 03 04:20:51 AM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393742413 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.393742413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2238038 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 597103475 ps |
| CPU time | 19.97 seconds |
| Started | Oct 03 04:20:45 AM UTC 24 |
| Finished | Oct 03 04:21:06 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238038 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.2238038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3818260244 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 92043064 ps |
| CPU time | 3.8 seconds |
| Started | Oct 03 04:20:50 AM UTC 24 |
| Finished | Oct 03 04:20:55 AM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3818260244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.spi_device_csr_mem_rw_with_rand_reset.3818260244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2005985973 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 153204708 ps |
| CPU time | 3.03 seconds |
| Started | Oct 03 04:20:50 AM UTC 24 |
| Finished | Oct 03 04:20:54 AM UTC 24 |
| Peak memory | 225344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005985973 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2005985973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.4063598448 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 33782697 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:20:50 AM UTC 24 |
| Finished | Oct 03 04:20:52 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063598448 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4063598448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1224338390 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 627351200 ps |
| CPU time | 4.51 seconds |
| Started | Oct 03 04:20:50 AM UTC 24 |
| Finished | Oct 03 04:20:56 AM UTC 24 |
| Peak memory | 225472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224338390 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand ing.1224338390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2896080990 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 128950356 ps |
| CPU time | 2.35 seconds |
| Started | Oct 03 04:20:49 AM UTC 24 |
| Finished | Oct 03 04:20:52 AM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896080990 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2896080990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.1519094936 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 207496021 ps |
| CPU time | 6.79 seconds |
| Started | Oct 03 04:20:49 AM UTC 24 |
| Finished | Oct 03 04:20:57 AM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519094936 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.1519094936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1155405187 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 109635226 ps |
| CPU time | 6.32 seconds |
| Started | Oct 03 04:20:53 AM UTC 24 |
| Finished | Oct 03 04:21:00 AM UTC 24 |
| Peak memory | 229788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1155405187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.spi_device_csr_mem_rw_with_rand_reset.1155405187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.190425152 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 107923009 ps |
| CPU time | 2.45 seconds |
| Started | Oct 03 04:20:52 AM UTC 24 |
| Finished | Oct 03 04:20:55 AM UTC 24 |
| Peak memory | 225296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190425152 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.190425152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4268112285 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 13679365 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:20:52 AM UTC 24 |
| Finished | Oct 03 04:20:54 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268112285 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4268112285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.637737164 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 164641718 ps |
| CPU time | 4.97 seconds |
| Started | Oct 03 04:20:53 AM UTC 24 |
| Finished | Oct 03 04:20:59 AM UTC 24 |
| Peak memory | 225428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637737164 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.637737164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.3506225387 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 242168636 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 04:20:51 AM UTC 24 |
| Finished | Oct 03 04:20:55 AM UTC 24 |
| Peak memory | 227656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506225387 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3506225387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.3194143559 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1128695325 ps |
| CPU time | 13.05 seconds |
| Started | Oct 03 04:20:52 AM UTC 24 |
| Finished | Oct 03 04:21:06 AM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194143559 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.3194143559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3837624004 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 155690563 ps |
| CPU time | 3.75 seconds |
| Started | Oct 03 03:55:00 AM UTC 24 |
| Finished | Oct 03 03:55:04 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837624004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3837624004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3863146671 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5810171300 ps |
| CPU time | 39.63 seconds |
| Started | Oct 03 03:55:16 AM UTC 24 |
| Finished | Oct 03 03:55:57 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863146671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3863146671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.2756566633 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 53916433825 ps |
| CPU time | 546.47 seconds |
| Started | Oct 03 03:55:39 AM UTC 24 |
| Finished | Oct 03 04:04:53 AM UTC 24 |
| Peak memory | 275976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756566633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2756566633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1376665475 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 72073680198 ps |
| CPU time | 182.43 seconds |
| Started | Oct 03 03:55:10 AM UTC 24 |
| Finished | Oct 03 03:58:16 AM UTC 24 |
| Peak memory | 245312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376665475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.1376665475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2098638750 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2923642458 ps |
| CPU time | 6.28 seconds |
| Started | Oct 03 03:54:44 AM UTC 24 |
| Finished | Oct 03 03:54:51 AM UTC 24 |
| Peak memory | 234764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098638750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2098638750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.4074044932 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 786557724 ps |
| CPU time | 5.46 seconds |
| Started | Oct 03 03:54:40 AM UTC 24 |
| Finished | Oct 03 03:54:47 AM UTC 24 |
| Peak memory | 234920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074044932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4074044932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.252380795 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4460965712 ps |
| CPU time | 22.29 seconds |
| Started | Oct 03 03:55:15 AM UTC 24 |
| Finished | Oct 03 03:55:39 AM UTC 24 |
| Peak memory | 233456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252380795 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.252380795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.2917286215 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1835457575 ps |
| CPU time | 39.9 seconds |
| Started | Oct 03 03:54:33 AM UTC 24 |
| Finished | Oct 03 03:55:14 AM UTC 24 |
| Peak memory | 227332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917286215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2917286215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.2546067874 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 44288087 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 03:54:37 AM UTC 24 |
| Finished | Oct 03 03:54:40 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546067874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2546067874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1549446949 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 95344570 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 03:54:34 AM UTC 24 |
| Finished | Oct 03 03:54:36 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549446949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1549446949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.2463745791 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2176307641 ps |
| CPU time | 9.21 seconds |
| Started | Oct 03 03:54:59 AM UTC 24 |
| Finished | Oct 03 03:55:09 AM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463745791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2463745791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.862069485 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 27419086 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 03:57:46 AM UTC 24 |
| Finished | Oct 03 03:57:49 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862069485 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.862069485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2526302778 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 407310560 ps |
| CPU time | 3.39 seconds |
| Started | Oct 03 03:57:24 AM UTC 24 |
| Finished | Oct 03 03:57:29 AM UTC 24 |
| Peak memory | 234264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526302778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2526302778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.3031086614 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 114473483 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 03:56:43 AM UTC 24 |
| Finished | Oct 03 03:56:45 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031086614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3031086614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2497420353 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8496638152 ps |
| CPU time | 77.56 seconds |
| Started | Oct 03 03:57:36 AM UTC 24 |
| Finished | Oct 03 03:58:56 AM UTC 24 |
| Peak memory | 261628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497420353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.2497420353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2962184264 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 323744628 ps |
| CPU time | 11.6 seconds |
| Started | Oct 03 03:57:29 AM UTC 24 |
| Finished | Oct 03 03:57:41 AM UTC 24 |
| Peak memory | 234936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962184264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2962184264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.2570030258 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 288157509 ps |
| CPU time | 4.58 seconds |
| Started | Oct 03 03:57:18 AM UTC 24 |
| Finished | Oct 03 03:57:24 AM UTC 24 |
| Peak memory | 234604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570030258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2570030258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.4112192105 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 393325645 ps |
| CPU time | 9.84 seconds |
| Started | Oct 03 03:57:22 AM UTC 24 |
| Finished | Oct 03 03:57:33 AM UTC 24 |
| Peak memory | 234748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112192105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4112192105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.476207017 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1421762212 ps |
| CPU time | 6.1 seconds |
| Started | Oct 03 03:57:14 AM UTC 24 |
| Finished | Oct 03 03:57:21 AM UTC 24 |
| Peak memory | 244984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476207017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.476207017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.440665990 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2804801065 ps |
| CPU time | 8.69 seconds |
| Started | Oct 03 03:57:14 AM UTC 24 |
| Finished | Oct 03 03:57:24 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440665990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.440665990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3700753083 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 492622358 ps |
| CPU time | 11.08 seconds |
| Started | Oct 03 03:57:33 AM UTC 24 |
| Finished | Oct 03 03:57:45 AM UTC 24 |
| Peak memory | 233324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700753083 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.3700753083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.3540060058 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 83341439 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 03:57:45 AM UTC 24 |
| Finished | Oct 03 03:57:48 AM UTC 24 |
| Peak memory | 256992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540060058 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3540060058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.1701242555 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 43288938 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 03:57:42 AM UTC 24 |
| Finished | Oct 03 03:57:45 AM UTC 24 |
| Peak memory | 215724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701242555 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.1701242555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.627994059 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 13388347528 ps |
| CPU time | 27.11 seconds |
| Started | Oct 03 03:56:49 AM UTC 24 |
| Finished | Oct 03 03:57:18 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627994059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.627994059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.1229846812 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 642955735 ps |
| CPU time | 3.12 seconds |
| Started | Oct 03 03:57:09 AM UTC 24 |
| Finished | Oct 03 03:57:13 AM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229846812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1229846812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.1209431459 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 258061567 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 03:57:05 AM UTC 24 |
| Finished | Oct 03 03:57:08 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209431459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1209431459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3705971499 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 660020485 ps |
| CPU time | 6.4 seconds |
| Started | Oct 03 03:57:24 AM UTC 24 |
| Finished | Oct 03 03:57:32 AM UTC 24 |
| Peak memory | 244996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705971499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3705971499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.3035315125 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 103047156 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:06:35 AM UTC 24 |
| Finished | Oct 03 04:06:37 AM UTC 24 |
| Peak memory | 213648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035315125 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.3035315125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3730945374 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 351927788 ps |
| CPU time | 7.61 seconds |
| Started | Oct 03 04:06:14 AM UTC 24 |
| Finished | Oct 03 04:06:23 AM UTC 24 |
| Peak memory | 244924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730945374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3730945374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.3185363576 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 51375401 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 04:05:58 AM UTC 24 |
| Finished | Oct 03 04:06:00 AM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185363576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3185363576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.3006663011 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1857022785 ps |
| CPU time | 47.84 seconds |
| Started | Oct 03 04:06:23 AM UTC 24 |
| Finished | Oct 03 04:07:13 AM UTC 24 |
| Peak memory | 251084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006663011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3006663011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1877600204 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2884727102 ps |
| CPU time | 53.56 seconds |
| Started | Oct 03 04:06:27 AM UTC 24 |
| Finished | Oct 03 04:07:22 AM UTC 24 |
| Peak memory | 261912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877600204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1877600204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.2176972244 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 7770184490 ps |
| CPU time | 79.22 seconds |
| Started | Oct 03 04:06:31 AM UTC 24 |
| Finished | Oct 03 04:07:52 AM UTC 24 |
| Peak memory | 263616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176972244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.2176972244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1229478446 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1765438821 ps |
| CPU time | 29.13 seconds |
| Started | Oct 03 04:06:14 AM UTC 24 |
| Finished | Oct 03 04:06:45 AM UTC 24 |
| Peak memory | 261572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229478446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1229478446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.1555630030 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 317536501 ps |
| CPU time | 10.46 seconds |
| Started | Oct 03 04:06:08 AM UTC 24 |
| Finished | Oct 03 04:06:19 AM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555630030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1555630030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.2907466353 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 502321563 ps |
| CPU time | 19.01 seconds |
| Started | Oct 03 04:06:10 AM UTC 24 |
| Finished | Oct 03 04:06:30 AM UTC 24 |
| Peak memory | 234744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907466353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2907466353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3207144616 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 233516837 ps |
| CPU time | 2.88 seconds |
| Started | Oct 03 04:06:06 AM UTC 24 |
| Finished | Oct 03 04:06:09 AM UTC 24 |
| Peak memory | 244656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207144616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.3207144616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3439826586 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2930330991 ps |
| CPU time | 6.5 seconds |
| Started | Oct 03 04:06:06 AM UTC 24 |
| Finished | Oct 03 04:06:13 AM UTC 24 |
| Peak memory | 234812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439826586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3439826586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2322012648 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3558723624 ps |
| CPU time | 12.94 seconds |
| Started | Oct 03 04:06:20 AM UTC 24 |
| Finished | Oct 03 04:06:34 AM UTC 24 |
| Peak memory | 231292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322012648 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.2322012648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1149112375 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 32111402944 ps |
| CPU time | 59.08 seconds |
| Started | Oct 03 04:06:01 AM UTC 24 |
| Finished | Oct 03 04:07:02 AM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149112375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1149112375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2563741602 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 409484481 ps |
| CPU time | 3.18 seconds |
| Started | Oct 03 04:06:00 AM UTC 24 |
| Finished | Oct 03 04:06:04 AM UTC 24 |
| Peak memory | 227112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563741602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2563741602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1991745318 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 37775480 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:06:04 AM UTC 24 |
| Finished | Oct 03 04:06:06 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991745318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1991745318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.2376979679 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 68030812 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:06:01 AM UTC 24 |
| Finished | Oct 03 04:06:03 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376979679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2376979679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.107886333 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 3676773483 ps |
| CPU time | 14.36 seconds |
| Started | Oct 03 04:06:10 AM UTC 24 |
| Finished | Oct 03 04:06:25 AM UTC 24 |
| Peak memory | 239808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107886333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.107886333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.1806393782 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 16508210 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:07:33 AM UTC 24 |
| Finished | Oct 03 04:07:35 AM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806393782 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.1806393782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.1046865795 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 253230670 ps |
| CPU time | 6.67 seconds |
| Started | Oct 03 04:07:21 AM UTC 24 |
| Finished | Oct 03 04:07:29 AM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046865795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1046865795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.2876055987 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 19451249 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 04:06:38 AM UTC 24 |
| Finished | Oct 03 04:06:40 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876055987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2876055987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.3236776340 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 178487678 ps |
| CPU time | 7.61 seconds |
| Started | Oct 03 04:07:26 AM UTC 24 |
| Finished | Oct 03 04:07:35 AM UTC 24 |
| Peak memory | 244996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236776340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3236776340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2693711617 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 8751009102 ps |
| CPU time | 62.28 seconds |
| Started | Oct 03 04:07:30 AM UTC 24 |
| Finished | Oct 03 04:08:34 AM UTC 24 |
| Peak memory | 235264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693711617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2693711617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2151180980 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3378127554 ps |
| CPU time | 71.15 seconds |
| Started | Oct 03 04:07:32 AM UTC 24 |
| Finished | Oct 03 04:08:45 AM UTC 24 |
| Peak memory | 261824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151180980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.2151180980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.3760892350 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1201275704 ps |
| CPU time | 21.44 seconds |
| Started | Oct 03 04:07:22 AM UTC 24 |
| Finished | Oct 03 04:07:45 AM UTC 24 |
| Peak memory | 234688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760892350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.3760892350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1651463007 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 771151217 ps |
| CPU time | 8.05 seconds |
| Started | Oct 03 04:07:14 AM UTC 24 |
| Finished | Oct 03 04:07:24 AM UTC 24 |
| Peak memory | 234780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651463007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1651463007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.3839439176 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 432528150 ps |
| CPU time | 3.49 seconds |
| Started | Oct 03 04:07:15 AM UTC 24 |
| Finished | Oct 03 04:07:20 AM UTC 24 |
| Peak memory | 244936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839439176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3839439176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3088283803 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 952549434 ps |
| CPU time | 10.5 seconds |
| Started | Oct 03 04:07:10 AM UTC 24 |
| Finished | Oct 03 04:07:22 AM UTC 24 |
| Peak memory | 244916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088283803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.3088283803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.375376186 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 31079180165 ps |
| CPU time | 35.33 seconds |
| Started | Oct 03 04:07:09 AM UTC 24 |
| Finished | Oct 03 04:07:45 AM UTC 24 |
| Peak memory | 245116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375376186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.375376186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3177016866 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 650034995 ps |
| CPU time | 5.56 seconds |
| Started | Oct 03 04:07:25 AM UTC 24 |
| Finished | Oct 03 04:07:31 AM UTC 24 |
| Peak memory | 229116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177016866 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.3177016866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2325391663 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 22499203566 ps |
| CPU time | 45.53 seconds |
| Started | Oct 03 04:06:45 AM UTC 24 |
| Finished | Oct 03 04:07:32 AM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325391663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2325391663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3227042068 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4855738262 ps |
| CPU time | 31.19 seconds |
| Started | Oct 03 04:06:44 AM UTC 24 |
| Finished | Oct 03 04:07:17 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227042068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3227042068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.2946425964 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 17463262 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 04:07:06 AM UTC 24 |
| Finished | Oct 03 04:07:08 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946425964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2946425964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1628419570 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 29205001 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 04:07:02 AM UTC 24 |
| Finished | Oct 03 04:07:04 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628419570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1628419570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1032825197 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5916087412 ps |
| CPU time | 5.64 seconds |
| Started | Oct 03 04:07:17 AM UTC 24 |
| Finished | Oct 03 04:07:24 AM UTC 24 |
| Peak memory | 245072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032825197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1032825197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.926216269 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 17521663 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 04:07:56 AM UTC 24 |
| Finished | Oct 03 04:07:58 AM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926216269 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.926216269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.112193816 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 355762243 ps |
| CPU time | 4.84 seconds |
| Started | Oct 03 04:07:46 AM UTC 24 |
| Finished | Oct 03 04:07:52 AM UTC 24 |
| Peak memory | 234700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112193816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.112193816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.342269032 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 20481577 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:07:35 AM UTC 24 |
| Finished | Oct 03 04:07:38 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342269032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.342269032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.1037245879 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 12557643 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 04:07:51 AM UTC 24 |
| Finished | Oct 03 04:07:53 AM UTC 24 |
| Peak memory | 226808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037245879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1037245879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.1205046234 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 208225842 ps |
| CPU time | 2.79 seconds |
| Started | Oct 03 04:07:52 AM UTC 24 |
| Finished | Oct 03 04:07:56 AM UTC 24 |
| Peak memory | 229420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205046234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1205046234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.3281959466 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2777704386 ps |
| CPU time | 53.31 seconds |
| Started | Oct 03 04:07:53 AM UTC 24 |
| Finished | Oct 03 04:08:48 AM UTC 24 |
| Peak memory | 261564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281959466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.3281959466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.3130719089 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 28664597909 ps |
| CPU time | 51.08 seconds |
| Started | Oct 03 04:07:46 AM UTC 24 |
| Finished | Oct 03 04:08:39 AM UTC 24 |
| Peak memory | 234812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130719089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3130719089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1435578219 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 69831137288 ps |
| CPU time | 138.79 seconds |
| Started | Oct 03 04:07:51 AM UTC 24 |
| Finished | Oct 03 04:10:12 AM UTC 24 |
| Peak memory | 261696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435578219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.1435578219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.986008296 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 533527356 ps |
| CPU time | 9.94 seconds |
| Started | Oct 03 04:07:40 AM UTC 24 |
| Finished | Oct 03 04:07:51 AM UTC 24 |
| Peak memory | 234648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986008296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.986008296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.1618697362 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1459227136 ps |
| CPU time | 14.41 seconds |
| Started | Oct 03 04:07:42 AM UTC 24 |
| Finished | Oct 03 04:07:57 AM UTC 24 |
| Peak memory | 244880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618697362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1618697362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.209646518 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3232769239 ps |
| CPU time | 16.38 seconds |
| Started | Oct 03 04:07:40 AM UTC 24 |
| Finished | Oct 03 04:07:57 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209646518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.209646518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.230782387 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 528179826 ps |
| CPU time | 5.5 seconds |
| Started | Oct 03 04:07:39 AM UTC 24 |
| Finished | Oct 03 04:07:45 AM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230782387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.230782387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.887444282 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 784835956 ps |
| CPU time | 10.54 seconds |
| Started | Oct 03 04:07:51 AM UTC 24 |
| Finished | Oct 03 04:08:03 AM UTC 24 |
| Peak memory | 233584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887444282 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.887444282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.2999496458 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1831338853 ps |
| CPU time | 17.21 seconds |
| Started | Oct 03 04:07:36 AM UTC 24 |
| Finished | Oct 03 04:07:55 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999496458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2999496458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.382239696 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4692049149 ps |
| CPU time | 18.8 seconds |
| Started | Oct 03 04:07:35 AM UTC 24 |
| Finished | Oct 03 04:07:55 AM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382239696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.382239696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.2524348915 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 90321942 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 04:07:39 AM UTC 24 |
| Finished | Oct 03 04:07:41 AM UTC 24 |
| Peak memory | 216088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524348915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2524348915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3324545602 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 26461126 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 04:07:36 AM UTC 24 |
| Finished | Oct 03 04:07:39 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324545602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3324545602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3139114063 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 540779673 ps |
| CPU time | 3.52 seconds |
| Started | Oct 03 04:07:46 AM UTC 24 |
| Finished | Oct 03 04:07:50 AM UTC 24 |
| Peak memory | 234368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139114063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3139114063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.11308972 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 46036018 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:08:31 AM UTC 24 |
| Finished | Oct 03 04:08:33 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11308972 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.11308972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.2809542697 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2207870431 ps |
| CPU time | 8.64 seconds |
| Started | Oct 03 04:08:11 AM UTC 24 |
| Finished | Oct 03 04:08:20 AM UTC 24 |
| Peak memory | 234816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809542697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2809542697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3884514187 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 78154644 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:07:57 AM UTC 24 |
| Finished | Oct 03 04:07:59 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884514187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3884514187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.2863674386 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 10744631427 ps |
| CPU time | 62.03 seconds |
| Started | Oct 03 04:08:20 AM UTC 24 |
| Finished | Oct 03 04:09:24 AM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863674386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2863674386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.2567244415 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 12221065714 ps |
| CPU time | 168.02 seconds |
| Started | Oct 03 04:08:21 AM UTC 24 |
| Finished | Oct 03 04:11:12 AM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567244415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2567244415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1890633419 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6732750172 ps |
| CPU time | 46.37 seconds |
| Started | Oct 03 04:08:23 AM UTC 24 |
| Finished | Oct 03 04:09:11 AM UTC 24 |
| Peak memory | 247220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890633419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.1890633419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3441071553 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 4389645879 ps |
| CPU time | 22.33 seconds |
| Started | Oct 03 04:08:12 AM UTC 24 |
| Finished | Oct 03 04:08:35 AM UTC 24 |
| Peak memory | 234828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441071553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3441071553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.3427942883 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 876426379 ps |
| CPU time | 7.13 seconds |
| Started | Oct 03 04:08:02 AM UTC 24 |
| Finished | Oct 03 04:08:10 AM UTC 24 |
| Peak memory | 234648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427942883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3427942883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.297472325 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 626838786 ps |
| CPU time | 8.11 seconds |
| Started | Oct 03 04:08:03 AM UTC 24 |
| Finished | Oct 03 04:08:13 AM UTC 24 |
| Peak memory | 234748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297472325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.297472325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2893739926 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 12646215603 ps |
| CPU time | 15.78 seconds |
| Started | Oct 03 04:08:02 AM UTC 24 |
| Finished | Oct 03 04:08:19 AM UTC 24 |
| Peak memory | 245112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893739926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.2893739926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.380928512 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 35445616695 ps |
| CPU time | 42.3 seconds |
| Started | Oct 03 04:08:00 AM UTC 24 |
| Finished | Oct 03 04:08:44 AM UTC 24 |
| Peak memory | 235076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380928512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.380928512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.194526841 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1297118594 ps |
| CPU time | 11.16 seconds |
| Started | Oct 03 04:08:15 AM UTC 24 |
| Finished | Oct 03 04:08:27 AM UTC 24 |
| Peak memory | 229120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194526841 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.194526841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2771191054 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 216361641 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:08:28 AM UTC 24 |
| Finished | Oct 03 04:08:30 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771191054 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.2771191054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.414526428 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 24541086103 ps |
| CPU time | 38.58 seconds |
| Started | Oct 03 04:07:58 AM UTC 24 |
| Finished | Oct 03 04:08:38 AM UTC 24 |
| Peak memory | 227340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414526428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.414526428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.398684742 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1370814783 ps |
| CPU time | 6.4 seconds |
| Started | Oct 03 04:07:58 AM UTC 24 |
| Finished | Oct 03 04:08:05 AM UTC 24 |
| Peak memory | 227272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398684742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.398684742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.3380307859 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 19594902 ps |
| CPU time | 0.91 seconds |
| Started | Oct 03 04:07:59 AM UTC 24 |
| Finished | Oct 03 04:08:01 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380307859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3380307859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.83144858 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 128247585 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 04:07:59 AM UTC 24 |
| Finished | Oct 03 04:08:02 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83144858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.83144858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.3224596203 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 290877201 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 04:08:06 AM UTC 24 |
| Finished | Oct 03 04:08:10 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224596203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3224596203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.414174943 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 20795511 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:08:50 AM UTC 24 |
| Finished | Oct 03 04:08:52 AM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414174943 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.414174943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3770156421 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 180621963 ps |
| CPU time | 2.96 seconds |
| Started | Oct 03 04:08:45 AM UTC 24 |
| Finished | Oct 03 04:08:49 AM UTC 24 |
| Peak memory | 244928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770156421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3770156421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.3443010983 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 38286833 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:08:35 AM UTC 24 |
| Finished | Oct 03 04:08:37 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443010983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3443010983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.4254587707 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 17564203805 ps |
| CPU time | 87.52 seconds |
| Started | Oct 03 04:08:49 AM UTC 24 |
| Finished | Oct 03 04:10:19 AM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254587707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4254587707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.4201989324 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5319671144 ps |
| CPU time | 96.67 seconds |
| Started | Oct 03 04:08:50 AM UTC 24 |
| Finished | Oct 03 04:10:29 AM UTC 24 |
| Peak memory | 261628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201989324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4201989324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.4284663311 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 62260238343 ps |
| CPU time | 586.21 seconds |
| Started | Oct 03 04:08:50 AM UTC 24 |
| Finished | Oct 03 04:18:45 AM UTC 24 |
| Peak memory | 278208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284663311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.4284663311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.3828801208 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 23367212404 ps |
| CPU time | 79.39 seconds |
| Started | Oct 03 04:08:47 AM UTC 24 |
| Finished | Oct 03 04:10:08 AM UTC 24 |
| Peak memory | 261428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828801208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.3828801208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3637874396 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 615307449 ps |
| CPU time | 7.95 seconds |
| Started | Oct 03 04:08:40 AM UTC 24 |
| Finished | Oct 03 04:08:49 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637874396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3637874396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.1568504934 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 758796780 ps |
| CPU time | 12.7 seconds |
| Started | Oct 03 04:08:41 AM UTC 24 |
| Finished | Oct 03 04:08:55 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568504934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1568504934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2783881438 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 262053268 ps |
| CPU time | 2.6 seconds |
| Started | Oct 03 04:08:40 AM UTC 24 |
| Finished | Oct 03 04:08:44 AM UTC 24 |
| Peak memory | 234576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783881438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.2783881438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3928698521 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 285773838 ps |
| CPU time | 6.18 seconds |
| Started | Oct 03 04:08:39 AM UTC 24 |
| Finished | Oct 03 04:08:46 AM UTC 24 |
| Peak memory | 234632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928698521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3928698521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.1837520918 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5500234480 ps |
| CPU time | 14.23 seconds |
| Started | Oct 03 04:08:49 AM UTC 24 |
| Finished | Oct 03 04:09:04 AM UTC 24 |
| Peak memory | 231292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837520918 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.1837520918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.2239669072 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 45008351521 ps |
| CPU time | 163.95 seconds |
| Started | Oct 03 04:08:50 AM UTC 24 |
| Finished | Oct 03 04:11:37 AM UTC 24 |
| Peak memory | 263616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239669072 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.2239669072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.2293391128 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1978306501 ps |
| CPU time | 38.49 seconds |
| Started | Oct 03 04:08:36 AM UTC 24 |
| Finished | Oct 03 04:09:16 AM UTC 24 |
| Peak memory | 227432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293391128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2293391128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2732688765 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2245435902 ps |
| CPU time | 14.18 seconds |
| Started | Oct 03 04:08:36 AM UTC 24 |
| Finished | Oct 03 04:08:51 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732688765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2732688765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.2737392582 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 313671380 ps |
| CPU time | 10.01 seconds |
| Started | Oct 03 04:08:38 AM UTC 24 |
| Finished | Oct 03 04:08:49 AM UTC 24 |
| Peak memory | 227436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737392582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2737392582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2674447711 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 69966261 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 04:08:38 AM UTC 24 |
| Finished | Oct 03 04:08:40 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674447711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2674447711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.1374235667 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1361284897 ps |
| CPU time | 3.63 seconds |
| Started | Oct 03 04:08:44 AM UTC 24 |
| Finished | Oct 03 04:08:49 AM UTC 24 |
| Peak memory | 244988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374235667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1374235667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.577773411 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 83783923 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 04:09:16 AM UTC 24 |
| Finished | Oct 03 04:09:19 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577773411 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.577773411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2693301611 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 281994945 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 04:09:05 AM UTC 24 |
| Finished | Oct 03 04:09:10 AM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693301611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2693301611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.167398423 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 44228416 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 04:08:52 AM UTC 24 |
| Finished | Oct 03 04:08:54 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167398423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.167398423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1004632506 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 21581309519 ps |
| CPU time | 142.54 seconds |
| Started | Oct 03 04:09:12 AM UTC 24 |
| Finished | Oct 03 04:11:37 AM UTC 24 |
| Peak memory | 261700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004632506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1004632506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.863001224 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 31315510519 ps |
| CPU time | 80.7 seconds |
| Started | Oct 03 04:09:13 AM UTC 24 |
| Finished | Oct 03 04:10:36 AM UTC 24 |
| Peak memory | 267704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863001224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.863001224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.4277955050 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 377185995010 ps |
| CPU time | 794.59 seconds |
| Started | Oct 03 04:09:13 AM UTC 24 |
| Finished | Oct 03 04:22:38 AM UTC 24 |
| Peak memory | 273856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277955050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.4277955050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.293298582 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 917592947 ps |
| CPU time | 4.72 seconds |
| Started | Oct 03 04:09:08 AM UTC 24 |
| Finished | Oct 03 04:09:14 AM UTC 24 |
| Peak memory | 234648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293298582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.293298582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3193159219 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 12338952232 ps |
| CPU time | 69.28 seconds |
| Started | Oct 03 04:09:08 AM UTC 24 |
| Finished | Oct 03 04:10:19 AM UTC 24 |
| Peak memory | 263480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193159219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.3193159219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.661508725 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 4802909200 ps |
| CPU time | 16.89 seconds |
| Started | Oct 03 04:08:59 AM UTC 24 |
| Finished | Oct 03 04:09:18 AM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661508725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.661508725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.3919208814 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3105112595 ps |
| CPU time | 11.45 seconds |
| Started | Oct 03 04:08:59 AM UTC 24 |
| Finished | Oct 03 04:09:12 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919208814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3919208814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.3758551400 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4295223295 ps |
| CPU time | 20.71 seconds |
| Started | Oct 03 04:08:56 AM UTC 24 |
| Finished | Oct 03 04:09:18 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758551400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3758551400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.57801125 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 157538286 ps |
| CPU time | 4.79 seconds |
| Started | Oct 03 04:09:11 AM UTC 24 |
| Finished | Oct 03 04:09:17 AM UTC 24 |
| Peak memory | 233624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57801125 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.57801125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.112362679 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 63346358013 ps |
| CPU time | 734.87 seconds |
| Started | Oct 03 04:09:14 AM UTC 24 |
| Finished | Oct 03 04:21:40 AM UTC 24 |
| Peak memory | 277956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112362679 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.112362679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.4022041930 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5193301895 ps |
| CPU time | 35.37 seconds |
| Started | Oct 03 04:08:55 AM UTC 24 |
| Finished | Oct 03 04:09:32 AM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022041930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4022041930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2336791311 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 28209713 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 04:08:54 AM UTC 24 |
| Finished | Oct 03 04:08:56 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336791311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2336791311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.178013209 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 14878324 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:08:56 AM UTC 24 |
| Finished | Oct 03 04:08:58 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178013209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.178013209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.2136907553 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 108945751 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 04:08:56 AM UTC 24 |
| Finished | Oct 03 04:08:58 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136907553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2136907553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.1648794014 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 51970531 ps |
| CPU time | 3.53 seconds |
| Started | Oct 03 04:09:03 AM UTC 24 |
| Finished | Oct 03 04:09:07 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648794014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1648794014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.2476201860 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 11445949 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 04:09:34 AM UTC 24 |
| Finished | Oct 03 04:09:37 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476201860 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.2476201860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.2777560760 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 818052791 ps |
| CPU time | 5.57 seconds |
| Started | Oct 03 04:09:26 AM UTC 24 |
| Finished | Oct 03 04:09:32 AM UTC 24 |
| Peak memory | 234676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777560760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2777560760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.4212629223 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 20512337 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:09:19 AM UTC 24 |
| Finished | Oct 03 04:09:21 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212629223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4212629223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.1257943585 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 63044848535 ps |
| CPU time | 159.7 seconds |
| Started | Oct 03 04:09:33 AM UTC 24 |
| Finished | Oct 03 04:12:16 AM UTC 24 |
| Peak memory | 267592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257943585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1257943585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3510174021 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 16701436065 ps |
| CPU time | 53.41 seconds |
| Started | Oct 03 04:09:33 AM UTC 24 |
| Finished | Oct 03 04:10:28 AM UTC 24 |
| Peak memory | 268040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510174021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3510174021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2645325523 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 25058814684 ps |
| CPU time | 283.19 seconds |
| Started | Oct 03 04:09:33 AM UTC 24 |
| Finished | Oct 03 04:14:21 AM UTC 24 |
| Peak memory | 261824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645325523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2645325523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.4037542860 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 3143646745 ps |
| CPU time | 57.74 seconds |
| Started | Oct 03 04:09:32 AM UTC 24 |
| Finished | Oct 03 04:10:31 AM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037542860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4037542860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2596132557 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 5224500943 ps |
| CPU time | 19.13 seconds |
| Started | Oct 03 04:09:33 AM UTC 24 |
| Finished | Oct 03 04:09:54 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596132557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.2596132557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.324192210 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1352716830 ps |
| CPU time | 8.42 seconds |
| Started | Oct 03 04:09:24 AM UTC 24 |
| Finished | Oct 03 04:09:34 AM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324192210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.324192210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.1783974456 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 12746203496 ps |
| CPU time | 41.81 seconds |
| Started | Oct 03 04:09:24 AM UTC 24 |
| Finished | Oct 03 04:10:08 AM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783974456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1783974456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.4012076257 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1234387592 ps |
| CPU time | 6.48 seconds |
| Started | Oct 03 04:09:23 AM UTC 24 |
| Finished | Oct 03 04:09:31 AM UTC 24 |
| Peak memory | 234636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012076257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.4012076257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1080632990 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1014606181 ps |
| CPU time | 9.33 seconds |
| Started | Oct 03 04:09:22 AM UTC 24 |
| Finished | Oct 03 04:09:33 AM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080632990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1080632990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.113925825 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2919170323 ps |
| CPU time | 14.09 seconds |
| Started | Oct 03 04:09:33 AM UTC 24 |
| Finished | Oct 03 04:09:49 AM UTC 24 |
| Peak memory | 231620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113925825 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.113925825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.978610287 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 59325099 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 04:09:34 AM UTC 24 |
| Finished | Oct 03 04:09:37 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978610287 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.978610287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.3521717774 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 600936848 ps |
| CPU time | 12.15 seconds |
| Started | Oct 03 04:09:20 AM UTC 24 |
| Finished | Oct 03 04:09:33 AM UTC 24 |
| Peak memory | 227368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521717774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3521717774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.2516878527 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3065085085 ps |
| CPU time | 11.75 seconds |
| Started | Oct 03 04:09:20 AM UTC 24 |
| Finished | Oct 03 04:09:33 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516878527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2516878527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.74722430 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 21332755 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 04:09:22 AM UTC 24 |
| Finished | Oct 03 04:09:24 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74722430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.74722430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3934403901 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 34832480 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 04:09:21 AM UTC 24 |
| Finished | Oct 03 04:09:23 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934403901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3934403901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.1297717025 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4208163656 ps |
| CPU time | 5.72 seconds |
| Started | Oct 03 04:09:26 AM UTC 24 |
| Finished | Oct 03 04:09:32 AM UTC 24 |
| Peak memory | 247108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297717025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1297717025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.2360597474 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 11627258 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:10:02 AM UTC 24 |
| Finished | Oct 03 04:10:04 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360597474 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.2360597474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.945257841 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 902638602 ps |
| CPU time | 6.8 seconds |
| Started | Oct 03 04:09:53 AM UTC 24 |
| Finished | Oct 03 04:10:01 AM UTC 24 |
| Peak memory | 245180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945257841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.945257841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.3453086984 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 13310747 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 04:09:34 AM UTC 24 |
| Finished | Oct 03 04:09:37 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453086984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3453086984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.41956126 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 91955982663 ps |
| CPU time | 214.31 seconds |
| Started | Oct 03 04:09:54 AM UTC 24 |
| Finished | Oct 03 04:13:32 AM UTC 24 |
| Peak memory | 261448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41956126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.41956126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.655717255 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2385729198 ps |
| CPU time | 8.67 seconds |
| Started | Oct 03 04:09:53 AM UTC 24 |
| Finished | Oct 03 04:10:03 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655717255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.655717255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1274153349 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 32307668162 ps |
| CPU time | 175.59 seconds |
| Started | Oct 03 04:09:53 AM UTC 24 |
| Finished | Oct 03 04:12:51 AM UTC 24 |
| Peak memory | 281872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274153349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.1274153349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.2421477966 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 276287799 ps |
| CPU time | 3.22 seconds |
| Started | Oct 03 04:09:48 AM UTC 24 |
| Finished | Oct 03 04:09:53 AM UTC 24 |
| Peak memory | 234056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421477966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2421477966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.3029496603 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 12903289326 ps |
| CPU time | 13.34 seconds |
| Started | Oct 03 04:09:49 AM UTC 24 |
| Finished | Oct 03 04:10:04 AM UTC 24 |
| Peak memory | 234876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029496603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3029496603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.3724362245 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 32897859 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 04:09:48 AM UTC 24 |
| Finished | Oct 03 04:09:52 AM UTC 24 |
| Peak memory | 244736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724362245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.3724362245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.458213898 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 693154780 ps |
| CPU time | 3.35 seconds |
| Started | Oct 03 04:09:47 AM UTC 24 |
| Finished | Oct 03 04:09:51 AM UTC 24 |
| Peak memory | 244984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458213898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.458213898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.3230536764 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 957894497 ps |
| CPU time | 5.45 seconds |
| Started | Oct 03 04:09:54 AM UTC 24 |
| Finished | Oct 03 04:10:00 AM UTC 24 |
| Peak memory | 229372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230536764 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.3230536764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.3077134436 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 77483296530 ps |
| CPU time | 905.77 seconds |
| Started | Oct 03 04:10:01 AM UTC 24 |
| Finished | Oct 03 04:25:19 AM UTC 24 |
| Peak memory | 278268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077134436 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.3077134436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.2697873744 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 5314815482 ps |
| CPU time | 40.88 seconds |
| Started | Oct 03 04:09:38 AM UTC 24 |
| Finished | Oct 03 04:10:20 AM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697873744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2697873744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3196525743 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 4981821529 ps |
| CPU time | 7.36 seconds |
| Started | Oct 03 04:09:38 AM UTC 24 |
| Finished | Oct 03 04:09:46 AM UTC 24 |
| Peak memory | 227776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196525743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3196525743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.2244133035 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 97826834 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 04:09:44 AM UTC 24 |
| Finished | Oct 03 04:09:47 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244133035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2244133035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1663995190 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 27992443 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 04:09:41 AM UTC 24 |
| Finished | Oct 03 04:09:43 AM UTC 24 |
| Peak memory | 215888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663995190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1663995190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.1101530259 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 15685315775 ps |
| CPU time | 47.13 seconds |
| Started | Oct 03 04:09:49 AM UTC 24 |
| Finished | Oct 03 04:10:38 AM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101530259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1101530259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.2707144499 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 24094290 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 04:10:20 AM UTC 24 |
| Finished | Oct 03 04:10:22 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707144499 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.2707144499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3102180821 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 90160502 ps |
| CPU time | 2.97 seconds |
| Started | Oct 03 04:10:12 AM UTC 24 |
| Finished | Oct 03 04:10:16 AM UTC 24 |
| Peak memory | 234232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102180821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3102180821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.2009818354 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 41504742 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:10:04 AM UTC 24 |
| Finished | Oct 03 04:10:06 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009818354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2009818354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1252855083 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 9121250930 ps |
| CPU time | 26.4 seconds |
| Started | Oct 03 04:10:16 AM UTC 24 |
| Finished | Oct 03 04:10:44 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252855083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1252855083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2507895276 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3492356607 ps |
| CPU time | 55.89 seconds |
| Started | Oct 03 04:10:19 AM UTC 24 |
| Finished | Oct 03 04:11:16 AM UTC 24 |
| Peak memory | 261888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507895276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.2507895276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.1484490046 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 103908618174 ps |
| CPU time | 327.91 seconds |
| Started | Oct 03 04:10:15 AM UTC 24 |
| Finished | Oct 03 04:15:48 AM UTC 24 |
| Peak memory | 263488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484490046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.1484490046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.2080800593 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 214310938 ps |
| CPU time | 4.06 seconds |
| Started | Oct 03 04:10:10 AM UTC 24 |
| Finished | Oct 03 04:10:15 AM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080800593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2080800593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.65233154 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 642793871 ps |
| CPU time | 18.58 seconds |
| Started | Oct 03 04:10:10 AM UTC 24 |
| Finished | Oct 03 04:10:29 AM UTC 24 |
| Peak memory | 249028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65233154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.65233154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3021352320 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 505427056 ps |
| CPU time | 6.3 seconds |
| Started | Oct 03 04:10:08 AM UTC 24 |
| Finished | Oct 03 04:10:16 AM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021352320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.3021352320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.485549653 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 4696822138 ps |
| CPU time | 8.01 seconds |
| Started | Oct 03 04:10:08 AM UTC 24 |
| Finished | Oct 03 04:10:17 AM UTC 24 |
| Peak memory | 234808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485549653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.485549653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.23791631 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3811382887 ps |
| CPU time | 7.43 seconds |
| Started | Oct 03 04:10:16 AM UTC 24 |
| Finished | Oct 03 04:10:25 AM UTC 24 |
| Peak memory | 231400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23791631 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.23791631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.1295749928 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 34229357 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 04:10:20 AM UTC 24 |
| Finished | Oct 03 04:10:22 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295749928 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.1295749928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2754186089 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 32240222 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:10:06 AM UTC 24 |
| Finished | Oct 03 04:10:08 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754186089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2754186089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2882747266 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3852653269 ps |
| CPU time | 23.28 seconds |
| Started | Oct 03 04:10:05 AM UTC 24 |
| Finished | Oct 03 04:10:29 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882747266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2882747266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.819054257 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 32641489 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 04:10:08 AM UTC 24 |
| Finished | Oct 03 04:10:10 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819054257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.819054257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3628028975 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 95145006 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 04:10:07 AM UTC 24 |
| Finished | Oct 03 04:10:09 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628028975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3628028975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3282847935 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 816321663 ps |
| CPU time | 12.21 seconds |
| Started | Oct 03 04:10:11 AM UTC 24 |
| Finished | Oct 03 04:10:24 AM UTC 24 |
| Peak memory | 234744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282847935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3282847935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.47617150 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 37518699 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 04:10:37 AM UTC 24 |
| Finished | Oct 03 04:10:39 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47617150 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.47617150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.3811057991 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 138979314 ps |
| CPU time | 4.58 seconds |
| Started | Oct 03 04:10:30 AM UTC 24 |
| Finished | Oct 03 04:10:35 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811057991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3811057991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.2675886268 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 44349329 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:10:21 AM UTC 24 |
| Finished | Oct 03 04:10:23 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675886268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2675886268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.3117302960 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 44196906444 ps |
| CPU time | 109.17 seconds |
| Started | Oct 03 04:10:30 AM UTC 24 |
| Finished | Oct 03 04:12:21 AM UTC 24 |
| Peak memory | 265492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117302960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3117302960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.59816896 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 99892108012 ps |
| CPU time | 339.57 seconds |
| Started | Oct 03 04:10:32 AM UTC 24 |
| Finished | Oct 03 04:16:17 AM UTC 24 |
| Peak memory | 265984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59816896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.59816896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.3521412488 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 51484744827 ps |
| CPU time | 508.08 seconds |
| Started | Oct 03 04:10:32 AM UTC 24 |
| Finished | Oct 03 04:19:07 AM UTC 24 |
| Peak memory | 267708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521412488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.3521412488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1105173384 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 733575882 ps |
| CPU time | 11.08 seconds |
| Started | Oct 03 04:10:30 AM UTC 24 |
| Finished | Oct 03 04:10:42 AM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105173384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1105173384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.621631986 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 90422431442 ps |
| CPU time | 358.74 seconds |
| Started | Oct 03 04:10:30 AM UTC 24 |
| Finished | Oct 03 04:16:34 AM UTC 24 |
| Peak memory | 265516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621631986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.621631986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.746835638 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 301254832 ps |
| CPU time | 3.19 seconds |
| Started | Oct 03 04:10:27 AM UTC 24 |
| Finished | Oct 03 04:10:32 AM UTC 24 |
| Peak memory | 233804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746835638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.746835638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.502205860 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 512283410 ps |
| CPU time | 11.75 seconds |
| Started | Oct 03 04:10:29 AM UTC 24 |
| Finished | Oct 03 04:10:41 AM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502205860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.502205860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3428961669 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 11402702675 ps |
| CPU time | 18.68 seconds |
| Started | Oct 03 04:10:27 AM UTC 24 |
| Finished | Oct 03 04:10:47 AM UTC 24 |
| Peak memory | 234764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428961669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.3428961669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.471902091 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5788877027 ps |
| CPU time | 15.37 seconds |
| Started | Oct 03 04:10:26 AM UTC 24 |
| Finished | Oct 03 04:10:43 AM UTC 24 |
| Peak memory | 245312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471902091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.471902091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2290720484 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 437429687 ps |
| CPU time | 6.14 seconds |
| Started | Oct 03 04:10:30 AM UTC 24 |
| Finished | Oct 03 04:10:37 AM UTC 24 |
| Peak memory | 231156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290720484 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.2290720484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.3960498183 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 12187857696 ps |
| CPU time | 148.02 seconds |
| Started | Oct 03 04:10:35 AM UTC 24 |
| Finished | Oct 03 04:13:06 AM UTC 24 |
| Peak memory | 265980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960498183 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.3960498183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.576181644 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 60380459 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 04:10:24 AM UTC 24 |
| Finished | Oct 03 04:10:26 AM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576181644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.576181644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.203291098 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 254665146 ps |
| CPU time | 2.85 seconds |
| Started | Oct 03 04:10:23 AM UTC 24 |
| Finished | Oct 03 04:10:27 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203291098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.203291098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.2492050662 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 116795364 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 04:10:25 AM UTC 24 |
| Finished | Oct 03 04:10:29 AM UTC 24 |
| Peak memory | 227712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492050662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2492050662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.352210215 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 96494197 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 04:10:25 AM UTC 24 |
| Finished | Oct 03 04:10:28 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352210215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.352210215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.1852810104 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 9343502813 ps |
| CPU time | 45.96 seconds |
| Started | Oct 03 04:10:29 AM UTC 24 |
| Finished | Oct 03 04:11:16 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852810104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1852810104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.713458342 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 26787732 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 03:59:01 AM UTC 24 |
| Finished | Oct 03 03:59:03 AM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713458342 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.713458342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.4240995380 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 419671468 ps |
| CPU time | 8.66 seconds |
| Started | Oct 03 03:58:23 AM UTC 24 |
| Finished | Oct 03 03:58:33 AM UTC 24 |
| Peak memory | 234632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240995380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4240995380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1616611824 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 18720996 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 03:57:50 AM UTC 24 |
| Finished | Oct 03 03:57:52 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616611824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1616611824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3793453916 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2534200279 ps |
| CPU time | 48.45 seconds |
| Started | Oct 03 03:58:47 AM UTC 24 |
| Finished | Oct 03 03:59:38 AM UTC 24 |
| Peak memory | 265860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793453916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3793453916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.3945052151 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 14374126095 ps |
| CPU time | 151.26 seconds |
| Started | Oct 03 03:58:47 AM UTC 24 |
| Finished | Oct 03 04:01:22 AM UTC 24 |
| Peak memory | 263756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945052151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3945052151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1821345034 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3957657251 ps |
| CPU time | 24.45 seconds |
| Started | Oct 03 03:58:48 AM UTC 24 |
| Finished | Oct 03 03:59:14 AM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821345034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.1821345034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.1416809178 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2720737813 ps |
| CPU time | 29.79 seconds |
| Started | Oct 03 03:58:25 AM UTC 24 |
| Finished | Oct 03 03:58:57 AM UTC 24 |
| Peak memory | 234816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416809178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1416809178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.1754516654 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1910921510 ps |
| CPU time | 20.26 seconds |
| Started | Oct 03 03:58:16 AM UTC 24 |
| Finished | Oct 03 03:58:38 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754516654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1754516654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.580161591 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1260625807 ps |
| CPU time | 29.29 seconds |
| Started | Oct 03 03:58:16 AM UTC 24 |
| Finished | Oct 03 03:58:47 AM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580161591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.580161591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.9693670 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 6210589629 ps |
| CPU time | 16.79 seconds |
| Started | Oct 03 03:58:06 AM UTC 24 |
| Finished | Oct 03 03:58:24 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9693670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.9693670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3969620803 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 241064190 ps |
| CPU time | 10.82 seconds |
| Started | Oct 03 03:58:03 AM UTC 24 |
| Finished | Oct 03 03:58:15 AM UTC 24 |
| Peak memory | 244924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969620803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3969620803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.34790705 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 92408826 ps |
| CPU time | 5.95 seconds |
| Started | Oct 03 03:58:39 AM UTC 24 |
| Finished | Oct 03 03:58:46 AM UTC 24 |
| Peak memory | 233804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34790705 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.34790705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.313259123 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 123838331 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 03:58:58 AM UTC 24 |
| Finished | Oct 03 03:59:00 AM UTC 24 |
| Peak memory | 256992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313259123 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.313259123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3418622315 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8275412757 ps |
| CPU time | 51.89 seconds |
| Started | Oct 03 03:57:53 AM UTC 24 |
| Finished | Oct 03 03:58:46 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418622315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3418622315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3936771582 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 569231425 ps |
| CPU time | 7.59 seconds |
| Started | Oct 03 03:57:53 AM UTC 24 |
| Finished | Oct 03 03:58:01 AM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936771582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3936771582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.168433308 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 87405361 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 03:58:02 AM UTC 24 |
| Finished | Oct 03 03:58:06 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168433308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.168433308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.763501112 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 200540786 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 03:58:00 AM UTC 24 |
| Finished | Oct 03 03:58:03 AM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763501112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.763501112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.479614046 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 91189167 ps |
| CPU time | 3.42 seconds |
| Started | Oct 03 03:58:18 AM UTC 24 |
| Finished | Oct 03 03:58:22 AM UTC 24 |
| Peak memory | 234376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479614046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.479614046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.2995276069 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 53967844 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 04:10:51 AM UTC 24 |
| Finished | Oct 03 04:10:53 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995276069 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.2995276069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.3112511532 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2319720877 ps |
| CPU time | 10.07 seconds |
| Started | Oct 03 04:10:44 AM UTC 24 |
| Finished | Oct 03 04:10:56 AM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112511532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3112511532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2882160620 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 33580704 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 04:10:37 AM UTC 24 |
| Finished | Oct 03 04:10:39 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882160620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2882160620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2620411738 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 10377836564 ps |
| CPU time | 75.86 seconds |
| Started | Oct 03 04:10:49 AM UTC 24 |
| Finished | Oct 03 04:12:07 AM UTC 24 |
| Peak memory | 267972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620411738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2620411738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.1392641422 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 15945639833 ps |
| CPU time | 108.22 seconds |
| Started | Oct 03 04:10:50 AM UTC 24 |
| Finished | Oct 03 04:12:41 AM UTC 24 |
| Peak memory | 263612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392641422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.1392641422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.490837546 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 17158393497 ps |
| CPU time | 58.29 seconds |
| Started | Oct 03 04:10:45 AM UTC 24 |
| Finished | Oct 03 04:11:44 AM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490837546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.490837546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1411508513 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 37420143981 ps |
| CPU time | 109.42 seconds |
| Started | Oct 03 04:10:48 AM UTC 24 |
| Finished | Oct 03 04:12:39 AM UTC 24 |
| Peak memory | 263476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411508513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.1411508513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.3145736385 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 842394387 ps |
| CPU time | 6.21 seconds |
| Started | Oct 03 04:10:43 AM UTC 24 |
| Finished | Oct 03 04:10:51 AM UTC 24 |
| Peak memory | 234756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145736385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3145736385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.3634350926 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2750878068 ps |
| CPU time | 14.58 seconds |
| Started | Oct 03 04:10:43 AM UTC 24 |
| Finished | Oct 03 04:10:59 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634350926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3634350926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2104334642 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 734450142 ps |
| CPU time | 4.09 seconds |
| Started | Oct 03 04:10:43 AM UTC 24 |
| Finished | Oct 03 04:10:48 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104334642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.2104334642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.2933396774 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 155545110 ps |
| CPU time | 4.28 seconds |
| Started | Oct 03 04:10:42 AM UTC 24 |
| Finished | Oct 03 04:10:47 AM UTC 24 |
| Peak memory | 234700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933396774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2933396774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.4122645657 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 5952488450 ps |
| CPU time | 18.44 seconds |
| Started | Oct 03 04:10:49 AM UTC 24 |
| Finished | Oct 03 04:11:08 AM UTC 24 |
| Peak memory | 233428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122645657 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.4122645657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.648892361 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 95318506 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 04:10:51 AM UTC 24 |
| Finished | Oct 03 04:10:54 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648892361 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.648892361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.361829130 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 18915331451 ps |
| CPU time | 24.74 seconds |
| Started | Oct 03 04:10:39 AM UTC 24 |
| Finished | Oct 03 04:11:05 AM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361829130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.361829130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1792207883 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 642054353 ps |
| CPU time | 3.21 seconds |
| Started | Oct 03 04:10:38 AM UTC 24 |
| Finished | Oct 03 04:10:42 AM UTC 24 |
| Peak memory | 216880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792207883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1792207883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.3238681584 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 65527612 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 04:10:40 AM UTC 24 |
| Finished | Oct 03 04:10:43 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238681584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3238681584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1823774391 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 140265093 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 04:10:40 AM UTC 24 |
| Finished | Oct 03 04:10:42 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823774391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1823774391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.3102764524 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 252612857 ps |
| CPU time | 4.13 seconds |
| Started | Oct 03 04:10:44 AM UTC 24 |
| Finished | Oct 03 04:10:50 AM UTC 24 |
| Peak memory | 234636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102764524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3102764524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.1519591036 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 33524984 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 04:11:15 AM UTC 24 |
| Finished | Oct 03 04:11:18 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519591036 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1519591036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.1444047149 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 124174938 ps |
| CPU time | 3.33 seconds |
| Started | Oct 03 04:11:06 AM UTC 24 |
| Finished | Oct 03 04:11:10 AM UTC 24 |
| Peak memory | 244920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444047149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1444047149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2547208965 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 37148114 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:10:54 AM UTC 24 |
| Finished | Oct 03 04:10:57 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547208965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2547208965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.3872677614 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2567623263 ps |
| CPU time | 47.62 seconds |
| Started | Oct 03 04:11:11 AM UTC 24 |
| Finished | Oct 03 04:12:01 AM UTC 24 |
| Peak memory | 261448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872677614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3872677614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1619367186 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1251448978 ps |
| CPU time | 24.1 seconds |
| Started | Oct 03 04:11:13 AM UTC 24 |
| Finished | Oct 03 04:11:38 AM UTC 24 |
| Peak memory | 241976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619367186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1619367186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1966677449 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 72281991019 ps |
| CPU time | 442.06 seconds |
| Started | Oct 03 04:11:14 AM UTC 24 |
| Finished | Oct 03 04:18:43 AM UTC 24 |
| Peak memory | 278204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966677449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.1966677449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3724718468 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 670450476 ps |
| CPU time | 5.72 seconds |
| Started | Oct 03 04:11:07 AM UTC 24 |
| Finished | Oct 03 04:11:14 AM UTC 24 |
| Peak memory | 244928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724718468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3724718468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.1779562625 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 16319936587 ps |
| CPU time | 166.18 seconds |
| Started | Oct 03 04:11:08 AM UTC 24 |
| Finished | Oct 03 04:13:58 AM UTC 24 |
| Peak memory | 265528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779562625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.1779562625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1855878550 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 53105753 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 04:11:01 AM UTC 24 |
| Finished | Oct 03 04:11:06 AM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855878550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1855878550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.737827834 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 868321795 ps |
| CPU time | 20.41 seconds |
| Started | Oct 03 04:11:03 AM UTC 24 |
| Finished | Oct 03 04:11:25 AM UTC 24 |
| Peak memory | 234748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737827834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.737827834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3689608134 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 164217664 ps |
| CPU time | 3.35 seconds |
| Started | Oct 03 04:11:01 AM UTC 24 |
| Finished | Oct 03 04:11:05 AM UTC 24 |
| Peak memory | 244656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689608134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3689608134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1727212624 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2718693612 ps |
| CPU time | 18.92 seconds |
| Started | Oct 03 04:11:01 AM UTC 24 |
| Finished | Oct 03 04:11:21 AM UTC 24 |
| Peak memory | 245124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727212624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1727212624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.4200714002 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 3573191049 ps |
| CPU time | 11.01 seconds |
| Started | Oct 03 04:11:09 AM UTC 24 |
| Finished | Oct 03 04:11:22 AM UTC 24 |
| Peak memory | 233764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200714002 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.4200714002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1953569278 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 323580155451 ps |
| CPU time | 366.15 seconds |
| Started | Oct 03 04:11:14 AM UTC 24 |
| Finished | Oct 03 04:17:26 AM UTC 24 |
| Peak memory | 277952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953569278 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.1953569278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.3103188905 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 8444582070 ps |
| CPU time | 29.82 seconds |
| Started | Oct 03 04:10:56 AM UTC 24 |
| Finished | Oct 03 04:11:27 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103188905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3103188905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2664243940 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 3086913297 ps |
| CPU time | 17.9 seconds |
| Started | Oct 03 04:10:54 AM UTC 24 |
| Finished | Oct 03 04:11:14 AM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664243940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2664243940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.1171287664 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 78802810 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 04:10:58 AM UTC 24 |
| Finished | Oct 03 04:11:01 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171287664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1171287664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.332215563 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 60958929 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 04:10:57 AM UTC 24 |
| Finished | Oct 03 04:11:00 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332215563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.332215563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.1192998764 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1006318175 ps |
| CPU time | 7.05 seconds |
| Started | Oct 03 04:11:06 AM UTC 24 |
| Finished | Oct 03 04:11:14 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192998764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1192998764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.1059621392 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 81570000 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:11:30 AM UTC 24 |
| Finished | Oct 03 04:11:32 AM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059621392 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.1059621392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2620517179 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1284983193 ps |
| CPU time | 5.72 seconds |
| Started | Oct 03 04:11:22 AM UTC 24 |
| Finished | Oct 03 04:11:29 AM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620517179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2620517179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.3482664489 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 17007831 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:11:15 AM UTC 24 |
| Finished | Oct 03 04:11:18 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482664489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3482664489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.2978775338 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 28256276419 ps |
| CPU time | 318.35 seconds |
| Started | Oct 03 04:11:25 AM UTC 24 |
| Finished | Oct 03 04:16:48 AM UTC 24 |
| Peak memory | 267588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978775338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2978775338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.1513525559 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 63075980670 ps |
| CPU time | 153.42 seconds |
| Started | Oct 03 04:11:27 AM UTC 24 |
| Finished | Oct 03 04:14:03 AM UTC 24 |
| Peak memory | 265668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513525559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1513525559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3683688434 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 28603783129 ps |
| CPU time | 308.55 seconds |
| Started | Oct 03 04:11:29 AM UTC 24 |
| Finished | Oct 03 04:16:42 AM UTC 24 |
| Peak memory | 263872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683688434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.3683688434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.2805245068 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 252804308 ps |
| CPU time | 8.62 seconds |
| Started | Oct 03 04:11:22 AM UTC 24 |
| Finished | Oct 03 04:11:32 AM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805245068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2805245068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.4160488440 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 63372533094 ps |
| CPU time | 169.17 seconds |
| Started | Oct 03 04:11:22 AM UTC 24 |
| Finished | Oct 03 04:14:14 AM UTC 24 |
| Peak memory | 265588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160488440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.4160488440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.3960069904 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2520140273 ps |
| CPU time | 26.49 seconds |
| Started | Oct 03 04:11:21 AM UTC 24 |
| Finished | Oct 03 04:11:49 AM UTC 24 |
| Peak memory | 245400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960069904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3960069904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.584561006 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 137528938 ps |
| CPU time | 4.35 seconds |
| Started | Oct 03 04:11:21 AM UTC 24 |
| Finished | Oct 03 04:11:26 AM UTC 24 |
| Peak memory | 234644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584561006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.584561006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.2074589017 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1422384926 ps |
| CPU time | 8.69 seconds |
| Started | Oct 03 04:11:21 AM UTC 24 |
| Finished | Oct 03 04:11:30 AM UTC 24 |
| Peak memory | 251128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074589017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.2074589017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.3582825742 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 805441143 ps |
| CPU time | 12.94 seconds |
| Started | Oct 03 04:11:19 AM UTC 24 |
| Finished | Oct 03 04:11:33 AM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582825742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3582825742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1456477532 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 189397005 ps |
| CPU time | 6.74 seconds |
| Started | Oct 03 04:11:23 AM UTC 24 |
| Finished | Oct 03 04:11:31 AM UTC 24 |
| Peak memory | 233272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456477532 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.1456477532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.1614957177 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 6496150628 ps |
| CPU time | 186.7 seconds |
| Started | Oct 03 04:11:29 AM UTC 24 |
| Finished | Oct 03 04:14:39 AM UTC 24 |
| Peak memory | 294592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614957177 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.1614957177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1159782637 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 17358580 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:11:17 AM UTC 24 |
| Finished | Oct 03 04:11:20 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159782637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1159782637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.3285954495 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 205533730 ps |
| CPU time | 3.7 seconds |
| Started | Oct 03 04:11:15 AM UTC 24 |
| Finished | Oct 03 04:11:20 AM UTC 24 |
| Peak memory | 227108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285954495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3285954495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.1636395998 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 33419149 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 04:11:18 AM UTC 24 |
| Finished | Oct 03 04:11:21 AM UTC 24 |
| Peak memory | 227288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636395998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1636395998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3546043437 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 26114000 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 04:11:17 AM UTC 24 |
| Finished | Oct 03 04:11:20 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546043437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3546043437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.2274026687 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4861581104 ps |
| CPU time | 12.24 seconds |
| Started | Oct 03 04:11:22 AM UTC 24 |
| Finished | Oct 03 04:11:35 AM UTC 24 |
| Peak memory | 241804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274026687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2274026687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.3672896839 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 13115654 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:11:48 AM UTC 24 |
| Finished | Oct 03 04:11:50 AM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672896839 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.3672896839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.2289147853 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 414523586 ps |
| CPU time | 6.63 seconds |
| Started | Oct 03 04:11:38 AM UTC 24 |
| Finished | Oct 03 04:11:46 AM UTC 24 |
| Peak memory | 244992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289147853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2289147853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2631694621 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 43844311 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 04:11:31 AM UTC 24 |
| Finished | Oct 03 04:11:33 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631694621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2631694621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.4258403169 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 49571017398 ps |
| CPU time | 56.11 seconds |
| Started | Oct 03 04:11:43 AM UTC 24 |
| Finished | Oct 03 04:12:41 AM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258403169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4258403169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.3499337354 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 28697683090 ps |
| CPU time | 14.99 seconds |
| Started | Oct 03 04:11:45 AM UTC 24 |
| Finished | Oct 03 04:12:02 AM UTC 24 |
| Peak memory | 234884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499337354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3499337354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1360085863 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 50489931145 ps |
| CPU time | 176.03 seconds |
| Started | Oct 03 04:11:47 AM UTC 24 |
| Finished | Oct 03 04:14:46 AM UTC 24 |
| Peak memory | 278268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360085863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.1360085863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.2473783486 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 400622706 ps |
| CPU time | 6.52 seconds |
| Started | Oct 03 04:11:39 AM UTC 24 |
| Finished | Oct 03 04:11:47 AM UTC 24 |
| Peak memory | 234752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473783486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2473783486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.341084113 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 440681803 ps |
| CPU time | 6.42 seconds |
| Started | Oct 03 04:11:39 AM UTC 24 |
| Finished | Oct 03 04:11:47 AM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341084113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.341084113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.1510512218 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 86565981 ps |
| CPU time | 3.14 seconds |
| Started | Oct 03 04:11:37 AM UTC 24 |
| Finished | Oct 03 04:11:41 AM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510512218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1510512218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.2456347733 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 78761043708 ps |
| CPU time | 132.75 seconds |
| Started | Oct 03 04:11:37 AM UTC 24 |
| Finished | Oct 03 04:13:52 AM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456347733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2456347733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1448767305 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2415057505 ps |
| CPU time | 4.86 seconds |
| Started | Oct 03 04:11:37 AM UTC 24 |
| Finished | Oct 03 04:11:42 AM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448767305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.1448767305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1211139198 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 10841990285 ps |
| CPU time | 23.66 seconds |
| Started | Oct 03 04:11:34 AM UTC 24 |
| Finished | Oct 03 04:11:59 AM UTC 24 |
| Peak memory | 245112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211139198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1211139198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2957362360 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 827042732 ps |
| CPU time | 13.18 seconds |
| Started | Oct 03 04:11:41 AM UTC 24 |
| Finished | Oct 03 04:11:56 AM UTC 24 |
| Peak memory | 233572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957362360 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2957362360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.808276094 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 65675272 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 04:11:48 AM UTC 24 |
| Finished | Oct 03 04:11:50 AM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808276094 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.808276094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3250117823 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2395045644 ps |
| CPU time | 15.8 seconds |
| Started | Oct 03 04:11:33 AM UTC 24 |
| Finished | Oct 03 04:11:50 AM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250117823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3250117823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.998056943 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 87399691007 ps |
| CPU time | 36.66 seconds |
| Started | Oct 03 04:11:32 AM UTC 24 |
| Finished | Oct 03 04:12:10 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998056943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.998056943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.135518392 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 51169061 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 04:11:33 AM UTC 24 |
| Finished | Oct 03 04:11:36 AM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135518392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.135518392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1364642718 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 135255980 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 04:11:33 AM UTC 24 |
| Finished | Oct 03 04:11:35 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364642718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1364642718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.1682076694 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 7287796938 ps |
| CPU time | 30.38 seconds |
| Started | Oct 03 04:11:38 AM UTC 24 |
| Finished | Oct 03 04:12:10 AM UTC 24 |
| Peak memory | 245060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682076694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1682076694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.121151566 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 14083443 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 04:12:07 AM UTC 24 |
| Finished | Oct 03 04:12:10 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121151566 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.121151566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3055806592 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 220980085 ps |
| CPU time | 5.63 seconds |
| Started | Oct 03 04:11:59 AM UTC 24 |
| Finished | Oct 03 04:12:05 AM UTC 24 |
| Peak memory | 244988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055806592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3055806592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.727983866 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 17478361 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:11:50 AM UTC 24 |
| Finished | Oct 03 04:11:52 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727983866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.727983866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.2104421713 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 19520624444 ps |
| CPU time | 59.59 seconds |
| Started | Oct 03 04:12:05 AM UTC 24 |
| Finished | Oct 03 04:13:07 AM UTC 24 |
| Peak memory | 234828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104421713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2104421713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.373489013 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 81346874737 ps |
| CPU time | 455.26 seconds |
| Started | Oct 03 04:12:07 AM UTC 24 |
| Finished | Oct 03 04:19:49 AM UTC 24 |
| Peak memory | 267896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373489013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.373489013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.4108586753 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 279976876 ps |
| CPU time | 2.91 seconds |
| Started | Oct 03 04:12:00 AM UTC 24 |
| Finished | Oct 03 04:12:04 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108586753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4108586753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2631680577 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 10904956364 ps |
| CPU time | 57.1 seconds |
| Started | Oct 03 04:12:02 AM UTC 24 |
| Finished | Oct 03 04:13:01 AM UTC 24 |
| Peak memory | 261436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631680577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2631680577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.956478879 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 5923300635 ps |
| CPU time | 16.15 seconds |
| Started | Oct 03 04:11:54 AM UTC 24 |
| Finished | Oct 03 04:12:12 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956478879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.956478879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1875056922 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2920893206 ps |
| CPU time | 19.22 seconds |
| Started | Oct 03 04:11:57 AM UTC 24 |
| Finished | Oct 03 04:12:17 AM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875056922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1875056922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.2545261474 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 347206260 ps |
| CPU time | 10.57 seconds |
| Started | Oct 03 04:11:54 AM UTC 24 |
| Finished | Oct 03 04:12:06 AM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545261474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.2545261474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.401550780 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 26530896883 ps |
| CPU time | 21.35 seconds |
| Started | Oct 03 04:11:53 AM UTC 24 |
| Finished | Oct 03 04:12:16 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401550780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.401550780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3704710354 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1527155378 ps |
| CPU time | 18.71 seconds |
| Started | Oct 03 04:12:03 AM UTC 24 |
| Finished | Oct 03 04:12:23 AM UTC 24 |
| Peak memory | 231164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704710354 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.3704710354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.155462516 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2344523443 ps |
| CPU time | 28.15 seconds |
| Started | Oct 03 04:12:07 AM UTC 24 |
| Finished | Oct 03 04:12:37 AM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155462516 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.155462516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.1635365837 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 6467267220 ps |
| CPU time | 14.66 seconds |
| Started | Oct 03 04:11:51 AM UTC 24 |
| Finished | Oct 03 04:12:07 AM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635365837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1635365837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1884064942 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1268507311 ps |
| CPU time | 6.39 seconds |
| Started | Oct 03 04:11:51 AM UTC 24 |
| Finished | Oct 03 04:11:58 AM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884064942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1884064942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.450392376 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 44759552 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 04:11:51 AM UTC 24 |
| Finished | Oct 03 04:11:53 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450392376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.450392376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.3228514032 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 801914297 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 04:11:51 AM UTC 24 |
| Finished | Oct 03 04:11:54 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228514032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3228514032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.175890264 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 36071556287 ps |
| CPU time | 14.56 seconds |
| Started | Oct 03 04:11:58 AM UTC 24 |
| Finished | Oct 03 04:12:13 AM UTC 24 |
| Peak memory | 234880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175890264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.175890264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.2748216944 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 14269232 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:12:23 AM UTC 24 |
| Finished | Oct 03 04:12:25 AM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748216944 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.2748216944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.79494240 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 890568859 ps |
| CPU time | 16.34 seconds |
| Started | Oct 03 04:12:18 AM UTC 24 |
| Finished | Oct 03 04:12:35 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79494240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.79494240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.341384604 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 15748203 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:12:11 AM UTC 24 |
| Finished | Oct 03 04:12:13 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341384604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.341384604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.3629777475 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 28478308125 ps |
| CPU time | 139.24 seconds |
| Started | Oct 03 04:12:22 AM UTC 24 |
| Finished | Oct 03 04:14:44 AM UTC 24 |
| Peak memory | 263492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629777475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3629777475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.2977714067 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 51614224331 ps |
| CPU time | 169.9 seconds |
| Started | Oct 03 04:12:22 AM UTC 24 |
| Finished | Oct 03 04:15:15 AM UTC 24 |
| Peak memory | 265664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977714067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2977714067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.638159036 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 3736146301 ps |
| CPU time | 60.61 seconds |
| Started | Oct 03 04:12:22 AM UTC 24 |
| Finished | Oct 03 04:13:25 AM UTC 24 |
| Peak memory | 267772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638159036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.638159036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.2942585499 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1307064427 ps |
| CPU time | 19.28 seconds |
| Started | Oct 03 04:12:18 AM UTC 24 |
| Finished | Oct 03 04:12:38 AM UTC 24 |
| Peak memory | 245004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942585499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2942585499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2709959558 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 59489895295 ps |
| CPU time | 557.15 seconds |
| Started | Oct 03 04:12:18 AM UTC 24 |
| Finished | Oct 03 04:21:42 AM UTC 24 |
| Peak memory | 277820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709959558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.2709959558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.1189817173 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1489641295 ps |
| CPU time | 16.69 seconds |
| Started | Oct 03 04:12:16 AM UTC 24 |
| Finished | Oct 03 04:12:34 AM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189817173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1189817173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.3274931174 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1053775450 ps |
| CPU time | 19.63 seconds |
| Started | Oct 03 04:12:16 AM UTC 24 |
| Finished | Oct 03 04:12:37 AM UTC 24 |
| Peak memory | 244868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274931174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3274931174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1693578281 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 432100513 ps |
| CPU time | 5.59 seconds |
| Started | Oct 03 04:12:15 AM UTC 24 |
| Finished | Oct 03 04:12:22 AM UTC 24 |
| Peak memory | 245180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693578281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.1693578281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.478019925 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 11467725179 ps |
| CPU time | 28.63 seconds |
| Started | Oct 03 04:12:14 AM UTC 24 |
| Finished | Oct 03 04:12:44 AM UTC 24 |
| Peak memory | 245116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478019925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.478019925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3889539287 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3446178069 ps |
| CPU time | 15.43 seconds |
| Started | Oct 03 04:12:20 AM UTC 24 |
| Finished | Oct 03 04:12:36 AM UTC 24 |
| Peak memory | 233460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889539287 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.3889539287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1867802647 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 395372652 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 04:12:22 AM UTC 24 |
| Finished | Oct 03 04:12:25 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867802647 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1867802647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.3336911098 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 13351562 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 04:12:12 AM UTC 24 |
| Finished | Oct 03 04:12:14 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336911098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3336911098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.107953400 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2238600912 ps |
| CPU time | 10.33 seconds |
| Started | Oct 03 04:12:11 AM UTC 24 |
| Finished | Oct 03 04:12:22 AM UTC 24 |
| Peak memory | 227724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107953400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.107953400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.3356615985 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 147954922 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 04:12:14 AM UTC 24 |
| Finished | Oct 03 04:12:17 AM UTC 24 |
| Peak memory | 228988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356615985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3356615985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1201730173 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 116153659 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 04:12:13 AM UTC 24 |
| Finished | Oct 03 04:12:15 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201730173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1201730173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.2586403523 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 333852502 ps |
| CPU time | 3.44 seconds |
| Started | Oct 03 04:12:16 AM UTC 24 |
| Finished | Oct 03 04:12:21 AM UTC 24 |
| Peak memory | 244884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586403523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2586403523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.1035851606 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 37852763 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:12:42 AM UTC 24 |
| Finished | Oct 03 04:12:45 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035851606 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.1035851606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.57951775 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 633467598 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 04:12:37 AM UTC 24 |
| Finished | Oct 03 04:12:43 AM UTC 24 |
| Peak memory | 234744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57951775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.57951775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.1696019354 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 12325768 ps |
| CPU time | 1 seconds |
| Started | Oct 03 04:12:23 AM UTC 24 |
| Finished | Oct 03 04:12:25 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696019354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1696019354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.629248247 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 125743366680 ps |
| CPU time | 368.34 seconds |
| Started | Oct 03 04:12:39 AM UTC 24 |
| Finished | Oct 03 04:18:53 AM UTC 24 |
| Peak memory | 267900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629248247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.629248247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3235215664 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 64608890377 ps |
| CPU time | 149.85 seconds |
| Started | Oct 03 04:12:39 AM UTC 24 |
| Finished | Oct 03 04:15:12 AM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235215664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3235215664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.1436989238 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 9410891007 ps |
| CPU time | 45.73 seconds |
| Started | Oct 03 04:12:41 AM UTC 24 |
| Finished | Oct 03 04:13:28 AM UTC 24 |
| Peak memory | 261568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436989238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.1436989238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.705183595 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2232934076 ps |
| CPU time | 41.46 seconds |
| Started | Oct 03 04:12:37 AM UTC 24 |
| Finished | Oct 03 04:13:21 AM UTC 24 |
| Peak memory | 234880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705183595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.705183595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.4017703112 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 13001060133 ps |
| CPU time | 110.13 seconds |
| Started | Oct 03 04:12:37 AM UTC 24 |
| Finished | Oct 03 04:14:30 AM UTC 24 |
| Peak memory | 267580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017703112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.4017703112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.1540495291 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 5557753648 ps |
| CPU time | 5.71 seconds |
| Started | Oct 03 04:12:35 AM UTC 24 |
| Finished | Oct 03 04:12:42 AM UTC 24 |
| Peak memory | 234780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540495291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1540495291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.1072679817 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 6342864886 ps |
| CPU time | 18.87 seconds |
| Started | Oct 03 04:12:35 AM UTC 24 |
| Finished | Oct 03 04:12:55 AM UTC 24 |
| Peak memory | 234816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072679817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1072679817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.3277582554 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 20341918415 ps |
| CPU time | 25.92 seconds |
| Started | Oct 03 04:12:33 AM UTC 24 |
| Finished | Oct 03 04:13:00 AM UTC 24 |
| Peak memory | 261760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277582554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.3277582554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.2746569906 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2738166409 ps |
| CPU time | 6.88 seconds |
| Started | Oct 03 04:12:32 AM UTC 24 |
| Finished | Oct 03 04:12:40 AM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746569906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2746569906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.3631598707 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 80452722 ps |
| CPU time | 5.42 seconds |
| Started | Oct 03 04:12:39 AM UTC 24 |
| Finished | Oct 03 04:12:46 AM UTC 24 |
| Peak memory | 229108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631598707 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.3631598707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.1643866598 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 10586522727 ps |
| CPU time | 93.17 seconds |
| Started | Oct 03 04:12:41 AM UTC 24 |
| Finished | Oct 03 04:14:17 AM UTC 24 |
| Peak memory | 265664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643866598 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.1643866598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.1427284020 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 12947240498 ps |
| CPU time | 22.33 seconds |
| Started | Oct 03 04:12:27 AM UTC 24 |
| Finished | Oct 03 04:12:50 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427284020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1427284020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.973186758 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 6218698506 ps |
| CPU time | 10.45 seconds |
| Started | Oct 03 04:12:25 AM UTC 24 |
| Finished | Oct 03 04:12:37 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973186758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.973186758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.1241994376 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 671786276 ps |
| CPU time | 3.74 seconds |
| Started | Oct 03 04:12:30 AM UTC 24 |
| Finished | Oct 03 04:12:35 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241994376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1241994376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2378582231 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 15911277 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 04:12:27 AM UTC 24 |
| Finished | Oct 03 04:12:29 AM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378582231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2378582231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.3720277583 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 473780938 ps |
| CPU time | 7.48 seconds |
| Started | Oct 03 04:12:36 AM UTC 24 |
| Finished | Oct 03 04:12:45 AM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720277583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3720277583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.378140469 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 17023220 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 04:12:57 AM UTC 24 |
| Finished | Oct 03 04:12:59 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378140469 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.378140469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.109532438 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 464587945 ps |
| CPU time | 3.77 seconds |
| Started | Oct 03 04:12:51 AM UTC 24 |
| Finished | Oct 03 04:12:56 AM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109532438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.109532438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.1413935247 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 16861696 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 04:12:42 AM UTC 24 |
| Finished | Oct 03 04:12:45 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413935247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1413935247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.887693606 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 671653654 ps |
| CPU time | 17.52 seconds |
| Started | Oct 03 04:12:53 AM UTC 24 |
| Finished | Oct 03 04:13:12 AM UTC 24 |
| Peak memory | 247236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887693606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.887693606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.3889134077 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 118753085935 ps |
| CPU time | 57.55 seconds |
| Started | Oct 03 04:12:53 AM UTC 24 |
| Finished | Oct 03 04:13:52 AM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889134077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3889134077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1932927749 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 146046683027 ps |
| CPU time | 303.96 seconds |
| Started | Oct 03 04:12:56 AM UTC 24 |
| Finished | Oct 03 04:18:04 AM UTC 24 |
| Peak memory | 277816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932927749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.1932927749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3838237648 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2371984310 ps |
| CPU time | 17.29 seconds |
| Started | Oct 03 04:12:51 AM UTC 24 |
| Finished | Oct 03 04:13:10 AM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838237648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3838237648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3101203786 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 30189100752 ps |
| CPU time | 306.45 seconds |
| Started | Oct 03 04:12:51 AM UTC 24 |
| Finished | Oct 03 04:18:03 AM UTC 24 |
| Peak memory | 261692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101203786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.3101203786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.673887989 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1968549353 ps |
| CPU time | 8.78 seconds |
| Started | Oct 03 04:12:47 AM UTC 24 |
| Finished | Oct 03 04:12:57 AM UTC 24 |
| Peak memory | 241788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673887989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.673887989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.1587882342 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 356446101 ps |
| CPU time | 15.04 seconds |
| Started | Oct 03 04:12:48 AM UTC 24 |
| Finished | Oct 03 04:13:04 AM UTC 24 |
| Peak memory | 247228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587882342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1587882342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3618070097 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 29381292 ps |
| CPU time | 3.07 seconds |
| Started | Oct 03 04:12:46 AM UTC 24 |
| Finished | Oct 03 04:12:50 AM UTC 24 |
| Peak memory | 244604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618070097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.3618070097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.573396097 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1642768271 ps |
| CPU time | 5.46 seconds |
| Started | Oct 03 04:12:46 AM UTC 24 |
| Finished | Oct 03 04:12:52 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573396097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.573396097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1688350923 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 442947055 ps |
| CPU time | 7.16 seconds |
| Started | Oct 03 04:12:52 AM UTC 24 |
| Finished | Oct 03 04:13:01 AM UTC 24 |
| Peak memory | 229116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688350923 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.1688350923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.841830975 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 258161040 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 04:12:57 AM UTC 24 |
| Finished | Oct 03 04:13:00 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841830975 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.841830975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1763564227 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 3436349135 ps |
| CPU time | 16.33 seconds |
| Started | Oct 03 04:12:43 AM UTC 24 |
| Finished | Oct 03 04:13:01 AM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763564227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1763564227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.3902578719 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 18013086459 ps |
| CPU time | 10.38 seconds |
| Started | Oct 03 04:12:43 AM UTC 24 |
| Finished | Oct 03 04:12:55 AM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902578719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3902578719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.2684008668 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 329381935 ps |
| CPU time | 3.19 seconds |
| Started | Oct 03 04:12:45 AM UTC 24 |
| Finished | Oct 03 04:12:50 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684008668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2684008668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.689486889 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 410845609 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 04:12:44 AM UTC 24 |
| Finished | Oct 03 04:12:47 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689486889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.689486889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.2325210518 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1972729635 ps |
| CPU time | 14.61 seconds |
| Started | Oct 03 04:12:51 AM UTC 24 |
| Finished | Oct 03 04:13:07 AM UTC 24 |
| Peak memory | 244884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325210518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2325210518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.313278723 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 12383440 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:13:14 AM UTC 24 |
| Finished | Oct 03 04:13:16 AM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313278723 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.313278723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1355612618 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 809454567 ps |
| CPU time | 7.25 seconds |
| Started | Oct 03 04:13:08 AM UTC 24 |
| Finished | Oct 03 04:13:16 AM UTC 24 |
| Peak memory | 234704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355612618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1355612618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.2831773104 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 52444792 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:12:58 AM UTC 24 |
| Finished | Oct 03 04:13:00 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831773104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2831773104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.1679647888 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 42700470100 ps |
| CPU time | 130.68 seconds |
| Started | Oct 03 04:13:09 AM UTC 24 |
| Finished | Oct 03 04:15:23 AM UTC 24 |
| Peak memory | 278144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679647888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1679647888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2036709221 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 6115468712 ps |
| CPU time | 82.15 seconds |
| Started | Oct 03 04:13:12 AM UTC 24 |
| Finished | Oct 03 04:14:36 AM UTC 24 |
| Peak memory | 265672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036709221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2036709221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1073573393 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 5413737130 ps |
| CPU time | 75.77 seconds |
| Started | Oct 03 04:13:12 AM UTC 24 |
| Finished | Oct 03 04:14:29 AM UTC 24 |
| Peak memory | 261816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073573393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.1073573393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.4271001906 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2980881488 ps |
| CPU time | 37.44 seconds |
| Started | Oct 03 04:13:08 AM UTC 24 |
| Finished | Oct 03 04:13:47 AM UTC 24 |
| Peak memory | 234816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271001906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4271001906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1113475799 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 9325172486 ps |
| CPU time | 64.34 seconds |
| Started | Oct 03 04:13:09 AM UTC 24 |
| Finished | Oct 03 04:14:15 AM UTC 24 |
| Peak memory | 261500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113475799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.1113475799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.1331425940 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 522597690 ps |
| CPU time | 9.48 seconds |
| Started | Oct 03 04:13:03 AM UTC 24 |
| Finished | Oct 03 04:13:13 AM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331425940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1331425940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.1851599546 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2093485303 ps |
| CPU time | 5.63 seconds |
| Started | Oct 03 04:13:05 AM UTC 24 |
| Finished | Oct 03 04:13:11 AM UTC 24 |
| Peak memory | 234744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851599546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1851599546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.341878364 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1113175311 ps |
| CPU time | 6.32 seconds |
| Started | Oct 03 04:13:02 AM UTC 24 |
| Finished | Oct 03 04:13:10 AM UTC 24 |
| Peak memory | 245248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341878364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.341878364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1539256567 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 4283227219 ps |
| CPU time | 24.18 seconds |
| Started | Oct 03 04:13:01 AM UTC 24 |
| Finished | Oct 03 04:13:27 AM UTC 24 |
| Peak memory | 245372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539256567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1539256567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1845727452 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 498365048 ps |
| CPU time | 5.96 seconds |
| Started | Oct 03 04:13:09 AM UTC 24 |
| Finished | Oct 03 04:13:16 AM UTC 24 |
| Peak memory | 233452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845727452 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.1845727452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.2492169683 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 28088099443 ps |
| CPU time | 116.16 seconds |
| Started | Oct 03 04:13:14 AM UTC 24 |
| Finished | Oct 03 04:15:12 AM UTC 24 |
| Peak memory | 265980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492169683 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.2492169683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.2130824919 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3543029490 ps |
| CPU time | 16.29 seconds |
| Started | Oct 03 04:13:01 AM UTC 24 |
| Finished | Oct 03 04:13:19 AM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130824919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2130824919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.918061053 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 782387942 ps |
| CPU time | 7.06 seconds |
| Started | Oct 03 04:13:00 AM UTC 24 |
| Finished | Oct 03 04:13:08 AM UTC 24 |
| Peak memory | 227380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918061053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.918061053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.699820017 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 200653667 ps |
| CPU time | 3.66 seconds |
| Started | Oct 03 04:13:01 AM UTC 24 |
| Finished | Oct 03 04:13:06 AM UTC 24 |
| Peak memory | 227260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699820017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.699820017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1796975126 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 82750322 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:13:01 AM UTC 24 |
| Finished | Oct 03 04:13:04 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796975126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1796975126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.807097482 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 36280134910 ps |
| CPU time | 39.03 seconds |
| Started | Oct 03 04:13:05 AM UTC 24 |
| Finished | Oct 03 04:13:45 AM UTC 24 |
| Peak memory | 245124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807097482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.807097482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.3149771616 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 96685052 ps |
| CPU time | 0.95 seconds |
| Started | Oct 03 04:13:35 AM UTC 24 |
| Finished | Oct 03 04:13:37 AM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149771616 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.3149771616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3329444902 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 815635182 ps |
| CPU time | 5.23 seconds |
| Started | Oct 03 04:13:27 AM UTC 24 |
| Finished | Oct 03 04:13:33 AM UTC 24 |
| Peak memory | 234752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329444902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3329444902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.177034205 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 23460162 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 04:13:14 AM UTC 24 |
| Finished | Oct 03 04:13:16 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177034205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.177034205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.389270878 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 25644917041 ps |
| CPU time | 128.95 seconds |
| Started | Oct 03 04:13:32 AM UTC 24 |
| Finished | Oct 03 04:15:44 AM UTC 24 |
| Peak memory | 265604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389270878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.389270878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1628915761 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 24507072821 ps |
| CPU time | 77.61 seconds |
| Started | Oct 03 04:13:32 AM UTC 24 |
| Finished | Oct 03 04:14:52 AM UTC 24 |
| Peak memory | 265732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628915761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1628915761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.549188211 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 16935527871 ps |
| CPU time | 132.13 seconds |
| Started | Oct 03 04:13:34 AM UTC 24 |
| Finished | Oct 03 04:15:49 AM UTC 24 |
| Peak memory | 278208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549188211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.549188211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.566041977 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 486789517 ps |
| CPU time | 9.07 seconds |
| Started | Oct 03 04:13:27 AM UTC 24 |
| Finished | Oct 03 04:13:37 AM UTC 24 |
| Peak memory | 234676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566041977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.566041977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3000883552 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 38418743557 ps |
| CPU time | 289.72 seconds |
| Started | Oct 03 04:13:29 AM UTC 24 |
| Finished | Oct 03 04:18:23 AM UTC 24 |
| Peak memory | 261436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000883552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3000883552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.4166951730 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 387661342 ps |
| CPU time | 10.28 seconds |
| Started | Oct 03 04:13:22 AM UTC 24 |
| Finished | Oct 03 04:13:34 AM UTC 24 |
| Peak memory | 234844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166951730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4166951730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.1113701603 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 52737032857 ps |
| CPU time | 155.73 seconds |
| Started | Oct 03 04:13:23 AM UTC 24 |
| Finished | Oct 03 04:16:01 AM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113701603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1113701603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1259551994 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 856884242 ps |
| CPU time | 12.86 seconds |
| Started | Oct 03 04:13:22 AM UTC 24 |
| Finished | Oct 03 04:13:37 AM UTC 24 |
| Peak memory | 261624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259551994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.1259551994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.334853936 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1288889464 ps |
| CPU time | 18.42 seconds |
| Started | Oct 03 04:13:20 AM UTC 24 |
| Finished | Oct 03 04:13:40 AM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334853936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.334853936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.1386927839 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 917638885 ps |
| CPU time | 15.77 seconds |
| Started | Oct 03 04:13:29 AM UTC 24 |
| Finished | Oct 03 04:13:46 AM UTC 24 |
| Peak memory | 233316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386927839 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.1386927839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.423116981 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 62570867758 ps |
| CPU time | 245.57 seconds |
| Started | Oct 03 04:13:35 AM UTC 24 |
| Finished | Oct 03 04:17:45 AM UTC 24 |
| Peak memory | 300740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423116981 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.423116981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.623000842 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 11997095 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 04:13:18 AM UTC 24 |
| Finished | Oct 03 04:13:20 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623000842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.623000842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3638837172 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1240120745 ps |
| CPU time | 6.18 seconds |
| Started | Oct 03 04:13:18 AM UTC 24 |
| Finished | Oct 03 04:13:25 AM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638837172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3638837172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.63347156 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 111554436 ps |
| CPU time | 2.61 seconds |
| Started | Oct 03 04:13:18 AM UTC 24 |
| Finished | Oct 03 04:13:22 AM UTC 24 |
| Peak memory | 217080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63347156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.63347156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2181960092 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 70298218 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 04:13:18 AM UTC 24 |
| Finished | Oct 03 04:13:20 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181960092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2181960092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.3961613846 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 299121907 ps |
| CPU time | 6.19 seconds |
| Started | Oct 03 04:13:23 AM UTC 24 |
| Finished | Oct 03 04:13:30 AM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961613846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3961613846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3404278122 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 43357647 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:00:19 AM UTC 24 |
| Finished | Oct 03 04:00:21 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404278122 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3404278122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.30055732 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 369952169 ps |
| CPU time | 3.56 seconds |
| Started | Oct 03 03:59:39 AM UTC 24 |
| Finished | Oct 03 03:59:43 AM UTC 24 |
| Peak memory | 234608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30055732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.30055732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1844465612 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 16925616 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 03:59:04 AM UTC 24 |
| Finished | Oct 03 03:59:06 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844465612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1844465612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.997816817 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 29478825586 ps |
| CPU time | 331.26 seconds |
| Started | Oct 03 03:59:50 AM UTC 24 |
| Finished | Oct 03 04:05:27 AM UTC 24 |
| Peak memory | 261564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997816817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.997816817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.2091797253 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 201052517 ps |
| CPU time | 8.44 seconds |
| Started | Oct 03 03:59:39 AM UTC 24 |
| Finished | Oct 03 03:59:48 AM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091797253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2091797253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1942793238 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 15359162409 ps |
| CPU time | 55.46 seconds |
| Started | Oct 03 03:59:44 AM UTC 24 |
| Finished | Oct 03 04:00:41 AM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942793238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.1942793238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.1390398044 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 604643318 ps |
| CPU time | 10.03 seconds |
| Started | Oct 03 03:59:32 AM UTC 24 |
| Finished | Oct 03 03:59:43 AM UTC 24 |
| Peak memory | 234808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390398044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1390398044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.2267945211 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 63861920 ps |
| CPU time | 2.57 seconds |
| Started | Oct 03 03:59:35 AM UTC 24 |
| Finished | Oct 03 03:59:38 AM UTC 24 |
| Peak memory | 244928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267945211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2267945211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2565532692 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 462839772 ps |
| CPU time | 11.79 seconds |
| Started | Oct 03 03:59:20 AM UTC 24 |
| Finished | Oct 03 03:59:33 AM UTC 24 |
| Peak memory | 244984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565532692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.2565532692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.4102556340 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2641699570 ps |
| CPU time | 15.06 seconds |
| Started | Oct 03 03:59:18 AM UTC 24 |
| Finished | Oct 03 03:59:35 AM UTC 24 |
| Peak memory | 245108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102556340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4102556340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.694492280 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 223755355 ps |
| CPU time | 4.61 seconds |
| Started | Oct 03 03:59:44 AM UTC 24 |
| Finished | Oct 03 03:59:50 AM UTC 24 |
| Peak memory | 233320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694492280 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.694492280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.1898942396 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 560053336 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 04:00:15 AM UTC 24 |
| Finished | Oct 03 04:00:18 AM UTC 24 |
| Peak memory | 256992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898942396 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1898942396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.786237481 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4379349452 ps |
| CPU time | 21.01 seconds |
| Started | Oct 03 03:59:51 AM UTC 24 |
| Finished | Oct 03 04:00:14 AM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786237481 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.786237481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1563748641 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 594344725 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 03:59:13 AM UTC 24 |
| Finished | Oct 03 03:59:16 AM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563748641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1563748641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1768742143 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 9332569295 ps |
| CPU time | 19.45 seconds |
| Started | Oct 03 03:59:10 AM UTC 24 |
| Finished | Oct 03 03:59:30 AM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768742143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1768742143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1017129100 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 16317993 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 03:59:17 AM UTC 24 |
| Finished | Oct 03 03:59:19 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017129100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1017129100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2532941349 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 46719085 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 03:59:15 AM UTC 24 |
| Finished | Oct 03 03:59:18 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532941349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2532941349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1194713232 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 624129505 ps |
| CPU time | 6.34 seconds |
| Started | Oct 03 03:59:36 AM UTC 24 |
| Finished | Oct 03 03:59:43 AM UTC 24 |
| Peak memory | 234664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194713232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1194713232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.3766956428 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 61131007 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 04:13:58 AM UTC 24 |
| Finished | Oct 03 04:14:00 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766956428 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.3766956428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3427584706 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 32757937 ps |
| CPU time | 2.69 seconds |
| Started | Oct 03 04:13:50 AM UTC 24 |
| Finished | Oct 03 04:13:54 AM UTC 24 |
| Peak memory | 234684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427584706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3427584706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.612543935 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 25616426 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 04:13:38 AM UTC 24 |
| Finished | Oct 03 04:13:40 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612543935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.612543935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.1538029552 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 28702670572 ps |
| CPU time | 149.15 seconds |
| Started | Oct 03 04:13:55 AM UTC 24 |
| Finished | Oct 03 04:16:27 AM UTC 24 |
| Peak memory | 267592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538029552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1538029552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.4121468535 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 118402677496 ps |
| CPU time | 560.03 seconds |
| Started | Oct 03 04:13:55 AM UTC 24 |
| Finished | Oct 03 04:23:22 AM UTC 24 |
| Peak memory | 265932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121468535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4121468535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.945100872 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 103975921072 ps |
| CPU time | 146.73 seconds |
| Started | Oct 03 04:13:56 AM UTC 24 |
| Finished | Oct 03 04:16:25 AM UTC 24 |
| Peak memory | 261440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945100872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.945100872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.1631028062 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 316072714 ps |
| CPU time | 4.02 seconds |
| Started | Oct 03 04:13:52 AM UTC 24 |
| Finished | Oct 03 04:13:57 AM UTC 24 |
| Peak memory | 245248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631028062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1631028062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.4238755115 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 28173492254 ps |
| CPU time | 148.09 seconds |
| Started | Oct 03 04:13:53 AM UTC 24 |
| Finished | Oct 03 04:16:23 AM UTC 24 |
| Peak memory | 265660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238755115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.4238755115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.1771318575 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 469568228 ps |
| CPU time | 3.23 seconds |
| Started | Oct 03 04:13:46 AM UTC 24 |
| Finished | Oct 03 04:13:50 AM UTC 24 |
| Peak memory | 233172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771318575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1771318575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.2190898968 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 4308841115 ps |
| CPU time | 27.1 seconds |
| Started | Oct 03 04:13:47 AM UTC 24 |
| Finished | Oct 03 04:14:16 AM UTC 24 |
| Peak memory | 234772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190898968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2190898968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.717813496 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 33448576679 ps |
| CPU time | 31.85 seconds |
| Started | Oct 03 04:13:44 AM UTC 24 |
| Finished | Oct 03 04:14:17 AM UTC 24 |
| Peak memory | 245004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717813496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.717813496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2758772093 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 494914677 ps |
| CPU time | 9.66 seconds |
| Started | Oct 03 04:13:44 AM UTC 24 |
| Finished | Oct 03 04:13:55 AM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758772093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2758772093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.19328171 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3710309985 ps |
| CPU time | 16.78 seconds |
| Started | Oct 03 04:13:53 AM UTC 24 |
| Finished | Oct 03 04:14:11 AM UTC 24 |
| Peak memory | 233456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19328171 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.19328171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.3313402726 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 64398221827 ps |
| CPU time | 709.23 seconds |
| Started | Oct 03 04:13:57 AM UTC 24 |
| Finished | Oct 03 04:25:56 AM UTC 24 |
| Peak memory | 284416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313402726 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.3313402726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3792214836 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 495472431 ps |
| CPU time | 9.29 seconds |
| Started | Oct 03 04:13:39 AM UTC 24 |
| Finished | Oct 03 04:13:49 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792214836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3792214836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.2786598929 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 13214514714 ps |
| CPU time | 15.45 seconds |
| Started | Oct 03 04:13:38 AM UTC 24 |
| Finished | Oct 03 04:13:54 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786598929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2786598929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.405947618 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 41516362 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 04:13:41 AM UTC 24 |
| Finished | Oct 03 04:13:43 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405947618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.405947618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1721375072 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 17166911 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 04:13:41 AM UTC 24 |
| Finished | Oct 03 04:13:43 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721375072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1721375072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.2924424182 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1693978619 ps |
| CPU time | 17.85 seconds |
| Started | Oct 03 04:13:48 AM UTC 24 |
| Finished | Oct 03 04:14:07 AM UTC 24 |
| Peak memory | 234676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924424182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2924424182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.911851323 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 38931092 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:14:24 AM UTC 24 |
| Finished | Oct 03 04:14:26 AM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911851323 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.911851323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.2114664174 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 957418464 ps |
| CPU time | 4.54 seconds |
| Started | Oct 03 04:14:17 AM UTC 24 |
| Finished | Oct 03 04:14:23 AM UTC 24 |
| Peak memory | 234696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114664174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2114664174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.842150028 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 63704605 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 04:14:01 AM UTC 24 |
| Finished | Oct 03 04:14:03 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842150028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.842150028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.2248165859 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 41773105 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 04:14:21 AM UTC 24 |
| Finished | Oct 03 04:14:23 AM UTC 24 |
| Peak memory | 226808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248165859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2248165859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1424825116 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 6143272683 ps |
| CPU time | 61.43 seconds |
| Started | Oct 03 04:14:22 AM UTC 24 |
| Finished | Oct 03 04:15:25 AM UTC 24 |
| Peak memory | 249288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424825116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1424825116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.578173226 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1790025341 ps |
| CPU time | 14.91 seconds |
| Started | Oct 03 04:14:22 AM UTC 24 |
| Finished | Oct 03 04:14:38 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578173226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.578173226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.2502922144 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 323512472 ps |
| CPU time | 3.3 seconds |
| Started | Oct 03 04:14:18 AM UTC 24 |
| Finished | Oct 03 04:14:23 AM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502922144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2502922144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.3712847836 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 142545125 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 04:14:18 AM UTC 24 |
| Finished | Oct 03 04:14:21 AM UTC 24 |
| Peak memory | 226864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712847836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.3712847836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.912199443 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 10029640346 ps |
| CPU time | 26.75 seconds |
| Started | Oct 03 04:14:16 AM UTC 24 |
| Finished | Oct 03 04:14:44 AM UTC 24 |
| Peak memory | 241852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912199443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.912199443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.1342466605 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 6803956869 ps |
| CPU time | 74.13 seconds |
| Started | Oct 03 04:14:16 AM UTC 24 |
| Finished | Oct 03 04:15:32 AM UTC 24 |
| Peak memory | 245052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342466605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1342466605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.2450115545 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1708696260 ps |
| CPU time | 17.8 seconds |
| Started | Oct 03 04:14:15 AM UTC 24 |
| Finished | Oct 03 04:14:34 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450115545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.2450115545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2202405328 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 6337460126 ps |
| CPU time | 16.09 seconds |
| Started | Oct 03 04:14:12 AM UTC 24 |
| Finished | Oct 03 04:14:29 AM UTC 24 |
| Peak memory | 245304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202405328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2202405328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.253907330 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 596071104 ps |
| CPU time | 9.21 seconds |
| Started | Oct 03 04:14:19 AM UTC 24 |
| Finished | Oct 03 04:14:30 AM UTC 24 |
| Peak memory | 233328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253907330 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.253907330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.444734972 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 23336276975 ps |
| CPU time | 287.79 seconds |
| Started | Oct 03 04:14:24 AM UTC 24 |
| Finished | Oct 03 04:19:16 AM UTC 24 |
| Peak memory | 263680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444734972 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.444734972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.487817495 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 43866409956 ps |
| CPU time | 36.66 seconds |
| Started | Oct 03 04:14:04 AM UTC 24 |
| Finished | Oct 03 04:14:43 AM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487817495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.487817495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.4235810660 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 17694116163 ps |
| CPU time | 13.72 seconds |
| Started | Oct 03 04:14:03 AM UTC 24 |
| Finished | Oct 03 04:14:18 AM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235810660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4235810660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.2663445206 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 249789969 ps |
| CPU time | 2.35 seconds |
| Started | Oct 03 04:14:12 AM UTC 24 |
| Finished | Oct 03 04:14:15 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663445206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2663445206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.4211865212 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 20554222 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:14:09 AM UTC 24 |
| Finished | Oct 03 04:14:11 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211865212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4211865212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.4036140489 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 289570893 ps |
| CPU time | 7.58 seconds |
| Started | Oct 03 04:14:17 AM UTC 24 |
| Finished | Oct 03 04:14:26 AM UTC 24 |
| Peak memory | 234924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036140489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4036140489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.4230046320 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 21530476 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 04:14:44 AM UTC 24 |
| Finished | Oct 03 04:14:46 AM UTC 24 |
| Peak memory | 213648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230046320 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.4230046320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3518369053 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1089617035 ps |
| CPU time | 8.8 seconds |
| Started | Oct 03 04:14:35 AM UTC 24 |
| Finished | Oct 03 04:14:45 AM UTC 24 |
| Peak memory | 244928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518369053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3518369053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.468570493 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 68772313 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:14:24 AM UTC 24 |
| Finished | Oct 03 04:14:26 AM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468570493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.468570493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.2540652371 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 15368146176 ps |
| CPU time | 146.3 seconds |
| Started | Oct 03 04:14:40 AM UTC 24 |
| Finished | Oct 03 04:17:09 AM UTC 24 |
| Peak memory | 261512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540652371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2540652371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.4096697445 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 1496172257193 ps |
| CPU time | 852.73 seconds |
| Started | Oct 03 04:14:42 AM UTC 24 |
| Finished | Oct 03 04:29:06 AM UTC 24 |
| Peak memory | 267716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096697445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4096697445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1782520663 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 683333301 ps |
| CPU time | 4.18 seconds |
| Started | Oct 03 04:14:42 AM UTC 24 |
| Finished | Oct 03 04:14:48 AM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782520663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1782520663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.773621927 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 48467833 ps |
| CPU time | 4.29 seconds |
| Started | Oct 03 04:14:36 AM UTC 24 |
| Finished | Oct 03 04:14:42 AM UTC 24 |
| Peak memory | 234700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773621927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.773621927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.3992605189 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 433004017 ps |
| CPU time | 9.36 seconds |
| Started | Oct 03 04:14:32 AM UTC 24 |
| Finished | Oct 03 04:14:42 AM UTC 24 |
| Peak memory | 244936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992605189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3992605189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.1259134596 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 291189089 ps |
| CPU time | 8.24 seconds |
| Started | Oct 03 04:14:32 AM UTC 24 |
| Finished | Oct 03 04:14:41 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259134596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1259134596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1469302209 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 5438914285 ps |
| CPU time | 9.36 seconds |
| Started | Oct 03 04:14:31 AM UTC 24 |
| Finished | Oct 03 04:14:41 AM UTC 24 |
| Peak memory | 234828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469302209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.1469302209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.385171865 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 7923570374 ps |
| CPU time | 11.64 seconds |
| Started | Oct 03 04:14:30 AM UTC 24 |
| Finished | Oct 03 04:14:43 AM UTC 24 |
| Peak memory | 234832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385171865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.385171865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3262168278 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 720049118 ps |
| CPU time | 12.86 seconds |
| Started | Oct 03 04:14:40 AM UTC 24 |
| Finished | Oct 03 04:14:54 AM UTC 24 |
| Peak memory | 234788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262168278 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.3262168278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.3631649941 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 188285612165 ps |
| CPU time | 339.38 seconds |
| Started | Oct 03 04:14:43 AM UTC 24 |
| Finished | Oct 03 04:20:27 AM UTC 24 |
| Peak memory | 280244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631649941 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.3631649941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.2019009111 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2044221415 ps |
| CPU time | 31.52 seconds |
| Started | Oct 03 04:14:27 AM UTC 24 |
| Finished | Oct 03 04:15:00 AM UTC 24 |
| Peak memory | 227328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019009111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2019009111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.594166991 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 62607997463 ps |
| CPU time | 37.27 seconds |
| Started | Oct 03 04:14:26 AM UTC 24 |
| Finished | Oct 03 04:15:05 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594166991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.594166991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.612785720 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 36315730 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 04:14:29 AM UTC 24 |
| Finished | Oct 03 04:14:32 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612785720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.612785720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1444829806 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 598664889 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 04:14:27 AM UTC 24 |
| Finished | Oct 03 04:14:30 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444829806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1444829806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.750598817 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1584887913 ps |
| CPU time | 4.73 seconds |
| Started | Oct 03 04:14:33 AM UTC 24 |
| Finished | Oct 03 04:14:39 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750598817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.750598817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.2567219733 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 13069651 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 04:15:03 AM UTC 24 |
| Finished | Oct 03 04:15:05 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567219733 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.2567219733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3675800488 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 639475948 ps |
| CPU time | 6.6 seconds |
| Started | Oct 03 04:14:49 AM UTC 24 |
| Finished | Oct 03 04:14:57 AM UTC 24 |
| Peak memory | 234636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675800488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3675800488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.1779528428 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 45599734 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:14:44 AM UTC 24 |
| Finished | Oct 03 04:14:46 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779528428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1779528428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.2348623747 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 18923297587 ps |
| CPU time | 155.09 seconds |
| Started | Oct 03 04:14:55 AM UTC 24 |
| Finished | Oct 03 04:17:33 AM UTC 24 |
| Peak memory | 261508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348623747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2348623747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.684652400 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 265098168248 ps |
| CPU time | 375.45 seconds |
| Started | Oct 03 04:14:58 AM UTC 24 |
| Finished | Oct 03 04:21:19 AM UTC 24 |
| Peak memory | 273852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684652400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.684652400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1352373358 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 46234993025 ps |
| CPU time | 256.87 seconds |
| Started | Oct 03 04:14:58 AM UTC 24 |
| Finished | Oct 03 04:19:19 AM UTC 24 |
| Peak memory | 265720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352373358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.1352373358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.60061138 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 338246659 ps |
| CPU time | 10.49 seconds |
| Started | Oct 03 04:14:51 AM UTC 24 |
| Finished | Oct 03 04:15:02 AM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60061138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.60061138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.3401394169 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 54280104431 ps |
| CPU time | 115.92 seconds |
| Started | Oct 03 04:14:53 AM UTC 24 |
| Finished | Oct 03 04:16:51 AM UTC 24 |
| Peak memory | 261432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401394169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.3401394169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.3302703295 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3891437916 ps |
| CPU time | 49.64 seconds |
| Started | Oct 03 04:14:47 AM UTC 24 |
| Finished | Oct 03 04:15:38 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302703295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3302703295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3418066789 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 15800034478 ps |
| CPU time | 51.39 seconds |
| Started | Oct 03 04:14:48 AM UTC 24 |
| Finished | Oct 03 04:15:41 AM UTC 24 |
| Peak memory | 234832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418066789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3418066789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.819786265 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 32157858 ps |
| CPU time | 3.25 seconds |
| Started | Oct 03 04:14:47 AM UTC 24 |
| Finished | Oct 03 04:14:51 AM UTC 24 |
| Peak memory | 244472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819786265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.819786265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.2938307852 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2642596298 ps |
| CPU time | 31.85 seconds |
| Started | Oct 03 04:14:47 AM UTC 24 |
| Finished | Oct 03 04:15:20 AM UTC 24 |
| Peak memory | 249196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938307852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2938307852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.136895100 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3130045692 ps |
| CPU time | 10.81 seconds |
| Started | Oct 03 04:14:53 AM UTC 24 |
| Finished | Oct 03 04:15:05 AM UTC 24 |
| Peak memory | 231300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136895100 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.136895100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1879397314 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 10788775313 ps |
| CPU time | 82.15 seconds |
| Started | Oct 03 04:15:01 AM UTC 24 |
| Finished | Oct 03 04:16:25 AM UTC 24 |
| Peak memory | 268032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879397314 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1879397314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.87817672 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 276849451 ps |
| CPU time | 4.08 seconds |
| Started | Oct 03 04:14:45 AM UTC 24 |
| Finished | Oct 03 04:14:50 AM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87817672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.87817672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.502931310 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 7311841774 ps |
| CPU time | 40.13 seconds |
| Started | Oct 03 04:14:45 AM UTC 24 |
| Finished | Oct 03 04:15:26 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502931310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.502931310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.607409952 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 119786547 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 04:14:46 AM UTC 24 |
| Finished | Oct 03 04:14:49 AM UTC 24 |
| Peak memory | 227116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607409952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.607409952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.93350585 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 23392088 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:14:45 AM UTC 24 |
| Finished | Oct 03 04:14:47 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93350585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.93350585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.124505835 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1214610590 ps |
| CPU time | 7.46 seconds |
| Started | Oct 03 04:14:48 AM UTC 24 |
| Finished | Oct 03 04:14:57 AM UTC 24 |
| Peak memory | 234644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124505835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.124505835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.51995980 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 14713492 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 04:15:25 AM UTC 24 |
| Finished | Oct 03 04:15:27 AM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51995980 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.51995980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.480476945 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 307272150 ps |
| CPU time | 3.52 seconds |
| Started | Oct 03 04:15:17 AM UTC 24 |
| Finished | Oct 03 04:15:22 AM UTC 24 |
| Peak memory | 244924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480476945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.480476945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.4520214 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 16525104 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 04:15:05 AM UTC 24 |
| Finished | Oct 03 04:15:08 AM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4520214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4520214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.3448187117 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 13031655703 ps |
| CPU time | 52.35 seconds |
| Started | Oct 03 04:15:21 AM UTC 24 |
| Finished | Oct 03 04:16:15 AM UTC 24 |
| Peak memory | 249228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448187117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3448187117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.2418533 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 56363863045 ps |
| CPU time | 197.28 seconds |
| Started | Oct 03 04:15:21 AM UTC 24 |
| Finished | Oct 03 04:18:42 AM UTC 24 |
| Peak memory | 275848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2418533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1302442938 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 31880965477 ps |
| CPU time | 339.91 seconds |
| Started | Oct 03 04:15:23 AM UTC 24 |
| Finished | Oct 03 04:21:08 AM UTC 24 |
| Peak memory | 277944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302442938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.1302442938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.877544915 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 300399572 ps |
| CPU time | 6.01 seconds |
| Started | Oct 03 04:15:17 AM UTC 24 |
| Finished | Oct 03 04:15:24 AM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877544915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.877544915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.268318696 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1777672816 ps |
| CPU time | 63.97 seconds |
| Started | Oct 03 04:15:18 AM UTC 24 |
| Finished | Oct 03 04:16:24 AM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268318696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.268318696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.702058023 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 16916669256 ps |
| CPU time | 39.55 seconds |
| Started | Oct 03 04:15:13 AM UTC 24 |
| Finished | Oct 03 04:15:54 AM UTC 24 |
| Peak memory | 245128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702058023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.702058023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.3250393156 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 6279633188 ps |
| CPU time | 77.02 seconds |
| Started | Oct 03 04:15:15 AM UTC 24 |
| Finished | Oct 03 04:16:34 AM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250393156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3250393156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.250432540 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 17134164158 ps |
| CPU time | 20.03 seconds |
| Started | Oct 03 04:15:13 AM UTC 24 |
| Finished | Oct 03 04:15:34 AM UTC 24 |
| Peak memory | 245008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250432540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.250432540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.2556311504 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 551985697 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 04:15:12 AM UTC 24 |
| Finished | Oct 03 04:15:16 AM UTC 24 |
| Peak memory | 245316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556311504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2556311504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2905941665 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 111567470 ps |
| CPU time | 6.1 seconds |
| Started | Oct 03 04:15:20 AM UTC 24 |
| Finished | Oct 03 04:15:27 AM UTC 24 |
| Peak memory | 233596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905941665 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.2905941665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.2069833777 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 16100490772 ps |
| CPU time | 218.35 seconds |
| Started | Oct 03 04:15:24 AM UTC 24 |
| Finished | Oct 03 04:19:06 AM UTC 24 |
| Peak memory | 284076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069833777 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.2069833777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.169954136 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3225814507 ps |
| CPU time | 9.27 seconds |
| Started | Oct 03 04:15:06 AM UTC 24 |
| Finished | Oct 03 04:15:17 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169954136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.169954136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3405261435 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 175200877 ps |
| CPU time | 4.1 seconds |
| Started | Oct 03 04:15:05 AM UTC 24 |
| Finished | Oct 03 04:15:10 AM UTC 24 |
| Peak memory | 227444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405261435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3405261435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.1726282774 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 167807351 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 04:15:12 AM UTC 24 |
| Finished | Oct 03 04:15:15 AM UTC 24 |
| Peak memory | 217004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726282774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1726282774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.656432786 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 134150882 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 04:15:09 AM UTC 24 |
| Finished | Oct 03 04:15:11 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656432786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.656432786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.3705381345 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 34842807 ps |
| CPU time | 2.92 seconds |
| Started | Oct 03 04:15:16 AM UTC 24 |
| Finished | Oct 03 04:15:20 AM UTC 24 |
| Peak memory | 234364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705381345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3705381345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2589341346 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 41243320 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:15:50 AM UTC 24 |
| Finished | Oct 03 04:15:52 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589341346 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.2589341346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1901632758 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2239242694 ps |
| CPU time | 32.3 seconds |
| Started | Oct 03 04:15:39 AM UTC 24 |
| Finished | Oct 03 04:16:13 AM UTC 24 |
| Peak memory | 244736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901632758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1901632758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.3569225318 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 87105440 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 04:15:26 AM UTC 24 |
| Finished | Oct 03 04:15:28 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569225318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3569225318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.1449041937 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 263466523279 ps |
| CPU time | 174.15 seconds |
| Started | Oct 03 04:15:43 AM UTC 24 |
| Finished | Oct 03 04:18:40 AM UTC 24 |
| Peak memory | 261512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449041937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1449041937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1196345138 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 60084542810 ps |
| CPU time | 108.43 seconds |
| Started | Oct 03 04:15:45 AM UTC 24 |
| Finished | Oct 03 04:17:35 AM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196345138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1196345138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.431689324 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3593803607 ps |
| CPU time | 41.84 seconds |
| Started | Oct 03 04:15:48 AM UTC 24 |
| Finished | Oct 03 04:16:31 AM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431689324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.431689324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.2694986389 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3729634545 ps |
| CPU time | 31.62 seconds |
| Started | Oct 03 04:15:39 AM UTC 24 |
| Finished | Oct 03 04:16:12 AM UTC 24 |
| Peak memory | 245120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694986389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2694986389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2924675150 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 15161348080 ps |
| CPU time | 137.09 seconds |
| Started | Oct 03 04:15:39 AM UTC 24 |
| Finished | Oct 03 04:17:59 AM UTC 24 |
| Peak memory | 248848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924675150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.2924675150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.2478944350 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 156716778 ps |
| CPU time | 4.54 seconds |
| Started | Oct 03 04:15:33 AM UTC 24 |
| Finished | Oct 03 04:15:38 AM UTC 24 |
| Peak memory | 234756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478944350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2478944350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.1657107322 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 25995053921 ps |
| CPU time | 29.01 seconds |
| Started | Oct 03 04:15:33 AM UTC 24 |
| Finished | Oct 03 04:16:03 AM UTC 24 |
| Peak memory | 261440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657107322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1657107322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2876727275 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3438197959 ps |
| CPU time | 21.26 seconds |
| Started | Oct 03 04:15:32 AM UTC 24 |
| Finished | Oct 03 04:15:55 AM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876727275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2876727275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2848171196 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 382728895 ps |
| CPU time | 15.15 seconds |
| Started | Oct 03 04:15:31 AM UTC 24 |
| Finished | Oct 03 04:15:47 AM UTC 24 |
| Peak memory | 261316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848171196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2848171196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.2842900749 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 13358390358 ps |
| CPU time | 12.75 seconds |
| Started | Oct 03 04:15:41 AM UTC 24 |
| Finished | Oct 03 04:15:55 AM UTC 24 |
| Peak memory | 231292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842900749 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.2842900749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.3142665370 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 716416349526 ps |
| CPU time | 858.13 seconds |
| Started | Oct 03 04:15:49 AM UTC 24 |
| Finished | Oct 03 04:30:18 AM UTC 24 |
| Peak memory | 282100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142665370 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.3142665370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.4043155778 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1691197161 ps |
| CPU time | 12.52 seconds |
| Started | Oct 03 04:15:27 AM UTC 24 |
| Finished | Oct 03 04:15:41 AM UTC 24 |
| Peak memory | 231480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043155778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4043155778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1992302460 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 12441091 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 04:15:27 AM UTC 24 |
| Finished | Oct 03 04:15:30 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992302460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1992302460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.2722956823 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 50134354 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 04:15:30 AM UTC 24 |
| Finished | Oct 03 04:15:32 AM UTC 24 |
| Peak memory | 227244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722956823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2722956823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.1793894485 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 126547747 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:15:28 AM UTC 24 |
| Finished | Oct 03 04:15:31 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793894485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1793894485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.3815234763 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 992431029 ps |
| CPU time | 13.99 seconds |
| Started | Oct 03 04:15:35 AM UTC 24 |
| Finished | Oct 03 04:15:50 AM UTC 24 |
| Peak memory | 234768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815234763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3815234763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.2096581791 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 28883342 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 04:16:18 AM UTC 24 |
| Finished | Oct 03 04:16:20 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096581791 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.2096581791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.39174062 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5763634676 ps |
| CPU time | 13.73 seconds |
| Started | Oct 03 04:16:02 AM UTC 24 |
| Finished | Oct 03 04:16:17 AM UTC 24 |
| Peak memory | 234836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39174062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.39174062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.4049707202 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 19162480 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 04:15:51 AM UTC 24 |
| Finished | Oct 03 04:15:53 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049707202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4049707202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.3278166290 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1850338896 ps |
| CPU time | 28.26 seconds |
| Started | Oct 03 04:16:13 AM UTC 24 |
| Finished | Oct 03 04:16:43 AM UTC 24 |
| Peak memory | 261324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278166290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3278166290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3476047620 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 209357846783 ps |
| CPU time | 257.11 seconds |
| Started | Oct 03 04:16:14 AM UTC 24 |
| Finished | Oct 03 04:20:36 AM UTC 24 |
| Peak memory | 278016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476047620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3476047620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2784066370 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 249476516394 ps |
| CPU time | 243.57 seconds |
| Started | Oct 03 04:16:16 AM UTC 24 |
| Finished | Oct 03 04:20:23 AM UTC 24 |
| Peak memory | 261564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784066370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.2784066370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.604380430 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1064137215 ps |
| CPU time | 25.03 seconds |
| Started | Oct 03 04:16:02 AM UTC 24 |
| Finished | Oct 03 04:16:28 AM UTC 24 |
| Peak memory | 244924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604380430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.604380430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.3878595684 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2817935442 ps |
| CPU time | 31.89 seconds |
| Started | Oct 03 04:16:04 AM UTC 24 |
| Finished | Oct 03 04:16:37 AM UTC 24 |
| Peak memory | 261696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878595684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.3878595684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.1831431635 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 9612420477 ps |
| CPU time | 22.25 seconds |
| Started | Oct 03 04:15:58 AM UTC 24 |
| Finished | Oct 03 04:16:22 AM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831431635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1831431635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.3304953844 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 21986056179 ps |
| CPU time | 23.36 seconds |
| Started | Oct 03 04:16:00 AM UTC 24 |
| Finished | Oct 03 04:16:25 AM UTC 24 |
| Peak memory | 247352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304953844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3304953844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2277386433 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 22860305313 ps |
| CPU time | 27.01 seconds |
| Started | Oct 03 04:15:57 AM UTC 24 |
| Finished | Oct 03 04:16:25 AM UTC 24 |
| Peak memory | 249208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277386433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.2277386433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.551489019 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 2037885556 ps |
| CPU time | 15.86 seconds |
| Started | Oct 03 04:15:56 AM UTC 24 |
| Finished | Oct 03 04:16:14 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551489019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.551489019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.252762078 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 641701199 ps |
| CPU time | 12.6 seconds |
| Started | Oct 03 04:16:10 AM UTC 24 |
| Finished | Oct 03 04:16:24 AM UTC 24 |
| Peak memory | 233320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252762078 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.252762078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.501133455 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 720896723163 ps |
| CPU time | 783.69 seconds |
| Started | Oct 03 04:16:16 AM UTC 24 |
| Finished | Oct 03 04:29:30 AM UTC 24 |
| Peak memory | 282372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501133455 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.501133455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.752229500 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1433024048 ps |
| CPU time | 5.67 seconds |
| Started | Oct 03 04:15:54 AM UTC 24 |
| Finished | Oct 03 04:16:01 AM UTC 24 |
| Peak memory | 227588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752229500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.752229500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.3306205726 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 551837235 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 04:15:53 AM UTC 24 |
| Finished | Oct 03 04:15:56 AM UTC 24 |
| Peak memory | 216608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306205726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3306205726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.555446799 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 86040654 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 04:15:55 AM UTC 24 |
| Finished | Oct 03 04:16:00 AM UTC 24 |
| Peak memory | 227328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555446799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.555446799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.1857584470 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 96525875 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 04:15:55 AM UTC 24 |
| Finished | Oct 03 04:15:58 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857584470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1857584470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.3923599079 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 375417285 ps |
| CPU time | 6.48 seconds |
| Started | Oct 03 04:16:02 AM UTC 24 |
| Finished | Oct 03 04:16:10 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923599079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3923599079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.567135454 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 74628676 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 04:16:32 AM UTC 24 |
| Finished | Oct 03 04:16:34 AM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567135454 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.567135454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.970134 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1212160798 ps |
| CPU time | 4.74 seconds |
| Started | Oct 03 04:16:27 AM UTC 24 |
| Finished | Oct 03 04:16:33 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_dev ice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.970134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.38422867 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 60901786 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 04:16:18 AM UTC 24 |
| Finished | Oct 03 04:16:20 AM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38422867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.38422867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1008266927 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 32088775755 ps |
| CPU time | 399.79 seconds |
| Started | Oct 03 04:16:29 AM UTC 24 |
| Finished | Oct 03 04:23:15 AM UTC 24 |
| Peak memory | 277832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008266927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1008266927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1953924554 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 6997942964 ps |
| CPU time | 73.45 seconds |
| Started | Oct 03 04:16:29 AM UTC 24 |
| Finished | Oct 03 04:17:44 AM UTC 24 |
| Peak memory | 244288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953924554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1953924554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1396617723 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 3223927296 ps |
| CPU time | 62.71 seconds |
| Started | Oct 03 04:16:32 AM UTC 24 |
| Finished | Oct 03 04:17:37 AM UTC 24 |
| Peak memory | 261556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396617723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1396617723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.2134534690 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 495198759 ps |
| CPU time | 6.53 seconds |
| Started | Oct 03 04:16:27 AM UTC 24 |
| Finished | Oct 03 04:16:34 AM UTC 24 |
| Peak memory | 234688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134534690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2134534690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.961448956 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 6577834570 ps |
| CPU time | 25.29 seconds |
| Started | Oct 03 04:16:25 AM UTC 24 |
| Finished | Oct 03 04:16:52 AM UTC 24 |
| Peak memory | 245076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961448956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.961448956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.348524746 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 358792241 ps |
| CPU time | 5.21 seconds |
| Started | Oct 03 04:16:25 AM UTC 24 |
| Finished | Oct 03 04:16:32 AM UTC 24 |
| Peak memory | 245244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348524746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.348524746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1702161539 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5284157777 ps |
| CPU time | 22.59 seconds |
| Started | Oct 03 04:16:25 AM UTC 24 |
| Finished | Oct 03 04:16:49 AM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702161539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.1702161539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2800198481 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 295756488 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 04:16:24 AM UTC 24 |
| Finished | Oct 03 04:16:28 AM UTC 24 |
| Peak memory | 234424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800198481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2800198481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1256046679 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4623665964 ps |
| CPU time | 11.42 seconds |
| Started | Oct 03 04:16:28 AM UTC 24 |
| Finished | Oct 03 04:16:41 AM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256046679 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1256046679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1739042187 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 162202119 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 04:16:32 AM UTC 24 |
| Finished | Oct 03 04:16:35 AM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739042187 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.1739042187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.2095282411 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 8800913345 ps |
| CPU time | 11.72 seconds |
| Started | Oct 03 04:16:21 AM UTC 24 |
| Finished | Oct 03 04:16:34 AM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095282411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2095282411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2085834076 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 5053981040 ps |
| CPU time | 32.2 seconds |
| Started | Oct 03 04:16:21 AM UTC 24 |
| Finished | Oct 03 04:16:54 AM UTC 24 |
| Peak memory | 227784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085834076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2085834076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.2482508308 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 67602635 ps |
| CPU time | 5.75 seconds |
| Started | Oct 03 04:16:24 AM UTC 24 |
| Finished | Oct 03 04:16:31 AM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482508308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2482508308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1342817300 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 76689446 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 04:16:22 AM UTC 24 |
| Finished | Oct 03 04:16:24 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342817300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1342817300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.1611300070 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 112907816191 ps |
| CPU time | 33.41 seconds |
| Started | Oct 03 04:16:26 AM UTC 24 |
| Finished | Oct 03 04:17:00 AM UTC 24 |
| Peak memory | 245120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611300070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1611300070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.3044817990 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 23942616 ps |
| CPU time | 0.98 seconds |
| Started | Oct 03 04:16:51 AM UTC 24 |
| Finished | Oct 03 04:16:53 AM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044817990 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.3044817990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.57206100 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 112470784 ps |
| CPU time | 3.95 seconds |
| Started | Oct 03 04:16:38 AM UTC 24 |
| Finished | Oct 03 04:16:43 AM UTC 24 |
| Peak memory | 244920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57206100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.57206100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.2625726545 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 57113968 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:16:33 AM UTC 24 |
| Finished | Oct 03 04:16:35 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625726545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2625726545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.242250927 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 25131705421 ps |
| CPU time | 123.22 seconds |
| Started | Oct 03 04:16:44 AM UTC 24 |
| Finished | Oct 03 04:18:49 AM UTC 24 |
| Peak memory | 277896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242250927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.242250927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.516331072 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 49054972524 ps |
| CPU time | 50.11 seconds |
| Started | Oct 03 04:16:45 AM UTC 24 |
| Finished | Oct 03 04:17:36 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516331072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.516331072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1387330127 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 67610220423 ps |
| CPU time | 131.03 seconds |
| Started | Oct 03 04:16:50 AM UTC 24 |
| Finished | Oct 03 04:19:03 AM UTC 24 |
| Peak memory | 261572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387330127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.1387330127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.4043875601 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 320553449 ps |
| CPU time | 7.62 seconds |
| Started | Oct 03 04:16:41 AM UTC 24 |
| Finished | Oct 03 04:16:50 AM UTC 24 |
| Peak memory | 244924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043875601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4043875601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3229730716 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2436401291 ps |
| CPU time | 52.87 seconds |
| Started | Oct 03 04:16:42 AM UTC 24 |
| Finished | Oct 03 04:17:37 AM UTC 24 |
| Peak memory | 261696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229730716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.3229730716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.703708662 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3803936451 ps |
| CPU time | 15.45 seconds |
| Started | Oct 03 04:16:37 AM UTC 24 |
| Finished | Oct 03 04:16:54 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703708662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.703708662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.1274226350 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1533067089 ps |
| CPU time | 20.46 seconds |
| Started | Oct 03 04:16:38 AM UTC 24 |
| Finished | Oct 03 04:17:00 AM UTC 24 |
| Peak memory | 234576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274226350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1274226350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1221375453 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 426846257 ps |
| CPU time | 6.19 seconds |
| Started | Oct 03 04:16:36 AM UTC 24 |
| Finished | Oct 03 04:16:43 AM UTC 24 |
| Peak memory | 245244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221375453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.1221375453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2345671725 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 55038835347 ps |
| CPU time | 34.07 seconds |
| Started | Oct 03 04:16:36 AM UTC 24 |
| Finished | Oct 03 04:17:11 AM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345671725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2345671725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2146389761 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 697733464 ps |
| CPU time | 15.36 seconds |
| Started | Oct 03 04:16:43 AM UTC 24 |
| Finished | Oct 03 04:17:00 AM UTC 24 |
| Peak memory | 231164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146389761 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2146389761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1838752356 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 60143890 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 04:16:50 AM UTC 24 |
| Finished | Oct 03 04:16:52 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838752356 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.1838752356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.2222936728 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 37560822674 ps |
| CPU time | 55.04 seconds |
| Started | Oct 03 04:16:34 AM UTC 24 |
| Finished | Oct 03 04:17:31 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222936728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2222936728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1405817969 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 6944560734 ps |
| CPU time | 16.79 seconds |
| Started | Oct 03 04:16:34 AM UTC 24 |
| Finished | Oct 03 04:16:52 AM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405817969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1405817969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.1034237658 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 11462276 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 04:16:36 AM UTC 24 |
| Finished | Oct 03 04:16:38 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034237658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1034237658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.4123641307 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 395825401 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 04:16:35 AM UTC 24 |
| Finished | Oct 03 04:16:37 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123641307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4123641307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.3436204655 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 21330160106 ps |
| CPU time | 51.52 seconds |
| Started | Oct 03 04:16:38 AM UTC 24 |
| Finished | Oct 03 04:17:31 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436204655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3436204655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.3365754609 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 35586203 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 04:17:09 AM UTC 24 |
| Finished | Oct 03 04:17:11 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365754609 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.3365754609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.472018708 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 7518854532 ps |
| CPU time | 27.85 seconds |
| Started | Oct 03 04:16:59 AM UTC 24 |
| Finished | Oct 03 04:17:28 AM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472018708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.472018708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.831863308 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 59078441 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 04:16:52 AM UTC 24 |
| Finished | Oct 03 04:16:54 AM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831863308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.831863308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.4232370356 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 22923481657 ps |
| CPU time | 224.61 seconds |
| Started | Oct 03 04:17:01 AM UTC 24 |
| Finished | Oct 03 04:20:50 AM UTC 24 |
| Peak memory | 261440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232370356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4232370356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.683921054 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2415533302 ps |
| CPU time | 43.21 seconds |
| Started | Oct 03 04:17:02 AM UTC 24 |
| Finished | Oct 03 04:17:47 AM UTC 24 |
| Peak memory | 235004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683921054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.683921054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3894419911 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4895695497 ps |
| CPU time | 25.74 seconds |
| Started | Oct 03 04:17:02 AM UTC 24 |
| Finished | Oct 03 04:17:29 AM UTC 24 |
| Peak memory | 245504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894419911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.3894419911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.1338441068 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 1079137448 ps |
| CPU time | 16.38 seconds |
| Started | Oct 03 04:17:01 AM UTC 24 |
| Finished | Oct 03 04:17:19 AM UTC 24 |
| Peak memory | 244944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338441068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1338441068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1020852300 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 13509680088 ps |
| CPU time | 126.74 seconds |
| Started | Oct 03 04:17:01 AM UTC 24 |
| Finished | Oct 03 04:19:10 AM UTC 24 |
| Peak memory | 261264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020852300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.1020852300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.2348703196 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 164006158 ps |
| CPU time | 5.01 seconds |
| Started | Oct 03 04:16:56 AM UTC 24 |
| Finished | Oct 03 04:17:02 AM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348703196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2348703196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.31778932 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 15355631820 ps |
| CPU time | 36.12 seconds |
| Started | Oct 03 04:16:56 AM UTC 24 |
| Finished | Oct 03 04:17:33 AM UTC 24 |
| Peak memory | 247108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31778932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.31778932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2212909938 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 32337279277 ps |
| CPU time | 32.71 seconds |
| Started | Oct 03 04:16:56 AM UTC 24 |
| Finished | Oct 03 04:17:30 AM UTC 24 |
| Peak memory | 234764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212909938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.2212909938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.4231176127 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 418699756 ps |
| CPU time | 3.21 seconds |
| Started | Oct 03 04:16:54 AM UTC 24 |
| Finished | Oct 03 04:16:59 AM UTC 24 |
| Peak memory | 233356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231176127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4231176127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.166418624 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 152823791 ps |
| CPU time | 5.79 seconds |
| Started | Oct 03 04:17:01 AM UTC 24 |
| Finished | Oct 03 04:17:08 AM UTC 24 |
| Peak memory | 233432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166418624 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.166418624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.3721925093 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 37108578 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 04:17:06 AM UTC 24 |
| Finished | Oct 03 04:17:08 AM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721925093 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.3721925093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.4011162192 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 6930255644 ps |
| CPU time | 39.2 seconds |
| Started | Oct 03 04:16:53 AM UTC 24 |
| Finished | Oct 03 04:17:34 AM UTC 24 |
| Peak memory | 227784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011162192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4011162192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3299298796 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2651094959 ps |
| CPU time | 9.86 seconds |
| Started | Oct 03 04:16:53 AM UTC 24 |
| Finished | Oct 03 04:17:04 AM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299298796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3299298796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.81167036 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 205138116 ps |
| CPU time | 4.4 seconds |
| Started | Oct 03 04:16:54 AM UTC 24 |
| Finished | Oct 03 04:17:00 AM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81167036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.81167036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.2094062915 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 46300277 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:16:53 AM UTC 24 |
| Finished | Oct 03 04:16:55 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094062915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2094062915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.3353698798 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 185001871 ps |
| CPU time | 3.95 seconds |
| Started | Oct 03 04:16:57 AM UTC 24 |
| Finished | Oct 03 04:17:02 AM UTC 24 |
| Peak memory | 235004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353698798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3353698798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2659705812 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 13694167 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:01:21 AM UTC 24 |
| Finished | Oct 03 04:01:23 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659705812 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2659705812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3457535386 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 789355414 ps |
| CPU time | 5.68 seconds |
| Started | Oct 03 04:00:56 AM UTC 24 |
| Finished | Oct 03 04:01:03 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457535386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3457535386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.1897715956 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 13836328 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:00:22 AM UTC 24 |
| Finished | Oct 03 04:00:24 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897715956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1897715956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.961734978 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 6310961365 ps |
| CPU time | 55.65 seconds |
| Started | Oct 03 04:01:03 AM UTC 24 |
| Finished | Oct 03 04:02:01 AM UTC 24 |
| Peak memory | 263484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961734978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.961734978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2559683989 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1408126159 ps |
| CPU time | 10.43 seconds |
| Started | Oct 03 04:01:00 AM UTC 24 |
| Finished | Oct 03 04:01:12 AM UTC 24 |
| Peak memory | 251072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559683989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2559683989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2572882457 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 105426336 ps |
| CPU time | 3.72 seconds |
| Started | Oct 03 04:00:49 AM UTC 24 |
| Finished | Oct 03 04:00:53 AM UTC 24 |
| Peak memory | 244612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572882457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2572882457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.2486424581 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 67190445 ps |
| CPU time | 2.9 seconds |
| Started | Oct 03 04:00:51 AM UTC 24 |
| Finished | Oct 03 04:00:55 AM UTC 24 |
| Peak memory | 233292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486424581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2486424581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.297532886 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1099721284 ps |
| CPU time | 13.14 seconds |
| Started | Oct 03 04:00:47 AM UTC 24 |
| Finished | Oct 03 04:01:02 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297532886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.297532886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2095443357 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12678204339 ps |
| CPU time | 31.02 seconds |
| Started | Oct 03 04:00:44 AM UTC 24 |
| Finished | Oct 03 04:01:17 AM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095443357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2095443357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.426735167 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 221557462 ps |
| CPU time | 5.38 seconds |
| Started | Oct 03 04:01:02 AM UTC 24 |
| Finished | Oct 03 04:01:09 AM UTC 24 |
| Peak memory | 231356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426735167 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.426735167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.1146142350 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 33580096 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 04:01:18 AM UTC 24 |
| Finished | Oct 03 04:01:21 AM UTC 24 |
| Peak memory | 256992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146142350 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1146142350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.8369118 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 138209412869 ps |
| CPU time | 377.03 seconds |
| Started | Oct 03 04:01:13 AM UTC 24 |
| Finished | Oct 03 04:07:36 AM UTC 24 |
| Peak memory | 275960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8369118 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.8369118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.1110806306 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1070608237 ps |
| CPU time | 17.1 seconds |
| Started | Oct 03 04:00:28 AM UTC 24 |
| Finished | Oct 03 04:00:46 AM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110806306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1110806306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2095328140 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 777085556 ps |
| CPU time | 10.65 seconds |
| Started | Oct 03 04:00:28 AM UTC 24 |
| Finished | Oct 03 04:00:40 AM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095328140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2095328140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2835666362 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 466799012 ps |
| CPU time | 4.6 seconds |
| Started | Oct 03 04:00:42 AM UTC 24 |
| Finished | Oct 03 04:00:48 AM UTC 24 |
| Peak memory | 227384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835666362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2835666362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2508761429 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 133302847 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 04:00:41 AM UTC 24 |
| Finished | Oct 03 04:00:44 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508761429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2508761429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1165212546 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3328754175 ps |
| CPU time | 24.11 seconds |
| Started | Oct 03 04:00:55 AM UTC 24 |
| Finished | Oct 03 04:01:20 AM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165212546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1165212546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.354493826 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 13662010 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:17:32 AM UTC 24 |
| Finished | Oct 03 04:17:35 AM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354493826 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.354493826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2400501711 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4034856754 ps |
| CPU time | 23.14 seconds |
| Started | Oct 03 04:17:27 AM UTC 24 |
| Finished | Oct 03 04:17:51 AM UTC 24 |
| Peak memory | 234876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400501711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2400501711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.2572177182 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 20662937 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 04:17:09 AM UTC 24 |
| Finished | Oct 03 04:17:11 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572177182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2572177182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.3015230781 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 24310144265 ps |
| CPU time | 99.66 seconds |
| Started | Oct 03 04:17:30 AM UTC 24 |
| Finished | Oct 03 04:19:12 AM UTC 24 |
| Peak memory | 265596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015230781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3015230781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.2321166645 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4490737562 ps |
| CPU time | 65.66 seconds |
| Started | Oct 03 04:17:31 AM UTC 24 |
| Finished | Oct 03 04:18:39 AM UTC 24 |
| Peak memory | 261636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321166645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2321166645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.107263699 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 116652900749 ps |
| CPU time | 573.44 seconds |
| Started | Oct 03 04:17:32 AM UTC 24 |
| Finished | Oct 03 04:27:13 AM UTC 24 |
| Peak memory | 265920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107263699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.107263699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.3833105365 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 9530777891 ps |
| CPU time | 12.87 seconds |
| Started | Oct 03 04:17:28 AM UTC 24 |
| Finished | Oct 03 04:17:42 AM UTC 24 |
| Peak memory | 234832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833105365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3833105365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2208369332 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2464074048 ps |
| CPU time | 52.58 seconds |
| Started | Oct 03 04:17:29 AM UTC 24 |
| Finished | Oct 03 04:18:23 AM UTC 24 |
| Peak memory | 278136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208369332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.2208369332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1169681388 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 6771813633 ps |
| CPU time | 24.99 seconds |
| Started | Oct 03 04:17:19 AM UTC 24 |
| Finished | Oct 03 04:17:46 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169681388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1169681388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.3489595907 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 32045439650 ps |
| CPU time | 23.15 seconds |
| Started | Oct 03 04:17:20 AM UTC 24 |
| Finished | Oct 03 04:17:45 AM UTC 24 |
| Peak memory | 235132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489595907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3489595907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.899426432 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 72024907 ps |
| CPU time | 3.46 seconds |
| Started | Oct 03 04:17:15 AM UTC 24 |
| Finished | Oct 03 04:17:20 AM UTC 24 |
| Peak memory | 244924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899426432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.899426432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.781802544 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2351537133 ps |
| CPU time | 10.57 seconds |
| Started | Oct 03 04:17:15 AM UTC 24 |
| Finished | Oct 03 04:17:27 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781802544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.781802544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.4136937751 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1138554946 ps |
| CPU time | 7.93 seconds |
| Started | Oct 03 04:17:29 AM UTC 24 |
| Finished | Oct 03 04:17:38 AM UTC 24 |
| Peak memory | 229116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136937751 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.4136937751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.1553465457 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 361618819 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 04:17:32 AM UTC 24 |
| Finished | Oct 03 04:17:35 AM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553465457 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.1553465457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.261148895 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1193216825 ps |
| CPU time | 14.44 seconds |
| Started | Oct 03 04:17:12 AM UTC 24 |
| Finished | Oct 03 04:17:28 AM UTC 24 |
| Peak memory | 226932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261148895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.261148895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.2330123704 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 13014897763 ps |
| CPU time | 8.69 seconds |
| Started | Oct 03 04:17:10 AM UTC 24 |
| Finished | Oct 03 04:17:20 AM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330123704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2330123704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.1517793612 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 22770247 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 04:17:12 AM UTC 24 |
| Finished | Oct 03 04:17:14 AM UTC 24 |
| Peak memory | 217004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517793612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1517793612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.836710133 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 167314404 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 04:17:12 AM UTC 24 |
| Finished | Oct 03 04:17:14 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836710133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.836710133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.1309996068 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 1737642255 ps |
| CPU time | 12.54 seconds |
| Started | Oct 03 04:17:21 AM UTC 24 |
| Finished | Oct 03 04:17:34 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309996068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1309996068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1510174990 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 15920879 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 04:17:45 AM UTC 24 |
| Finished | Oct 03 04:17:47 AM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510174990 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.1510174990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3830893617 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 55276050 ps |
| CPU time | 3.84 seconds |
| Started | Oct 03 04:17:37 AM UTC 24 |
| Finished | Oct 03 04:17:42 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830893617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3830893617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1701279820 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 13598666 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 04:17:33 AM UTC 24 |
| Finished | Oct 03 04:17:36 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701279820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1701279820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.2970212243 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5126513561 ps |
| CPU time | 46.18 seconds |
| Started | Oct 03 04:17:43 AM UTC 24 |
| Finished | Oct 03 04:18:31 AM UTC 24 |
| Peak memory | 247112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970212243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2970212243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2600569241 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 6192120203 ps |
| CPU time | 95.29 seconds |
| Started | Oct 03 04:17:43 AM UTC 24 |
| Finished | Oct 03 04:19:21 AM UTC 24 |
| Peak memory | 261828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600569241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2600569241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1854896653 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 43085446397 ps |
| CPU time | 299.51 seconds |
| Started | Oct 03 04:17:43 AM UTC 24 |
| Finished | Oct 03 04:22:47 AM UTC 24 |
| Peak memory | 261948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854896653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.1854896653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.2174630113 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1829996640 ps |
| CPU time | 24.17 seconds |
| Started | Oct 03 04:17:38 AM UTC 24 |
| Finished | Oct 03 04:18:04 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174630113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2174630113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.1975971286 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 373163901 ps |
| CPU time | 5.96 seconds |
| Started | Oct 03 04:17:37 AM UTC 24 |
| Finished | Oct 03 04:17:44 AM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975971286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1975971286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.2025462323 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1031554613 ps |
| CPU time | 15.65 seconds |
| Started | Oct 03 04:17:37 AM UTC 24 |
| Finished | Oct 03 04:17:54 AM UTC 24 |
| Peak memory | 261312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025462323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2025462323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1071774525 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4646461114 ps |
| CPU time | 6.65 seconds |
| Started | Oct 03 04:17:36 AM UTC 24 |
| Finished | Oct 03 04:17:44 AM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071774525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.1071774525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2757850324 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 8300295247 ps |
| CPU time | 11.79 seconds |
| Started | Oct 03 04:17:36 AM UTC 24 |
| Finished | Oct 03 04:17:49 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757850324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2757850324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2780056859 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1576105662 ps |
| CPU time | 11.6 seconds |
| Started | Oct 03 04:17:38 AM UTC 24 |
| Finished | Oct 03 04:17:51 AM UTC 24 |
| Peak memory | 233248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780056859 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.2780056859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.2004429074 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 136418723 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 04:17:44 AM UTC 24 |
| Finished | Oct 03 04:17:46 AM UTC 24 |
| Peak memory | 215756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004429074 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.2004429074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.2459019748 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 29081351 ps |
| CPU time | 0.98 seconds |
| Started | Oct 03 04:17:35 AM UTC 24 |
| Finished | Oct 03 04:17:37 AM UTC 24 |
| Peak memory | 215700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459019748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2459019748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1389590448 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3167685525 ps |
| CPU time | 11.26 seconds |
| Started | Oct 03 04:17:35 AM UTC 24 |
| Finished | Oct 03 04:17:47 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389590448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1389590448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.2161263591 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 419916461 ps |
| CPU time | 5.81 seconds |
| Started | Oct 03 04:17:36 AM UTC 24 |
| Finished | Oct 03 04:17:43 AM UTC 24 |
| Peak memory | 227588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161263591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2161263591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3906474678 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 61934528 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:17:35 AM UTC 24 |
| Finished | Oct 03 04:17:37 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906474678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3906474678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.733190398 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 715742790 ps |
| CPU time | 3.83 seconds |
| Started | Oct 03 04:17:37 AM UTC 24 |
| Finished | Oct 03 04:17:42 AM UTC 24 |
| Peak memory | 234644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733190398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.733190398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1378629797 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 40023100 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 04:17:57 AM UTC 24 |
| Finished | Oct 03 04:18:00 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378629797 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.1378629797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.254758863 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 379303919 ps |
| CPU time | 5.72 seconds |
| Started | Oct 03 04:17:50 AM UTC 24 |
| Finished | Oct 03 04:17:57 AM UTC 24 |
| Peak memory | 234676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254758863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.254758863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.3397727159 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 14035779 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 04:17:45 AM UTC 24 |
| Finished | Oct 03 04:17:47 AM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397727159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3397727159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.1724666735 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 24574594547 ps |
| CPU time | 26.58 seconds |
| Started | Oct 03 04:17:52 AM UTC 24 |
| Finished | Oct 03 04:18:20 AM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724666735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1724666735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.3813391698 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 9961810994 ps |
| CPU time | 25.34 seconds |
| Started | Oct 03 04:17:54 AM UTC 24 |
| Finished | Oct 03 04:18:21 AM UTC 24 |
| Peak memory | 261760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813391698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3813391698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2412342829 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 23875349726 ps |
| CPU time | 314.34 seconds |
| Started | Oct 03 04:17:55 AM UTC 24 |
| Finished | Oct 03 04:23:15 AM UTC 24 |
| Peak memory | 267772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412342829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.2412342829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3988307993 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 770153909 ps |
| CPU time | 8.51 seconds |
| Started | Oct 03 04:17:50 AM UTC 24 |
| Finished | Oct 03 04:17:59 AM UTC 24 |
| Peak memory | 234936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988307993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3988307993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.1402908973 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 32752063855 ps |
| CPU time | 311.97 seconds |
| Started | Oct 03 04:17:51 AM UTC 24 |
| Finished | Oct 03 04:23:07 AM UTC 24 |
| Peak memory | 273724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402908973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.1402908973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.1693745299 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 3082518984 ps |
| CPU time | 11.37 seconds |
| Started | Oct 03 04:17:48 AM UTC 24 |
| Finished | Oct 03 04:18:01 AM UTC 24 |
| Peak memory | 231892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693745299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1693745299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.4287017238 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 431911751 ps |
| CPU time | 16.05 seconds |
| Started | Oct 03 04:17:48 AM UTC 24 |
| Finished | Oct 03 04:18:06 AM UTC 24 |
| Peak memory | 251084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287017238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4287017238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2178482461 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 9080008303 ps |
| CPU time | 17.9 seconds |
| Started | Oct 03 04:17:47 AM UTC 24 |
| Finished | Oct 03 04:18:07 AM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178482461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.2178482461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2832451894 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 569824297 ps |
| CPU time | 11.89 seconds |
| Started | Oct 03 04:17:47 AM UTC 24 |
| Finished | Oct 03 04:18:01 AM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832451894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2832451894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.716031861 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 157693372 ps |
| CPU time | 4.99 seconds |
| Started | Oct 03 04:17:52 AM UTC 24 |
| Finished | Oct 03 04:17:58 AM UTC 24 |
| Peak memory | 229120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716031861 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.716031861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3797039433 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 546562436 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 04:17:56 AM UTC 24 |
| Finished | Oct 03 04:17:59 AM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797039433 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.3797039433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.1435059942 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 323001822 ps |
| CPU time | 7.55 seconds |
| Started | Oct 03 04:17:46 AM UTC 24 |
| Finished | Oct 03 04:17:55 AM UTC 24 |
| Peak memory | 227308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435059942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1435059942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3019650645 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 344103100 ps |
| CPU time | 2.73 seconds |
| Started | Oct 03 04:17:46 AM UTC 24 |
| Finished | Oct 03 04:17:50 AM UTC 24 |
| Peak memory | 227344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019650645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3019650645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.4010636595 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 588765410 ps |
| CPU time | 5.69 seconds |
| Started | Oct 03 04:17:46 AM UTC 24 |
| Finished | Oct 03 04:17:53 AM UTC 24 |
| Peak memory | 227332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010636595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4010636595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.882785030 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 127907794 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 04:17:46 AM UTC 24 |
| Finished | Oct 03 04:17:49 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882785030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.882785030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.83403458 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 6644129904 ps |
| CPU time | 14.08 seconds |
| Started | Oct 03 04:17:48 AM UTC 24 |
| Finished | Oct 03 04:18:04 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83403458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.83403458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.739663407 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 13437768 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 04:18:15 AM UTC 24 |
| Finished | Oct 03 04:18:17 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739663407 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.739663407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.4004863156 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 498744697 ps |
| CPU time | 4.16 seconds |
| Started | Oct 03 04:18:04 AM UTC 24 |
| Finished | Oct 03 04:18:10 AM UTC 24 |
| Peak memory | 234628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004863156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4004863156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2222082858 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 54934405 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:17:59 AM UTC 24 |
| Finished | Oct 03 04:18:01 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222082858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2222082858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1406702594 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 9844635763 ps |
| CPU time | 73.33 seconds |
| Started | Oct 03 04:18:05 AM UTC 24 |
| Finished | Oct 03 04:19:21 AM UTC 24 |
| Peak memory | 261696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406702594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1406702594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.861605013 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 25892240984 ps |
| CPU time | 217.48 seconds |
| Started | Oct 03 04:18:06 AM UTC 24 |
| Finished | Oct 03 04:21:48 AM UTC 24 |
| Peak memory | 265664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861605013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.861605013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.2731064601 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2603752169 ps |
| CPU time | 84.35 seconds |
| Started | Oct 03 04:18:08 AM UTC 24 |
| Finished | Oct 03 04:19:34 AM UTC 24 |
| Peak memory | 284088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731064601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.2731064601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2239682562 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 3000335299 ps |
| CPU time | 28.11 seconds |
| Started | Oct 03 04:18:04 AM UTC 24 |
| Finished | Oct 03 04:18:34 AM UTC 24 |
| Peak memory | 245056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239682562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2239682562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.4046679787 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 26471970968 ps |
| CPU time | 99.52 seconds |
| Started | Oct 03 04:18:04 AM UTC 24 |
| Finished | Oct 03 04:19:46 AM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046679787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.4046679787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.264855636 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 15501981236 ps |
| CPU time | 40.5 seconds |
| Started | Oct 03 04:18:03 AM UTC 24 |
| Finished | Oct 03 04:18:45 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264855636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.264855636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1838095111 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 14942395926 ps |
| CPU time | 97.65 seconds |
| Started | Oct 03 04:18:03 AM UTC 24 |
| Finished | Oct 03 04:19:43 AM UTC 24 |
| Peak memory | 261516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838095111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1838095111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.859491076 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 504265911 ps |
| CPU time | 11.78 seconds |
| Started | Oct 03 04:18:02 AM UTC 24 |
| Finished | Oct 03 04:18:15 AM UTC 24 |
| Peak memory | 245052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859491076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.859491076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2460354038 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 11103580286 ps |
| CPU time | 13.57 seconds |
| Started | Oct 03 04:18:02 AM UTC 24 |
| Finished | Oct 03 04:18:17 AM UTC 24 |
| Peak memory | 234812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460354038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2460354038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1097682490 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 297072673 ps |
| CPU time | 8.14 seconds |
| Started | Oct 03 04:18:05 AM UTC 24 |
| Finished | Oct 03 04:18:15 AM UTC 24 |
| Peak memory | 233644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097682490 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.1097682490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.626223813 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 18588059946 ps |
| CPU time | 71.26 seconds |
| Started | Oct 03 04:18:11 AM UTC 24 |
| Finished | Oct 03 04:19:24 AM UTC 24 |
| Peak memory | 263624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626223813 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.626223813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.4266899569 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 5672137115 ps |
| CPU time | 47.32 seconds |
| Started | Oct 03 04:18:01 AM UTC 24 |
| Finished | Oct 03 04:18:50 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266899569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4266899569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.413499993 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 46451292 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 04:17:59 AM UTC 24 |
| Finished | Oct 03 04:18:02 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413499993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.413499993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.630944486 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 29249890 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 04:18:01 AM UTC 24 |
| Finished | Oct 03 04:18:03 AM UTC 24 |
| Peak memory | 215952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630944486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.630944486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3446495204 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 61126416 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 04:18:01 AM UTC 24 |
| Finished | Oct 03 04:18:03 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446495204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3446495204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.244512569 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 841330200 ps |
| CPU time | 8.8 seconds |
| Started | Oct 03 04:18:04 AM UTC 24 |
| Finished | Oct 03 04:18:14 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244512569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.244512569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.1786898328 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 11941157 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 04:18:41 AM UTC 24 |
| Finished | Oct 03 04:18:43 AM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786898328 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.1786898328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1341439402 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 1136429875 ps |
| CPU time | 10.56 seconds |
| Started | Oct 03 04:18:29 AM UTC 24 |
| Finished | Oct 03 04:18:40 AM UTC 24 |
| Peak memory | 244880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341439402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1341439402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2579316568 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 15083533 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 04:18:16 AM UTC 24 |
| Finished | Oct 03 04:18:18 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579316568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2579316568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.151922364 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 21955316311 ps |
| CPU time | 169.85 seconds |
| Started | Oct 03 04:18:33 AM UTC 24 |
| Finished | Oct 03 04:21:26 AM UTC 24 |
| Peak memory | 263552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151922364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.151922364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2490161515 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 8604529101 ps |
| CPU time | 129.23 seconds |
| Started | Oct 03 04:18:35 AM UTC 24 |
| Finished | Oct 03 04:20:47 AM UTC 24 |
| Peak memory | 261828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490161515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2490161515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.3796823886 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5620737976 ps |
| CPU time | 86.04 seconds |
| Started | Oct 03 04:18:35 AM UTC 24 |
| Finished | Oct 03 04:20:03 AM UTC 24 |
| Peak memory | 284348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796823886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.3796823886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.1967610009 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 686636453 ps |
| CPU time | 9.45 seconds |
| Started | Oct 03 04:18:30 AM UTC 24 |
| Finished | Oct 03 04:18:40 AM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967610009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1967610009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3986612305 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 17042446760 ps |
| CPU time | 101.41 seconds |
| Started | Oct 03 04:18:31 AM UTC 24 |
| Finished | Oct 03 04:20:14 AM UTC 24 |
| Peak memory | 265520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986612305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.3986612305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.4277901145 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2514971238 ps |
| CPU time | 9.69 seconds |
| Started | Oct 03 04:18:21 AM UTC 24 |
| Finished | Oct 03 04:18:32 AM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277901145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4277901145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.411304847 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1928647986 ps |
| CPU time | 30.51 seconds |
| Started | Oct 03 04:18:23 AM UTC 24 |
| Finished | Oct 03 04:18:55 AM UTC 24 |
| Peak memory | 241996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411304847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.411304847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2349375900 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 170580851 ps |
| CPU time | 5.78 seconds |
| Started | Oct 03 04:18:21 AM UTC 24 |
| Finished | Oct 03 04:18:28 AM UTC 24 |
| Peak memory | 245244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349375900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.2349375900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.358982159 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 43737541559 ps |
| CPU time | 39.13 seconds |
| Started | Oct 03 04:18:21 AM UTC 24 |
| Finished | Oct 03 04:19:02 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358982159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.358982159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3836299386 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 15050512509 ps |
| CPU time | 16.33 seconds |
| Started | Oct 03 04:18:32 AM UTC 24 |
| Finished | Oct 03 04:18:50 AM UTC 24 |
| Peak memory | 231352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836299386 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.3836299386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1556729569 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 32461467400 ps |
| CPU time | 407.08 seconds |
| Started | Oct 03 04:18:39 AM UTC 24 |
| Finished | Oct 03 04:25:32 AM UTC 24 |
| Peak memory | 277952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556729569 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.1556729569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.1798001088 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 4726668007 ps |
| CPU time | 28.08 seconds |
| Started | Oct 03 04:18:18 AM UTC 24 |
| Finished | Oct 03 04:18:47 AM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798001088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1798001088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1468059849 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 6585690658 ps |
| CPU time | 16.99 seconds |
| Started | Oct 03 04:18:16 AM UTC 24 |
| Finished | Oct 03 04:18:34 AM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468059849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1468059849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.3936843024 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 260346104 ps |
| CPU time | 8.44 seconds |
| Started | Oct 03 04:18:19 AM UTC 24 |
| Finished | Oct 03 04:18:29 AM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936843024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3936843024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1452883356 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 353950433 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 04:18:18 AM UTC 24 |
| Finished | Oct 03 04:18:20 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452883356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1452883356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.726857675 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 425257633 ps |
| CPU time | 4.92 seconds |
| Started | Oct 03 04:18:24 AM UTC 24 |
| Finished | Oct 03 04:18:29 AM UTC 24 |
| Peak memory | 245248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726857675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.726857675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3009787023 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 51458007 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 04:18:54 AM UTC 24 |
| Finished | Oct 03 04:18:56 AM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009787023 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.3009787023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3388568681 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 73132036 ps |
| CPU time | 4.74 seconds |
| Started | Oct 03 04:18:47 AM UTC 24 |
| Finished | Oct 03 04:18:53 AM UTC 24 |
| Peak memory | 244924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388568681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3388568681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.1365740891 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 13797194 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 04:18:41 AM UTC 24 |
| Finished | Oct 03 04:18:43 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365740891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1365740891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.568844727 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 63033121018 ps |
| CPU time | 227.34 seconds |
| Started | Oct 03 04:18:51 AM UTC 24 |
| Finished | Oct 03 04:22:42 AM UTC 24 |
| Peak memory | 261444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568844727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.568844727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3085606175 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 106434978321 ps |
| CPU time | 172.04 seconds |
| Started | Oct 03 04:18:52 AM UTC 24 |
| Finished | Oct 03 04:21:47 AM UTC 24 |
| Peak memory | 251392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085606175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3085606175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3806026431 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 8020031066 ps |
| CPU time | 49.48 seconds |
| Started | Oct 03 04:18:53 AM UTC 24 |
| Finished | Oct 03 04:19:44 AM UTC 24 |
| Peak memory | 261564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806026431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.3806026431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.895806860 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 648265236 ps |
| CPU time | 4.45 seconds |
| Started | Oct 03 04:18:49 AM UTC 24 |
| Finished | Oct 03 04:18:54 AM UTC 24 |
| Peak memory | 244996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895806860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.895806860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2727210262 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 559101945 ps |
| CPU time | 18.34 seconds |
| Started | Oct 03 04:18:50 AM UTC 24 |
| Finished | Oct 03 04:19:09 AM UTC 24 |
| Peak memory | 244984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727210262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.2727210262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.3671712056 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 131506900 ps |
| CPU time | 6.68 seconds |
| Started | Oct 03 04:18:45 AM UTC 24 |
| Finished | Oct 03 04:18:53 AM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671712056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3671712056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3408602295 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 864958520 ps |
| CPU time | 12.04 seconds |
| Started | Oct 03 04:18:46 AM UTC 24 |
| Finished | Oct 03 04:18:59 AM UTC 24 |
| Peak memory | 251128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408602295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3408602295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3927527233 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1770649583 ps |
| CPU time | 11.78 seconds |
| Started | Oct 03 04:18:44 AM UTC 24 |
| Finished | Oct 03 04:18:57 AM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927527233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.3927527233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.112897892 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 227559555 ps |
| CPU time | 7.09 seconds |
| Started | Oct 03 04:18:44 AM UTC 24 |
| Finished | Oct 03 04:18:52 AM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112897892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.112897892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2982227999 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 1154225701 ps |
| CPU time | 15.75 seconds |
| Started | Oct 03 04:18:51 AM UTC 24 |
| Finished | Oct 03 04:19:08 AM UTC 24 |
| Peak memory | 233272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982227999 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.2982227999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2794390729 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 61225878134 ps |
| CPU time | 341.97 seconds |
| Started | Oct 03 04:18:54 AM UTC 24 |
| Finished | Oct 03 04:24:41 AM UTC 24 |
| Peak memory | 263608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794390729 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.2794390729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.928204250 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 1672454689 ps |
| CPU time | 8.27 seconds |
| Started | Oct 03 04:18:42 AM UTC 24 |
| Finished | Oct 03 04:18:51 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928204250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.928204250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3695360210 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3995171679 ps |
| CPU time | 13.81 seconds |
| Started | Oct 03 04:18:42 AM UTC 24 |
| Finished | Oct 03 04:18:57 AM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695360210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3695360210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.1078420132 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 103361382 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:18:44 AM UTC 24 |
| Finished | Oct 03 04:18:46 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078420132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1078420132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2292036297 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 117659763 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 04:18:43 AM UTC 24 |
| Finished | Oct 03 04:18:45 AM UTC 24 |
| Peak memory | 215892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292036297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2292036297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.2212801570 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 958992526 ps |
| CPU time | 5.35 seconds |
| Started | Oct 03 04:18:46 AM UTC 24 |
| Finished | Oct 03 04:18:53 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212801570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2212801570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.812095245 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 88739302 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 04:19:09 AM UTC 24 |
| Finished | Oct 03 04:19:11 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812095245 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.812095245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2658404760 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 816915569 ps |
| CPU time | 6.03 seconds |
| Started | Oct 03 04:19:01 AM UTC 24 |
| Finished | Oct 03 04:19:08 AM UTC 24 |
| Peak memory | 244936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658404760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2658404760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.645028647 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 40068620 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 04:18:54 AM UTC 24 |
| Finished | Oct 03 04:18:56 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645028647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.645028647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.521615135 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 31560878710 ps |
| CPU time | 101.32 seconds |
| Started | Oct 03 04:19:06 AM UTC 24 |
| Finished | Oct 03 04:20:50 AM UTC 24 |
| Peak memory | 277884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521615135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.521615135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3567700337 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 1870057664 ps |
| CPU time | 11.27 seconds |
| Started | Oct 03 04:19:07 AM UTC 24 |
| Finished | Oct 03 04:19:20 AM UTC 24 |
| Peak memory | 231560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567700337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3567700337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1106887355 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 10461595611 ps |
| CPU time | 142.08 seconds |
| Started | Oct 03 04:19:08 AM UTC 24 |
| Finished | Oct 03 04:21:32 AM UTC 24 |
| Peak memory | 263616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106887355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.1106887355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.19220906 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 122679900 ps |
| CPU time | 4.1 seconds |
| Started | Oct 03 04:19:02 AM UTC 24 |
| Finished | Oct 03 04:19:07 AM UTC 24 |
| Peak memory | 234708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19220906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.19220906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.668953280 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 73132436937 ps |
| CPU time | 275.21 seconds |
| Started | Oct 03 04:19:03 AM UTC 24 |
| Finished | Oct 03 04:23:43 AM UTC 24 |
| Peak memory | 267840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668953280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.668953280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.3231436264 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 1649761071 ps |
| CPU time | 7.47 seconds |
| Started | Oct 03 04:18:58 AM UTC 24 |
| Finished | Oct 03 04:19:06 AM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231436264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3231436264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.3594340255 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 9866982645 ps |
| CPU time | 36.58 seconds |
| Started | Oct 03 04:19:00 AM UTC 24 |
| Finished | Oct 03 04:19:38 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594340255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3594340255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1098707587 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 403182491 ps |
| CPU time | 3.45 seconds |
| Started | Oct 03 04:18:58 AM UTC 24 |
| Finished | Oct 03 04:19:02 AM UTC 24 |
| Peak memory | 234600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098707587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.1098707587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3881405336 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 1156015575 ps |
| CPU time | 6.9 seconds |
| Started | Oct 03 04:18:58 AM UTC 24 |
| Finished | Oct 03 04:19:06 AM UTC 24 |
| Peak memory | 244944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881405336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3881405336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1245591704 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 4158197940 ps |
| CPU time | 10.94 seconds |
| Started | Oct 03 04:19:04 AM UTC 24 |
| Finished | Oct 03 04:19:16 AM UTC 24 |
| Peak memory | 231420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245591704 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.1245591704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.3693409918 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 65225139935 ps |
| CPU time | 284.95 seconds |
| Started | Oct 03 04:19:08 AM UTC 24 |
| Finished | Oct 03 04:23:57 AM UTC 24 |
| Peak memory | 294600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693409918 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.3693409918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.1528215022 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 8626698290 ps |
| CPU time | 31.66 seconds |
| Started | Oct 03 04:18:55 AM UTC 24 |
| Finished | Oct 03 04:19:29 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528215022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1528215022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2745610120 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 4711489416 ps |
| CPU time | 14.53 seconds |
| Started | Oct 03 04:18:54 AM UTC 24 |
| Finished | Oct 03 04:19:10 AM UTC 24 |
| Peak memory | 227784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745610120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2745610120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1685882617 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 39546970 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 04:18:58 AM UTC 24 |
| Finished | Oct 03 04:19:00 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685882617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1685882617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3456230202 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 45235330 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 04:18:57 AM UTC 24 |
| Finished | Oct 03 04:18:59 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456230202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3456230202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.880533238 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 3475791656 ps |
| CPU time | 22.68 seconds |
| Started | Oct 03 04:19:00 AM UTC 24 |
| Finished | Oct 03 04:19:24 AM UTC 24 |
| Peak memory | 245124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880533238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.880533238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.568251389 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 98531908 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:19:22 AM UTC 24 |
| Finished | Oct 03 04:19:25 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568251389 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.568251389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3374569557 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 223733537 ps |
| CPU time | 3.16 seconds |
| Started | Oct 03 04:19:16 AM UTC 24 |
| Finished | Oct 03 04:19:20 AM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374569557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3374569557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3304624219 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 33415932 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 04:19:09 AM UTC 24 |
| Finished | Oct 03 04:19:11 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304624219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3304624219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.978643916 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 16126164919 ps |
| CPU time | 123.22 seconds |
| Started | Oct 03 04:19:21 AM UTC 24 |
| Finished | Oct 03 04:21:27 AM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978643916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.978643916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.276273240 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 12101428617 ps |
| CPU time | 95.3 seconds |
| Started | Oct 03 04:19:21 AM UTC 24 |
| Finished | Oct 03 04:20:58 AM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276273240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.276273240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2870522404 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 81415114842 ps |
| CPU time | 276.15 seconds |
| Started | Oct 03 04:19:22 AM UTC 24 |
| Finished | Oct 03 04:24:03 AM UTC 24 |
| Peak memory | 267708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870522404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.2870522404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1443434111 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 6666276779 ps |
| CPU time | 49.49 seconds |
| Started | Oct 03 04:19:17 AM UTC 24 |
| Finished | Oct 03 04:20:08 AM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443434111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1443434111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2338102977 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 17999192372 ps |
| CPU time | 113.98 seconds |
| Started | Oct 03 04:19:17 AM UTC 24 |
| Finished | Oct 03 04:21:13 AM UTC 24 |
| Peak memory | 245308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338102977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.2338102977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.2660230583 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 14950789259 ps |
| CPU time | 25.21 seconds |
| Started | Oct 03 04:19:12 AM UTC 24 |
| Finished | Oct 03 04:19:39 AM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660230583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2660230583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.346387479 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 1032232158 ps |
| CPU time | 20.71 seconds |
| Started | Oct 03 04:19:14 AM UTC 24 |
| Finished | Oct 03 04:19:36 AM UTC 24 |
| Peak memory | 244928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346387479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.346387479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2444134313 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 778668016 ps |
| CPU time | 8.14 seconds |
| Started | Oct 03 04:19:12 AM UTC 24 |
| Finished | Oct 03 04:19:21 AM UTC 24 |
| Peak memory | 234636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444134313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2444134313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.982635121 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 1456407895 ps |
| CPU time | 17.77 seconds |
| Started | Oct 03 04:19:12 AM UTC 24 |
| Finished | Oct 03 04:19:31 AM UTC 24 |
| Peak memory | 244876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982635121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.982635121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.3705639878 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 3097663711 ps |
| CPU time | 23.44 seconds |
| Started | Oct 03 04:19:20 AM UTC 24 |
| Finished | Oct 03 04:19:45 AM UTC 24 |
| Peak memory | 231292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705639878 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.3705639878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.3381763071 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 54443090177 ps |
| CPU time | 375.53 seconds |
| Started | Oct 03 04:19:22 AM UTC 24 |
| Finished | Oct 03 04:25:43 AM UTC 24 |
| Peak memory | 284356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381763071 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.3381763071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.3601095496 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 1254155152 ps |
| CPU time | 12.91 seconds |
| Started | Oct 03 04:19:10 AM UTC 24 |
| Finished | Oct 03 04:19:24 AM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601095496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3601095496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1020545019 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 910391483 ps |
| CPU time | 5.09 seconds |
| Started | Oct 03 04:19:09 AM UTC 24 |
| Finished | Oct 03 04:19:15 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020545019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1020545019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.3472438386 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 37238142 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 04:19:11 AM UTC 24 |
| Finished | Oct 03 04:19:14 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472438386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3472438386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3811401028 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1099377198 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 04:19:11 AM UTC 24 |
| Finished | Oct 03 04:19:14 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811401028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3811401028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.3565943597 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 18732192043 ps |
| CPU time | 11.84 seconds |
| Started | Oct 03 04:19:15 AM UTC 24 |
| Finished | Oct 03 04:19:27 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565943597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3565943597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3252186206 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 51224776 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 04:19:40 AM UTC 24 |
| Finished | Oct 03 04:19:42 AM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252186206 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.3252186206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2186545058 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2443715481 ps |
| CPU time | 6.91 seconds |
| Started | Oct 03 04:19:32 AM UTC 24 |
| Finished | Oct 03 04:19:40 AM UTC 24 |
| Peak memory | 245004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186545058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2186545058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.407413239 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 56797915 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 04:19:24 AM UTC 24 |
| Finished | Oct 03 04:19:27 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407413239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.407413239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3545521421 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 14354806861 ps |
| CPU time | 31.9 seconds |
| Started | Oct 03 04:19:39 AM UTC 24 |
| Finished | Oct 03 04:20:12 AM UTC 24 |
| Peak memory | 247296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545521421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3545521421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2142135143 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 33761417582 ps |
| CPU time | 123.75 seconds |
| Started | Oct 03 04:19:39 AM UTC 24 |
| Finished | Oct 03 04:21:45 AM UTC 24 |
| Peak memory | 261564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142135143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.2142135143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.1777988839 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 129558682 ps |
| CPU time | 6.77 seconds |
| Started | Oct 03 04:19:33 AM UTC 24 |
| Finished | Oct 03 04:19:41 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777988839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1777988839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1264949452 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 38445350 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 04:19:35 AM UTC 24 |
| Finished | Oct 03 04:19:37 AM UTC 24 |
| Peak memory | 226864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264949452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.1264949452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1651439050 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 117696534 ps |
| CPU time | 3.03 seconds |
| Started | Oct 03 04:19:30 AM UTC 24 |
| Finished | Oct 03 04:19:34 AM UTC 24 |
| Peak memory | 233800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651439050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1651439050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.3934168663 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 3485583334 ps |
| CPU time | 17.2 seconds |
| Started | Oct 03 04:19:30 AM UTC 24 |
| Finished | Oct 03 04:19:48 AM UTC 24 |
| Peak memory | 245112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934168663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3934168663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3724479102 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 8132313177 ps |
| CPU time | 10.34 seconds |
| Started | Oct 03 04:19:29 AM UTC 24 |
| Finished | Oct 03 04:19:40 AM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724479102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.3724479102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3632294513 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 29884995 ps |
| CPU time | 3.08 seconds |
| Started | Oct 03 04:19:29 AM UTC 24 |
| Finished | Oct 03 04:19:33 AM UTC 24 |
| Peak memory | 244596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632294513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3632294513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2324125911 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 148556532 ps |
| CPU time | 4.18 seconds |
| Started | Oct 03 04:19:35 AM UTC 24 |
| Finished | Oct 03 04:19:41 AM UTC 24 |
| Peak memory | 233604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324125911 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2324125911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.2791886994 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 187251549612 ps |
| CPU time | 526.69 seconds |
| Started | Oct 03 04:19:40 AM UTC 24 |
| Finished | Oct 03 04:28:34 AM UTC 24 |
| Peak memory | 294624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791886994 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.2791886994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.4022953100 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 2115353184 ps |
| CPU time | 18.71 seconds |
| Started | Oct 03 04:19:24 AM UTC 24 |
| Finished | Oct 03 04:19:45 AM UTC 24 |
| Peak memory | 227328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022953100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4022953100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.3418348252 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2909190999 ps |
| CPU time | 3.22 seconds |
| Started | Oct 03 04:19:24 AM UTC 24 |
| Finished | Oct 03 04:19:29 AM UTC 24 |
| Peak memory | 217004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418348252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3418348252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.2912121365 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 416578072 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 04:19:28 AM UTC 24 |
| Finished | Oct 03 04:19:30 AM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912121365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2912121365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1289285723 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 53875375 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 04:19:26 AM UTC 24 |
| Finished | Oct 03 04:19:28 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289285723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1289285723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.2758080354 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 2999985405 ps |
| CPU time | 13.97 seconds |
| Started | Oct 03 04:19:31 AM UTC 24 |
| Finished | Oct 03 04:19:46 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758080354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2758080354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.2442062259 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 19508876 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 04:19:54 AM UTC 24 |
| Finished | Oct 03 04:19:56 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442062259 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.2442062259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3987737536 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 721626709 ps |
| CPU time | 8.91 seconds |
| Started | Oct 03 04:19:46 AM UTC 24 |
| Finished | Oct 03 04:19:56 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987737536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3987737536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3749567290 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 18263178 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 04:19:41 AM UTC 24 |
| Finished | Oct 03 04:19:44 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749567290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3749567290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.1218921212 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 23719659975 ps |
| CPU time | 206.89 seconds |
| Started | Oct 03 04:19:49 AM UTC 24 |
| Finished | Oct 03 04:23:19 AM UTC 24 |
| Peak memory | 263560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218921212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1218921212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3404488712 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2297957903 ps |
| CPU time | 35.6 seconds |
| Started | Oct 03 04:19:50 AM UTC 24 |
| Finished | Oct 03 04:20:27 AM UTC 24 |
| Peak memory | 263636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404488712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3404488712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1965250501 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 6072592794 ps |
| CPU time | 69.07 seconds |
| Started | Oct 03 04:19:51 AM UTC 24 |
| Finished | Oct 03 04:21:02 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965250501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.1965250501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.1651925175 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 98755959 ps |
| CPU time | 4.07 seconds |
| Started | Oct 03 04:19:47 AM UTC 24 |
| Finished | Oct 03 04:19:52 AM UTC 24 |
| Peak memory | 234632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651925175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1651925175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.831741362 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 34077279343 ps |
| CPU time | 96.33 seconds |
| Started | Oct 03 04:19:47 AM UTC 24 |
| Finished | Oct 03 04:21:26 AM UTC 24 |
| Peak memory | 261428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831741362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.831741362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.991787912 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 1372793516 ps |
| CPU time | 10.87 seconds |
| Started | Oct 03 04:19:45 AM UTC 24 |
| Finished | Oct 03 04:19:57 AM UTC 24 |
| Peak memory | 234648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991787912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.991787912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2523620110 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 481251730 ps |
| CPU time | 15.26 seconds |
| Started | Oct 03 04:19:46 AM UTC 24 |
| Finished | Oct 03 04:20:03 AM UTC 24 |
| Peak memory | 251068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523620110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2523620110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.1905185759 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 8751689832 ps |
| CPU time | 19.38 seconds |
| Started | Oct 03 04:19:45 AM UTC 24 |
| Finished | Oct 03 04:20:06 AM UTC 24 |
| Peak memory | 245004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905185759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.1905185759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2727103700 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 1471196247 ps |
| CPU time | 7.09 seconds |
| Started | Oct 03 04:19:44 AM UTC 24 |
| Finished | Oct 03 04:19:52 AM UTC 24 |
| Peak memory | 244992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727103700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2727103700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.680033743 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 418009428 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 04:19:48 AM UTC 24 |
| Finished | Oct 03 04:19:53 AM UTC 24 |
| Peak memory | 233336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680033743 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.680033743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1389925937 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 183345377962 ps |
| CPU time | 840.37 seconds |
| Started | Oct 03 04:19:52 AM UTC 24 |
| Finished | Oct 03 04:34:03 AM UTC 24 |
| Peak memory | 294400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389925937 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.1389925937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.4233724842 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 41308380154 ps |
| CPU time | 49.98 seconds |
| Started | Oct 03 04:19:41 AM UTC 24 |
| Finished | Oct 03 04:20:33 AM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233724842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4233724842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3731302295 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 4245156701 ps |
| CPU time | 18.28 seconds |
| Started | Oct 03 04:19:41 AM UTC 24 |
| Finished | Oct 03 04:20:01 AM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731302295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3731302295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.2402611892 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 66844342 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 04:19:43 AM UTC 24 |
| Finished | Oct 03 04:19:47 AM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402611892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2402611892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2239404434 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 85116022 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 04:19:42 AM UTC 24 |
| Finished | Oct 03 04:19:45 AM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239404434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2239404434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.3799892785 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 616782943 ps |
| CPU time | 3.4 seconds |
| Started | Oct 03 04:19:46 AM UTC 24 |
| Finished | Oct 03 04:19:51 AM UTC 24 |
| Peak memory | 233884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799892785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3799892785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2182166495 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 16865028 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 04:02:17 AM UTC 24 |
| Finished | Oct 03 04:02:19 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182166495 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2182166495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2888144252 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 110633933 ps |
| CPU time | 4.01 seconds |
| Started | Oct 03 04:01:53 AM UTC 24 |
| Finished | Oct 03 04:01:58 AM UTC 24 |
| Peak memory | 244880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888144252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2888144252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.24636102 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 101590307 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 04:01:21 AM UTC 24 |
| Finished | Oct 03 04:01:23 AM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24636102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.24636102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2479643287 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 585353701227 ps |
| CPU time | 421.95 seconds |
| Started | Oct 03 04:01:59 AM UTC 24 |
| Finished | Oct 03 04:09:07 AM UTC 24 |
| Peak memory | 267720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479643287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2479643287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.455982852 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1920954040 ps |
| CPU time | 36.8 seconds |
| Started | Oct 03 04:02:01 AM UTC 24 |
| Finished | Oct 03 04:02:40 AM UTC 24 |
| Peak memory | 261440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455982852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.455982852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3122708703 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 834612915 ps |
| CPU time | 20.76 seconds |
| Started | Oct 03 04:01:54 AM UTC 24 |
| Finished | Oct 03 04:02:16 AM UTC 24 |
| Peak memory | 234644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122708703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3122708703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.446484530 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 15605468948 ps |
| CPU time | 139.15 seconds |
| Started | Oct 03 04:01:54 AM UTC 24 |
| Finished | Oct 03 04:04:16 AM UTC 24 |
| Peak memory | 277820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446484530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.446484530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3664158859 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 105391221 ps |
| CPU time | 3.85 seconds |
| Started | Oct 03 04:01:34 AM UTC 24 |
| Finished | Oct 03 04:01:38 AM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664158859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3664158859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.3665414868 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 7023141139 ps |
| CPU time | 36.75 seconds |
| Started | Oct 03 04:01:40 AM UTC 24 |
| Finished | Oct 03 04:02:18 AM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665414868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3665414868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2541004485 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2245915249 ps |
| CPU time | 16.54 seconds |
| Started | Oct 03 04:01:32 AM UTC 24 |
| Finished | Oct 03 04:01:49 AM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541004485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.2541004485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.374675538 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 7245276335 ps |
| CPU time | 21.83 seconds |
| Started | Oct 03 04:01:29 AM UTC 24 |
| Finished | Oct 03 04:01:53 AM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374675538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.374675538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1378522516 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 767836595 ps |
| CPU time | 18.1 seconds |
| Started | Oct 03 04:01:55 AM UTC 24 |
| Finished | Oct 03 04:02:15 AM UTC 24 |
| Peak memory | 231172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378522516 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.1378522516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.30880927 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 18252438431 ps |
| CPU time | 71.26 seconds |
| Started | Oct 03 04:02:16 AM UTC 24 |
| Finished | Oct 03 04:03:29 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30880927 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.30880927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2611158129 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1007565014 ps |
| CPU time | 3.54 seconds |
| Started | Oct 03 04:01:24 AM UTC 24 |
| Finished | Oct 03 04:01:29 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611158129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2611158129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.1621042000 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 39108365 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 04:01:29 AM UTC 24 |
| Finished | Oct 03 04:01:33 AM UTC 24 |
| Peak memory | 217008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621042000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1621042000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2947131006 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 43775979 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 04:01:26 AM UTC 24 |
| Finished | Oct 03 04:01:29 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947131006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2947131006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3456984987 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 153831882 ps |
| CPU time | 3.25 seconds |
| Started | Oct 03 04:01:50 AM UTC 24 |
| Finished | Oct 03 04:01:54 AM UTC 24 |
| Peak memory | 234420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456984987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3456984987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1621197545 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 11588975 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 04:03:30 AM UTC 24 |
| Finished | Oct 03 04:03:32 AM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621197545 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1621197545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2193197627 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 847541027 ps |
| CPU time | 6.07 seconds |
| Started | Oct 03 04:02:43 AM UTC 24 |
| Finished | Oct 03 04:02:50 AM UTC 24 |
| Peak memory | 234676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193197627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2193197627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.896891580 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 15185756 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 04:02:19 AM UTC 24 |
| Finished | Oct 03 04:02:21 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896891580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.896891580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.1986804772 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 155875889642 ps |
| CPU time | 363.7 seconds |
| Started | Oct 03 04:02:53 AM UTC 24 |
| Finished | Oct 03 04:09:02 AM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986804772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1986804772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1795246480 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 11215328785 ps |
| CPU time | 111.29 seconds |
| Started | Oct 03 04:03:02 AM UTC 24 |
| Finished | Oct 03 04:04:55 AM UTC 24 |
| Peak memory | 278208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795246480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.1795246480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.108726534 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 189681742 ps |
| CPU time | 4.99 seconds |
| Started | Oct 03 04:02:47 AM UTC 24 |
| Finished | Oct 03 04:02:53 AM UTC 24 |
| Peak memory | 244928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108726534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.108726534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3804388329 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 595637105 ps |
| CPU time | 10.9 seconds |
| Started | Oct 03 04:02:40 AM UTC 24 |
| Finished | Oct 03 04:02:52 AM UTC 24 |
| Peak memory | 244992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804388329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3804388329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.3748165533 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 9917165771 ps |
| CPU time | 80.11 seconds |
| Started | Oct 03 04:02:40 AM UTC 24 |
| Finished | Oct 03 04:04:02 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748165533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3748165533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1291441682 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 6282739800 ps |
| CPU time | 26.15 seconds |
| Started | Oct 03 04:02:34 AM UTC 24 |
| Finished | Oct 03 04:03:01 AM UTC 24 |
| Peak memory | 245040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291441682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1291441682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1078816794 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 16615050568 ps |
| CPU time | 17.33 seconds |
| Started | Oct 03 04:02:30 AM UTC 24 |
| Finished | Oct 03 04:02:48 AM UTC 24 |
| Peak memory | 244980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078816794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1078816794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3633786270 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1650024328 ps |
| CPU time | 9.18 seconds |
| Started | Oct 03 04:02:51 AM UTC 24 |
| Finished | Oct 03 04:03:02 AM UTC 24 |
| Peak memory | 233264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633786270 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.3633786270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.3497199815 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6683421505 ps |
| CPU time | 86.83 seconds |
| Started | Oct 03 04:03:03 AM UTC 24 |
| Finished | Oct 03 04:04:32 AM UTC 24 |
| Peak memory | 263484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497199815 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.3497199815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.4208296256 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4647213591 ps |
| CPU time | 15.92 seconds |
| Started | Oct 03 04:02:22 AM UTC 24 |
| Finished | Oct 03 04:02:39 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208296256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4208296256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1245196471 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4073700930 ps |
| CPU time | 9.7 seconds |
| Started | Oct 03 04:02:22 AM UTC 24 |
| Finished | Oct 03 04:02:33 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245196471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1245196471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.342113716 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 24471285 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 04:02:26 AM UTC 24 |
| Finished | Oct 03 04:02:29 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342113716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.342113716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3288457154 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 552000900 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 04:02:23 AM UTC 24 |
| Finished | Oct 03 04:02:26 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288457154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3288457154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1413698312 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 374980054 ps |
| CPU time | 4.2 seconds |
| Started | Oct 03 04:02:41 AM UTC 24 |
| Finished | Oct 03 04:02:46 AM UTC 24 |
| Peak memory | 244932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413698312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1413698312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.3988861738 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 14997582 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 04:04:33 AM UTC 24 |
| Finished | Oct 03 04:04:35 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988861738 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3988861738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2116629743 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 32382507 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 04:04:06 AM UTC 24 |
| Finished | Oct 03 04:04:10 AM UTC 24 |
| Peak memory | 244596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116629743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2116629743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.440311330 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 13290820 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:03:33 AM UTC 24 |
| Finished | Oct 03 04:03:35 AM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440311330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.440311330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2769257504 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 24271420327 ps |
| CPU time | 233.07 seconds |
| Started | Oct 03 04:04:16 AM UTC 24 |
| Finished | Oct 03 04:08:13 AM UTC 24 |
| Peak memory | 263880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769257504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2769257504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1382921007 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3130511064 ps |
| CPU time | 56.7 seconds |
| Started | Oct 03 04:04:18 AM UTC 24 |
| Finished | Oct 03 04:05:17 AM UTC 24 |
| Peak memory | 249544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382921007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1382921007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.246358482 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 20655127420 ps |
| CPU time | 96.36 seconds |
| Started | Oct 03 04:04:26 AM UTC 24 |
| Finished | Oct 03 04:06:04 AM UTC 24 |
| Peak memory | 245132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246358482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.246358482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.3996617796 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 109843805 ps |
| CPU time | 5.51 seconds |
| Started | Oct 03 04:04:11 AM UTC 24 |
| Finished | Oct 03 04:04:18 AM UTC 24 |
| Peak memory | 244936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996617796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3996617796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2161973493 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5260965684 ps |
| CPU time | 88.43 seconds |
| Started | Oct 03 04:04:12 AM UTC 24 |
| Finished | Oct 03 04:05:43 AM UTC 24 |
| Peak memory | 277820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161973493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.2161973493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2470556067 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 277167184 ps |
| CPU time | 8.94 seconds |
| Started | Oct 03 04:04:01 AM UTC 24 |
| Finished | Oct 03 04:04:11 AM UTC 24 |
| Peak memory | 234652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470556067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2470556067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.2071120231 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1719410441 ps |
| CPU time | 25.47 seconds |
| Started | Oct 03 04:04:03 AM UTC 24 |
| Finished | Oct 03 04:04:30 AM UTC 24 |
| Peak memory | 251028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071120231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2071120231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.4175972277 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2237655229 ps |
| CPU time | 12.33 seconds |
| Started | Oct 03 04:03:51 AM UTC 24 |
| Finished | Oct 03 04:04:04 AM UTC 24 |
| Peak memory | 245120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175972277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.4175972277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.4266335578 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 11668028902 ps |
| CPU time | 13.25 seconds |
| Started | Oct 03 04:03:51 AM UTC 24 |
| Finished | Oct 03 04:04:05 AM UTC 24 |
| Peak memory | 235132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266335578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4266335578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1845360268 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1041005995 ps |
| CPU time | 8.25 seconds |
| Started | Oct 03 04:04:15 AM UTC 24 |
| Finished | Oct 03 04:04:25 AM UTC 24 |
| Peak memory | 231280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845360268 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.1845360268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.1741871448 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1686834046 ps |
| CPU time | 8.18 seconds |
| Started | Oct 03 04:03:40 AM UTC 24 |
| Finished | Oct 03 04:03:50 AM UTC 24 |
| Peak memory | 227388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741871448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1741871448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2181950907 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 17911006400 ps |
| CPU time | 18.86 seconds |
| Started | Oct 03 04:03:39 AM UTC 24 |
| Finished | Oct 03 04:03:59 AM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181950907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2181950907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.1687572424 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 122391841 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 04:03:48 AM UTC 24 |
| Finished | Oct 03 04:03:50 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687572424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1687572424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1964415410 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 87730268 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 04:03:44 AM UTC 24 |
| Finished | Oct 03 04:03:47 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964415410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1964415410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3321907845 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 866624276 ps |
| CPU time | 8.39 seconds |
| Started | Oct 03 04:04:05 AM UTC 24 |
| Finished | Oct 03 04:04:15 AM UTC 24 |
| Peak memory | 249044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321907845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3321907845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.906080029 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 34831680 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 04:05:28 AM UTC 24 |
| Finished | Oct 03 04:05:30 AM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906080029 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.906080029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2826702118 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 110454628 ps |
| CPU time | 3.26 seconds |
| Started | Oct 03 04:05:11 AM UTC 24 |
| Finished | Oct 03 04:05:15 AM UTC 24 |
| Peak memory | 244656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826702118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2826702118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1142964980 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 17189468 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 04:04:36 AM UTC 24 |
| Finished | Oct 03 04:04:38 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142964980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1142964980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.4180890448 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 9446020543 ps |
| CPU time | 54.48 seconds |
| Started | Oct 03 04:05:17 AM UTC 24 |
| Finished | Oct 03 04:06:13 AM UTC 24 |
| Peak memory | 261448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180890448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4180890448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3019891581 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3390062167 ps |
| CPU time | 18.71 seconds |
| Started | Oct 03 04:05:13 AM UTC 24 |
| Finished | Oct 03 04:05:33 AM UTC 24 |
| Peak memory | 234812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019891581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3019891581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.606379258 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 46448359709 ps |
| CPU time | 276.69 seconds |
| Started | Oct 03 04:05:14 AM UTC 24 |
| Finished | Oct 03 04:09:55 AM UTC 24 |
| Peak memory | 261564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606379258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.606379258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.1232732697 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 13343569587 ps |
| CPU time | 37.77 seconds |
| Started | Oct 03 04:05:04 AM UTC 24 |
| Finished | Oct 03 04:05:43 AM UTC 24 |
| Peak memory | 235140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232732697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1232732697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3278105289 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 725722596 ps |
| CPU time | 8.57 seconds |
| Started | Oct 03 04:05:09 AM UTC 24 |
| Finished | Oct 03 04:05:19 AM UTC 24 |
| Peak memory | 234996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278105289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3278105289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.4098195731 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 252676118 ps |
| CPU time | 10.4 seconds |
| Started | Oct 03 04:05:01 AM UTC 24 |
| Finished | Oct 03 04:05:12 AM UTC 24 |
| Peak memory | 245312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098195731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.4098195731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3586121066 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 381728400 ps |
| CPU time | 15.13 seconds |
| Started | Oct 03 04:04:58 AM UTC 24 |
| Finished | Oct 03 04:05:14 AM UTC 24 |
| Peak memory | 234644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586121066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3586121066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.138473445 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 130340401 ps |
| CPU time | 6.04 seconds |
| Started | Oct 03 04:05:15 AM UTC 24 |
| Finished | Oct 03 04:05:23 AM UTC 24 |
| Peak memory | 233408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138473445 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.138473445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1455343359 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 110245141615 ps |
| CPU time | 526.61 seconds |
| Started | Oct 03 04:05:24 AM UTC 24 |
| Finished | Oct 03 04:14:17 AM UTC 24 |
| Peak memory | 265920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455343359 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.1455343359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.1302181612 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4359986263 ps |
| CPU time | 31.42 seconds |
| Started | Oct 03 04:04:54 AM UTC 24 |
| Finished | Oct 03 04:05:27 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302181612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1302181612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.42749897 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3803587256 ps |
| CPU time | 27.08 seconds |
| Started | Oct 03 04:04:42 AM UTC 24 |
| Finished | Oct 03 04:05:10 AM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42749897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.42749897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.75179868 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 159114640 ps |
| CPU time | 10.48 seconds |
| Started | Oct 03 04:04:56 AM UTC 24 |
| Finished | Oct 03 04:05:08 AM UTC 24 |
| Peak memory | 227332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75179868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.75179868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.692938799 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 59137185 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 04:04:54 AM UTC 24 |
| Finished | Oct 03 04:04:57 AM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692938799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.692938799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.517967860 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 12006666333 ps |
| CPU time | 28.52 seconds |
| Started | Oct 03 04:05:11 AM UTC 24 |
| Finished | Oct 03 04:05:41 AM UTC 24 |
| Peak memory | 234820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517967860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.517967860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.854656187 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 79474291 ps |
| CPU time | 0.98 seconds |
| Started | Oct 03 04:05:57 AM UTC 24 |
| Finished | Oct 03 04:05:59 AM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854656187 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.854656187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3568337035 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 92706856 ps |
| CPU time | 3.91 seconds |
| Started | Oct 03 04:05:44 AM UTC 24 |
| Finished | Oct 03 04:05:49 AM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568337035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3568337035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.2332248331 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 48642316 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 04:05:28 AM UTC 24 |
| Finished | Oct 03 04:05:30 AM UTC 24 |
| Peak memory | 215532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332248331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2332248331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3894723228 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 82380167211 ps |
| CPU time | 270.76 seconds |
| Started | Oct 03 04:05:52 AM UTC 24 |
| Finished | Oct 03 04:10:27 AM UTC 24 |
| Peak memory | 261448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894723228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3894723228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3856429386 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 28467059129 ps |
| CPU time | 146.49 seconds |
| Started | Oct 03 04:05:52 AM UTC 24 |
| Finished | Oct 03 04:08:22 AM UTC 24 |
| Peak memory | 267716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856429386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3856429386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2376741579 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5282202025 ps |
| CPU time | 78.7 seconds |
| Started | Oct 03 04:05:54 AM UTC 24 |
| Finished | Oct 03 04:07:15 AM UTC 24 |
| Peak memory | 261884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376741579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.2376741579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.583304855 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 163274845 ps |
| CPU time | 6.38 seconds |
| Started | Oct 03 04:05:48 AM UTC 24 |
| Finished | Oct 03 04:05:56 AM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583304855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.583304855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1732307381 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1653868404 ps |
| CPU time | 28.16 seconds |
| Started | Oct 03 04:05:49 AM UTC 24 |
| Finished | Oct 03 04:06:19 AM UTC 24 |
| Peak memory | 261300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732307381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.1732307381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2031856791 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 302149787 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 04:05:43 AM UTC 24 |
| Finished | Oct 03 04:05:47 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031856791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2031856791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.1814545535 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 53872977 ps |
| CPU time | 3.26 seconds |
| Started | Oct 03 04:05:44 AM UTC 24 |
| Finished | Oct 03 04:05:49 AM UTC 24 |
| Peak memory | 244608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814545535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1814545535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2608991550 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3491695130 ps |
| CPU time | 9.24 seconds |
| Started | Oct 03 04:05:42 AM UTC 24 |
| Finished | Oct 03 04:05:52 AM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608991550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.2608991550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2903328095 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 75029675 ps |
| CPU time | 3.9 seconds |
| Started | Oct 03 04:05:38 AM UTC 24 |
| Finished | Oct 03 04:05:43 AM UTC 24 |
| Peak memory | 244988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903328095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2903328095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.356158198 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 289270096 ps |
| CPU time | 5.95 seconds |
| Started | Oct 03 04:05:50 AM UTC 24 |
| Finished | Oct 03 04:05:57 AM UTC 24 |
| Peak memory | 233584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356158198 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.356158198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.2334326372 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 51708107 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 04:05:54 AM UTC 24 |
| Finished | Oct 03 04:05:57 AM UTC 24 |
| Peak memory | 215724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334326372 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.2334326372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3511395644 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 15589859838 ps |
| CPU time | 54.15 seconds |
| Started | Oct 03 04:05:34 AM UTC 24 |
| Finished | Oct 03 04:06:30 AM UTC 24 |
| Peak memory | 227752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511395644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3511395644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.530839360 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 27693346353 ps |
| CPU time | 19.57 seconds |
| Started | Oct 03 04:05:31 AM UTC 24 |
| Finished | Oct 03 04:05:52 AM UTC 24 |
| Peak memory | 227512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530839360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.530839360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.547538680 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 113532786 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 04:05:38 AM UTC 24 |
| Finished | Oct 03 04:05:42 AM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547538680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.547538680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1327678407 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 82132012 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 04:05:34 AM UTC 24 |
| Finished | Oct 03 04:05:37 AM UTC 24 |
| Peak memory | 215824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327678407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1327678407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2886057605 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5239219877 ps |
| CPU time | 6.03 seconds |
| Started | Oct 03 04:05:44 AM UTC 24 |
| Finished | Oct 03 04:05:51 AM UTC 24 |
| Peak memory | 234772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886057605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2886057605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest |
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