| T839 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2420332422 |
|
|
Oct 09 10:41:43 AM UTC 24 |
Oct 09 10:42:11 AM UTC 24 |
19467862026 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.188307061 |
|
|
Oct 09 10:42:09 AM UTC 24 |
Oct 09 10:42:12 AM UTC 24 |
38991819 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.763701099 |
|
|
Oct 09 10:42:11 AM UTC 24 |
Oct 09 10:42:13 AM UTC 24 |
81058697 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.4232259457 |
|
|
Oct 09 10:42:11 AM UTC 24 |
Oct 09 10:42:14 AM UTC 24 |
55422706 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.684458504 |
|
|
Oct 09 10:36:43 AM UTC 24 |
Oct 09 10:42:14 AM UTC 24 |
149747440156 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.810170362 |
|
|
Oct 09 10:41:58 AM UTC 24 |
Oct 09 10:42:14 AM UTC 24 |
2885492570 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.3568412876 |
|
|
Oct 09 10:42:11 AM UTC 24 |
Oct 09 10:42:17 AM UTC 24 |
1321929284 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.3335898431 |
|
|
Oct 09 10:42:14 AM UTC 24 |
Oct 09 10:42:19 AM UTC 24 |
49809145 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.697459323 |
|
|
Oct 09 10:42:15 AM UTC 24 |
Oct 09 10:42:20 AM UTC 24 |
82865059 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2810479274 |
|
|
Oct 09 10:42:25 AM UTC 24 |
Oct 09 10:42:27 AM UTC 24 |
18932243 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1901281780 |
|
|
Oct 09 10:42:09 AM UTC 24 |
Oct 09 10:42:20 AM UTC 24 |
2464104415 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.18907790 |
|
|
Oct 09 10:42:15 AM UTC 24 |
Oct 09 10:42:22 AM UTC 24 |
893765732 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3627128565 |
|
|
Oct 09 10:41:14 AM UTC 24 |
Oct 09 10:42:24 AM UTC 24 |
61736329752 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.1571723803 |
|
|
Oct 09 10:42:15 AM UTC 24 |
Oct 09 10:42:24 AM UTC 24 |
1672346462 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.971408968 |
|
|
Oct 09 10:41:59 AM UTC 24 |
Oct 09 10:42:24 AM UTC 24 |
7179231395 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3933489970 |
|
|
Oct 09 10:42:20 AM UTC 24 |
Oct 09 10:42:27 AM UTC 24 |
119999622 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.573304895 |
|
|
Oct 09 10:42:13 AM UTC 24 |
Oct 09 10:42:27 AM UTC 24 |
3910047667 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.582981166 |
|
|
Oct 09 10:40:15 AM UTC 24 |
Oct 09 10:42:29 AM UTC 24 |
14936108151 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1110397118 |
|
|
Oct 09 10:42:28 AM UTC 24 |
Oct 09 10:42:30 AM UTC 24 |
12116795 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.3370347595 |
|
|
Oct 09 10:42:28 AM UTC 24 |
Oct 09 10:42:30 AM UTC 24 |
17087650 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3118657597 |
|
|
Oct 09 10:42:29 AM UTC 24 |
Oct 09 10:42:32 AM UTC 24 |
17533556 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.196199069 |
|
|
Oct 09 10:42:31 AM UTC 24 |
Oct 09 10:42:34 AM UTC 24 |
26270355 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.3751024380 |
|
|
Oct 09 10:42:18 AM UTC 24 |
Oct 09 10:42:37 AM UTC 24 |
1835923984 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3294177208 |
|
|
Oct 09 10:41:18 AM UTC 24 |
Oct 09 10:42:37 AM UTC 24 |
8994708775 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2949960380 |
|
|
Oct 09 10:42:35 AM UTC 24 |
Oct 09 10:42:39 AM UTC 24 |
266954310 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.1301777610 |
|
|
Oct 09 10:42:28 AM UTC 24 |
Oct 09 10:42:40 AM UTC 24 |
1476570283 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1439931084 |
|
|
Oct 09 10:42:31 AM UTC 24 |
Oct 09 10:42:40 AM UTC 24 |
888723197 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.4005014603 |
|
|
Oct 09 10:42:12 AM UTC 24 |
Oct 09 10:42:43 AM UTC 24 |
13409926254 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.351430272 |
|
|
Oct 09 10:38:53 AM UTC 24 |
Oct 09 10:42:45 AM UTC 24 |
21705378549 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1788186873 |
|
|
Oct 09 10:42:33 AM UTC 24 |
Oct 09 10:42:49 AM UTC 24 |
2717289703 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2764076801 |
|
|
Oct 09 10:42:39 AM UTC 24 |
Oct 09 10:42:56 AM UTC 24 |
5119637454 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1105714338 |
|
|
Oct 09 10:42:40 AM UTC 24 |
Oct 09 10:42:58 AM UTC 24 |
3868605951 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2380476296 |
|
|
Oct 09 10:42:46 AM UTC 24 |
Oct 09 10:43:00 AM UTC 24 |
450774492 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1501501321 |
|
|
Oct 09 10:42:59 AM UTC 24 |
Oct 09 10:43:01 AM UTC 24 |
12456841 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.57847243 |
|
|
Oct 09 10:43:00 AM UTC 24 |
Oct 09 10:43:03 AM UTC 24 |
19547498 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.4133208359 |
|
|
Oct 09 10:42:38 AM UTC 24 |
Oct 09 10:43:04 AM UTC 24 |
1214758552 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.3669254167 |
|
|
Oct 09 10:40:56 AM UTC 24 |
Oct 09 10:43:05 AM UTC 24 |
31253181566 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2908013759 |
|
|
Oct 09 10:43:04 AM UTC 24 |
Oct 09 10:43:06 AM UTC 24 |
32254777 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3590965324 |
|
|
Oct 09 10:43:05 AM UTC 24 |
Oct 09 10:43:07 AM UTC 24 |
73245963 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.1518948260 |
|
|
Oct 09 10:44:18 AM UTC 24 |
Oct 09 10:44:21 AM UTC 24 |
14604965 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2695192761 |
|
|
Oct 09 10:42:44 AM UTC 24 |
Oct 09 10:43:09 AM UTC 24 |
10862773261 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.800125160 |
|
|
Oct 09 10:41:15 AM UTC 24 |
Oct 09 10:43:12 AM UTC 24 |
49845867733 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.1073388415 |
|
|
Oct 09 10:43:07 AM UTC 24 |
Oct 09 10:43:12 AM UTC 24 |
1015558368 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1266246258 |
|
|
Oct 09 10:43:07 AM UTC 24 |
Oct 09 10:43:13 AM UTC 24 |
243570657 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.1293954785 |
|
|
Oct 09 10:41:32 AM UTC 24 |
Oct 09 10:43:14 AM UTC 24 |
35272554689 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2498519776 |
|
|
Oct 09 10:43:10 AM UTC 24 |
Oct 09 10:43:14 AM UTC 24 |
147105104 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1389888487 |
|
|
Oct 09 10:43:00 AM UTC 24 |
Oct 09 10:43:15 AM UTC 24 |
9760596364 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3235972554 |
|
|
Oct 09 10:43:08 AM UTC 24 |
Oct 09 10:43:15 AM UTC 24 |
213727948 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.1112368857 |
|
|
Oct 09 10:40:35 AM UTC 24 |
Oct 09 10:43:17 AM UTC 24 |
16343090445 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.739177248 |
|
|
Oct 09 10:43:13 AM UTC 24 |
Oct 09 10:43:18 AM UTC 24 |
128678801 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2678471180 |
|
|
Oct 09 10:43:15 AM UTC 24 |
Oct 09 10:43:18 AM UTC 24 |
17066548 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.309815331 |
|
|
Oct 09 10:39:22 AM UTC 24 |
Oct 09 10:43:19 AM UTC 24 |
25215472186 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1282750930 |
|
|
Oct 09 10:43:19 AM UTC 24 |
Oct 09 10:43:21 AM UTC 24 |
63152318 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2185492642 |
|
|
Oct 09 10:43:20 AM UTC 24 |
Oct 09 10:43:22 AM UTC 24 |
15030847 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.828067526 |
|
|
Oct 09 10:42:19 AM UTC 24 |
Oct 09 10:43:23 AM UTC 24 |
7439530234 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.3303832574 |
|
|
Oct 09 10:40:14 AM UTC 24 |
Oct 09 10:43:25 AM UTC 24 |
19749825987 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1039354971 |
|
|
Oct 09 10:43:16 AM UTC 24 |
Oct 09 10:43:26 AM UTC 24 |
1779677084 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2260683420 |
|
|
Oct 09 10:43:14 AM UTC 24 |
Oct 09 10:43:26 AM UTC 24 |
1542871028 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3939627590 |
|
|
Oct 09 10:43:24 AM UTC 24 |
Oct 09 10:43:27 AM UTC 24 |
170804556 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1915099760 |
|
|
Oct 09 10:43:26 AM UTC 24 |
Oct 09 10:43:29 AM UTC 24 |
35696220 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2493442179 |
|
|
Oct 09 10:43:22 AM UTC 24 |
Oct 09 10:43:29 AM UTC 24 |
1239657511 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1641174791 |
|
|
Oct 09 10:43:13 AM UTC 24 |
Oct 09 10:43:30 AM UTC 24 |
7330126352 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.637133819 |
|
|
Oct 09 10:43:27 AM UTC 24 |
Oct 09 10:43:39 AM UTC 24 |
1899551847 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1938286412 |
|
|
Oct 09 10:43:26 AM UTC 24 |
Oct 09 10:43:40 AM UTC 24 |
613745433 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.1863035644 |
|
|
Oct 09 10:35:20 AM UTC 24 |
Oct 09 10:43:40 AM UTC 24 |
71402213732 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.3006257229 |
|
|
Oct 09 10:43:01 AM UTC 24 |
Oct 09 10:43:41 AM UTC 24 |
9328305060 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.2889717117 |
|
|
Oct 09 10:43:23 AM UTC 24 |
Oct 09 10:43:41 AM UTC 24 |
4357528371 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1008727044 |
|
|
Oct 09 10:42:41 AM UTC 24 |
Oct 09 10:43:43 AM UTC 24 |
2533945881 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2684722032 |
|
|
Oct 09 10:41:17 AM UTC 24 |
Oct 09 10:43:46 AM UTC 24 |
11049430866 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.266284007 |
|
|
Oct 09 10:43:31 AM UTC 24 |
Oct 09 10:43:49 AM UTC 24 |
1363466369 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2413161177 |
|
|
Oct 09 10:40:56 AM UTC 24 |
Oct 09 10:43:49 AM UTC 24 |
15538504889 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.3546442816 |
|
|
Oct 09 10:43:28 AM UTC 24 |
Oct 09 10:43:52 AM UTC 24 |
8183167762 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.2296193458 |
|
|
Oct 09 10:43:50 AM UTC 24 |
Oct 09 10:43:52 AM UTC 24 |
17170163 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.2069857219 |
|
|
Oct 09 10:43:50 AM UTC 24 |
Oct 09 10:43:52 AM UTC 24 |
54660027 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.4165707790 |
|
|
Oct 09 10:43:30 AM UTC 24 |
Oct 09 10:43:53 AM UTC 24 |
1910422587 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2164373495 |
|
|
Oct 09 10:43:31 AM UTC 24 |
Oct 09 10:43:55 AM UTC 24 |
15782856921 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1983550360 |
|
|
Oct 09 10:43:53 AM UTC 24 |
Oct 09 10:43:55 AM UTC 24 |
22552498 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.1475822078 |
|
|
Oct 09 10:43:40 AM UTC 24 |
Oct 09 10:43:56 AM UTC 24 |
576406121 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.59306229 |
|
|
Oct 09 10:43:54 AM UTC 24 |
Oct 09 10:43:59 AM UTC 24 |
91455986 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.395460469 |
|
|
Oct 09 10:39:35 AM UTC 24 |
Oct 09 10:44:03 AM UTC 24 |
33831339194 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2694240405 |
|
|
Oct 09 10:43:56 AM UTC 24 |
Oct 09 10:44:05 AM UTC 24 |
1944516503 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.819642639 |
|
|
Oct 09 10:43:41 AM UTC 24 |
Oct 09 10:44:06 AM UTC 24 |
1806147804 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.3506480056 |
|
|
Oct 09 10:43:56 AM UTC 24 |
Oct 09 10:44:06 AM UTC 24 |
326053704 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3420176413 |
|
|
Oct 09 10:43:53 AM UTC 24 |
Oct 09 10:44:09 AM UTC 24 |
1451977766 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.2519067628 |
|
|
Oct 09 10:44:07 AM UTC 24 |
Oct 09 10:44:12 AM UTC 24 |
42351060 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3932490674 |
|
|
Oct 09 10:43:53 AM UTC 24 |
Oct 09 10:44:13 AM UTC 24 |
2587149990 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.3992276368 |
|
|
Oct 09 10:44:05 AM UTC 24 |
Oct 09 10:44:15 AM UTC 24 |
2344529762 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.2396605087 |
|
|
Oct 09 10:44:07 AM UTC 24 |
Oct 09 10:44:16 AM UTC 24 |
459074536 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3650725666 |
|
|
Oct 09 10:43:16 AM UTC 24 |
Oct 09 10:44:18 AM UTC 24 |
7605193877 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.4074133496 |
|
|
Oct 09 10:43:56 AM UTC 24 |
Oct 09 10:44:18 AM UTC 24 |
4099415208 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1192318282 |
|
|
Oct 09 10:44:10 AM UTC 24 |
Oct 09 10:44:19 AM UTC 24 |
766041113 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2998552712 |
|
|
Oct 09 10:44:20 AM UTC 24 |
Oct 09 10:44:22 AM UTC 24 |
30511649 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.4151143029 |
|
|
Oct 09 10:44:23 AM UTC 24 |
Oct 09 10:44:25 AM UTC 24 |
62550841 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.2878711750 |
|
|
Oct 09 10:44:23 AM UTC 24 |
Oct 09 10:44:25 AM UTC 24 |
202784585 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2176856683 |
|
|
Oct 09 10:44:17 AM UTC 24 |
Oct 09 10:44:37 AM UTC 24 |
627485701 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1291449447 |
|
|
Oct 09 10:44:26 AM UTC 24 |
Oct 09 10:44:40 AM UTC 24 |
5535966994 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.1519152530 |
|
|
Oct 09 10:44:13 AM UTC 24 |
Oct 09 10:44:41 AM UTC 24 |
48696225729 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.411754499 |
|
|
Oct 09 10:44:37 AM UTC 24 |
Oct 09 10:44:41 AM UTC 24 |
107719775 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1853650750 |
|
|
Oct 09 10:44:26 AM UTC 24 |
Oct 09 10:44:42 AM UTC 24 |
1162633628 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.481394171 |
|
|
Oct 09 10:44:22 AM UTC 24 |
Oct 09 10:44:44 AM UTC 24 |
20471486237 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.1490841956 |
|
|
Oct 09 10:44:41 AM UTC 24 |
Oct 09 10:44:46 AM UTC 24 |
36296817 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3986990113 |
|
|
Oct 09 10:43:59 AM UTC 24 |
Oct 09 10:44:48 AM UTC 24 |
5685448306 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2908644591 |
|
|
Oct 09 10:43:42 AM UTC 24 |
Oct 09 10:44:50 AM UTC 24 |
6963866189 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3528433734 |
|
|
Oct 09 10:44:42 AM UTC 24 |
Oct 09 10:44:53 AM UTC 24 |
1841431725 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.4147143736 |
|
|
Oct 09 10:44:47 AM UTC 24 |
Oct 09 10:44:54 AM UTC 24 |
136213607 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.2564622493 |
|
|
Oct 09 10:44:42 AM UTC 24 |
Oct 09 10:44:56 AM UTC 24 |
3073363915 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.344473153 |
|
|
Oct 09 10:33:01 AM UTC 24 |
Oct 09 10:44:56 AM UTC 24 |
69174114774 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2773560310 |
|
|
Oct 09 10:44:56 AM UTC 24 |
Oct 09 10:44:59 AM UTC 24 |
18437427 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3330196118 |
|
|
Oct 09 10:44:57 AM UTC 24 |
Oct 09 10:45:00 AM UTC 24 |
27752981 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.577494480 |
|
|
Oct 09 10:42:46 AM UTC 24 |
Oct 09 10:45:01 AM UTC 24 |
44938471974 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2674236234 |
|
|
Oct 09 10:44:08 AM UTC 24 |
Oct 09 10:45:01 AM UTC 24 |
9998748287 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.4241991007 |
|
|
Oct 09 10:38:52 AM UTC 24 |
Oct 09 10:45:02 AM UTC 24 |
154517368481 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.3635297672 |
|
|
Oct 09 10:45:03 AM UTC 24 |
Oct 09 10:45:05 AM UTC 24 |
16116615 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1987375272 |
|
|
Oct 09 10:45:02 AM UTC 24 |
Oct 09 10:45:05 AM UTC 24 |
48672349 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.4197407216 |
|
|
Oct 09 10:45:01 AM UTC 24 |
Oct 09 10:45:05 AM UTC 24 |
700409610 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.3965976713 |
|
|
Oct 09 10:44:59 AM UTC 24 |
Oct 09 10:45:08 AM UTC 24 |
5634145554 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.678781821 |
|
|
Oct 09 10:45:03 AM UTC 24 |
Oct 09 10:45:08 AM UTC 24 |
184499966 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2826116730 |
|
|
Oct 09 10:45:09 AM UTC 24 |
Oct 09 10:45:17 AM UTC 24 |
479985276 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3064208102 |
|
|
Oct 09 10:42:23 AM UTC 24 |
Oct 09 10:45:20 AM UTC 24 |
38384641276 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.4069010755 |
|
|
Oct 09 10:45:09 AM UTC 24 |
Oct 09 10:45:21 AM UTC 24 |
1240871716 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.844547487 |
|
|
Oct 09 10:45:06 AM UTC 24 |
Oct 09 10:45:27 AM UTC 24 |
2623416135 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2608856847 |
|
|
Oct 09 10:43:41 AM UTC 24 |
Oct 09 10:45:30 AM UTC 24 |
3440681584 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1822182348 |
|
|
Oct 09 10:45:06 AM UTC 24 |
Oct 09 10:45:30 AM UTC 24 |
9944011498 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.248127294 |
|
|
Oct 09 10:42:21 AM UTC 24 |
Oct 09 10:45:31 AM UTC 24 |
22813848640 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.2211200601 |
|
|
Oct 09 10:44:54 AM UTC 24 |
Oct 09 10:45:32 AM UTC 24 |
4916401224 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3491151301 |
|
|
Oct 09 10:38:53 AM UTC 24 |
Oct 09 10:45:33 AM UTC 24 |
174577631470 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.821296144 |
|
|
Oct 09 10:45:33 AM UTC 24 |
Oct 09 10:45:35 AM UTC 24 |
45259250 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.677312866 |
|
|
Oct 09 10:43:19 AM UTC 24 |
Oct 09 10:45:36 AM UTC 24 |
7645852083 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.3054137201 |
|
|
Oct 09 10:45:34 AM UTC 24 |
Oct 09 10:45:36 AM UTC 24 |
18963665 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2097806318 |
|
|
Oct 09 10:45:37 AM UTC 24 |
Oct 09 10:45:40 AM UTC 24 |
22916235 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.1998144000 |
|
|
Oct 09 10:44:15 AM UTC 24 |
Oct 09 10:45:40 AM UTC 24 |
13382743294 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.1852986334 |
|
|
Oct 09 10:44:43 AM UTC 24 |
Oct 09 10:45:41 AM UTC 24 |
3302659129 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.4168411645 |
|
|
Oct 09 10:45:40 AM UTC 24 |
Oct 09 10:45:44 AM UTC 24 |
95782976 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1401861944 |
|
|
Oct 09 10:45:23 AM UTC 24 |
Oct 09 10:45:46 AM UTC 24 |
3590878008 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2817532094 |
|
|
Oct 09 10:45:36 AM UTC 24 |
Oct 09 10:45:47 AM UTC 24 |
17566561249 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.182221023 |
|
|
Oct 09 10:45:17 AM UTC 24 |
Oct 09 10:45:47 AM UTC 24 |
4370661863 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3916832088 |
|
|
Oct 09 10:45:45 AM UTC 24 |
Oct 09 10:45:50 AM UTC 24 |
1628841942 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.77625963 |
|
|
Oct 09 10:45:42 AM UTC 24 |
Oct 09 10:45:50 AM UTC 24 |
5148298076 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.934488129 |
|
|
Oct 09 10:45:37 AM UTC 24 |
Oct 09 10:45:50 AM UTC 24 |
848306761 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.4014555390 |
|
|
Oct 09 10:45:48 AM UTC 24 |
Oct 09 10:45:53 AM UTC 24 |
202419865 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.4258386020 |
|
|
Oct 09 10:41:35 AM UTC 24 |
Oct 09 10:45:53 AM UTC 24 |
129436901447 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2363988765 |
|
|
Oct 09 10:45:48 AM UTC 24 |
Oct 09 10:45:54 AM UTC 24 |
110274665 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2291270875 |
|
|
Oct 09 10:42:25 AM UTC 24 |
Oct 09 10:46:00 AM UTC 24 |
16009004816 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1228932529 |
|
|
Oct 09 10:45:51 AM UTC 24 |
Oct 09 10:46:03 AM UTC 24 |
3671515657 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.3275158879 |
|
|
Oct 09 10:45:47 AM UTC 24 |
Oct 09 10:46:03 AM UTC 24 |
1094535915 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3539283286 |
|
|
Oct 09 10:46:01 AM UTC 24 |
Oct 09 10:46:03 AM UTC 24 |
14682625 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.239580087 |
|
|
Oct 09 10:46:04 AM UTC 24 |
Oct 09 10:46:06 AM UTC 24 |
63701509 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1047631837 |
|
|
Oct 09 10:46:04 AM UTC 24 |
Oct 09 10:46:06 AM UTC 24 |
70512264 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.3737670638 |
|
|
Oct 09 10:45:50 AM UTC 24 |
Oct 09 10:46:09 AM UTC 24 |
5389280857 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2685550258 |
|
|
Oct 09 10:46:07 AM UTC 24 |
Oct 09 10:46:10 AM UTC 24 |
20789094 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.3632922266 |
|
|
Oct 09 10:46:08 AM UTC 24 |
Oct 09 10:46:10 AM UTC 24 |
63036576 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3717680204 |
|
|
Oct 09 10:46:10 AM UTC 24 |
Oct 09 10:46:14 AM UTC 24 |
64192226 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2442697188 |
|
|
Oct 09 10:46:11 AM UTC 24 |
Oct 09 10:46:15 AM UTC 24 |
420440363 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.701113277 |
|
|
Oct 09 10:45:51 AM UTC 24 |
Oct 09 10:46:15 AM UTC 24 |
1242239997 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1614939172 |
|
|
Oct 09 10:45:42 AM UTC 24 |
Oct 09 10:46:17 AM UTC 24 |
15853644174 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1399620282 |
|
|
Oct 09 10:42:25 AM UTC 24 |
Oct 09 10:46:18 AM UTC 24 |
40622175679 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2419132664 |
|
|
Oct 09 10:39:29 AM UTC 24 |
Oct 09 10:46:18 AM UTC 24 |
53987018191 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1197806247 |
|
|
Oct 09 10:46:11 AM UTC 24 |
Oct 09 10:46:19 AM UTC 24 |
1436925927 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.1443707745 |
|
|
Oct 09 10:42:41 AM UTC 24 |
Oct 09 10:46:20 AM UTC 24 |
70456686588 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3156409018 |
|
|
Oct 09 10:46:18 AM UTC 24 |
Oct 09 10:46:24 AM UTC 24 |
98750096 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3216948860 |
|
|
Oct 09 10:46:16 AM UTC 24 |
Oct 09 10:46:26 AM UTC 24 |
1190791460 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1573213104 |
|
|
Oct 09 10:46:19 AM UTC 24 |
Oct 09 10:46:26 AM UTC 24 |
90253553 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1291070822 |
|
|
Oct 09 10:46:27 AM UTC 24 |
Oct 09 10:46:29 AM UTC 24 |
122680008 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.1654775122 |
|
|
Oct 09 10:46:27 AM UTC 24 |
Oct 09 10:46:29 AM UTC 24 |
19946521 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2939182121 |
|
|
Oct 09 10:46:04 AM UTC 24 |
Oct 09 10:46:32 AM UTC 24 |
56241707549 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.3285146890 |
|
|
Oct 09 10:46:16 AM UTC 24 |
Oct 09 10:46:35 AM UTC 24 |
3384161266 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.3153414721 |
|
|
Oct 09 10:36:38 AM UTC 24 |
Oct 09 10:46:38 AM UTC 24 |
107227880072 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3316440051 |
|
|
Oct 09 10:42:57 AM UTC 24 |
Oct 09 10:46:40 AM UTC 24 |
268395591046 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.148691638 |
|
|
Oct 09 10:44:51 AM UTC 24 |
Oct 09 10:46:45 AM UTC 24 |
13618966600 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.4044648458 |
|
|
Oct 09 10:41:59 AM UTC 24 |
Oct 09 10:46:52 AM UTC 24 |
39823763448 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3574966025 |
|
|
Oct 09 10:45:54 AM UTC 24 |
Oct 09 10:47:05 AM UTC 24 |
71120688867 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.375366563 |
|
|
Oct 09 10:43:41 AM UTC 24 |
Oct 09 10:47:24 AM UTC 24 |
167050456513 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2340289674 |
|
|
Oct 09 10:46:18 AM UTC 24 |
Oct 09 10:47:26 AM UTC 24 |
2087551897 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.891358923 |
|
|
Oct 09 10:46:15 AM UTC 24 |
Oct 09 10:47:34 AM UTC 24 |
23916770284 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.2335996349 |
|
|
Oct 09 10:41:58 AM UTC 24 |
Oct 09 10:47:41 AM UTC 24 |
136493434710 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1811209976 |
|
|
Oct 09 10:41:59 AM UTC 24 |
Oct 09 10:48:03 AM UTC 24 |
108772434205 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1947971814 |
|
|
Oct 09 10:45:20 AM UTC 24 |
Oct 09 10:48:08 AM UTC 24 |
57473653341 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.1541765959 |
|
|
Oct 09 10:45:29 AM UTC 24 |
Oct 09 10:48:11 AM UTC 24 |
12462634566 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2712322389 |
|
|
Oct 09 10:44:53 AM UTC 24 |
Oct 09 10:48:18 AM UTC 24 |
192988168654 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.1147882661 |
|
|
Oct 09 10:39:55 AM UTC 24 |
Oct 09 10:48:23 AM UTC 24 |
179874047280 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.4256126636 |
|
|
Oct 09 10:46:21 AM UTC 24 |
Oct 09 10:48:34 AM UTC 24 |
51454572959 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.1541837153 |
|
|
Oct 09 10:33:06 AM UTC 24 |
Oct 09 10:48:40 AM UTC 24 |
1283117281396 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.103504118 |
|
|
Oct 09 10:41:35 AM UTC 24 |
Oct 09 10:48:58 AM UTC 24 |
625873418152 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.931711764 |
|
|
Oct 09 10:41:35 AM UTC 24 |
Oct 09 10:48:58 AM UTC 24 |
44885981321 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.783983556 |
|
|
Oct 09 10:45:06 AM UTC 24 |
Oct 09 10:49:04 AM UTC 24 |
27360980108 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3793772311 |
|
|
Oct 09 10:43:18 AM UTC 24 |
Oct 09 10:49:15 AM UTC 24 |
38038469047 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2303668414 |
|
|
Oct 09 10:44:49 AM UTC 24 |
Oct 09 10:49:35 AM UTC 24 |
35633098735 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1911103092 |
|
|
Oct 09 10:43:43 AM UTC 24 |
Oct 09 10:49:50 AM UTC 24 |
71124918516 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1354454490 |
|
|
Oct 09 10:40:54 AM UTC 24 |
Oct 09 10:49:59 AM UTC 24 |
135067352838 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2679584731 |
|
|
Oct 09 10:45:31 AM UTC 24 |
Oct 09 10:50:07 AM UTC 24 |
359472534645 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2755765844 |
|
|
Oct 09 10:44:14 AM UTC 24 |
Oct 09 10:50:13 AM UTC 24 |
37724964988 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.805640470 |
|
|
Oct 09 10:43:16 AM UTC 24 |
Oct 09 10:50:55 AM UTC 24 |
55185980115 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2809184031 |
|
|
Oct 09 10:42:50 AM UTC 24 |
Oct 09 10:51:11 AM UTC 24 |
184311682276 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.2440244025 |
|
|
Oct 09 10:45:32 AM UTC 24 |
Oct 09 10:51:54 AM UTC 24 |
122452557469 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3247170691 |
|
|
Oct 09 10:40:37 AM UTC 24 |
Oct 09 10:51:54 AM UTC 24 |
117392748693 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.2577550354 |
|
|
Oct 09 10:46:20 AM UTC 24 |
Oct 09 10:52:05 AM UTC 24 |
187897338309 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2834424458 |
|
|
Oct 09 10:41:51 AM UTC 24 |
Oct 09 10:52:08 AM UTC 24 |
78985522193 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.464716155 |
|
|
Oct 09 10:45:31 AM UTC 24 |
Oct 09 10:52:57 AM UTC 24 |
175801209979 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.1614824673 |
|
|
Oct 09 10:38:34 AM UTC 24 |
Oct 09 10:53:49 AM UTC 24 |
96539427269 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.197277454 |
|
|
Oct 09 10:45:54 AM UTC 24 |
Oct 09 10:53:55 AM UTC 24 |
199251520643 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1030515052 |
|
|
Oct 09 10:40:57 AM UTC 24 |
Oct 09 10:54:43 AM UTC 24 |
74270710168 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1545637860 |
|
|
Oct 09 10:46:25 AM UTC 24 |
Oct 09 10:58:10 AM UTC 24 |
76647037816 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.722601860 |
|
|
Oct 09 10:45:54 AM UTC 24 |
Oct 09 10:58:11 AM UTC 24 |
69040156940 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1898706835 |
|
|
Oct 09 10:43:48 AM UTC 24 |
Oct 09 11:02:57 AM UTC 24 |
118768753809 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3195415379 |
|
|
Oct 09 10:45:55 AM UTC 24 |
Oct 09 11:09:45 AM UTC 24 |
167511185202 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2892458619 |
|
|
Oct 09 02:33:41 PM UTC 24 |
Oct 09 02:33:44 PM UTC 24 |
97678770 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2358573090 |
|
|
Oct 09 02:33:42 PM UTC 24 |
Oct 09 02:33:45 PM UTC 24 |
30277267 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3522117210 |
|
|
Oct 09 02:33:41 PM UTC 24 |
Oct 09 02:33:45 PM UTC 24 |
576583247 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3304109883 |
|
|
Oct 09 02:33:45 PM UTC 24 |
Oct 09 02:33:48 PM UTC 24 |
25204516 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2635715904 |
|
|
Oct 09 02:33:45 PM UTC 24 |
Oct 09 02:33:48 PM UTC 24 |
131052962 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2872656325 |
|
|
Oct 09 02:33:46 PM UTC 24 |
Oct 09 02:33:50 PM UTC 24 |
84788300 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2701255597 |
|
|
Oct 09 02:33:51 PM UTC 24 |
Oct 09 02:33:54 PM UTC 24 |
35398872 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3317838359 |
|
|
Oct 09 02:33:50 PM UTC 24 |
Oct 09 02:33:54 PM UTC 24 |
50565270 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.742860877 |
|
|
Oct 09 02:33:49 PM UTC 24 |
Oct 09 02:33:55 PM UTC 24 |
243224383 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2766997704 |
|
|
Oct 09 02:33:52 PM UTC 24 |
Oct 09 02:33:55 PM UTC 24 |
37107193 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.125577435 |
|
|
Oct 09 02:33:54 PM UTC 24 |
Oct 09 02:33:56 PM UTC 24 |
30563299 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.3013928389 |
|
|
Oct 09 02:33:53 PM UTC 24 |
Oct 09 02:33:57 PM UTC 24 |
89876822 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3699106551 |
|
|
Oct 09 02:33:51 PM UTC 24 |
Oct 09 02:33:58 PM UTC 24 |
78717731 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3893695967 |
|
|
Oct 09 02:33:56 PM UTC 24 |
Oct 09 02:33:59 PM UTC 24 |
24475429 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1205041980 |
|
|
Oct 09 02:33:56 PM UTC 24 |
Oct 09 02:33:59 PM UTC 24 |
29025889 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.4056645568 |
|
|
Oct 09 02:33:57 PM UTC 24 |
Oct 09 02:34:00 PM UTC 24 |
123585307 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2815030702 |
|
|
Oct 09 02:33:46 PM UTC 24 |
Oct 09 02:34:00 PM UTC 24 |
2529224526 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2719781673 |
|
|
Oct 09 02:33:55 PM UTC 24 |
Oct 09 02:34:00 PM UTC 24 |
120917400 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3885845948 |
|
|
Oct 09 02:33:56 PM UTC 24 |
Oct 09 02:34:00 PM UTC 24 |
153445296 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3660041757 |
|
|
Oct 09 02:33:58 PM UTC 24 |
Oct 09 02:34:01 PM UTC 24 |
124949866 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.271960838 |
|
|
Oct 09 02:33:55 PM UTC 24 |
Oct 09 02:34:01 PM UTC 24 |
48659670 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.164472141 |
|
|
Oct 09 02:34:00 PM UTC 24 |
Oct 09 02:34:03 PM UTC 24 |
36466959 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.519269641 |
|
|
Oct 09 02:34:02 PM UTC 24 |
Oct 09 02:34:04 PM UTC 24 |
16846515 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3624741951 |
|
|
Oct 09 02:34:00 PM UTC 24 |
Oct 09 02:34:04 PM UTC 24 |
448418210 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.4153683562 |
|
|
Oct 09 02:34:02 PM UTC 24 |
Oct 09 02:34:04 PM UTC 24 |
11667006 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.561279737 |
|
|
Oct 09 02:33:56 PM UTC 24 |
Oct 09 02:34:06 PM UTC 24 |
1456698458 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1439324511 |
|
|
Oct 09 02:33:49 PM UTC 24 |
Oct 09 02:34:06 PM UTC 24 |
1794860520 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2292554645 |
|
|
Oct 09 02:34:03 PM UTC 24 |
Oct 09 02:34:06 PM UTC 24 |
39462152 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1815852568 |
|
|
Oct 09 02:34:03 PM UTC 24 |
Oct 09 02:34:06 PM UTC 24 |
40839566 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1853847896 |
|
|
Oct 09 02:34:02 PM UTC 24 |
Oct 09 02:34:06 PM UTC 24 |
91894110 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2801286353 |
|
|
Oct 09 02:34:02 PM UTC 24 |
Oct 09 02:34:07 PM UTC 24 |
99249322 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2777047230 |
|
|
Oct 09 02:33:55 PM UTC 24 |
Oct 09 02:34:08 PM UTC 24 |
408363857 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.4261082550 |
|
|
Oct 09 02:34:04 PM UTC 24 |
Oct 09 02:34:08 PM UTC 24 |
169054272 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.206151200 |
|
|
Oct 09 02:33:41 PM UTC 24 |
Oct 09 02:34:08 PM UTC 24 |
4361193602 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2590089886 |
|
|
Oct 09 02:34:02 PM UTC 24 |
Oct 09 02:34:08 PM UTC 24 |
56159608 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.624020939 |
|
|
Oct 09 02:34:07 PM UTC 24 |
Oct 09 02:34:10 PM UTC 24 |
43477526 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.4193116468 |
|
|
Oct 09 02:34:08 PM UTC 24 |
Oct 09 02:34:11 PM UTC 24 |
37785912 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1271600583 |
|
|
Oct 09 02:34:08 PM UTC 24 |
Oct 09 02:34:11 PM UTC 24 |
77041428 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2791177904 |
|
|
Oct 09 02:34:02 PM UTC 24 |
Oct 09 02:34:11 PM UTC 24 |
468650590 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3382970812 |
|
|
Oct 09 02:33:51 PM UTC 24 |
Oct 09 02:34:11 PM UTC 24 |
1220185934 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2695697727 |
|
|
Oct 09 02:34:08 PM UTC 24 |
Oct 09 02:34:13 PM UTC 24 |
59121168 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.906768157 |
|
|
Oct 09 02:34:07 PM UTC 24 |
Oct 09 02:34:14 PM UTC 24 |
221973850 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3069671529 |
|
|
Oct 09 02:34:20 PM UTC 24 |
Oct 09 02:34:23 PM UTC 24 |
189388692 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2159171779 |
|
|
Oct 09 02:34:07 PM UTC 24 |
Oct 09 02:34:14 PM UTC 24 |
55425596 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1088624337 |
|
|
Oct 09 02:34:02 PM UTC 24 |
Oct 09 02:34:14 PM UTC 24 |
442884457 ps |