| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.74 | 98.65 | 96.80 | 99.01 | 89.36 | 98.51 | 95.57 | 99.26 |
| T177 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.200193580 | Oct 09 02:34:00 PM UTC 24 | Oct 09 02:34:15 PM UTC 24 | 931607759 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2666806915 | Oct 09 02:34:09 PM UTC 24 | Oct 09 02:34:15 PM UTC 24 | 411679657 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.1392096506 | Oct 09 02:34:07 PM UTC 24 | Oct 09 02:34:15 PM UTC 24 | 255928416 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1147055176 | Oct 09 02:34:12 PM UTC 24 | Oct 09 02:34:15 PM UTC 24 | 264265355 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.87812138 | Oct 09 02:34:13 PM UTC 24 | Oct 09 02:34:15 PM UTC 24 | 14878412 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1004349732 | Oct 09 02:34:06 PM UTC 24 | Oct 09 02:34:16 PM UTC 24 | 642475043 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3458431960 | Oct 09 02:34:12 PM UTC 24 | Oct 09 02:34:17 PM UTC 24 | 124129753 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1997251338 | Oct 09 02:34:15 PM UTC 24 | Oct 09 02:34:18 PM UTC 24 | 20917042 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.531381407 | Oct 09 02:34:16 PM UTC 24 | Oct 09 02:34:18 PM UTC 24 | 19482331 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1844860315 | Oct 09 02:34:16 PM UTC 24 | Oct 09 02:34:19 PM UTC 24 | 41839265 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1749977820 | Oct 09 02:34:15 PM UTC 24 | Oct 09 02:34:20 PM UTC 24 | 106012051 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3990090849 | Oct 09 02:34:15 PM UTC 24 | Oct 09 02:34:20 PM UTC 24 | 152359457 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3242131228 | Oct 09 02:34:15 PM UTC 24 | Oct 09 02:34:20 PM UTC 24 | 2152703170 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3547946090 | Oct 09 02:34:12 PM UTC 24 | Oct 09 02:34:20 PM UTC 24 | 587667143 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3263983668 | Oct 09 02:34:16 PM UTC 24 | Oct 09 02:34:21 PM UTC 24 | 148182351 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.203940745 | Oct 09 02:34:19 PM UTC 24 | Oct 09 02:34:21 PM UTC 24 | 17924092 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.403170755 | Oct 09 02:34:16 PM UTC 24 | Oct 09 02:34:22 PM UTC 24 | 718186174 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.1548772666 | Oct 09 02:34:19 PM UTC 24 | Oct 09 02:34:23 PM UTC 24 | 55338190 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1364997361 | Oct 09 02:34:16 PM UTC 24 | Oct 09 02:34:23 PM UTC 24 | 108182463 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3500133873 | Oct 09 02:34:07 PM UTC 24 | Oct 09 02:34:23 PM UTC 24 | 549751248 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1581500011 | Oct 09 02:34:22 PM UTC 24 | Oct 09 02:34:24 PM UTC 24 | 23466016 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1336691915 | Oct 09 02:34:20 PM UTC 24 | Oct 09 02:34:25 PM UTC 24 | 743394142 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3209127994 | Oct 09 02:34:22 PM UTC 24 | Oct 09 02:34:25 PM UTC 24 | 196945755 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2317811437 | Oct 09 02:34:22 PM UTC 24 | Oct 09 02:34:25 PM UTC 24 | 66894790 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3591053621 | Oct 09 02:34:22 PM UTC 24 | Oct 09 02:34:25 PM UTC 24 | 26547361 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.727774605 | Oct 09 02:34:21 PM UTC 24 | Oct 09 02:34:26 PM UTC 24 | 357599299 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1047472534 | Oct 09 02:34:23 PM UTC 24 | Oct 09 02:34:26 PM UTC 24 | 82919455 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4017720723 | Oct 09 02:34:24 PM UTC 24 | Oct 09 02:34:27 PM UTC 24 | 34643305 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2741255041 | Oct 09 02:34:26 PM UTC 24 | Oct 09 02:34:28 PM UTC 24 | 27118656 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3197782062 | Oct 09 02:34:24 PM UTC 24 | Oct 09 02:34:30 PM UTC 24 | 450464227 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3495138852 | Oct 09 02:34:11 PM UTC 24 | Oct 09 02:34:30 PM UTC 24 | 1219863853 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3648401735 | Oct 09 02:34:27 PM UTC 24 | Oct 09 02:34:30 PM UTC 24 | 179299938 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1089231039 | Oct 09 02:34:28 PM UTC 24 | Oct 09 02:34:31 PM UTC 24 | 42956266 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3329381264 | Oct 09 02:34:25 PM UTC 24 | Oct 09 02:34:30 PM UTC 24 | 60252180 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2403641366 | Oct 09 02:34:25 PM UTC 24 | Oct 09 02:34:32 PM UTC 24 | 64710138 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3253547887 | Oct 09 02:34:24 PM UTC 24 | Oct 09 02:34:32 PM UTC 24 | 561541932 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.34596176 | Oct 09 02:34:27 PM UTC 24 | Oct 09 02:34:32 PM UTC 24 | 46867493 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3514867305 | Oct 09 02:34:27 PM UTC 24 | Oct 09 02:34:32 PM UTC 24 | 96425117 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2137852679 | Oct 09 02:34:27 PM UTC 24 | Oct 09 02:34:32 PM UTC 24 | 238836560 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.911998468 | Oct 09 02:33:55 PM UTC 24 | Oct 09 02:34:32 PM UTC 24 | 10021229493 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2094510945 | Oct 09 02:34:31 PM UTC 24 | Oct 09 02:34:33 PM UTC 24 | 68504596 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2924770080 | Oct 09 02:34:32 PM UTC 24 | Oct 09 02:34:34 PM UTC 24 | 17679062 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3270453809 | Oct 09 02:34:31 PM UTC 24 | Oct 09 02:34:34 PM UTC 24 | 299107450 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.836884400 | Oct 09 02:34:31 PM UTC 24 | Oct 09 02:34:34 PM UTC 24 | 214432118 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3529256192 | Oct 09 02:34:18 PM UTC 24 | Oct 09 02:34:35 PM UTC 24 | 405963790 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2623318008 | Oct 09 02:34:35 PM UTC 24 | Oct 09 02:34:37 PM UTC 24 | 15327092 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2677292311 | Oct 09 02:34:10 PM UTC 24 | Oct 09 02:34:37 PM UTC 24 | 5026902303 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1029788693 | Oct 09 02:34:34 PM UTC 24 | Oct 09 02:34:38 PM UTC 24 | 130824120 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2837910164 | Oct 09 02:34:34 PM UTC 24 | Oct 09 02:34:38 PM UTC 24 | 147680936 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2343963026 | Oct 09 02:34:32 PM UTC 24 | Oct 09 02:34:38 PM UTC 24 | 317782203 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1559179370 | Oct 09 02:34:33 PM UTC 24 | Oct 09 02:34:38 PM UTC 24 | 117016823 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3192235838 | Oct 09 02:34:16 PM UTC 24 | Oct 09 02:34:38 PM UTC 24 | 5557364605 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1031700871 | Oct 09 02:34:34 PM UTC 24 | Oct 09 02:34:39 PM UTC 24 | 626462949 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.2412128138 | Oct 09 02:34:35 PM UTC 24 | Oct 09 02:34:39 PM UTC 24 | 86737604 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.432419290 | Oct 09 02:34:35 PM UTC 24 | Oct 09 02:34:39 PM UTC 24 | 55905795 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.2570491897 | Oct 09 02:34:26 PM UTC 24 | Oct 09 02:34:40 PM UTC 24 | 206832596 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3376779904 | Oct 09 02:34:12 PM UTC 24 | Oct 09 02:34:41 PM UTC 24 | 3819009134 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.1331037196 | Oct 09 02:34:39 PM UTC 24 | Oct 09 02:34:41 PM UTC 24 | 132380887 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.3097809861 | Oct 09 02:34:40 PM UTC 24 | Oct 09 02:34:42 PM UTC 24 | 23276378 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2645210380 | Oct 09 02:34:35 PM UTC 24 | Oct 09 02:34:42 PM UTC 24 | 57576870 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1340092782 | Oct 09 02:34:39 PM UTC 24 | Oct 09 02:34:42 PM UTC 24 | 69374958 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.170134485 | Oct 09 02:34:06 PM UTC 24 | Oct 09 02:34:42 PM UTC 24 | 3695463424 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.1524422122 | Oct 09 02:34:21 PM UTC 24 | Oct 09 02:34:42 PM UTC 24 | 2763850760 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.437131503 | Oct 09 02:34:36 PM UTC 24 | Oct 09 02:34:43 PM UTC 24 | 161010183 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1940515088 | Oct 09 02:34:34 PM UTC 24 | Oct 09 02:34:43 PM UTC 24 | 3059682153 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.314476210 | Oct 09 02:34:39 PM UTC 24 | Oct 09 02:34:44 PM UTC 24 | 286527320 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3327164088 | Oct 09 02:34:42 PM UTC 24 | Oct 09 02:34:44 PM UTC 24 | 25883737 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1133135485 | Oct 09 02:34:41 PM UTC 24 | Oct 09 02:34:45 PM UTC 24 | 60336928 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2039093407 | Oct 09 02:34:39 PM UTC 24 | Oct 09 02:34:45 PM UTC 24 | 524398051 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1024781961 | Oct 09 02:34:41 PM UTC 24 | Oct 09 02:34:45 PM UTC 24 | 441649875 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.2632555038 | Oct 09 02:34:27 PM UTC 24 | Oct 09 02:34:46 PM UTC 24 | 2115330217 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.528938097 | Oct 09 02:34:41 PM UTC 24 | Oct 09 02:34:46 PM UTC 24 | 249626217 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2586082253 | Oct 09 02:34:39 PM UTC 24 | Oct 09 02:34:47 PM UTC 24 | 4240152947 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2032885149 | Oct 09 02:34:38 PM UTC 24 | Oct 09 02:34:48 PM UTC 24 | 1682983464 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1907878012 | Oct 09 02:34:44 PM UTC 24 | Oct 09 02:34:48 PM UTC 24 | 101766729 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.451023331 | Oct 09 02:34:44 PM UTC 24 | Oct 09 02:34:48 PM UTC 24 | 53691843 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.3268539794 | Oct 09 02:34:32 PM UTC 24 | Oct 09 02:34:48 PM UTC 24 | 428823276 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.740171691 | Oct 09 02:34:46 PM UTC 24 | Oct 09 02:34:48 PM UTC 24 | 11983546 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.828590886 | Oct 09 02:34:44 PM UTC 24 | Oct 09 02:34:49 PM UTC 24 | 108025665 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.205199908 | Oct 09 02:34:46 PM UTC 24 | Oct 09 02:34:50 PM UTC 24 | 210359773 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1840832700 | Oct 09 02:34:44 PM UTC 24 | Oct 09 02:34:50 PM UTC 24 | 233479254 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.370792720 | Oct 09 02:34:42 PM UTC 24 | Oct 09 02:34:50 PM UTC 24 | 303936260 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2762979736 | Oct 09 02:34:48 PM UTC 24 | Oct 09 02:34:50 PM UTC 24 | 18954010 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.86421612 | Oct 09 02:34:48 PM UTC 24 | Oct 09 02:34:51 PM UTC 24 | 104779538 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.21890653 | Oct 09 02:34:46 PM UTC 24 | Oct 09 02:34:51 PM UTC 24 | 441537841 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.432039413 | Oct 09 02:34:46 PM UTC 24 | Oct 09 02:34:51 PM UTC 24 | 878068426 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2813325347 | Oct 09 02:34:24 PM UTC 24 | Oct 09 02:34:52 PM UTC 24 | 1976715073 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.4153981161 | Oct 09 02:34:50 PM UTC 24 | Oct 09 02:34:52 PM UTC 24 | 19510540 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.2725060371 | Oct 09 02:34:46 PM UTC 24 | Oct 09 02:34:53 PM UTC 24 | 70195782 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3867252318 | Oct 09 02:34:48 PM UTC 24 | Oct 09 02:34:53 PM UTC 24 | 271827560 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3236684258 | Oct 09 02:34:51 PM UTC 24 | Oct 09 02:34:54 PM UTC 24 | 63148811 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.36126164 | Oct 09 02:34:50 PM UTC 24 | Oct 09 02:34:54 PM UTC 24 | 206368274 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3049167777 | Oct 09 02:34:50 PM UTC 24 | Oct 09 02:34:54 PM UTC 24 | 92327636 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3410979656 | Oct 09 02:34:52 PM UTC 24 | Oct 09 02:34:54 PM UTC 24 | 37522366 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2365323913 | Oct 09 02:34:50 PM UTC 24 | Oct 09 02:34:54 PM UTC 24 | 79816070 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.1485529963 | Oct 09 02:34:52 PM UTC 24 | Oct 09 02:34:54 PM UTC 24 | 47688506 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.4259651262 | Oct 09 02:34:52 PM UTC 24 | Oct 09 02:34:54 PM UTC 24 | 17515896 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.74877488 | Oct 09 02:34:52 PM UTC 24 | Oct 09 02:34:54 PM UTC 24 | 18600702 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.373189656 | Oct 09 02:34:52 PM UTC 24 | Oct 09 02:34:55 PM UTC 24 | 17231758 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.763151372 | Oct 09 02:34:52 PM UTC 24 | Oct 09 02:34:55 PM UTC 24 | 15248204 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.585789433 | Oct 09 02:34:50 PM UTC 24 | Oct 09 02:34:55 PM UTC 24 | 36994829 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2378414652 | Oct 09 02:34:54 PM UTC 24 | Oct 09 02:34:56 PM UTC 24 | 21096458 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3875479986 | Oct 09 02:34:54 PM UTC 24 | Oct 09 02:34:57 PM UTC 24 | 50478386 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1865753238 | Oct 09 02:34:54 PM UTC 24 | Oct 09 02:34:57 PM UTC 24 | 32683047 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.1319184236 | Oct 09 02:34:54 PM UTC 24 | Oct 09 02:34:57 PM UTC 24 | 53226038 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.34333150 | Oct 09 02:34:54 PM UTC 24 | Oct 09 02:34:57 PM UTC 24 | 17477965 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3348650783 | Oct 09 02:34:58 PM UTC 24 | Oct 09 02:35:00 PM UTC 24 | 22913133 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.30529400 | Oct 09 02:34:58 PM UTC 24 | Oct 09 02:35:00 PM UTC 24 | 16028395 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1799311847 | Oct 09 02:34:58 PM UTC 24 | Oct 09 02:35:00 PM UTC 24 | 31682213 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.53194217 | Oct 09 02:34:58 PM UTC 24 | Oct 09 02:35:00 PM UTC 24 | 48079471 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.406375021 | Oct 09 02:34:58 PM UTC 24 | Oct 09 02:35:00 PM UTC 24 | 24721190 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1319485947 | Oct 09 02:34:58 PM UTC 24 | Oct 09 02:35:00 PM UTC 24 | 30643589 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3683538833 | Oct 09 02:34:58 PM UTC 24 | Oct 09 02:35:00 PM UTC 24 | 43561490 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3098681853 | Oct 09 02:34:59 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 16866680 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1472306104 | Oct 09 02:34:58 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 39846492 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.2819623744 | Oct 09 02:34:50 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 1516400212 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.1105591118 | Oct 09 02:34:59 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 30757322 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3357420545 | Oct 09 02:34:59 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 13332293 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2733982356 | Oct 09 02:34:59 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 33845675 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2152506591 | Oct 09 02:34:59 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 31140607 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1065094802 | Oct 09 02:34:59 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 17426123 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.4154191003 | Oct 09 02:34:59 PM UTC 24 | Oct 09 02:35:01 PM UTC 24 | 19426015 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.883704276 | Oct 09 02:34:39 PM UTC 24 | Oct 09 02:35:02 PM UTC 24 | 840514161 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.4102938580 | Oct 09 02:34:42 PM UTC 24 | Oct 09 02:35:02 PM UTC 24 | 980559574 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1972283588 | Oct 09 02:34:44 PM UTC 24 | Oct 09 02:35:02 PM UTC 24 | 560378532 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1244144375 | Oct 09 02:35:03 PM UTC 24 | Oct 09 02:35:05 PM UTC 24 | 50738615 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.221349405 | Oct 09 02:35:03 PM UTC 24 | Oct 09 02:35:05 PM UTC 24 | 15625870 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2874068546 | Oct 09 02:35:03 PM UTC 24 | Oct 09 02:35:05 PM UTC 24 | 185966149 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2634243768 | Oct 09 02:35:03 PM UTC 24 | Oct 09 02:35:05 PM UTC 24 | 34602678 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.829773288 | Oct 09 02:34:47 PM UTC 24 | Oct 09 02:35:08 PM UTC 24 | 3270387223 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.1533585510 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 368588087 ps |
| CPU time | 1.6 seconds |
| Started | Oct 09 10:23:50 AM UTC 24 |
| Finished | Oct 09 10:23:53 AM UTC 24 |
| Peak memory | 227008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533585510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1533585510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2049650109 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1370666291 ps |
| CPU time | 10.2 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:24:04 AM UTC 24 |
| Peak memory | 231192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049650109 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.2049650109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.382047291 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4859908584 ps |
| CPU time | 66.27 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:25:03 AM UTC 24 |
| Peak memory | 261672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382047291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.382047291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.3957504882 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 20043221062 ps |
| CPU time | 191.08 seconds |
| Started | Oct 09 10:26:30 AM UTC 24 |
| Finished | Oct 09 10:29:44 AM UTC 24 |
| Peak memory | 282124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957504882 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.3957504882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.1487823745 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6689811753 ps |
| CPU time | 141.9 seconds |
| Started | Oct 09 10:24:24 AM UTC 24 |
| Finished | Oct 09 10:26:49 AM UTC 24 |
| Peak memory | 278028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487823745 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.1487823745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.94344404 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 16608588580 ps |
| CPU time | 15.43 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:24:09 AM UTC 24 |
| Peak memory | 234788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94344404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.94344404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1454963593 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5630359002 ps |
| CPU time | 9.03 seconds |
| Started | Oct 09 10:23:48 AM UTC 24 |
| Finished | Oct 09 10:23:59 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454963593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1454963593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.206151200 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4361193602 ps |
| CPU time | 25.15 seconds |
| Started | Oct 09 02:33:41 PM UTC 24 |
| Finished | Oct 09 02:34:08 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206151200 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.206151200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3350990662 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 24282195560 ps |
| CPU time | 177.34 seconds |
| Started | Oct 09 10:25:12 AM UTC 24 |
| Finished | Oct 09 10:28:13 AM UTC 24 |
| Peak memory | 267784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350990662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.3350990662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1086010174 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15642534 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 226764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086010174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1086010174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.221750228 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 69642985150 ps |
| CPU time | 399.21 seconds |
| Started | Oct 09 10:25:15 AM UTC 24 |
| Finished | Oct 09 10:32:00 AM UTC 24 |
| Peak memory | 278032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221750228 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.221750228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3131741145 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 382251758 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 10:23:53 AM UTC 24 |
| Finished | Oct 09 10:23:56 AM UTC 24 |
| Peak memory | 257076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131741145 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3131741145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.493498850 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4613153542 ps |
| CPU time | 118.43 seconds |
| Started | Oct 09 10:23:59 AM UTC 24 |
| Finished | Oct 09 10:26:00 AM UTC 24 |
| Peak memory | 278020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493498850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.493498850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2194294787 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 25422385498 ps |
| CPU time | 247.92 seconds |
| Started | Oct 09 10:24:40 AM UTC 24 |
| Finished | Oct 09 10:28:52 AM UTC 24 |
| Peak memory | 278040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194294787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2194294787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3699106551 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 78717731 ps |
| CPU time | 5.83 seconds |
| Started | Oct 09 02:33:51 PM UTC 24 |
| Finished | Oct 09 02:33:58 PM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699106551 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3699106551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.250414051 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 15884831886 ps |
| CPU time | 44.81 seconds |
| Started | Oct 09 10:27:34 AM UTC 24 |
| Finished | Oct 09 10:28:21 AM UTC 24 |
| Peak memory | 263908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250414051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.250414051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3112972253 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6766174195 ps |
| CPU time | 31.8 seconds |
| Started | Oct 09 10:23:57 AM UTC 24 |
| Finished | Oct 09 10:24:31 AM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112972253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.3112972253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3259254278 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 18671414682 ps |
| CPU time | 305.24 seconds |
| Started | Oct 09 10:24:01 AM UTC 24 |
| Finished | Oct 09 10:29:10 AM UTC 24 |
| Peak memory | 278024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259254278 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.3259254278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2955036950 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 87873724758 ps |
| CPU time | 711.2 seconds |
| Started | Oct 09 10:25:45 AM UTC 24 |
| Finished | Oct 09 10:37:45 AM UTC 24 |
| Peak memory | 278036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955036950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2955036950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.117063626 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 62498919058 ps |
| CPU time | 197.05 seconds |
| Started | Oct 09 10:24:39 AM UTC 24 |
| Finished | Oct 09 10:27:59 AM UTC 24 |
| Peak memory | 261668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117063626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.117063626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1439324511 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1794860520 ps |
| CPU time | 15.59 seconds |
| Started | Oct 09 02:33:49 PM UTC 24 |
| Finished | Oct 09 02:34:06 PM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439324511 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.1439324511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.958016547 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 30955374596 ps |
| CPU time | 349.76 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:29:50 AM UTC 24 |
| Peak memory | 265680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958016547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.958016547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.4196208349 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 118003925096 ps |
| CPU time | 394.18 seconds |
| Started | Oct 09 10:31:35 AM UTC 24 |
| Finished | Oct 09 10:38:15 AM UTC 24 |
| Peak memory | 280212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196208349 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.4196208349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3798308382 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 38130537689 ps |
| CPU time | 195.1 seconds |
| Started | Oct 09 10:26:28 AM UTC 24 |
| Finished | Oct 09 10:29:46 AM UTC 24 |
| Peak memory | 278028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798308382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.3798308382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2376529143 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 10886822422 ps |
| CPU time | 191.61 seconds |
| Started | Oct 09 10:24:22 AM UTC 24 |
| Finished | Oct 09 10:27:37 AM UTC 24 |
| Peak memory | 284100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376529143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.2376529143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3047228291 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2539368257 ps |
| CPU time | 30.12 seconds |
| Started | Oct 09 10:24:06 AM UTC 24 |
| Finished | Oct 09 10:24:38 AM UTC 24 |
| Peak memory | 231524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047228291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3047228291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2164768956 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 17997811219 ps |
| CPU time | 67.74 seconds |
| Started | Oct 09 10:23:59 AM UTC 24 |
| Finished | Oct 09 10:25:09 AM UTC 24 |
| Peak memory | 267672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164768956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2164768956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3195415379 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 167511185202 ps |
| CPU time | 1412.43 seconds |
| Started | Oct 09 10:45:55 AM UTC 24 |
| Finished | Oct 09 11:09:45 AM UTC 24 |
| Peak memory | 316844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195415379 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.3195415379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.3926764500 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 33209769362 ps |
| CPU time | 208.12 seconds |
| Started | Oct 09 10:29:28 AM UTC 24 |
| Finished | Oct 09 10:33:00 AM UTC 24 |
| Peak memory | 284120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926764500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3926764500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.3377264567 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 26556033 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 10:23:53 AM UTC 24 |
| Finished | Oct 09 10:23:55 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377264567 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3377264567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3815281016 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 101712124725 ps |
| CPU time | 335.97 seconds |
| Started | Oct 09 10:24:20 AM UTC 24 |
| Finished | Oct 09 10:30:01 AM UTC 24 |
| Peak memory | 265628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815281016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3815281016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.2522295999 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 124127833 ps |
| CPU time | 8.23 seconds |
| Started | Oct 09 10:24:16 AM UTC 24 |
| Finished | Oct 09 10:24:25 AM UTC 24 |
| Peak memory | 249044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522295999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2522295999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3376779904 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3819009134 ps |
| CPU time | 27.61 seconds |
| Started | Oct 09 02:34:12 PM UTC 24 |
| Finished | Oct 09 02:34:41 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376779904 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.3376779904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2608856847 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3440681584 ps |
| CPU time | 106.22 seconds |
| Started | Oct 09 10:43:41 AM UTC 24 |
| Finished | Oct 09 10:45:30 AM UTC 24 |
| Peak memory | 273676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608856847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.2608856847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.989382741 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 37785389594 ps |
| CPU time | 345.57 seconds |
| Started | Oct 09 10:27:01 AM UTC 24 |
| Finished | Oct 09 10:32:51 AM UTC 24 |
| Peak memory | 273928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989382741 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.989382741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1898706835 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 118768753809 ps |
| CPU time | 1135.93 seconds |
| Started | Oct 09 10:43:48 AM UTC 24 |
| Finished | Oct 09 11:02:57 AM UTC 24 |
| Peak memory | 296324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898706835 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.1898706835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2403641366 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 64710138 ps |
| CPU time | 5.71 seconds |
| Started | Oct 09 02:34:25 PM UTC 24 |
| Finished | Oct 09 02:34:32 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403641366 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.2403641366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1024521573 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2812083318 ps |
| CPU time | 30.7 seconds |
| Started | Oct 09 10:29:22 AM UTC 24 |
| Finished | Oct 09 10:29:54 AM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024521573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1024521573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1025584639 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2744624011 ps |
| CPU time | 60.71 seconds |
| Started | Oct 09 10:29:57 AM UTC 24 |
| Finished | Oct 09 10:30:59 AM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025584639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1025584639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3045977280 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 55635041037 ps |
| CPU time | 292.18 seconds |
| Started | Oct 09 10:32:39 AM UTC 24 |
| Finished | Oct 09 10:37:36 AM UTC 24 |
| Peak memory | 261604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045977280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.3045977280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.3669254167 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 31253181566 ps |
| CPU time | 127.37 seconds |
| Started | Oct 09 10:40:56 AM UTC 24 |
| Finished | Oct 09 10:43:05 AM UTC 24 |
| Peak memory | 283972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669254167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3669254167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.4102938580 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 980559574 ps |
| CPU time | 18.53 seconds |
| Started | Oct 09 02:34:42 PM UTC 24 |
| Finished | Oct 09 02:35:02 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102938580 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.4102938580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.1966224593 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 67933505733 ps |
| CPU time | 294.24 seconds |
| Started | Oct 09 10:23:53 AM UTC 24 |
| Finished | Oct 09 10:28:52 AM UTC 24 |
| Peak memory | 265672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966224593 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.1966224593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.1383221038 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2110448513 ps |
| CPU time | 20.32 seconds |
| Started | Oct 09 10:31:55 AM UTC 24 |
| Finished | Oct 09 10:32:17 AM UTC 24 |
| Peak memory | 234704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383221038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1383221038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.1541837153 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 1283117281396 ps |
| CPU time | 923.76 seconds |
| Started | Oct 09 10:33:06 AM UTC 24 |
| Finished | Oct 09 10:48:40 AM UTC 24 |
| Peak memory | 280208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541837153 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.1541837153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.4257672001 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 44334823987 ps |
| CPU time | 326.93 seconds |
| Started | Oct 09 10:34:15 AM UTC 24 |
| Finished | Oct 09 10:39:46 AM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257672001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4257672001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2913160075 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 7956088107 ps |
| CPU time | 96.68 seconds |
| Started | Oct 09 10:24:37 AM UTC 24 |
| Finished | Oct 09 10:26:15 AM UTC 24 |
| Peak memory | 263556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913160075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.2913160075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1970397436 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 65393519 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:23:47 AM UTC 24 |
| Finished | Oct 09 10:23:50 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970397436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1970397436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2343963026 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 317782203 ps |
| CPU time | 5 seconds |
| Started | Oct 09 02:34:32 PM UTC 24 |
| Finished | Oct 09 02:34:38 PM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343963026 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.2343963026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.2764029443 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 8173809743 ps |
| CPU time | 132.73 seconds |
| Started | Oct 09 10:29:55 AM UTC 24 |
| Finished | Oct 09 10:32:11 AM UTC 24 |
| Peak memory | 278104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764029443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2764029443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.4111675369 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 46678303453 ps |
| CPU time | 173.66 seconds |
| Started | Oct 09 10:30:45 AM UTC 24 |
| Finished | Oct 09 10:33:42 AM UTC 24 |
| Peak memory | 263692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111675369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.4111675369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3357247661 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1719961168 ps |
| CPU time | 15.37 seconds |
| Started | Oct 09 10:33:33 AM UTC 24 |
| Finished | Oct 09 10:33:50 AM UTC 24 |
| Peak memory | 251088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357247661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3357247661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.3303832574 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 19749825987 ps |
| CPU time | 188.08 seconds |
| Started | Oct 09 10:40:14 AM UTC 24 |
| Finished | Oct 09 10:43:25 AM UTC 24 |
| Peak memory | 278044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303832574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3303832574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1030515052 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 74270710168 ps |
| CPU time | 815.82 seconds |
| Started | Oct 09 10:40:57 AM UTC 24 |
| Finished | Oct 09 10:54:43 AM UTC 24 |
| Peak memory | 298440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030515052 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.1030515052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3497564219 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 4125989296 ps |
| CPU time | 50.02 seconds |
| Started | Oct 09 10:28:57 AM UTC 24 |
| Finished | Oct 09 10:29:49 AM UTC 24 |
| Peak memory | 234992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497564219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3497564219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.347089539 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 8584052993 ps |
| CPU time | 79.06 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:25:14 AM UTC 24 |
| Peak memory | 245076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347089539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.347089539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3304109883 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 25204516 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 02:33:45 PM UTC 24 |
| Finished | Oct 09 02:33:48 PM UTC 24 |
| Peak memory | 227388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304109883 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.3304109883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2815030702 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 2529224526 ps |
| CPU time | 12.79 seconds |
| Started | Oct 09 02:33:46 PM UTC 24 |
| Finished | Oct 09 02:34:00 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815030702 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.2815030702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3317838359 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 50565270 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 02:33:50 PM UTC 24 |
| Finished | Oct 09 02:33:54 PM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3317838359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.spi_device_csr_mem_rw_with_rand_reset.3317838359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2872656325 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 84788300 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 02:33:46 PM UTC 24 |
| Finished | Oct 09 02:33:50 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872656325 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2872656325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2892458619 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 97678770 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 02:33:41 PM UTC 24 |
| Finished | Oct 09 02:33:44 PM UTC 24 |
| Peak memory | 213316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892458619 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2892458619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2635715904 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 131052962 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 02:33:45 PM UTC 24 |
| Finished | Oct 09 02:33:48 PM UTC 24 |
| Peak memory | 224580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635715904 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.2635715904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2358573090 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 30277267 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 02:33:42 PM UTC 24 |
| Finished | Oct 09 02:33:45 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358573090 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.2358573090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.742860877 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 243224383 ps |
| CPU time | 4.31 seconds |
| Started | Oct 09 02:33:49 PM UTC 24 |
| Finished | Oct 09 02:33:55 PM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742860877 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.742860877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3522117210 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 576583247 ps |
| CPU time | 2.69 seconds |
| Started | Oct 09 02:33:41 PM UTC 24 |
| Finished | Oct 09 02:33:45 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522117210 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3522117210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2777047230 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 408363857 ps |
| CPU time | 11.39 seconds |
| Started | Oct 09 02:33:55 PM UTC 24 |
| Finished | Oct 09 02:34:08 PM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777047230 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.2777047230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.911998468 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 10021229493 ps |
| CPU time | 35.81 seconds |
| Started | Oct 09 02:33:55 PM UTC 24 |
| Finished | Oct 09 02:34:32 PM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911998468 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.911998468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.125577435 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 30563299 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 02:33:54 PM UTC 24 |
| Finished | Oct 09 02:33:56 PM UTC 24 |
| Peak memory | 226688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125577435 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.125577435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1205041980 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 29025889 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 02:33:56 PM UTC 24 |
| Finished | Oct 09 02:33:59 PM UTC 24 |
| Peak memory | 226684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1205041980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.spi_device_csr_mem_rw_with_rand_reset.1205041980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2719781673 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 120917400 ps |
| CPU time | 3.87 seconds |
| Started | Oct 09 02:33:55 PM UTC 24 |
| Finished | Oct 09 02:34:00 PM UTC 24 |
| Peak memory | 225356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719781673 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2719781673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2701255597 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 35398872 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 02:33:51 PM UTC 24 |
| Finished | Oct 09 02:33:54 PM UTC 24 |
| Peak memory | 212052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701255597 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2701255597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.3013928389 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 89876822 ps |
| CPU time | 2.92 seconds |
| Started | Oct 09 02:33:53 PM UTC 24 |
| Finished | Oct 09 02:33:57 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013928389 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.3013928389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2766997704 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 37107193 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 02:33:52 PM UTC 24 |
| Finished | Oct 09 02:33:55 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766997704 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.2766997704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.271960838 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 48659670 ps |
| CPU time | 4.35 seconds |
| Started | Oct 09 02:33:55 PM UTC 24 |
| Finished | Oct 09 02:34:01 PM UTC 24 |
| Peak memory | 225468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271960838 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.271960838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3382970812 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1220185934 ps |
| CPU time | 18.53 seconds |
| Started | Oct 09 02:33:51 PM UTC 24 |
| Finished | Oct 09 02:34:11 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382970812 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.3382970812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.34596176 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 46867493 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 02:34:27 PM UTC 24 |
| Finished | Oct 09 02:34:32 PM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=34596176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 10.spi_device_csr_mem_rw_with_rand_reset.34596176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3648401735 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 179299938 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 02:34:27 PM UTC 24 |
| Finished | Oct 09 02:34:30 PM UTC 24 |
| Peak memory | 226576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648401735 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.3648401735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2741255041 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 27118656 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 02:34:26 PM UTC 24 |
| Finished | Oct 09 02:34:28 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741255041 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.2741255041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2137852679 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 238836560 ps |
| CPU time | 3.94 seconds |
| Started | Oct 09 02:34:27 PM UTC 24 |
| Finished | Oct 09 02:34:32 PM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137852679 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstan ding.2137852679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.2570491897 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 206832596 ps |
| CPU time | 12.94 seconds |
| Started | Oct 09 02:34:26 PM UTC 24 |
| Finished | Oct 09 02:34:40 PM UTC 24 |
| Peak memory | 232756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570491897 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.2570491897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.836884400 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 214432118 ps |
| CPU time | 2.45 seconds |
| Started | Oct 09 02:34:31 PM UTC 24 |
| Finished | Oct 09 02:34:34 PM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=836884400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.spi_device_csr_mem_rw_with_rand_reset.836884400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2094510945 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 68504596 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 02:34:31 PM UTC 24 |
| Finished | Oct 09 02:34:33 PM UTC 24 |
| Peak memory | 224524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094510945 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.2094510945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1089231039 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 42956266 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 02:34:28 PM UTC 24 |
| Finished | Oct 09 02:34:31 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089231039 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.1089231039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3270453809 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 299107450 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 02:34:31 PM UTC 24 |
| Finished | Oct 09 02:34:34 PM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270453809 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstan ding.3270453809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3514867305 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 96425117 ps |
| CPU time | 3.56 seconds |
| Started | Oct 09 02:34:27 PM UTC 24 |
| Finished | Oct 09 02:34:32 PM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514867305 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.3514867305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.2632555038 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2115330217 ps |
| CPU time | 16.92 seconds |
| Started | Oct 09 02:34:27 PM UTC 24 |
| Finished | Oct 09 02:34:46 PM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632555038 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.2632555038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2837910164 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 147680936 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 02:34:34 PM UTC 24 |
| Finished | Oct 09 02:34:38 PM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2837910164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.spi_device_csr_mem_rw_with_rand_reset.2837910164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1559179370 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 117016823 ps |
| CPU time | 3.46 seconds |
| Started | Oct 09 02:34:33 PM UTC 24 |
| Finished | Oct 09 02:34:38 PM UTC 24 |
| Peak memory | 225476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559179370 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.1559179370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2924770080 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 17679062 ps |
| CPU time | 1 seconds |
| Started | Oct 09 02:34:32 PM UTC 24 |
| Finished | Oct 09 02:34:34 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924770080 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2924770080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1031700871 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 626462949 ps |
| CPU time | 3.94 seconds |
| Started | Oct 09 02:34:34 PM UTC 24 |
| Finished | Oct 09 02:34:39 PM UTC 24 |
| Peak memory | 225432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031700871 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan ding.1031700871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.3268539794 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 428823276 ps |
| CPU time | 14.83 seconds |
| Started | Oct 09 02:34:32 PM UTC 24 |
| Finished | Oct 09 02:34:48 PM UTC 24 |
| Peak memory | 227588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268539794 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.3268539794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2645210380 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 57576870 ps |
| CPU time | 5.51 seconds |
| Started | Oct 09 02:34:35 PM UTC 24 |
| Finished | Oct 09 02:34:42 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2645210380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.spi_device_csr_mem_rw_with_rand_reset.2645210380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.2412128138 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 86737604 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 02:34:35 PM UTC 24 |
| Finished | Oct 09 02:34:39 PM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412128138 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.2412128138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2623318008 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 15327092 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 02:34:35 PM UTC 24 |
| Finished | Oct 09 02:34:37 PM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623318008 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.2623318008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.432419290 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 55905795 ps |
| CPU time | 2.98 seconds |
| Started | Oct 09 02:34:35 PM UTC 24 |
| Finished | Oct 09 02:34:39 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432419290 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstand ing.432419290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1029788693 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 130824120 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 02:34:34 PM UTC 24 |
| Finished | Oct 09 02:34:38 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029788693 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.1029788693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1940515088 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3059682153 ps |
| CPU time | 8.56 seconds |
| Started | Oct 09 02:34:34 PM UTC 24 |
| Finished | Oct 09 02:34:43 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940515088 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.1940515088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2039093407 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 524398051 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 02:34:39 PM UTC 24 |
| Finished | Oct 09 02:34:45 PM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2039093407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.spi_device_csr_mem_rw_with_rand_reset.2039093407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1340092782 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 69374958 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 02:34:39 PM UTC 24 |
| Finished | Oct 09 02:34:42 PM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340092782 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.1340092782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.1331037196 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 132380887 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 02:34:39 PM UTC 24 |
| Finished | Oct 09 02:34:41 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331037196 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.1331037196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.314476210 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 286527320 ps |
| CPU time | 3.78 seconds |
| Started | Oct 09 02:34:39 PM UTC 24 |
| Finished | Oct 09 02:34:44 PM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314476210 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstand ing.314476210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.437131503 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 161010183 ps |
| CPU time | 5.42 seconds |
| Started | Oct 09 02:34:36 PM UTC 24 |
| Finished | Oct 09 02:34:43 PM UTC 24 |
| Peak memory | 227844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437131503 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.437131503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.2032885149 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1682983464 ps |
| CPU time | 8.97 seconds |
| Started | Oct 09 02:34:38 PM UTC 24 |
| Finished | Oct 09 02:34:48 PM UTC 24 |
| Peak memory | 227468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032885149 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.2032885149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.528938097 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 249626217 ps |
| CPU time | 4.28 seconds |
| Started | Oct 09 02:34:41 PM UTC 24 |
| Finished | Oct 09 02:34:46 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=528938097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.spi_device_csr_mem_rw_with_rand_reset.528938097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1024781961 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 441649875 ps |
| CPU time | 3.49 seconds |
| Started | Oct 09 02:34:41 PM UTC 24 |
| Finished | Oct 09 02:34:45 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024781961 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.1024781961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.3097809861 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 23276378 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 02:34:40 PM UTC 24 |
| Finished | Oct 09 02:34:42 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097809861 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.3097809861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1133135485 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 60336928 ps |
| CPU time | 2.78 seconds |
| Started | Oct 09 02:34:41 PM UTC 24 |
| Finished | Oct 09 02:34:45 PM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133135485 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstan ding.1133135485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.2586082253 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 4240152947 ps |
| CPU time | 6.12 seconds |
| Started | Oct 09 02:34:39 PM UTC 24 |
| Finished | Oct 09 02:34:47 PM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586082253 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.2586082253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.883704276 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 840514161 ps |
| CPU time | 21.24 seconds |
| Started | Oct 09 02:34:39 PM UTC 24 |
| Finished | Oct 09 02:35:02 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883704276 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.883704276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1840832700 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 233479254 ps |
| CPU time | 4.41 seconds |
| Started | Oct 09 02:34:44 PM UTC 24 |
| Finished | Oct 09 02:34:50 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1840832700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.spi_device_csr_mem_rw_with_rand_reset.1840832700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1907878012 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 101766729 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 02:34:44 PM UTC 24 |
| Finished | Oct 09 02:34:48 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907878012 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.1907878012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3327164088 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 25883737 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 02:34:42 PM UTC 24 |
| Finished | Oct 09 02:34:44 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327164088 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.3327164088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.828590886 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 108025665 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 02:34:44 PM UTC 24 |
| Finished | Oct 09 02:34:49 PM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828590886 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstand ing.828590886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.370792720 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 303936260 ps |
| CPU time | 6.47 seconds |
| Started | Oct 09 02:34:42 PM UTC 24 |
| Finished | Oct 09 02:34:50 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370792720 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.370792720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.432039413 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 878068426 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 02:34:46 PM UTC 24 |
| Finished | Oct 09 02:34:51 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=432039413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.spi_device_csr_mem_rw_with_rand_reset.432039413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.21890653 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 441537841 ps |
| CPU time | 3.56 seconds |
| Started | Oct 09 02:34:46 PM UTC 24 |
| Finished | Oct 09 02:34:51 PM UTC 24 |
| Peak memory | 225344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21890653 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.21890653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.740171691 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 11983546 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 02:34:46 PM UTC 24 |
| Finished | Oct 09 02:34:48 PM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740171691 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.740171691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.205199908 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 210359773 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 02:34:46 PM UTC 24 |
| Finished | Oct 09 02:34:50 PM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205199908 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstand ing.205199908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.451023331 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 53691843 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 02:34:44 PM UTC 24 |
| Finished | Oct 09 02:34:48 PM UTC 24 |
| Peak memory | 225600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451023331 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.451023331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1972283588 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 560378532 ps |
| CPU time | 16.42 seconds |
| Started | Oct 09 02:34:44 PM UTC 24 |
| Finished | Oct 09 02:35:02 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972283588 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.1972283588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.36126164 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 206368274 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 02:34:50 PM UTC 24 |
| Finished | Oct 09 02:34:54 PM UTC 24 |
| Peak memory | 227652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=36126164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 18.spi_device_csr_mem_rw_with_rand_reset.36126164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.86421612 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 104779538 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 02:34:48 PM UTC 24 |
| Finished | Oct 09 02:34:51 PM UTC 24 |
| Peak memory | 214300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86421612 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.86421612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2762979736 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 18954010 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 02:34:48 PM UTC 24 |
| Finished | Oct 09 02:34:50 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762979736 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.2762979736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3867252318 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 271827560 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 02:34:48 PM UTC 24 |
| Finished | Oct 09 02:34:53 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867252318 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan ding.3867252318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.2725060371 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 70195782 ps |
| CPU time | 5.52 seconds |
| Started | Oct 09 02:34:46 PM UTC 24 |
| Finished | Oct 09 02:34:53 PM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725060371 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.2725060371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.829773288 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 3270387223 ps |
| CPU time | 20.26 seconds |
| Started | Oct 09 02:34:47 PM UTC 24 |
| Finished | Oct 09 02:35:08 PM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829773288 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.829773288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3236684258 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 63148811 ps |
| CPU time | 2 seconds |
| Started | Oct 09 02:34:51 PM UTC 24 |
| Finished | Oct 09 02:34:54 PM UTC 24 |
| Peak memory | 224636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3236684258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.spi_device_csr_mem_rw_with_rand_reset.3236684258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.585789433 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 36994829 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 02:34:50 PM UTC 24 |
| Finished | Oct 09 02:34:55 PM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585789433 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.585789433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.4153981161 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 19510540 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 02:34:50 PM UTC 24 |
| Finished | Oct 09 02:34:52 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153981161 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.4153981161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2365323913 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 79816070 ps |
| CPU time | 2.85 seconds |
| Started | Oct 09 02:34:50 PM UTC 24 |
| Finished | Oct 09 02:34:54 PM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365323913 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstan ding.2365323913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3049167777 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 92327636 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 02:34:50 PM UTC 24 |
| Finished | Oct 09 02:34:54 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049167777 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.3049167777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.2819623744 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 1516400212 ps |
| CPU time | 9.29 seconds |
| Started | Oct 09 02:34:50 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819623744 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.2819623744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1088624337 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 442884457 ps |
| CPU time | 11.34 seconds |
| Started | Oct 09 02:34:02 PM UTC 24 |
| Finished | Oct 09 02:34:14 PM UTC 24 |
| Peak memory | 215120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088624337 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.1088624337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.200193580 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 931607759 ps |
| CPU time | 13.37 seconds |
| Started | Oct 09 02:34:00 PM UTC 24 |
| Finished | Oct 09 02:34:15 PM UTC 24 |
| Peak memory | 225032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200193580 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.200193580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.164472141 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 36466959 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 02:34:00 PM UTC 24 |
| Finished | Oct 09 02:34:03 PM UTC 24 |
| Peak memory | 226304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164472141 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.164472141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2801286353 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 99249322 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 02:34:02 PM UTC 24 |
| Finished | Oct 09 02:34:07 PM UTC 24 |
| Peak memory | 229640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2801286353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.spi_device_csr_mem_rw_with_rand_reset.2801286353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3624741951 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 448418210 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 02:34:00 PM UTC 24 |
| Finished | Oct 09 02:34:04 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624741951 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3624741951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3893695967 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 24475429 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 02:33:56 PM UTC 24 |
| Finished | Oct 09 02:33:59 PM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893695967 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3893695967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3660041757 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 124949866 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 02:33:58 PM UTC 24 |
| Finished | Oct 09 02:34:01 PM UTC 24 |
| Peak memory | 224580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660041757 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.3660041757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.4056645568 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 123585307 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 02:33:57 PM UTC 24 |
| Finished | Oct 09 02:34:00 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056645568 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.4056645568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2590089886 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 56159608 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 02:34:02 PM UTC 24 |
| Finished | Oct 09 02:34:08 PM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590089886 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand ing.2590089886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3885845948 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 153445296 ps |
| CPU time | 3.06 seconds |
| Started | Oct 09 02:33:56 PM UTC 24 |
| Finished | Oct 09 02:34:00 PM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885845948 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3885845948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.561279737 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1456698458 ps |
| CPU time | 8.15 seconds |
| Started | Oct 09 02:33:56 PM UTC 24 |
| Finished | Oct 09 02:34:06 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561279737 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.561279737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.4259651262 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 17515896 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 02:34:52 PM UTC 24 |
| Finished | Oct 09 02:34:54 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259651262 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.4259651262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3410979656 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 37522366 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 02:34:52 PM UTC 24 |
| Finished | Oct 09 02:34:54 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410979656 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.3410979656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.1485529963 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 47688506 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 02:34:52 PM UTC 24 |
| Finished | Oct 09 02:34:54 PM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485529963 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.1485529963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.373189656 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 17231758 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 02:34:52 PM UTC 24 |
| Finished | Oct 09 02:34:55 PM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373189656 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.373189656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.74877488 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 18600702 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 02:34:52 PM UTC 24 |
| Finished | Oct 09 02:34:54 PM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74877488 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.74877488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.763151372 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 15248204 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 02:34:52 PM UTC 24 |
| Finished | Oct 09 02:34:55 PM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763151372 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.763151372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3875479986 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 50478386 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 02:34:54 PM UTC 24 |
| Finished | Oct 09 02:34:57 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875479986 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.3875479986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2378414652 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 21096458 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 02:34:54 PM UTC 24 |
| Finished | Oct 09 02:34:56 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378414652 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.2378414652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.1319184236 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 53226038 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 02:34:54 PM UTC 24 |
| Finished | Oct 09 02:34:57 PM UTC 24 |
| Peak memory | 212196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319184236 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.1319184236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.34333150 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 17477965 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 02:34:54 PM UTC 24 |
| Finished | Oct 09 02:34:57 PM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34333150 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.34333150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1004349732 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 642475043 ps |
| CPU time | 8.55 seconds |
| Started | Oct 09 02:34:06 PM UTC 24 |
| Finished | Oct 09 02:34:16 PM UTC 24 |
| Peak memory | 215120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004349732 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.1004349732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.170134485 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 3695463424 ps |
| CPU time | 34.92 seconds |
| Started | Oct 09 02:34:06 PM UTC 24 |
| Finished | Oct 09 02:34:42 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170134485 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.170134485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2292554645 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 39462152 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 02:34:03 PM UTC 24 |
| Finished | Oct 09 02:34:06 PM UTC 24 |
| Peak memory | 214964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292554645 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.2292554645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2159171779 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 55425596 ps |
| CPU time | 5.26 seconds |
| Started | Oct 09 02:34:07 PM UTC 24 |
| Finished | Oct 09 02:34:14 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2159171779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.spi_device_csr_mem_rw_with_rand_reset.2159171779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.4261082550 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 169054272 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 02:34:04 PM UTC 24 |
| Finished | Oct 09 02:34:08 PM UTC 24 |
| Peak memory | 224536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261082550 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4261082550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.519269641 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 16846515 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 02:34:02 PM UTC 24 |
| Finished | Oct 09 02:34:04 PM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519269641 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.519269641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1815852568 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 40839566 ps |
| CPU time | 1.88 seconds |
| Started | Oct 09 02:34:03 PM UTC 24 |
| Finished | Oct 09 02:34:06 PM UTC 24 |
| Peak memory | 224580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815852568 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.1815852568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.4153683562 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 11667006 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 02:34:02 PM UTC 24 |
| Finished | Oct 09 02:34:04 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153683562 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.4153683562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.906768157 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 221973850 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 02:34:07 PM UTC 24 |
| Finished | Oct 09 02:34:14 PM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906768157 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.906768157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1853847896 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 91894110 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 02:34:02 PM UTC 24 |
| Finished | Oct 09 02:34:06 PM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853847896 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1853847896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2791177904 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 468650590 ps |
| CPU time | 8.08 seconds |
| Started | Oct 09 02:34:02 PM UTC 24 |
| Finished | Oct 09 02:34:11 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791177904 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.2791177904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1865753238 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 32683047 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 02:34:54 PM UTC 24 |
| Finished | Oct 09 02:34:57 PM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865753238 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.1865753238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.30529400 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 16028395 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 02:34:58 PM UTC 24 |
| Finished | Oct 09 02:35:00 PM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30529400 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.30529400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3348650783 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 22913133 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 02:34:58 PM UTC 24 |
| Finished | Oct 09 02:35:00 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348650783 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3348650783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.406375021 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 24721190 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 02:34:58 PM UTC 24 |
| Finished | Oct 09 02:35:00 PM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406375021 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.406375021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1319485947 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 30643589 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 02:34:58 PM UTC 24 |
| Finished | Oct 09 02:35:00 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319485947 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.1319485947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1799311847 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 31682213 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 02:34:58 PM UTC 24 |
| Finished | Oct 09 02:35:00 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799311847 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.1799311847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.53194217 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 48079471 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 02:34:58 PM UTC 24 |
| Finished | Oct 09 02:35:00 PM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53194217 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.53194217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3683538833 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 43561490 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 02:34:58 PM UTC 24 |
| Finished | Oct 09 02:35:00 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683538833 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3683538833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1472306104 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 39846492 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 02:34:58 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472306104 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.1472306104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3098681853 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 16866680 ps |
| CPU time | 1 seconds |
| Started | Oct 09 02:34:59 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098681853 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.3098681853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.3495138852 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 1219863853 ps |
| CPU time | 17.86 seconds |
| Started | Oct 09 02:34:11 PM UTC 24 |
| Finished | Oct 09 02:34:30 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495138852 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.3495138852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2677292311 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 5026902303 ps |
| CPU time | 26.23 seconds |
| Started | Oct 09 02:34:10 PM UTC 24 |
| Finished | Oct 09 02:34:37 PM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677292311 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.2677292311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1271600583 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 77041428 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 02:34:08 PM UTC 24 |
| Finished | Oct 09 02:34:11 PM UTC 24 |
| Peak memory | 214284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271600583 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.1271600583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3458431960 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 124129753 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 02:34:12 PM UTC 24 |
| Finished | Oct 09 02:34:17 PM UTC 24 |
| Peak memory | 227732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3458431960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.spi_device_csr_mem_rw_with_rand_reset.3458431960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2666806915 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 411679657 ps |
| CPU time | 3.89 seconds |
| Started | Oct 09 02:34:09 PM UTC 24 |
| Finished | Oct 09 02:34:15 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666806915 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2666806915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.624020939 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 43477526 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 02:34:07 PM UTC 24 |
| Finished | Oct 09 02:34:10 PM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624020939 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.624020939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2695697727 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 59121168 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 02:34:08 PM UTC 24 |
| Finished | Oct 09 02:34:13 PM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695697727 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.2695697727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.4193116468 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 37785912 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 02:34:08 PM UTC 24 |
| Finished | Oct 09 02:34:11 PM UTC 24 |
| Peak memory | 212212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193116468 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.4193116468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1147055176 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 264265355 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 02:34:12 PM UTC 24 |
| Finished | Oct 09 02:34:15 PM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147055176 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstand ing.1147055176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.1392096506 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 255928416 ps |
| CPU time | 6.32 seconds |
| Started | Oct 09 02:34:07 PM UTC 24 |
| Finished | Oct 09 02:34:15 PM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392096506 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1392096506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3500133873 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 549751248 ps |
| CPU time | 14.72 seconds |
| Started | Oct 09 02:34:07 PM UTC 24 |
| Finished | Oct 09 02:34:23 PM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500133873 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.3500133873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.1105591118 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 30757322 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 02:34:59 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105591118 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.1105591118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2733982356 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 33845675 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 02:34:59 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733982356 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.2733982356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3357420545 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 13332293 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 02:34:59 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357420545 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3357420545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1065094802 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 17426123 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 02:34:59 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065094802 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1065094802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2152506591 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 31140607 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 02:34:59 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152506591 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.2152506591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.4154191003 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 19426015 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 02:34:59 PM UTC 24 |
| Finished | Oct 09 02:35:01 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154191003 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.4154191003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.221349405 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 15625870 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 02:35:03 PM UTC 24 |
| Finished | Oct 09 02:35:05 PM UTC 24 |
| Peak memory | 212160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221349405 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.221349405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1244144375 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 50738615 ps |
| CPU time | 0.79 seconds |
| Started | Oct 09 02:35:03 PM UTC 24 |
| Finished | Oct 09 02:35:05 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244144375 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.1244144375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.2874068546 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 185966149 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 02:35:03 PM UTC 24 |
| Finished | Oct 09 02:35:05 PM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874068546 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.2874068546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2634243768 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 34602678 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 02:35:03 PM UTC 24 |
| Finished | Oct 09 02:35:05 PM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634243768 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2634243768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3990090849 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 152359457 ps |
| CPU time | 4.08 seconds |
| Started | Oct 09 02:34:15 PM UTC 24 |
| Finished | Oct 09 02:34:20 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3990090849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.spi_device_csr_mem_rw_with_rand_reset.3990090849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1997251338 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 20917042 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 02:34:15 PM UTC 24 |
| Finished | Oct 09 02:34:18 PM UTC 24 |
| Peak memory | 215168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997251338 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1997251338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.87812138 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 14878412 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 02:34:13 PM UTC 24 |
| Finished | Oct 09 02:34:15 PM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87812138 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.87812138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3242131228 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2152703170 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 02:34:15 PM UTC 24 |
| Finished | Oct 09 02:34:20 PM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242131228 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstand ing.3242131228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3547946090 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 587667143 ps |
| CPU time | 7.32 seconds |
| Started | Oct 09 02:34:12 PM UTC 24 |
| Finished | Oct 09 02:34:20 PM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547946090 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3547946090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1364997361 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 108182463 ps |
| CPU time | 5.77 seconds |
| Started | Oct 09 02:34:16 PM UTC 24 |
| Finished | Oct 09 02:34:23 PM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1364997361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.spi_device_csr_mem_rw_with_rand_reset.1364997361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1844860315 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 41839265 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 02:34:16 PM UTC 24 |
| Finished | Oct 09 02:34:19 PM UTC 24 |
| Peak memory | 214300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844860315 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1844860315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.531381407 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 19482331 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 02:34:16 PM UTC 24 |
| Finished | Oct 09 02:34:18 PM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531381407 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.531381407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3263983668 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 148182351 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 02:34:16 PM UTC 24 |
| Finished | Oct 09 02:34:21 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263983668 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstand ing.3263983668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1749977820 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 106012051 ps |
| CPU time | 3.87 seconds |
| Started | Oct 09 02:34:15 PM UTC 24 |
| Finished | Oct 09 02:34:20 PM UTC 24 |
| Peak memory | 227588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749977820 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1749977820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3192235838 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5557364605 ps |
| CPU time | 20.62 seconds |
| Started | Oct 09 02:34:16 PM UTC 24 |
| Finished | Oct 09 02:34:38 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192235838 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.3192235838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3069671529 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 189388692 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 02:34:20 PM UTC 24 |
| Finished | Oct 09 02:34:23 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3069671529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.spi_device_csr_mem_rw_with_rand_reset.3069671529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.1548772666 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 55338190 ps |
| CPU time | 2.72 seconds |
| Started | Oct 09 02:34:19 PM UTC 24 |
| Finished | Oct 09 02:34:23 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548772666 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1548772666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.203940745 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 17924092 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 02:34:19 PM UTC 24 |
| Finished | Oct 09 02:34:21 PM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203940745 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.203940745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1336691915 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 743394142 ps |
| CPU time | 3.54 seconds |
| Started | Oct 09 02:34:20 PM UTC 24 |
| Finished | Oct 09 02:34:25 PM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336691915 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand ing.1336691915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.403170755 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 718186174 ps |
| CPU time | 4.77 seconds |
| Started | Oct 09 02:34:16 PM UTC 24 |
| Finished | Oct 09 02:34:22 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403170755 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.403170755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3529256192 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 405963790 ps |
| CPU time | 16.58 seconds |
| Started | Oct 09 02:34:18 PM UTC 24 |
| Finished | Oct 09 02:34:35 PM UTC 24 |
| Peak memory | 227736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529256192 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.3529256192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3209127994 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 196945755 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 02:34:22 PM UTC 24 |
| Finished | Oct 09 02:34:25 PM UTC 24 |
| Peak memory | 227708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3209127994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.spi_device_csr_mem_rw_with_rand_reset.3209127994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2317811437 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 66894790 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 02:34:22 PM UTC 24 |
| Finished | Oct 09 02:34:25 PM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317811437 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2317811437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1581500011 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 23466016 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 02:34:22 PM UTC 24 |
| Finished | Oct 09 02:34:24 PM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581500011 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1581500011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3591053621 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 26547361 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 02:34:22 PM UTC 24 |
| Finished | Oct 09 02:34:25 PM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591053621 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand ing.3591053621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.727774605 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 357599299 ps |
| CPU time | 2.98 seconds |
| Started | Oct 09 02:34:21 PM UTC 24 |
| Finished | Oct 09 02:34:26 PM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727774605 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.727774605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.1524422122 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2763850760 ps |
| CPU time | 19.36 seconds |
| Started | Oct 09 02:34:21 PM UTC 24 |
| Finished | Oct 09 02:34:42 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524422122 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.1524422122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3329381264 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 60252180 ps |
| CPU time | 4.75 seconds |
| Started | Oct 09 02:34:25 PM UTC 24 |
| Finished | Oct 09 02:34:30 PM UTC 24 |
| Peak memory | 227664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3329381264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.spi_device_csr_mem_rw_with_rand_reset.3329381264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3197782062 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 450464227 ps |
| CPU time | 4.01 seconds |
| Started | Oct 09 02:34:24 PM UTC 24 |
| Finished | Oct 09 02:34:30 PM UTC 24 |
| Peak memory | 217152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197782062 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3197782062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4017720723 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 34643305 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 02:34:24 PM UTC 24 |
| Finished | Oct 09 02:34:27 PM UTC 24 |
| Peak memory | 212172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017720723 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4017720723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3253547887 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 561541932 ps |
| CPU time | 6.14 seconds |
| Started | Oct 09 02:34:24 PM UTC 24 |
| Finished | Oct 09 02:34:32 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253547887 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand ing.3253547887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1047472534 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 82919455 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 02:34:23 PM UTC 24 |
| Finished | Oct 09 02:34:26 PM UTC 24 |
| Peak memory | 225744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047472534 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1047472534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2813325347 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1976715073 ps |
| CPU time | 26.57 seconds |
| Started | Oct 09 02:34:24 PM UTC 24 |
| Finished | Oct 09 02:34:52 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813325347 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2813325347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2712394954 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 206014767 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:23:56 AM UTC 24 |
| Peak memory | 243480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712394954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2712394954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3887063297 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 74598185651 ps |
| CPU time | 173.12 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:26:51 AM UTC 24 |
| Peak memory | 267672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887063297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3887063297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.685677399 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 113665934548 ps |
| CPU time | 198.98 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:27:15 AM UTC 24 |
| Peak memory | 265764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685677399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.685677399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.332371943 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 334863024 ps |
| CPU time | 4.47 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:23:58 AM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332371943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.332371943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.3227069922 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 202237666 ps |
| CPU time | 5.99 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:24:00 AM UTC 24 |
| Peak memory | 234672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227069922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3227069922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.4233171380 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 99536491 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:23:52 AM UTC 24 |
| Finished | Oct 09 10:23:59 AM UTC 24 |
| Peak memory | 234916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233171380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.4233171380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2970152964 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 540487306 ps |
| CPU time | 5.19 seconds |
| Started | Oct 09 10:23:51 AM UTC 24 |
| Finished | Oct 09 10:23:57 AM UTC 24 |
| Peak memory | 234856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970152964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2970152964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.3852997094 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9320844220 ps |
| CPU time | 12.57 seconds |
| Started | Oct 09 10:23:50 AM UTC 24 |
| Finished | Oct 09 10:24:04 AM UTC 24 |
| Peak memory | 231624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852997094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3852997094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2304090305 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 49409670 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 10:23:50 AM UTC 24 |
| Finished | Oct 09 10:23:52 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304090305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2304090305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.3934657374 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 94274811 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:24:04 AM UTC 24 |
| Finished | Oct 09 10:24:06 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934657374 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3934657374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2240382376 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 344341658 ps |
| CPU time | 3.56 seconds |
| Started | Oct 09 10:23:57 AM UTC 24 |
| Finished | Oct 09 10:24:03 AM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240382376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2240382376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.3477763394 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 70260930 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:23:53 AM UTC 24 |
| Finished | Oct 09 10:23:56 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477763394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3477763394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.4254428609 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 18602638626 ps |
| CPU time | 137.04 seconds |
| Started | Oct 09 10:23:58 AM UTC 24 |
| Finished | Oct 09 10:26:18 AM UTC 24 |
| Peak memory | 277840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254428609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4254428609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.559496013 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2116537884 ps |
| CPU time | 15.75 seconds |
| Started | Oct 09 10:23:57 AM UTC 24 |
| Finished | Oct 09 10:24:15 AM UTC 24 |
| Peak memory | 245084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559496013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.559496013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.730247115 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1524247446 ps |
| CPU time | 26.53 seconds |
| Started | Oct 09 10:23:57 AM UTC 24 |
| Finished | Oct 09 10:24:28 AM UTC 24 |
| Peak memory | 244976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730247115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.730247115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.1382056318 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2271631631 ps |
| CPU time | 24.25 seconds |
| Started | Oct 09 10:23:57 AM UTC 24 |
| Finished | Oct 09 10:24:26 AM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382056318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1382056318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2564558833 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 35274771369 ps |
| CPU time | 21.15 seconds |
| Started | Oct 09 10:23:56 AM UTC 24 |
| Finished | Oct 09 10:24:21 AM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564558833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.2564558833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.187495169 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 14414463584 ps |
| CPU time | 39.81 seconds |
| Started | Oct 09 10:23:55 AM UTC 24 |
| Finished | Oct 09 10:24:36 AM UTC 24 |
| Peak memory | 245088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187495169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.187495169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.4088238379 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 208967239 ps |
| CPU time | 5.64 seconds |
| Started | Oct 09 10:23:57 AM UTC 24 |
| Finished | Oct 09 10:24:05 AM UTC 24 |
| Peak memory | 233436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088238379 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.4088238379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.2954915123 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 124005751 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 10:24:01 AM UTC 24 |
| Finished | Oct 09 10:24:03 AM UTC 24 |
| Peak memory | 257076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954915123 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2954915123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.702198675 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 25083597129 ps |
| CPU time | 43.52 seconds |
| Started | Oct 09 10:23:54 AM UTC 24 |
| Finished | Oct 09 10:24:39 AM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702198675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.702198675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1690108047 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 21741631 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 10:23:53 AM UTC 24 |
| Finished | Oct 09 10:23:55 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690108047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1690108047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3340645905 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 49569744 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 10:23:54 AM UTC 24 |
| Finished | Oct 09 10:23:56 AM UTC 24 |
| Peak memory | 227328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340645905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3340645905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2388981664 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 24661425 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 10:23:54 AM UTC 24 |
| Finished | Oct 09 10:23:56 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388981664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2388981664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3351893925 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3877832878 ps |
| CPU time | 20.25 seconds |
| Started | Oct 09 10:23:57 AM UTC 24 |
| Finished | Oct 09 10:24:20 AM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351893925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3351893925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.2501426011 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 24679699 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:28:50 AM UTC 24 |
| Finished | Oct 09 10:28:52 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501426011 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.2501426011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2293276900 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 57895621 ps |
| CPU time | 3.96 seconds |
| Started | Oct 09 10:28:37 AM UTC 24 |
| Finished | Oct 09 10:28:42 AM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293276900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2293276900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.2880998903 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 33813355 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 10:28:12 AM UTC 24 |
| Finished | Oct 09 10:28:15 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880998903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2880998903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.108150740 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 8393139051 ps |
| CPU time | 31.62 seconds |
| Started | Oct 09 10:28:47 AM UTC 24 |
| Finished | Oct 09 10:29:20 AM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108150740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.108150740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1561612258 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4336176213 ps |
| CPU time | 21.17 seconds |
| Started | Oct 09 10:28:49 AM UTC 24 |
| Finished | Oct 09 10:29:11 AM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561612258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1561612258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3325063601 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 386964620118 ps |
| CPU time | 441.06 seconds |
| Started | Oct 09 10:28:49 AM UTC 24 |
| Finished | Oct 09 10:36:15 AM UTC 24 |
| Peak memory | 280272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325063601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.3325063601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.4224486573 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 952670859 ps |
| CPU time | 22.17 seconds |
| Started | Oct 09 10:28:41 AM UTC 24 |
| Finished | Oct 09 10:29:05 AM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224486573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4224486573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2748078543 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 72725743778 ps |
| CPU time | 186.74 seconds |
| Started | Oct 09 10:28:43 AM UTC 24 |
| Finished | Oct 09 10:31:54 AM UTC 24 |
| Peak memory | 271700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748078543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2748078543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.3646959527 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 390161830 ps |
| CPU time | 7.58 seconds |
| Started | Oct 09 10:28:28 AM UTC 24 |
| Finished | Oct 09 10:28:37 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646959527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3646959527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1289197632 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 18500149914 ps |
| CPU time | 74.52 seconds |
| Started | Oct 09 10:28:31 AM UTC 24 |
| Finished | Oct 09 10:29:48 AM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289197632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1289197632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1898140168 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 11907425289 ps |
| CPU time | 24.26 seconds |
| Started | Oct 09 10:28:24 AM UTC 24 |
| Finished | Oct 09 10:28:49 AM UTC 24 |
| Peak memory | 234920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898140168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.1898140168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3818885008 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 223382711 ps |
| CPU time | 6.73 seconds |
| Started | Oct 09 10:28:22 AM UTC 24 |
| Finished | Oct 09 10:28:30 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818885008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3818885008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1633289425 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2913859666 ps |
| CPU time | 13.75 seconds |
| Started | Oct 09 10:28:43 AM UTC 24 |
| Finished | Oct 09 10:28:58 AM UTC 24 |
| Peak memory | 231440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633289425 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1633289425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.262503672 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 9105891425 ps |
| CPU time | 126.81 seconds |
| Started | Oct 09 10:28:50 AM UTC 24 |
| Finished | Oct 09 10:30:59 AM UTC 24 |
| Peak memory | 261576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262503672 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.262503672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1703979610 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4023191793 ps |
| CPU time | 30.11 seconds |
| Started | Oct 09 10:28:17 AM UTC 24 |
| Finished | Oct 09 10:28:49 AM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703979610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1703979610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3383147452 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 4849536021 ps |
| CPU time | 29.35 seconds |
| Started | Oct 09 10:28:15 AM UTC 24 |
| Finished | Oct 09 10:28:46 AM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383147452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3383147452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.4121847225 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 55663912 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 10:28:20 AM UTC 24 |
| Finished | Oct 09 10:28:23 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121847225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4121847225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.2140081010 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 66402508 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:28:17 AM UTC 24 |
| Finished | Oct 09 10:28:20 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140081010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2140081010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.850933482 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1110004513 ps |
| CPU time | 9.23 seconds |
| Started | Oct 09 10:28:32 AM UTC 24 |
| Finished | Oct 09 10:28:43 AM UTC 24 |
| Peak memory | 234660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850933482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.850933482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.3728445265 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 30091383 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:29:12 AM UTC 24 |
| Finished | Oct 09 10:29:14 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728445265 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.3728445265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.4292429095 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 699643092 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 10:29:05 AM UTC 24 |
| Finished | Oct 09 10:29:10 AM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292429095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4292429095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.2744172651 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 226488132 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:28:50 AM UTC 24 |
| Finished | Oct 09 10:28:52 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744172651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2744172651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.258122909 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 21117894 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 10:29:11 AM UTC 24 |
| Finished | Oct 09 10:29:13 AM UTC 24 |
| Peak memory | 226696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258122909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.258122909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1355357270 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 31214060426 ps |
| CPU time | 184.39 seconds |
| Started | Oct 09 10:29:11 AM UTC 24 |
| Finished | Oct 09 10:32:18 AM UTC 24 |
| Peak memory | 278288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355357270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1355357270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2307512128 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5982188830 ps |
| CPU time | 36.74 seconds |
| Started | Oct 09 10:29:11 AM UTC 24 |
| Finished | Oct 09 10:29:49 AM UTC 24 |
| Peak memory | 245456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307512128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.2307512128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1680997061 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 280605190 ps |
| CPU time | 3.69 seconds |
| Started | Oct 09 10:29:05 AM UTC 24 |
| Finished | Oct 09 10:29:10 AM UTC 24 |
| Peak memory | 234684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680997061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1680997061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.3075612030 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 65980809295 ps |
| CPU time | 152.91 seconds |
| Started | Oct 09 10:29:07 AM UTC 24 |
| Finished | Oct 09 10:31:42 AM UTC 24 |
| Peak memory | 263500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075612030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.3075612030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2121194432 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 414495424 ps |
| CPU time | 12.1 seconds |
| Started | Oct 09 10:28:58 AM UTC 24 |
| Finished | Oct 09 10:29:11 AM UTC 24 |
| Peak memory | 251104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121194432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2121194432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2380872200 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 19315787774 ps |
| CPU time | 25.13 seconds |
| Started | Oct 09 10:28:56 AM UTC 24 |
| Finished | Oct 09 10:29:22 AM UTC 24 |
| Peak memory | 245024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380872200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.2380872200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.996520959 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 603703583 ps |
| CPU time | 14.4 seconds |
| Started | Oct 09 10:28:55 AM UTC 24 |
| Finished | Oct 09 10:29:11 AM UTC 24 |
| Peak memory | 245004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996520959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.996520959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3699049938 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 335300960 ps |
| CPU time | 5.52 seconds |
| Started | Oct 09 10:29:09 AM UTC 24 |
| Finished | Oct 09 10:29:15 AM UTC 24 |
| Peak memory | 231184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699049938 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.3699049938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.722943688 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 19200449383 ps |
| CPU time | 76.01 seconds |
| Started | Oct 09 10:29:12 AM UTC 24 |
| Finished | Oct 09 10:30:30 AM UTC 24 |
| Peak memory | 261588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722943688 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.722943688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.1847961324 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3504519524 ps |
| CPU time | 26.68 seconds |
| Started | Oct 09 10:28:54 AM UTC 24 |
| Finished | Oct 09 10:29:22 AM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847961324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1847961324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3491512121 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1596280699 ps |
| CPU time | 9.32 seconds |
| Started | Oct 09 10:28:53 AM UTC 24 |
| Finished | Oct 09 10:29:04 AM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491512121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3491512121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.3248115683 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 72567180 ps |
| CPU time | 2.19 seconds |
| Started | Oct 09 10:28:54 AM UTC 24 |
| Finished | Oct 09 10:28:57 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248115683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3248115683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.4202150196 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 106421839 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:28:54 AM UTC 24 |
| Finished | Oct 09 10:28:56 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202150196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4202150196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.3183821285 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4092613946 ps |
| CPU time | 18.42 seconds |
| Started | Oct 09 10:28:59 AM UTC 24 |
| Finished | Oct 09 10:29:19 AM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183821285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3183821285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.2222161852 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 14443173 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:29:38 AM UTC 24 |
| Finished | Oct 09 10:29:40 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222161852 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.2222161852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.1527961777 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 462467925 ps |
| CPU time | 4.88 seconds |
| Started | Oct 09 10:29:21 AM UTC 24 |
| Finished | Oct 09 10:29:27 AM UTC 24 |
| Peak memory | 244900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527961777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1527961777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3407100326 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 48327360 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:29:12 AM UTC 24 |
| Finished | Oct 09 10:29:14 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407100326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3407100326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.2071069247 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4565389675 ps |
| CPU time | 19.86 seconds |
| Started | Oct 09 10:29:27 AM UTC 24 |
| Finished | Oct 09 10:29:48 AM UTC 24 |
| Peak memory | 261516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071069247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2071069247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1151796784 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 74737914199 ps |
| CPU time | 358.59 seconds |
| Started | Oct 09 10:29:29 AM UTC 24 |
| Finished | Oct 09 10:35:32 AM UTC 24 |
| Peak memory | 277980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151796784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.1151796784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1919288537 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6750205111 ps |
| CPU time | 69.84 seconds |
| Started | Oct 09 10:29:22 AM UTC 24 |
| Finished | Oct 09 10:30:34 AM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919288537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.1919288537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2912584235 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 120280732 ps |
| CPU time | 4.5 seconds |
| Started | Oct 09 10:29:20 AM UTC 24 |
| Finished | Oct 09 10:29:26 AM UTC 24 |
| Peak memory | 244960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912584235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2912584235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.1166206317 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4259455448 ps |
| CPU time | 61.72 seconds |
| Started | Oct 09 10:29:20 AM UTC 24 |
| Finished | Oct 09 10:30:23 AM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166206317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1166206317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2997983696 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 28411868081 ps |
| CPU time | 24.83 seconds |
| Started | Oct 09 10:29:20 AM UTC 24 |
| Finished | Oct 09 10:29:46 AM UTC 24 |
| Peak memory | 245024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997983696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.2997983696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.731819322 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 83042668 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 10:29:17 AM UTC 24 |
| Finished | Oct 09 10:29:21 AM UTC 24 |
| Peak memory | 234916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731819322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.731819322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3824797754 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 344285458 ps |
| CPU time | 7.46 seconds |
| Started | Oct 09 10:29:23 AM UTC 24 |
| Finished | Oct 09 10:29:32 AM UTC 24 |
| Peak memory | 231184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824797754 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.3824797754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.3536177603 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 294712472725 ps |
| CPU time | 418.61 seconds |
| Started | Oct 09 10:29:33 AM UTC 24 |
| Finished | Oct 09 10:36:38 AM UTC 24 |
| Peak memory | 278160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536177603 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.3536177603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1680343833 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3742745493 ps |
| CPU time | 19.92 seconds |
| Started | Oct 09 10:29:15 AM UTC 24 |
| Finished | Oct 09 10:29:37 AM UTC 24 |
| Peak memory | 227656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680343833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1680343833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.504719659 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2024042364 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 10:29:15 AM UTC 24 |
| Finished | Oct 09 10:29:19 AM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504719659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.504719659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.1606029034 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 26384273 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 10:29:17 AM UTC 24 |
| Finished | Oct 09 10:29:19 AM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606029034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1606029034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1432126959 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 84633030 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:29:17 AM UTC 24 |
| Finished | Oct 09 10:29:19 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432126959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1432126959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.1985446485 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4670531999 ps |
| CPU time | 7.01 seconds |
| Started | Oct 09 10:29:20 AM UTC 24 |
| Finished | Oct 09 10:29:28 AM UTC 24 |
| Peak memory | 245076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985446485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1985446485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.353980051 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 11592048 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 10:30:01 AM UTC 24 |
| Finished | Oct 09 10:30:03 AM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353980051 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.353980051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3071370467 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 77070233 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 10:29:51 AM UTC 24 |
| Finished | Oct 09 10:29:56 AM UTC 24 |
| Peak memory | 234156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071370467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3071370467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3887812344 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 63948013 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 10:29:41 AM UTC 24 |
| Finished | Oct 09 10:29:43 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887812344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3887812344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2838072871 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 55626168989 ps |
| CPU time | 600.47 seconds |
| Started | Oct 09 10:29:57 AM UTC 24 |
| Finished | Oct 09 10:40:05 AM UTC 24 |
| Peak memory | 263880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838072871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.2838072871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.1499114216 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 34089835 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 10:29:55 AM UTC 24 |
| Finished | Oct 09 10:30:00 AM UTC 24 |
| Peak memory | 245008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499114216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1499114216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2924606940 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 3349268862 ps |
| CPU time | 68.98 seconds |
| Started | Oct 09 10:29:55 AM UTC 24 |
| Finished | Oct 09 10:31:06 AM UTC 24 |
| Peak memory | 279876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924606940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.2924606940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.4042415733 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1301178247 ps |
| CPU time | 18.21 seconds |
| Started | Oct 09 10:29:50 AM UTC 24 |
| Finished | Oct 09 10:30:10 AM UTC 24 |
| Peak memory | 234772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042415733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4042415733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.2390200851 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 117305389 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 10:29:50 AM UTC 24 |
| Finished | Oct 09 10:29:54 AM UTC 24 |
| Peak memory | 244692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390200851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2390200851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3452845121 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1242969033 ps |
| CPU time | 20.72 seconds |
| Started | Oct 09 10:29:49 AM UTC 24 |
| Finished | Oct 09 10:30:11 AM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452845121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.3452845121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2298066868 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 8545807418 ps |
| CPU time | 5.68 seconds |
| Started | Oct 09 10:29:49 AM UTC 24 |
| Finished | Oct 09 10:29:55 AM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298066868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2298066868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2481873899 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1262576900 ps |
| CPU time | 5.51 seconds |
| Started | Oct 09 10:29:55 AM UTC 24 |
| Finished | Oct 09 10:30:02 AM UTC 24 |
| Peak memory | 231292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481873899 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.2481873899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.4239014868 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 87918333468 ps |
| CPU time | 285.18 seconds |
| Started | Oct 09 10:29:58 AM UTC 24 |
| Finished | Oct 09 10:34:47 AM UTC 24 |
| Peak memory | 268048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239014868 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.4239014868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.990324493 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 7810352338 ps |
| CPU time | 26.94 seconds |
| Started | Oct 09 10:29:46 AM UTC 24 |
| Finished | Oct 09 10:30:15 AM UTC 24 |
| Peak memory | 227736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990324493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.990324493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.2642931581 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 33350009964 ps |
| CPU time | 18.56 seconds |
| Started | Oct 09 10:29:45 AM UTC 24 |
| Finished | Oct 09 10:30:06 AM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642931581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2642931581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.3065060220 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 465162805 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 10:29:48 AM UTC 24 |
| Finished | Oct 09 10:29:54 AM UTC 24 |
| Peak memory | 227352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065060220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3065060220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3733924040 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 165567156 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 10:29:46 AM UTC 24 |
| Finished | Oct 09 10:29:49 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733924040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3733924040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.3877453106 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 899059785 ps |
| CPU time | 4.83 seconds |
| Started | Oct 09 10:29:50 AM UTC 24 |
| Finished | Oct 09 10:29:57 AM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877453106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3877453106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.2923601608 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 14268359 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:30:25 AM UTC 24 |
| Finished | Oct 09 10:30:27 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923601608 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.2923601608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.4258344412 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 331201352 ps |
| CPU time | 3.23 seconds |
| Started | Oct 09 10:30:15 AM UTC 24 |
| Finished | Oct 09 10:30:19 AM UTC 24 |
| Peak memory | 234704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258344412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4258344412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.2157074055 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 17347957 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:30:02 AM UTC 24 |
| Finished | Oct 09 10:30:04 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157074055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2157074055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.4155658890 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 22734441069 ps |
| CPU time | 117.91 seconds |
| Started | Oct 09 10:30:18 AM UTC 24 |
| Finished | Oct 09 10:32:19 AM UTC 24 |
| Peak memory | 267668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155658890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4155658890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.817576775 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 56119490107 ps |
| CPU time | 277.81 seconds |
| Started | Oct 09 10:30:20 AM UTC 24 |
| Finished | Oct 09 10:35:03 AM UTC 24 |
| Peak memory | 267728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817576775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.817576775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.4190879232 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 7510251421 ps |
| CPU time | 101.96 seconds |
| Started | Oct 09 10:30:22 AM UTC 24 |
| Finished | Oct 09 10:32:06 AM UTC 24 |
| Peak memory | 263756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190879232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.4190879232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2274475946 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3651237014 ps |
| CPU time | 26.22 seconds |
| Started | Oct 09 10:30:16 AM UTC 24 |
| Finished | Oct 09 10:30:44 AM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274475946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2274475946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1709382926 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 12088226638 ps |
| CPU time | 103.59 seconds |
| Started | Oct 09 10:30:16 AM UTC 24 |
| Finished | Oct 09 10:32:02 AM UTC 24 |
| Peak memory | 261508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709382926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.1709382926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.1612826288 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 118471375 ps |
| CPU time | 2.69 seconds |
| Started | Oct 09 10:30:12 AM UTC 24 |
| Finished | Oct 09 10:30:16 AM UTC 24 |
| Peak memory | 244892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612826288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1612826288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.1875110329 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 284453318 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 10:30:12 AM UTC 24 |
| Finished | Oct 09 10:30:16 AM UTC 24 |
| Peak memory | 229276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875110329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1875110329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2847118006 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 10813664095 ps |
| CPU time | 11.62 seconds |
| Started | Oct 09 10:30:11 AM UTC 24 |
| Finished | Oct 09 10:30:24 AM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847118006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.2847118006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.2964920529 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 48517268 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 10:30:09 AM UTC 24 |
| Finished | Oct 09 10:30:15 AM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964920529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2964920529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.2572984669 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 662550197 ps |
| CPU time | 8.58 seconds |
| Started | Oct 09 10:30:16 AM UTC 24 |
| Finished | Oct 09 10:30:26 AM UTC 24 |
| Peak memory | 233324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572984669 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.2572984669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.550046426 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 83656178 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 10:30:25 AM UTC 24 |
| Finished | Oct 09 10:30:27 AM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550046426 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.550046426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.328205056 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3879114775 ps |
| CPU time | 34 seconds |
| Started | Oct 09 10:30:05 AM UTC 24 |
| Finished | Oct 09 10:30:41 AM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328205056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.328205056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2182811200 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 9247465247 ps |
| CPU time | 7.3 seconds |
| Started | Oct 09 10:30:04 AM UTC 24 |
| Finished | Oct 09 10:30:13 AM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182811200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2182811200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.4021861108 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 162342630 ps |
| CPU time | 3.41 seconds |
| Started | Oct 09 10:30:06 AM UTC 24 |
| Finished | Oct 09 10:30:11 AM UTC 24 |
| Peak memory | 227388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021861108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4021861108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.3178337168 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 249025664 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 10:30:06 AM UTC 24 |
| Finished | Oct 09 10:30:09 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178337168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3178337168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.102331587 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 4329365270 ps |
| CPU time | 18.71 seconds |
| Started | Oct 09 10:30:14 AM UTC 24 |
| Finished | Oct 09 10:30:34 AM UTC 24 |
| Peak memory | 245132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102331587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.102331587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.1194480727 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 47899082 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:30:50 AM UTC 24 |
| Finished | Oct 09 10:30:52 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194480727 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.1194480727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2715383429 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 833738469 ps |
| CPU time | 4.96 seconds |
| Started | Oct 09 10:30:38 AM UTC 24 |
| Finished | Oct 09 10:30:44 AM UTC 24 |
| Peak memory | 244944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715383429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2715383429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.2904930417 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 50644200 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:30:26 AM UTC 24 |
| Finished | Oct 09 10:30:28 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904930417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2904930417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.4027960024 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 9063557699 ps |
| CPU time | 83.48 seconds |
| Started | Oct 09 10:30:41 AM UTC 24 |
| Finished | Oct 09 10:32:07 AM UTC 24 |
| Peak memory | 263512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027960024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4027960024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1302921696 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 24096588606 ps |
| CPU time | 100.72 seconds |
| Started | Oct 09 10:30:42 AM UTC 24 |
| Finished | Oct 09 10:32:26 AM UTC 24 |
| Peak memory | 261588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302921696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1302921696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.422840684 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 222315118 ps |
| CPU time | 11.46 seconds |
| Started | Oct 09 10:30:38 AM UTC 24 |
| Finished | Oct 09 10:30:51 AM UTC 24 |
| Peak memory | 234768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422840684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.422840684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.2286212860 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1894321887 ps |
| CPU time | 28.36 seconds |
| Started | Oct 09 10:30:38 AM UTC 24 |
| Finished | Oct 09 10:31:08 AM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286212860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.2286212860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3081180419 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 411214291 ps |
| CPU time | 4.89 seconds |
| Started | Oct 09 10:30:35 AM UTC 24 |
| Finished | Oct 09 10:30:41 AM UTC 24 |
| Peak memory | 244968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081180419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3081180419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.2289460396 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4673362571 ps |
| CPU time | 69.15 seconds |
| Started | Oct 09 10:30:35 AM UTC 24 |
| Finished | Oct 09 10:31:46 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289460396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2289460396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.455378135 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 284362457 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 10:30:34 AM UTC 24 |
| Finished | Oct 09 10:30:38 AM UTC 24 |
| Peak memory | 233236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455378135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.455378135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.317679369 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 275593259 ps |
| CPU time | 4.07 seconds |
| Started | Oct 09 10:30:31 AM UTC 24 |
| Finished | Oct 09 10:30:37 AM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317679369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.317679369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.846344997 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3107504250 ps |
| CPU time | 7.43 seconds |
| Started | Oct 09 10:30:41 AM UTC 24 |
| Finished | Oct 09 10:30:50 AM UTC 24 |
| Peak memory | 233564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846344997 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.846344997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.2539086784 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 24426545149 ps |
| CPU time | 123.41 seconds |
| Started | Oct 09 10:30:45 AM UTC 24 |
| Finished | Oct 09 10:32:50 AM UTC 24 |
| Peak memory | 267976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539086784 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.2539086784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.1439610084 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1920351973 ps |
| CPU time | 8.09 seconds |
| Started | Oct 09 10:30:28 AM UTC 24 |
| Finished | Oct 09 10:30:37 AM UTC 24 |
| Peak memory | 227656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439610084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1439610084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2021212424 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 16762401997 ps |
| CPU time | 19.43 seconds |
| Started | Oct 09 10:30:28 AM UTC 24 |
| Finished | Oct 09 10:30:49 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021212424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2021212424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.885095499 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 271421756 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 10:30:30 AM UTC 24 |
| Finished | Oct 09 10:30:35 AM UTC 24 |
| Peak memory | 227352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885095499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.885095499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.4153513502 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 107169713 ps |
| CPU time | 1.85 seconds |
| Started | Oct 09 10:30:29 AM UTC 24 |
| Finished | Oct 09 10:30:32 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153513502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4153513502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2383643620 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 566024975 ps |
| CPU time | 4.41 seconds |
| Started | Oct 09 10:30:36 AM UTC 24 |
| Finished | Oct 09 10:30:41 AM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383643620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2383643620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.3038018585 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 51149778 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:31:36 AM UTC 24 |
| Finished | Oct 09 10:31:38 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038018585 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.3038018585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.1507480636 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5878888898 ps |
| CPU time | 23.05 seconds |
| Started | Oct 09 10:31:07 AM UTC 24 |
| Finished | Oct 09 10:31:31 AM UTC 24 |
| Peak memory | 234784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507480636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1507480636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.2668964395 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 76268444 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:30:51 AM UTC 24 |
| Finished | Oct 09 10:30:53 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668964395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2668964395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.3921119091 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1567835605 ps |
| CPU time | 38.81 seconds |
| Started | Oct 09 10:31:17 AM UTC 24 |
| Finished | Oct 09 10:31:58 AM UTC 24 |
| Peak memory | 261332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921119091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3921119091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.173888002 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 38291896924 ps |
| CPU time | 291.4 seconds |
| Started | Oct 09 10:31:31 AM UTC 24 |
| Finished | Oct 09 10:36:27 AM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173888002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.173888002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.1520915213 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 23139223 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:31:33 AM UTC 24 |
| Finished | Oct 09 10:31:35 AM UTC 24 |
| Peak memory | 226820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520915213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.1520915213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.138482970 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2683719967 ps |
| CPU time | 39.54 seconds |
| Started | Oct 09 10:31:09 AM UTC 24 |
| Finished | Oct 09 10:31:50 AM UTC 24 |
| Peak memory | 249112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138482970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.138482970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.1648836338 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3017101314 ps |
| CPU time | 49.37 seconds |
| Started | Oct 09 10:31:14 AM UTC 24 |
| Finished | Oct 09 10:32:05 AM UTC 24 |
| Peak memory | 265488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648836338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.1648836338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.2515237929 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2233468488 ps |
| CPU time | 12.33 seconds |
| Started | Oct 09 10:31:00 AM UTC 24 |
| Finished | Oct 09 10:31:13 AM UTC 24 |
| Peak memory | 245028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515237929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2515237929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.251980640 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 14953486432 ps |
| CPU time | 71.81 seconds |
| Started | Oct 09 10:31:01 AM UTC 24 |
| Finished | Oct 09 10:32:14 AM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251980640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.251980640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1085660077 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 4375601168 ps |
| CPU time | 15.58 seconds |
| Started | Oct 09 10:31:00 AM UTC 24 |
| Finished | Oct 09 10:31:16 AM UTC 24 |
| Peak memory | 245020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085660077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.1085660077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3471544681 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 166245619 ps |
| CPU time | 3.82 seconds |
| Started | Oct 09 10:30:58 AM UTC 24 |
| Finished | Oct 09 10:31:04 AM UTC 24 |
| Peak memory | 234768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471544681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3471544681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.4000029357 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3749203541 ps |
| CPU time | 11.64 seconds |
| Started | Oct 09 10:31:17 AM UTC 24 |
| Finished | Oct 09 10:31:30 AM UTC 24 |
| Peak memory | 229192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000029357 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.4000029357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.1364411145 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 14215470807 ps |
| CPU time | 45.64 seconds |
| Started | Oct 09 10:30:54 AM UTC 24 |
| Finished | Oct 09 10:31:42 AM UTC 24 |
| Peak memory | 227672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364411145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1364411145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.1889355917 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 25465463 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:30:53 AM UTC 24 |
| Finished | Oct 09 10:30:55 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889355917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1889355917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.3759730082 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 237808933 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 10:30:56 AM UTC 24 |
| Finished | Oct 09 10:30:59 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759730082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3759730082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2969866051 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 273832829 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 10:30:55 AM UTC 24 |
| Finished | Oct 09 10:30:58 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969866051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2969866051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.478594937 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 566423583 ps |
| CPU time | 10.64 seconds |
| Started | Oct 09 10:31:05 AM UTC 24 |
| Finished | Oct 09 10:31:17 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478594937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.478594937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.3842567836 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 14850514 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 10:32:08 AM UTC 24 |
| Finished | Oct 09 10:32:10 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842567836 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3842567836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.60404623 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 410910745 ps |
| CPU time | 9.79 seconds |
| Started | Oct 09 10:31:53 AM UTC 24 |
| Finished | Oct 09 10:32:04 AM UTC 24 |
| Peak memory | 244952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60404623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.60404623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.2280669732 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 71884586 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:31:39 AM UTC 24 |
| Finished | Oct 09 10:31:41 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280669732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2280669732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.891824463 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3899828242 ps |
| CPU time | 33.7 seconds |
| Started | Oct 09 10:32:02 AM UTC 24 |
| Finished | Oct 09 10:32:38 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891824463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.891824463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.1939674549 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 10721375557 ps |
| CPU time | 126.12 seconds |
| Started | Oct 09 10:32:05 AM UTC 24 |
| Finished | Oct 09 10:34:14 AM UTC 24 |
| Peak memory | 267732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939674549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1939674549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.433370318 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 16373307272 ps |
| CPU time | 162.16 seconds |
| Started | Oct 09 10:32:07 AM UTC 24 |
| Finished | Oct 09 10:34:52 AM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433370318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.433370318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.1829288684 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2108204451 ps |
| CPU time | 19.76 seconds |
| Started | Oct 09 10:31:59 AM UTC 24 |
| Finished | Oct 09 10:32:20 AM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829288684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.1829288684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.1768776266 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2577802504 ps |
| CPU time | 16.06 seconds |
| Started | Oct 09 10:31:51 AM UTC 24 |
| Finished | Oct 09 10:32:08 AM UTC 24 |
| Peak memory | 234740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768776266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1768776266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.824567382 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3654250979 ps |
| CPU time | 31.94 seconds |
| Started | Oct 09 10:31:53 AM UTC 24 |
| Finished | Oct 09 10:32:26 AM UTC 24 |
| Peak memory | 245028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824567382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.824567382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1079889898 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4177588206 ps |
| CPU time | 16.13 seconds |
| Started | Oct 09 10:31:49 AM UTC 24 |
| Finished | Oct 09 10:32:06 AM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079889898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.1079889898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1158713221 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 8974454728 ps |
| CPU time | 28.89 seconds |
| Started | Oct 09 10:31:46 AM UTC 24 |
| Finished | Oct 09 10:32:17 AM UTC 24 |
| Peak memory | 234848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158713221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1158713221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.2292776549 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2112602611 ps |
| CPU time | 22.74 seconds |
| Started | Oct 09 10:32:01 AM UTC 24 |
| Finished | Oct 09 10:32:25 AM UTC 24 |
| Peak memory | 231292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292776549 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.2292776549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.4033548228 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 37574943987 ps |
| CPU time | 124.33 seconds |
| Started | Oct 09 10:32:07 AM UTC 24 |
| Finished | Oct 09 10:34:14 AM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033548228 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.4033548228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.4083885443 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 497556735 ps |
| CPU time | 7.73 seconds |
| Started | Oct 09 10:31:43 AM UTC 24 |
| Finished | Oct 09 10:31:52 AM UTC 24 |
| Peak memory | 227388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083885443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4083885443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2161434972 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 197871533 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 10:31:42 AM UTC 24 |
| Finished | Oct 09 10:31:45 AM UTC 24 |
| Peak memory | 217144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161434972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2161434972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.1745320638 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1289074129 ps |
| CPU time | 5.21 seconds |
| Started | Oct 09 10:31:45 AM UTC 24 |
| Finished | Oct 09 10:31:52 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745320638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1745320638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.3385042692 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 149002783 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 10:31:45 AM UTC 24 |
| Finished | Oct 09 10:31:48 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385042692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3385042692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.4126640963 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 5228175679 ps |
| CPU time | 29.04 seconds |
| Started | Oct 09 10:31:53 AM UTC 24 |
| Finished | Oct 09 10:32:24 AM UTC 24 |
| Peak memory | 234980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126640963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4126640963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.4278798345 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 10757640 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:32:27 AM UTC 24 |
| Finished | Oct 09 10:32:29 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278798345 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.4278798345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3609206421 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 55776748 ps |
| CPU time | 2.74 seconds |
| Started | Oct 09 10:32:18 AM UTC 24 |
| Finished | Oct 09 10:32:22 AM UTC 24 |
| Peak memory | 244944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609206421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3609206421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.1161559502 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 44768629 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:32:08 AM UTC 24 |
| Finished | Oct 09 10:32:10 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161559502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1161559502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1508724805 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 376560700570 ps |
| CPU time | 530.83 seconds |
| Started | Oct 09 10:32:22 AM UTC 24 |
| Finished | Oct 09 10:41:20 AM UTC 24 |
| Peak memory | 263512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508724805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1508724805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2918567088 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3230336427 ps |
| CPU time | 91.38 seconds |
| Started | Oct 09 10:32:22 AM UTC 24 |
| Finished | Oct 09 10:33:56 AM UTC 24 |
| Peak memory | 267672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918567088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2918567088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2012801206 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 6484049050 ps |
| CPU time | 115.33 seconds |
| Started | Oct 09 10:32:24 AM UTC 24 |
| Finished | Oct 09 10:34:22 AM UTC 24 |
| Peak memory | 267728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012801206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.2012801206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.3704159724 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 101425633 ps |
| CPU time | 4.42 seconds |
| Started | Oct 09 10:32:19 AM UTC 24 |
| Finished | Oct 09 10:32:24 AM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704159724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3704159724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.102181517 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 28902016150 ps |
| CPU time | 63.9 seconds |
| Started | Oct 09 10:32:20 AM UTC 24 |
| Finished | Oct 09 10:33:26 AM UTC 24 |
| Peak memory | 261520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102181517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.102181517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.3830570163 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 997857311 ps |
| CPU time | 5.21 seconds |
| Started | Oct 09 10:32:16 AM UTC 24 |
| Finished | Oct 09 10:32:22 AM UTC 24 |
| Peak memory | 245024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830570163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3830570163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.2706822979 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 4456957435 ps |
| CPU time | 31.82 seconds |
| Started | Oct 09 10:32:17 AM UTC 24 |
| Finished | Oct 09 10:32:50 AM UTC 24 |
| Peak memory | 245080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706822979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2706822979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3222985819 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2749586459 ps |
| CPU time | 14.51 seconds |
| Started | Oct 09 10:32:14 AM UTC 24 |
| Finished | Oct 09 10:32:30 AM UTC 24 |
| Peak memory | 234780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222985819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.3222985819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.94850594 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1958624739 ps |
| CPU time | 12.39 seconds |
| Started | Oct 09 10:32:12 AM UTC 24 |
| Finished | Oct 09 10:32:26 AM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94850594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.94850594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.271898332 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 688659952 ps |
| CPU time | 6.99 seconds |
| Started | Oct 09 10:32:21 AM UTC 24 |
| Finished | Oct 09 10:32:29 AM UTC 24 |
| Peak memory | 231368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271898332 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.271898332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.2405165546 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 37796911437 ps |
| CPU time | 72.17 seconds |
| Started | Oct 09 10:32:25 AM UTC 24 |
| Finished | Oct 09 10:33:40 AM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405165546 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.2405165546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.600540154 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 6524404715 ps |
| CPU time | 32.56 seconds |
| Started | Oct 09 10:32:11 AM UTC 24 |
| Finished | Oct 09 10:32:45 AM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600540154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.600540154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.4277353205 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 6265720198 ps |
| CPU time | 33.26 seconds |
| Started | Oct 09 10:32:10 AM UTC 24 |
| Finished | Oct 09 10:32:45 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277353205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4277353205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.2075412631 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 127122137 ps |
| CPU time | 3.63 seconds |
| Started | Oct 09 10:32:11 AM UTC 24 |
| Finished | Oct 09 10:32:16 AM UTC 24 |
| Peak memory | 227348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075412631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2075412631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.2146214399 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 76606112 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:32:11 AM UTC 24 |
| Finished | Oct 09 10:32:13 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146214399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2146214399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3789222747 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 922353355 ps |
| CPU time | 8.47 seconds |
| Started | Oct 09 10:32:18 AM UTC 24 |
| Finished | Oct 09 10:32:27 AM UTC 24 |
| Peak memory | 251040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789222747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3789222747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1927442254 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 35114673 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:32:45 AM UTC 24 |
| Finished | Oct 09 10:32:47 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927442254 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1927442254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2949281350 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3527018824 ps |
| CPU time | 7.51 seconds |
| Started | Oct 09 10:32:37 AM UTC 24 |
| Finished | Oct 09 10:32:45 AM UTC 24 |
| Peak memory | 243912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949281350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2949281350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.2045993917 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 52695061 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 10:32:27 AM UTC 24 |
| Finished | Oct 09 10:32:29 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045993917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2045993917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.2520796383 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 107795208292 ps |
| CPU time | 218.63 seconds |
| Started | Oct 09 10:32:40 AM UTC 24 |
| Finished | Oct 09 10:36:22 AM UTC 24 |
| Peak memory | 265624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520796383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2520796383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.1448126143 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 25804115740 ps |
| CPU time | 115.49 seconds |
| Started | Oct 09 10:32:42 AM UTC 24 |
| Finished | Oct 09 10:34:40 AM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448126143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1448126143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.849625596 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 55845074962 ps |
| CPU time | 212.32 seconds |
| Started | Oct 09 10:32:42 AM UTC 24 |
| Finished | Oct 09 10:36:18 AM UTC 24 |
| Peak memory | 267788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849625596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.849625596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.4204605449 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 38080844 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 10:32:38 AM UTC 24 |
| Finished | Oct 09 10:32:42 AM UTC 24 |
| Peak memory | 244904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204605449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4204605449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2802777748 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 160027169 ps |
| CPU time | 6.15 seconds |
| Started | Oct 09 10:32:31 AM UTC 24 |
| Finished | Oct 09 10:32:39 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802777748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2802777748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.2367058530 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1248882416 ps |
| CPU time | 17.77 seconds |
| Started | Oct 09 10:32:33 AM UTC 24 |
| Finished | Oct 09 10:32:52 AM UTC 24 |
| Peak memory | 234704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367058530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2367058530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.2292343058 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1547055449 ps |
| CPU time | 4.02 seconds |
| Started | Oct 09 10:32:30 AM UTC 24 |
| Finished | Oct 09 10:32:35 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292343058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.2292343058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.2501335572 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 12861860132 ps |
| CPU time | 45.61 seconds |
| Started | Oct 09 10:32:30 AM UTC 24 |
| Finished | Oct 09 10:33:17 AM UTC 24 |
| Peak memory | 261728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501335572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2501335572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.3340124815 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1615835163 ps |
| CPU time | 17.19 seconds |
| Started | Oct 09 10:32:39 AM UTC 24 |
| Finished | Oct 09 10:32:57 AM UTC 24 |
| Peak memory | 231244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340124815 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.3340124815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.978054780 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 282502365 ps |
| CPU time | 1.92 seconds |
| Started | Oct 09 10:32:45 AM UTC 24 |
| Finished | Oct 09 10:32:48 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978054780 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.978054780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.247175129 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 449361457 ps |
| CPU time | 11.82 seconds |
| Started | Oct 09 10:32:28 AM UTC 24 |
| Finished | Oct 09 10:32:41 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247175129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.247175129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1925030317 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2587823842 ps |
| CPU time | 8.55 seconds |
| Started | Oct 09 10:32:28 AM UTC 24 |
| Finished | Oct 09 10:32:38 AM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925030317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1925030317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.1069866571 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 526304059 ps |
| CPU time | 5.87 seconds |
| Started | Oct 09 10:32:30 AM UTC 24 |
| Finished | Oct 09 10:32:37 AM UTC 24 |
| Peak memory | 227352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069866571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1069866571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.2017155949 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 38292045 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 10:32:30 AM UTC 24 |
| Finished | Oct 09 10:32:32 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017155949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2017155949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.1401160099 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 4040502916 ps |
| CPU time | 8.55 seconds |
| Started | Oct 09 10:32:35 AM UTC 24 |
| Finished | Oct 09 10:32:44 AM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401160099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1401160099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.3518763291 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 28613379 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 10:24:26 AM UTC 24 |
| Finished | Oct 09 10:24:28 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518763291 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3518763291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3044327716 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 155070534 ps |
| CPU time | 4.09 seconds |
| Started | Oct 09 10:24:12 AM UTC 24 |
| Finished | Oct 09 10:24:17 AM UTC 24 |
| Peak memory | 234816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044327716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3044327716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.272896350 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 18165971 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:24:04 AM UTC 24 |
| Finished | Oct 09 10:24:06 AM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272896350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.272896350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2356228224 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 37467639207 ps |
| CPU time | 263.78 seconds |
| Started | Oct 09 10:24:21 AM UTC 24 |
| Finished | Oct 09 10:28:49 AM UTC 24 |
| Peak memory | 261596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356228224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2356228224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.3801377144 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 26819476 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:24:18 AM UTC 24 |
| Finished | Oct 09 10:24:20 AM UTC 24 |
| Peak memory | 226816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801377144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.3801377144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.485834484 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 696716950 ps |
| CPU time | 12.82 seconds |
| Started | Oct 09 10:24:10 AM UTC 24 |
| Finished | Oct 09 10:24:24 AM UTC 24 |
| Peak memory | 234684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485834484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.485834484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.192860834 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 26970682834 ps |
| CPU time | 82.04 seconds |
| Started | Oct 09 10:24:11 AM UTC 24 |
| Finished | Oct 09 10:25:35 AM UTC 24 |
| Peak memory | 245036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192860834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.192860834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2726162947 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4036175002 ps |
| CPU time | 12.43 seconds |
| Started | Oct 09 10:24:10 AM UTC 24 |
| Finished | Oct 09 10:24:24 AM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726162947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.2726162947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2229720932 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 22957446478 ps |
| CPU time | 14.78 seconds |
| Started | Oct 09 10:24:08 AM UTC 24 |
| Finished | Oct 09 10:24:24 AM UTC 24 |
| Peak memory | 234852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229720932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2229720932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3130335551 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 328500578 ps |
| CPU time | 7.39 seconds |
| Started | Oct 09 10:24:18 AM UTC 24 |
| Finished | Oct 09 10:24:27 AM UTC 24 |
| Peak memory | 233416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130335551 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.3130335551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.2030623675 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 39534440 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 10:24:25 AM UTC 24 |
| Finished | Oct 09 10:24:28 AM UTC 24 |
| Peak memory | 257076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030623675 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2030623675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1754504824 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 879411467 ps |
| CPU time | 4.35 seconds |
| Started | Oct 09 10:24:05 AM UTC 24 |
| Finished | Oct 09 10:24:10 AM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754504824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1754504824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3042795354 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 33756292 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:24:07 AM UTC 24 |
| Finished | Oct 09 10:24:09 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042795354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3042795354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.443557065 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 85962836 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:24:07 AM UTC 24 |
| Finished | Oct 09 10:24:09 AM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443557065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.443557065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.68876841 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2638220123 ps |
| CPU time | 14.08 seconds |
| Started | Oct 09 10:24:12 AM UTC 24 |
| Finished | Oct 09 10:24:27 AM UTC 24 |
| Peak memory | 234848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68876841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.68876841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.650036056 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 11781809 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:33:14 AM UTC 24 |
| Finished | Oct 09 10:33:17 AM UTC 24 |
| Peak memory | 213736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650036056 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.650036056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.640964721 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 182477484 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 10:32:55 AM UTC 24 |
| Finished | Oct 09 10:33:00 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640964721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.640964721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2129464373 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 54160342 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:32:47 AM UTC 24 |
| Finished | Oct 09 10:32:49 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129464373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2129464373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.3376889516 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 27604392994 ps |
| CPU time | 112.43 seconds |
| Started | Oct 09 10:33:01 AM UTC 24 |
| Finished | Oct 09 10:34:55 AM UTC 24 |
| Peak memory | 265556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376889516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3376889516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.344473153 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 69174114774 ps |
| CPU time | 706.1 seconds |
| Started | Oct 09 10:33:01 AM UTC 24 |
| Finished | Oct 09 10:44:56 AM UTC 24 |
| Peak memory | 284176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344473153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.344473153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.400027332 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 163068066976 ps |
| CPU time | 444.64 seconds |
| Started | Oct 09 10:33:06 AM UTC 24 |
| Finished | Oct 09 10:40:37 AM UTC 24 |
| Peak memory | 278024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400027332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.400027332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.806065958 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 247960694 ps |
| CPU time | 5.68 seconds |
| Started | Oct 09 10:32:58 AM UTC 24 |
| Finished | Oct 09 10:33:05 AM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806065958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.806065958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.2909195897 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 20547158917 ps |
| CPU time | 166.66 seconds |
| Started | Oct 09 10:32:59 AM UTC 24 |
| Finished | Oct 09 10:35:48 AM UTC 24 |
| Peak memory | 263752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909195897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.2909195897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.3300106940 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2190730243 ps |
| CPU time | 24.49 seconds |
| Started | Oct 09 10:32:52 AM UTC 24 |
| Finished | Oct 09 10:33:18 AM UTC 24 |
| Peak memory | 245028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300106940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3300106940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.239776066 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 7516097394 ps |
| CPU time | 34.42 seconds |
| Started | Oct 09 10:32:52 AM UTC 24 |
| Finished | Oct 09 10:33:28 AM UTC 24 |
| Peak memory | 245080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239776066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.239776066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.166165911 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 19749057851 ps |
| CPU time | 13.33 seconds |
| Started | Oct 09 10:32:51 AM UTC 24 |
| Finished | Oct 09 10:33:05 AM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166165911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.166165911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.874939142 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 267943304 ps |
| CPU time | 6.79 seconds |
| Started | Oct 09 10:32:51 AM UTC 24 |
| Finished | Oct 09 10:32:59 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874939142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.874939142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3713774316 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1029476865 ps |
| CPU time | 12.05 seconds |
| Started | Oct 09 10:33:00 AM UTC 24 |
| Finished | Oct 09 10:33:13 AM UTC 24 |
| Peak memory | 233336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713774316 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.3713774316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.3261676674 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 14624389957 ps |
| CPU time | 28.1 seconds |
| Started | Oct 09 10:32:49 AM UTC 24 |
| Finished | Oct 09 10:33:18 AM UTC 24 |
| Peak memory | 231576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261676674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3261676674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1195940024 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1941550282 ps |
| CPU time | 9.79 seconds |
| Started | Oct 09 10:32:47 AM UTC 24 |
| Finished | Oct 09 10:32:58 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195940024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1195940024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.2999888928 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 625409906 ps |
| CPU time | 3.41 seconds |
| Started | Oct 09 10:32:50 AM UTC 24 |
| Finished | Oct 09 10:32:54 AM UTC 24 |
| Peak memory | 227344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999888928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2999888928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.2268623946 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 109835743 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 10:32:49 AM UTC 24 |
| Finished | Oct 09 10:32:51 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268623946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2268623946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.2163603581 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 13170537273 ps |
| CPU time | 46.54 seconds |
| Started | Oct 09 10:32:53 AM UTC 24 |
| Finished | Oct 09 10:33:41 AM UTC 24 |
| Peak memory | 245020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163603581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2163603581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.2949095113 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 11030095 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 10:33:43 AM UTC 24 |
| Finished | Oct 09 10:33:45 AM UTC 24 |
| Peak memory | 213704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949095113 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.2949095113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.1003149679 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 219838308 ps |
| CPU time | 6.13 seconds |
| Started | Oct 09 10:33:29 AM UTC 24 |
| Finished | Oct 09 10:33:37 AM UTC 24 |
| Peak memory | 244952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003149679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1003149679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.600211236 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 24190214 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:33:17 AM UTC 24 |
| Finished | Oct 09 10:33:20 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600211236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.600211236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.3079433084 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 126977213512 ps |
| CPU time | 450.93 seconds |
| Started | Oct 09 10:33:38 AM UTC 24 |
| Finished | Oct 09 10:41:14 AM UTC 24 |
| Peak memory | 277752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079433084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3079433084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1886136345 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 14096993426 ps |
| CPU time | 99.07 seconds |
| Started | Oct 09 10:33:38 AM UTC 24 |
| Finished | Oct 09 10:35:19 AM UTC 24 |
| Peak memory | 267732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886136345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1886136345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3397557511 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 16874977372 ps |
| CPU time | 135.81 seconds |
| Started | Oct 09 10:33:41 AM UTC 24 |
| Finished | Oct 09 10:35:59 AM UTC 24 |
| Peak memory | 247244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397557511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.3397557511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.1219497791 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 10543582455 ps |
| CPU time | 55.92 seconds |
| Started | Oct 09 10:33:35 AM UTC 24 |
| Finished | Oct 09 10:34:33 AM UTC 24 |
| Peak memory | 261468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219497791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.1219497791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.418504035 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 236061276 ps |
| CPU time | 5.57 seconds |
| Started | Oct 09 10:33:26 AM UTC 24 |
| Finished | Oct 09 10:33:33 AM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418504035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.418504035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.2546086996 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1171265848 ps |
| CPU time | 13.54 seconds |
| Started | Oct 09 10:33:27 AM UTC 24 |
| Finished | Oct 09 10:33:42 AM UTC 24 |
| Peak memory | 245004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546086996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2546086996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.2257750706 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2094766463 ps |
| CPU time | 11.25 seconds |
| Started | Oct 09 10:33:24 AM UTC 24 |
| Finished | Oct 09 10:33:36 AM UTC 24 |
| Peak memory | 234656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257750706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.2257750706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.875267940 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1133840680 ps |
| CPU time | 4.64 seconds |
| Started | Oct 09 10:33:23 AM UTC 24 |
| Finished | Oct 09 10:33:29 AM UTC 24 |
| Peak memory | 234856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875267940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.875267940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.2600929871 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2987069759 ps |
| CPU time | 9.32 seconds |
| Started | Oct 09 10:33:38 AM UTC 24 |
| Finished | Oct 09 10:33:48 AM UTC 24 |
| Peak memory | 231372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600929871 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.2600929871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1576246010 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 39305545916 ps |
| CPU time | 403.5 seconds |
| Started | Oct 09 10:33:42 AM UTC 24 |
| Finished | Oct 09 10:40:31 AM UTC 24 |
| Peak memory | 294484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576246010 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.1576246010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2127828290 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2305644575 ps |
| CPU time | 46.69 seconds |
| Started | Oct 09 10:33:18 AM UTC 24 |
| Finished | Oct 09 10:34:07 AM UTC 24 |
| Peak memory | 227656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127828290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2127828290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2839368979 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1136502000 ps |
| CPU time | 5.89 seconds |
| Started | Oct 09 10:33:18 AM UTC 24 |
| Finished | Oct 09 10:33:25 AM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839368979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2839368979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.4276608978 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 41101433 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:33:21 AM UTC 24 |
| Finished | Oct 09 10:33:23 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276608978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4276608978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.1258198516 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 92331998 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:33:19 AM UTC 24 |
| Finished | Oct 09 10:33:22 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258198516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1258198516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.2806653250 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 544436655 ps |
| CPU time | 6.25 seconds |
| Started | Oct 09 10:33:29 AM UTC 24 |
| Finished | Oct 09 10:33:37 AM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806653250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2806653250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.1090082147 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 11345544 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:34:19 AM UTC 24 |
| Finished | Oct 09 10:34:21 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090082147 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.1090082147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.1285342986 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 271365894 ps |
| CPU time | 3.3 seconds |
| Started | Oct 09 10:34:00 AM UTC 24 |
| Finished | Oct 09 10:34:04 AM UTC 24 |
| Peak memory | 244952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285342986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1285342986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.3260514111 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 54356177 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:33:43 AM UTC 24 |
| Finished | Oct 09 10:33:45 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260514111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3260514111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.3161860065 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 26545019829 ps |
| CPU time | 245.8 seconds |
| Started | Oct 09 10:34:09 AM UTC 24 |
| Finished | Oct 09 10:38:18 AM UTC 24 |
| Peak memory | 261460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161860065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3161860065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2347737002 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 18720902720 ps |
| CPU time | 129.74 seconds |
| Started | Oct 09 10:34:15 AM UTC 24 |
| Finished | Oct 09 10:36:27 AM UTC 24 |
| Peak memory | 263952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347737002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.2347737002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.1397381546 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3490946428 ps |
| CPU time | 17.07 seconds |
| Started | Oct 09 10:34:05 AM UTC 24 |
| Finished | Oct 09 10:34:24 AM UTC 24 |
| Peak memory | 234760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397381546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1397381546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3111270427 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2541393421 ps |
| CPU time | 64.38 seconds |
| Started | Oct 09 10:34:05 AM UTC 24 |
| Finished | Oct 09 10:35:11 AM UTC 24 |
| Peak memory | 263440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111270427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.3111270427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2865797335 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 836165405 ps |
| CPU time | 9.93 seconds |
| Started | Oct 09 10:33:57 AM UTC 24 |
| Finished | Oct 09 10:34:08 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865797335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2865797335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.402460175 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 6474506806 ps |
| CPU time | 39.93 seconds |
| Started | Oct 09 10:33:57 AM UTC 24 |
| Finished | Oct 09 10:34:38 AM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402460175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.402460175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.4085223679 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 31196230 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 10:33:55 AM UTC 24 |
| Finished | Oct 09 10:33:59 AM UTC 24 |
| Peak memory | 244632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085223679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.4085223679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.2026083468 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3401788666 ps |
| CPU time | 30.61 seconds |
| Started | Oct 09 10:33:53 AM UTC 24 |
| Finished | Oct 09 10:34:25 AM UTC 24 |
| Peak memory | 244892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026083468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2026083468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.722213818 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1339513536 ps |
| CPU time | 7.31 seconds |
| Started | Oct 09 10:34:07 AM UTC 24 |
| Finished | Oct 09 10:34:16 AM UTC 24 |
| Peak memory | 233292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722213818 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.722213818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.932588735 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 21729873371 ps |
| CPU time | 145.4 seconds |
| Started | Oct 09 10:34:17 AM UTC 24 |
| Finished | Oct 09 10:36:45 AM UTC 24 |
| Peak memory | 278084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932588735 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.932588735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.3458301991 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 11065793059 ps |
| CPU time | 30.37 seconds |
| Started | Oct 09 10:33:46 AM UTC 24 |
| Finished | Oct 09 10:34:18 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458301991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3458301991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.4163109480 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 3101356924 ps |
| CPU time | 8.38 seconds |
| Started | Oct 09 10:33:46 AM UTC 24 |
| Finished | Oct 09 10:33:56 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163109480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4163109480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.2111879675 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 54593512 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 10:33:52 AM UTC 24 |
| Finished | Oct 09 10:33:54 AM UTC 24 |
| Peak memory | 216960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111879675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2111879675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3429310996 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 257107744 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 10:33:49 AM UTC 24 |
| Finished | Oct 09 10:33:52 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429310996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3429310996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.2459958826 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 320121537 ps |
| CPU time | 5.05 seconds |
| Started | Oct 09 10:33:58 AM UTC 24 |
| Finished | Oct 09 10:34:04 AM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459958826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2459958826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.3936558380 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 57499137 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:34:50 AM UTC 24 |
| Finished | Oct 09 10:34:52 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936558380 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.3936558380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.971221486 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2893750728 ps |
| CPU time | 15.41 seconds |
| Started | Oct 09 10:34:39 AM UTC 24 |
| Finished | Oct 09 10:34:56 AM UTC 24 |
| Peak memory | 245008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971221486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.971221486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2669214570 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 44776012 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:34:22 AM UTC 24 |
| Finished | Oct 09 10:34:24 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669214570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2669214570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.997761660 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2880901639 ps |
| CPU time | 98.55 seconds |
| Started | Oct 09 10:34:43 AM UTC 24 |
| Finished | Oct 09 10:36:24 AM UTC 24 |
| Peak memory | 279888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997761660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.997761660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.2712517709 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 6397830047 ps |
| CPU time | 54.79 seconds |
| Started | Oct 09 10:34:44 AM UTC 24 |
| Finished | Oct 09 10:35:41 AM UTC 24 |
| Peak memory | 261576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712517709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2712517709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.289357096 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 18299593899 ps |
| CPU time | 182.1 seconds |
| Started | Oct 09 10:34:48 AM UTC 24 |
| Finished | Oct 09 10:37:53 AM UTC 24 |
| Peak memory | 265808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289357096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.289357096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.3594582123 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 16149515664 ps |
| CPU time | 49.34 seconds |
| Started | Oct 09 10:34:40 AM UTC 24 |
| Finished | Oct 09 10:35:31 AM UTC 24 |
| Peak memory | 261464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594582123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3594582123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1284684554 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 6411685402 ps |
| CPU time | 132.84 seconds |
| Started | Oct 09 10:34:41 AM UTC 24 |
| Finished | Oct 09 10:36:56 AM UTC 24 |
| Peak memory | 267668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284684554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.1284684554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.1754267701 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1521924800 ps |
| CPU time | 8.47 seconds |
| Started | Oct 09 10:34:30 AM UTC 24 |
| Finished | Oct 09 10:34:39 AM UTC 24 |
| Peak memory | 234768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754267701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1754267701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.2703939513 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1814469349 ps |
| CPU time | 7.58 seconds |
| Started | Oct 09 10:34:35 AM UTC 24 |
| Finished | Oct 09 10:34:44 AM UTC 24 |
| Peak memory | 234708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703939513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2703939513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.3225687706 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2345413947 ps |
| CPU time | 11.02 seconds |
| Started | Oct 09 10:34:29 AM UTC 24 |
| Finished | Oct 09 10:34:41 AM UTC 24 |
| Peak memory | 234736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225687706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.3225687706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.139746930 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 880080356 ps |
| CPU time | 6.25 seconds |
| Started | Oct 09 10:34:29 AM UTC 24 |
| Finished | Oct 09 10:34:36 AM UTC 24 |
| Peak memory | 234632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139746930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.139746930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3670878835 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 142801338 ps |
| CPU time | 5.24 seconds |
| Started | Oct 09 10:34:42 AM UTC 24 |
| Finished | Oct 09 10:34:49 AM UTC 24 |
| Peak memory | 231292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670878835 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.3670878835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.3734798484 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 110852044795 ps |
| CPU time | 188.7 seconds |
| Started | Oct 09 10:34:49 AM UTC 24 |
| Finished | Oct 09 10:38:01 AM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734798484 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.3734798484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.1112675293 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 5605892353 ps |
| CPU time | 41 seconds |
| Started | Oct 09 10:34:24 AM UTC 24 |
| Finished | Oct 09 10:35:07 AM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112675293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1112675293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.740467699 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 187187554 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 10:34:23 AM UTC 24 |
| Finished | Oct 09 10:34:27 AM UTC 24 |
| Peak memory | 227268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740467699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.740467699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.583835256 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 108228728 ps |
| CPU time | 1.97 seconds |
| Started | Oct 09 10:34:25 AM UTC 24 |
| Finished | Oct 09 10:34:29 AM UTC 24 |
| Peak memory | 227112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583835256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.583835256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.673060038 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 62166242 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 10:34:25 AM UTC 24 |
| Finished | Oct 09 10:34:28 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673060038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.673060038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.1218930855 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 495370709 ps |
| CPU time | 4.33 seconds |
| Started | Oct 09 10:34:37 AM UTC 24 |
| Finished | Oct 09 10:34:42 AM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218930855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1218930855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.61299305 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 11995540 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:35:32 AM UTC 24 |
| Finished | Oct 09 10:35:34 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61299305 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.61299305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1153978115 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 542911600 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 10:35:08 AM UTC 24 |
| Finished | Oct 09 10:35:14 AM UTC 24 |
| Peak memory | 234660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153978115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1153978115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.2466337189 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 15601417 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:34:53 AM UTC 24 |
| Finished | Oct 09 10:34:55 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466337189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2466337189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.1863035644 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 71402213732 ps |
| CPU time | 494.07 seconds |
| Started | Oct 09 10:35:20 AM UTC 24 |
| Finished | Oct 09 10:43:40 AM UTC 24 |
| Peak memory | 279856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863035644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1863035644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.1740805955 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3440086004 ps |
| CPU time | 66.29 seconds |
| Started | Oct 09 10:35:22 AM UTC 24 |
| Finished | Oct 09 10:36:30 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740805955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1740805955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1723661544 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 8243080370 ps |
| CPU time | 62.21 seconds |
| Started | Oct 09 10:35:27 AM UTC 24 |
| Finished | Oct 09 10:36:31 AM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723661544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.1723661544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.147055868 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3806157604 ps |
| CPU time | 50.19 seconds |
| Started | Oct 09 10:35:12 AM UTC 24 |
| Finished | Oct 09 10:36:04 AM UTC 24 |
| Peak memory | 245016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147055868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.147055868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.149229567 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3314792977 ps |
| CPU time | 17.31 seconds |
| Started | Oct 09 10:35:12 AM UTC 24 |
| Finished | Oct 09 10:35:30 AM UTC 24 |
| Peak memory | 239752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149229567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.149229567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.4170223144 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 400591512 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 10:35:03 AM UTC 24 |
| Finished | Oct 09 10:35:07 AM UTC 24 |
| Peak memory | 233756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170223144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4170223144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.3118659702 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3931585905 ps |
| CPU time | 21.63 seconds |
| Started | Oct 09 10:35:04 AM UTC 24 |
| Finished | Oct 09 10:35:27 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118659702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3118659702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1490036946 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 319086684 ps |
| CPU time | 10.66 seconds |
| Started | Oct 09 10:34:59 AM UTC 24 |
| Finished | Oct 09 10:35:11 AM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490036946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.1490036946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3477863612 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 9653234108 ps |
| CPU time | 40.53 seconds |
| Started | Oct 09 10:34:56 AM UTC 24 |
| Finished | Oct 09 10:35:38 AM UTC 24 |
| Peak memory | 239748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477863612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3477863612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2297224438 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 403518589 ps |
| CPU time | 5.18 seconds |
| Started | Oct 09 10:35:15 AM UTC 24 |
| Finished | Oct 09 10:35:21 AM UTC 24 |
| Peak memory | 233352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297224438 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.2297224438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.3882489412 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 139592818125 ps |
| CPU time | 253.93 seconds |
| Started | Oct 09 10:35:32 AM UTC 24 |
| Finished | Oct 09 10:39:49 AM UTC 24 |
| Peak memory | 267924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882489412 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.3882489412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.835226501 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 9773683885 ps |
| CPU time | 67.17 seconds |
| Started | Oct 09 10:34:56 AM UTC 24 |
| Finished | Oct 09 10:36:05 AM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835226501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.835226501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.3098861096 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 13242389 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:34:53 AM UTC 24 |
| Finished | Oct 09 10:34:55 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098861096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3098861096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.3373032639 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 248752614 ps |
| CPU time | 4.15 seconds |
| Started | Oct 09 10:34:56 AM UTC 24 |
| Finished | Oct 09 10:35:02 AM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373032639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3373032639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.4193474821 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 63095222 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:34:56 AM UTC 24 |
| Finished | Oct 09 10:34:58 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193474821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4193474821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.2138456131 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 15254289902 ps |
| CPU time | 27.75 seconds |
| Started | Oct 09 10:35:08 AM UTC 24 |
| Finished | Oct 09 10:35:37 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138456131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2138456131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.1090337139 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 14885931 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 10:36:02 AM UTC 24 |
| Finished | Oct 09 10:36:04 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090337139 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.1090337139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3835376066 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 76579901 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 10:35:47 AM UTC 24 |
| Finished | Oct 09 10:35:51 AM UTC 24 |
| Peak memory | 244952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835376066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3835376066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.462146789 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 12791234 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:35:34 AM UTC 24 |
| Finished | Oct 09 10:35:36 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462146789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.462146789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.1176197293 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 26270269588 ps |
| CPU time | 220.66 seconds |
| Started | Oct 09 10:35:52 AM UTC 24 |
| Finished | Oct 09 10:39:36 AM UTC 24 |
| Peak memory | 261660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176197293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1176197293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.144621644 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 275913343 ps |
| CPU time | 9.65 seconds |
| Started | Oct 09 10:35:57 AM UTC 24 |
| Finished | Oct 09 10:36:08 AM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144621644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.144621644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.438130124 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 17247218190 ps |
| CPU time | 112.13 seconds |
| Started | Oct 09 10:35:59 AM UTC 24 |
| Finished | Oct 09 10:37:54 AM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438130124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.438130124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.2050745270 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 492418437 ps |
| CPU time | 8.13 seconds |
| Started | Oct 09 10:35:47 AM UTC 24 |
| Finished | Oct 09 10:35:56 AM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050745270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2050745270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.1040894522 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 19956058167 ps |
| CPU time | 89.37 seconds |
| Started | Oct 09 10:35:49 AM UTC 24 |
| Finished | Oct 09 10:37:20 AM UTC 24 |
| Peak memory | 261648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040894522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.1040894522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.3385133423 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 639967614 ps |
| CPU time | 7.36 seconds |
| Started | Oct 09 10:35:41 AM UTC 24 |
| Finished | Oct 09 10:35:50 AM UTC 24 |
| Peak memory | 245024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385133423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3385133423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.210451335 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 54327613 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 10:35:41 AM UTC 24 |
| Finished | Oct 09 10:35:46 AM UTC 24 |
| Peak memory | 244632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210451335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.210451335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3132236808 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 18315806750 ps |
| CPU time | 27.67 seconds |
| Started | Oct 09 10:35:40 AM UTC 24 |
| Finished | Oct 09 10:36:09 AM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132236808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3132236808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.3313330124 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 106655525 ps |
| CPU time | 3.33 seconds |
| Started | Oct 09 10:35:39 AM UTC 24 |
| Finished | Oct 09 10:35:44 AM UTC 24 |
| Peak memory | 234392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313330124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3313330124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2776878809 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 5154627552 ps |
| CPU time | 6 seconds |
| Started | Oct 09 10:35:51 AM UTC 24 |
| Finished | Oct 09 10:35:58 AM UTC 24 |
| Peak memory | 231420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776878809 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.2776878809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.2866999491 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 12690781014 ps |
| CPU time | 110.11 seconds |
| Started | Oct 09 10:36:00 AM UTC 24 |
| Finished | Oct 09 10:37:53 AM UTC 24 |
| Peak memory | 277972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866999491 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.2866999491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.282534086 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 4818006408 ps |
| CPU time | 29.97 seconds |
| Started | Oct 09 10:35:37 AM UTC 24 |
| Finished | Oct 09 10:36:08 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282534086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.282534086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1254806547 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3300020090 ps |
| CPU time | 9.38 seconds |
| Started | Oct 09 10:35:35 AM UTC 24 |
| Finished | Oct 09 10:35:45 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254806547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1254806547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.3420768846 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 122266107 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:35:38 AM UTC 24 |
| Finished | Oct 09 10:35:40 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420768846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3420768846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.164120347 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 15796980 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:35:37 AM UTC 24 |
| Finished | Oct 09 10:35:39 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164120347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.164120347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.3439537310 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 11644232086 ps |
| CPU time | 16.05 seconds |
| Started | Oct 09 10:35:45 AM UTC 24 |
| Finished | Oct 09 10:36:02 AM UTC 24 |
| Peak memory | 245132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439537310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3439537310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3195924619 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 25266832 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 10:36:23 AM UTC 24 |
| Finished | Oct 09 10:36:25 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195924619 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3195924619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.2513761629 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 748372781 ps |
| CPU time | 3.04 seconds |
| Started | Oct 09 10:36:17 AM UTC 24 |
| Finished | Oct 09 10:36:21 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513761629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2513761629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.804064589 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 50822470 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:36:05 AM UTC 24 |
| Finished | Oct 09 10:36:07 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804064589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.804064589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.432525271 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 11702275112 ps |
| CPU time | 40.38 seconds |
| Started | Oct 09 10:36:19 AM UTC 24 |
| Finished | Oct 09 10:37:01 AM UTC 24 |
| Peak memory | 234840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432525271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.432525271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.1421043368 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 17687543756 ps |
| CPU time | 152.72 seconds |
| Started | Oct 09 10:36:20 AM UTC 24 |
| Finished | Oct 09 10:38:55 AM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421043368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1421043368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2907380589 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 7394842546 ps |
| CPU time | 49.02 seconds |
| Started | Oct 09 10:36:21 AM UTC 24 |
| Finished | Oct 09 10:37:12 AM UTC 24 |
| Peak memory | 263820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907380589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.2907380589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.247834037 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 734446939 ps |
| CPU time | 11.89 seconds |
| Started | Oct 09 10:36:18 AM UTC 24 |
| Finished | Oct 09 10:36:31 AM UTC 24 |
| Peak memory | 234728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247834037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.247834037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.2487837808 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 108857445964 ps |
| CPU time | 203.91 seconds |
| Started | Oct 09 10:36:19 AM UTC 24 |
| Finished | Oct 09 10:39:46 AM UTC 24 |
| Peak memory | 267808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487837808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.2487837808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2651261190 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 17098342277 ps |
| CPU time | 9.72 seconds |
| Started | Oct 09 10:36:11 AM UTC 24 |
| Finished | Oct 09 10:36:22 AM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651261190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2651261190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.2703596883 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3507817433 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 10:36:11 AM UTC 24 |
| Finished | Oct 09 10:36:18 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703596883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2703596883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.3352446742 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3751563329 ps |
| CPU time | 25.07 seconds |
| Started | Oct 09 10:36:10 AM UTC 24 |
| Finished | Oct 09 10:36:37 AM UTC 24 |
| Peak memory | 244968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352446742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.3352446742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.521035161 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 796298131 ps |
| CPU time | 8.2 seconds |
| Started | Oct 09 10:36:09 AM UTC 24 |
| Finished | Oct 09 10:36:18 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521035161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.521035161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.1385768178 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1951085861 ps |
| CPU time | 6.72 seconds |
| Started | Oct 09 10:36:19 AM UTC 24 |
| Finished | Oct 09 10:36:27 AM UTC 24 |
| Peak memory | 233588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385768178 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.1385768178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2805629717 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 28896059093 ps |
| CPU time | 266.11 seconds |
| Started | Oct 09 10:36:22 AM UTC 24 |
| Finished | Oct 09 10:40:53 AM UTC 24 |
| Peak memory | 265744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805629717 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2805629717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.1099217625 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 3460429503 ps |
| CPU time | 3.82 seconds |
| Started | Oct 09 10:36:06 AM UTC 24 |
| Finished | Oct 09 10:36:11 AM UTC 24 |
| Peak memory | 227644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099217625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1099217625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.304019092 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 2145028477 ps |
| CPU time | 10.38 seconds |
| Started | Oct 09 10:36:06 AM UTC 24 |
| Finished | Oct 09 10:36:17 AM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304019092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.304019092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.1329306821 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 44691598 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 10:36:09 AM UTC 24 |
| Finished | Oct 09 10:36:12 AM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329306821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1329306821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.1654216511 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1178069512 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 10:36:08 AM UTC 24 |
| Finished | Oct 09 10:36:10 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654216511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1654216511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.876604901 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 446289009 ps |
| CPU time | 4.01 seconds |
| Started | Oct 09 10:36:13 AM UTC 24 |
| Finished | Oct 09 10:36:19 AM UTC 24 |
| Peak memory | 234660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876604901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.876604901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.2376993372 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 13356431 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 10:36:46 AM UTC 24 |
| Finished | Oct 09 10:36:48 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376993372 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.2376993372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.2540482083 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 57821854 ps |
| CPU time | 3.14 seconds |
| Started | Oct 09 10:36:32 AM UTC 24 |
| Finished | Oct 09 10:36:37 AM UTC 24 |
| Peak memory | 244628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540482083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2540482083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.2295610067 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 84200466 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:36:25 AM UTC 24 |
| Finished | Oct 09 10:36:28 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295610067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2295610067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.3153414721 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 107227880072 ps |
| CPU time | 591.99 seconds |
| Started | Oct 09 10:36:38 AM UTC 24 |
| Finished | Oct 09 10:46:38 AM UTC 24 |
| Peak memory | 257364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153414721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3153414721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.689704548 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 24739941987 ps |
| CPU time | 253.63 seconds |
| Started | Oct 09 10:36:38 AM UTC 24 |
| Finished | Oct 09 10:40:55 AM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689704548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.689704548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.2682448966 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2664556988 ps |
| CPU time | 89.74 seconds |
| Started | Oct 09 10:36:39 AM UTC 24 |
| Finished | Oct 09 10:38:11 AM UTC 24 |
| Peak memory | 261640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682448966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.2682448966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.25474244 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 6345614960 ps |
| CPU time | 105.86 seconds |
| Started | Oct 09 10:36:32 AM UTC 24 |
| Finished | Oct 09 10:38:21 AM UTC 24 |
| Peak memory | 247196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25474244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.25474244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.86057847 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 14038168501 ps |
| CPU time | 113.62 seconds |
| Started | Oct 09 10:36:34 AM UTC 24 |
| Finished | Oct 09 10:38:30 AM UTC 24 |
| Peak memory | 263508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86057847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.86057847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.980527861 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1160984311 ps |
| CPU time | 14.58 seconds |
| Started | Oct 09 10:36:31 AM UTC 24 |
| Finished | Oct 09 10:36:47 AM UTC 24 |
| Peak memory | 234864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980527861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.980527861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.748731351 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 58561997 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 10:36:31 AM UTC 24 |
| Finished | Oct 09 10:36:36 AM UTC 24 |
| Peak memory | 244628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748731351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.748731351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.2398500884 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1198477856 ps |
| CPU time | 10.28 seconds |
| Started | Oct 09 10:36:31 AM UTC 24 |
| Finished | Oct 09 10:36:42 AM UTC 24 |
| Peak memory | 244904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398500884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.2398500884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.4154143473 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 100794136 ps |
| CPU time | 3.47 seconds |
| Started | Oct 09 10:36:29 AM UTC 24 |
| Finished | Oct 09 10:36:33 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154143473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4154143473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2239084539 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2850812410 ps |
| CPU time | 10.91 seconds |
| Started | Oct 09 10:36:37 AM UTC 24 |
| Finished | Oct 09 10:36:49 AM UTC 24 |
| Peak memory | 233624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239084539 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.2239084539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.684458504 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 149747440156 ps |
| CPU time | 326.48 seconds |
| Started | Oct 09 10:36:43 AM UTC 24 |
| Finished | Oct 09 10:42:14 AM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684458504 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.684458504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1686413714 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1938672761 ps |
| CPU time | 39.8 seconds |
| Started | Oct 09 10:36:28 AM UTC 24 |
| Finished | Oct 09 10:37:09 AM UTC 24 |
| Peak memory | 226388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686413714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1686413714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.371080017 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 6137274477 ps |
| CPU time | 22.91 seconds |
| Started | Oct 09 10:36:27 AM UTC 24 |
| Finished | Oct 09 10:36:51 AM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371080017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.371080017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1232382354 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 125603595 ps |
| CPU time | 2.61 seconds |
| Started | Oct 09 10:36:28 AM UTC 24 |
| Finished | Oct 09 10:36:32 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232382354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1232382354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2602022550 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 129676245 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 10:36:28 AM UTC 24 |
| Finished | Oct 09 10:36:30 AM UTC 24 |
| Peak memory | 213704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602022550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2602022550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.2330889569 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 6179751901 ps |
| CPU time | 12.42 seconds |
| Started | Oct 09 10:36:32 AM UTC 24 |
| Finished | Oct 09 10:36:46 AM UTC 24 |
| Peak memory | 234976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330889569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2330889569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.3690794017 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 14990581 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:37:16 AM UTC 24 |
| Finished | Oct 09 10:37:18 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690794017 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.3690794017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.3562871637 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 547716201 ps |
| CPU time | 5.2 seconds |
| Started | Oct 09 10:37:01 AM UTC 24 |
| Finished | Oct 09 10:37:07 AM UTC 24 |
| Peak memory | 245096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562871637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3562871637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.3672136833 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 67743963 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:36:47 AM UTC 24 |
| Finished | Oct 09 10:36:49 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672136833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3672136833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.3645248964 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 7820744051 ps |
| CPU time | 81.42 seconds |
| Started | Oct 09 10:37:10 AM UTC 24 |
| Finished | Oct 09 10:38:33 AM UTC 24 |
| Peak memory | 263520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645248964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3645248964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1438841264 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 643543112 ps |
| CPU time | 23.18 seconds |
| Started | Oct 09 10:37:13 AM UTC 24 |
| Finished | Oct 09 10:37:37 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438841264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1438841264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.622923633 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1700403879 ps |
| CPU time | 26.04 seconds |
| Started | Oct 09 10:37:15 AM UTC 24 |
| Finished | Oct 09 10:37:42 AM UTC 24 |
| Peak memory | 233752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622923633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.622923633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.4156544383 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 212952283 ps |
| CPU time | 6.03 seconds |
| Started | Oct 09 10:37:07 AM UTC 24 |
| Finished | Oct 09 10:37:15 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156544383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4156544383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3337277407 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 6842026383 ps |
| CPU time | 73.41 seconds |
| Started | Oct 09 10:37:07 AM UTC 24 |
| Finished | Oct 09 10:38:23 AM UTC 24 |
| Peak memory | 261460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337277407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.3337277407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.2347364843 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 713481743 ps |
| CPU time | 9.85 seconds |
| Started | Oct 09 10:36:54 AM UTC 24 |
| Finished | Oct 09 10:37:06 AM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347364843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2347364843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.2755904392 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 523591627 ps |
| CPU time | 8.06 seconds |
| Started | Oct 09 10:36:57 AM UTC 24 |
| Finished | Oct 09 10:37:06 AM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755904392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2755904392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.1908476284 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 814584041 ps |
| CPU time | 4.96 seconds |
| Started | Oct 09 10:36:53 AM UTC 24 |
| Finished | Oct 09 10:36:59 AM UTC 24 |
| Peak memory | 234848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908476284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.1908476284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.305382627 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 3753146708 ps |
| CPU time | 20.6 seconds |
| Started | Oct 09 10:36:52 AM UTC 24 |
| Finished | Oct 09 10:37:14 AM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305382627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.305382627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.3453728869 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 900606279 ps |
| CPU time | 11.32 seconds |
| Started | Oct 09 10:37:08 AM UTC 24 |
| Finished | Oct 09 10:37:21 AM UTC 24 |
| Peak memory | 231284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453728869 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.3453728869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.11427874 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 19330579557 ps |
| CPU time | 256.72 seconds |
| Started | Oct 09 10:37:15 AM UTC 24 |
| Finished | Oct 09 10:41:35 AM UTC 24 |
| Peak memory | 263700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11427874 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.11427874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.2681155203 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 6917802753 ps |
| CPU time | 62.98 seconds |
| Started | Oct 09 10:36:49 AM UTC 24 |
| Finished | Oct 09 10:37:54 AM UTC 24 |
| Peak memory | 227672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681155203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2681155203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.1682905685 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 27080633976 ps |
| CPU time | 23.56 seconds |
| Started | Oct 09 10:36:48 AM UTC 24 |
| Finished | Oct 09 10:37:14 AM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682905685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1682905685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.1718467447 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 211691841 ps |
| CPU time | 1.48 seconds |
| Started | Oct 09 10:36:51 AM UTC 24 |
| Finished | Oct 09 10:36:53 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718467447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1718467447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.2826724778 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 35659684 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 10:36:49 AM UTC 24 |
| Finished | Oct 09 10:36:52 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826724778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2826724778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.1260619128 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 10020960106 ps |
| CPU time | 13.55 seconds |
| Started | Oct 09 10:37:00 AM UTC 24 |
| Finished | Oct 09 10:37:15 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260619128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1260619128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.396284861 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 11985738 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:37:47 AM UTC 24 |
| Finished | Oct 09 10:37:49 AM UTC 24 |
| Peak memory | 213736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396284861 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.396284861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.766237714 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 227142606 ps |
| CPU time | 5.95 seconds |
| Started | Oct 09 10:37:36 AM UTC 24 |
| Finished | Oct 09 10:37:43 AM UTC 24 |
| Peak memory | 234856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766237714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.766237714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.454301244 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 47924433 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:37:16 AM UTC 24 |
| Finished | Oct 09 10:37:18 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454301244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.454301244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.741024705 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 21795625115 ps |
| CPU time | 181.59 seconds |
| Started | Oct 09 10:37:39 AM UTC 24 |
| Finished | Oct 09 10:40:44 AM UTC 24 |
| Peak memory | 277848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741024705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.741024705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.791338630 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 33089228519 ps |
| CPU time | 135.27 seconds |
| Started | Oct 09 10:37:42 AM UTC 24 |
| Finished | Oct 09 10:40:00 AM UTC 24 |
| Peak memory | 267792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791338630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.791338630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1165211983 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2250965439 ps |
| CPU time | 63.21 seconds |
| Started | Oct 09 10:37:43 AM UTC 24 |
| Finished | Oct 09 10:38:48 AM UTC 24 |
| Peak memory | 263564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165211983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.1165211983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.450483515 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1195677282 ps |
| CPU time | 8.87 seconds |
| Started | Oct 09 10:37:36 AM UTC 24 |
| Finished | Oct 09 10:37:46 AM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450483515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.450483515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.4041275909 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 23441720266 ps |
| CPU time | 107.39 seconds |
| Started | Oct 09 10:37:37 AM UTC 24 |
| Finished | Oct 09 10:39:27 AM UTC 24 |
| Peak memory | 265544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041275909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.4041275909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.1390237243 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 42062535 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 10:37:26 AM UTC 24 |
| Finished | Oct 09 10:37:30 AM UTC 24 |
| Peak memory | 234064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390237243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1390237243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.2025848550 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 25359899199 ps |
| CPU time | 69.65 seconds |
| Started | Oct 09 10:37:31 AM UTC 24 |
| Finished | Oct 09 10:38:42 AM UTC 24 |
| Peak memory | 245024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025848550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2025848550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.384915622 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1178353168 ps |
| CPU time | 7.99 seconds |
| Started | Oct 09 10:37:26 AM UTC 24 |
| Finished | Oct 09 10:37:35 AM UTC 24 |
| Peak memory | 234784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384915622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.384915622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.4286205284 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 889210751 ps |
| CPU time | 7.31 seconds |
| Started | Oct 09 10:37:24 AM UTC 24 |
| Finished | Oct 09 10:37:33 AM UTC 24 |
| Peak memory | 234656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286205284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4286205284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2679000386 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 5122611106 ps |
| CPU time | 15.27 seconds |
| Started | Oct 09 10:37:38 AM UTC 24 |
| Finished | Oct 09 10:37:55 AM UTC 24 |
| Peak memory | 234628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679000386 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.2679000386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.1004203791 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 43122174282 ps |
| CPU time | 174.94 seconds |
| Started | Oct 09 10:37:46 AM UTC 24 |
| Finished | Oct 09 10:40:44 AM UTC 24 |
| Peak memory | 278164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004203791 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.1004203791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.1127834306 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 250355192 ps |
| CPU time | 4.28 seconds |
| Started | Oct 09 10:37:19 AM UTC 24 |
| Finished | Oct 09 10:37:24 AM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127834306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1127834306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.1348104393 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1054712360 ps |
| CPU time | 14.63 seconds |
| Started | Oct 09 10:37:19 AM UTC 24 |
| Finished | Oct 09 10:37:35 AM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348104393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1348104393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.3256333814 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 14991687 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:37:22 AM UTC 24 |
| Finished | Oct 09 10:37:25 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256333814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3256333814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2196406432 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 166122136 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:37:21 AM UTC 24 |
| Finished | Oct 09 10:37:24 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196406432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2196406432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.3945923939 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 36834238 ps |
| CPU time | 3.39 seconds |
| Started | Oct 09 10:37:34 AM UTC 24 |
| Finished | Oct 09 10:37:38 AM UTC 24 |
| Peak memory | 245016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945923939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3945923939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3595088547 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 159909381 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:24:44 AM UTC 24 |
| Finished | Oct 09 10:24:46 AM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595088547 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3595088547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.4080196094 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 359888660 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 10:24:34 AM UTC 24 |
| Finished | Oct 09 10:24:39 AM UTC 24 |
| Peak memory | 245084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080196094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4080196094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.451240751 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 37736845 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:24:27 AM UTC 24 |
| Finished | Oct 09 10:24:29 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451240751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.451240751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.3128811913 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 177453517053 ps |
| CPU time | 647.22 seconds |
| Started | Oct 09 10:24:40 AM UTC 24 |
| Finished | Oct 09 10:35:36 AM UTC 24 |
| Peak memory | 280012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128811913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.3128811913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.3998044974 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1630487742 ps |
| CPU time | 4.75 seconds |
| Started | Oct 09 10:24:35 AM UTC 24 |
| Finished | Oct 09 10:24:40 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998044974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3998044974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.2233004883 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3656390170 ps |
| CPU time | 46.68 seconds |
| Started | Oct 09 10:24:30 AM UTC 24 |
| Finished | Oct 09 10:25:19 AM UTC 24 |
| Peak memory | 234776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233004883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2233004883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.4212564826 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2613624312 ps |
| CPU time | 37.11 seconds |
| Started | Oct 09 10:24:32 AM UTC 24 |
| Finished | Oct 09 10:25:11 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212564826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4212564826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2518279691 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 23982032439 ps |
| CPU time | 22.31 seconds |
| Started | Oct 09 10:24:30 AM UTC 24 |
| Finished | Oct 09 10:24:54 AM UTC 24 |
| Peak memory | 234792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518279691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.2518279691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3357798407 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 7383374518 ps |
| CPU time | 35.57 seconds |
| Started | Oct 09 10:24:29 AM UTC 24 |
| Finished | Oct 09 10:25:06 AM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357798407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3357798407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.1900489338 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 221265464 ps |
| CPU time | 5.99 seconds |
| Started | Oct 09 10:24:38 AM UTC 24 |
| Finished | Oct 09 10:24:45 AM UTC 24 |
| Peak memory | 233408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900489338 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.1900489338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2617034037 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 222732335 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 10:24:44 AM UTC 24 |
| Finished | Oct 09 10:24:47 AM UTC 24 |
| Peak memory | 257072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617034037 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2617034037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.3287793736 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 210740064 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 10:24:41 AM UTC 24 |
| Finished | Oct 09 10:24:44 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287793736 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.3287793736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2371005696 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 17589623808 ps |
| CPU time | 18.75 seconds |
| Started | Oct 09 10:24:28 AM UTC 24 |
| Finished | Oct 09 10:24:48 AM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371005696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2371005696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2346121434 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 304713537 ps |
| CPU time | 4.15 seconds |
| Started | Oct 09 10:24:28 AM UTC 24 |
| Finished | Oct 09 10:24:33 AM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346121434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2346121434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3705482498 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 47391398 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 10:24:29 AM UTC 24 |
| Finished | Oct 09 10:24:33 AM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705482498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3705482498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3162208560 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 91290656 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:24:29 AM UTC 24 |
| Finished | Oct 09 10:24:31 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162208560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3162208560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1584302572 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 133831089 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 10:24:32 AM UTC 24 |
| Finished | Oct 09 10:24:37 AM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584302572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1584302572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.4009808321 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 88101312 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:38:16 AM UTC 24 |
| Finished | Oct 09 10:38:19 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009808321 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.4009808321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.101836522 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 116602068 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 10:38:01 AM UTC 24 |
| Finished | Oct 09 10:38:05 AM UTC 24 |
| Peak memory | 234664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101836522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.101836522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.1229615211 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 50370602 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:37:50 AM UTC 24 |
| Finished | Oct 09 10:37:52 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229615211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1229615211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.3194290380 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 15652450108 ps |
| CPU time | 60.58 seconds |
| Started | Oct 09 10:38:06 AM UTC 24 |
| Finished | Oct 09 10:39:08 AM UTC 24 |
| Peak memory | 267604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194290380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3194290380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2582386093 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 90395957943 ps |
| CPU time | 202.04 seconds |
| Started | Oct 09 10:38:09 AM UTC 24 |
| Finished | Oct 09 10:41:34 AM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582386093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2582386093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2026135101 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5357305464 ps |
| CPU time | 91.98 seconds |
| Started | Oct 09 10:38:11 AM UTC 24 |
| Finished | Oct 09 10:39:45 AM UTC 24 |
| Peak memory | 277968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026135101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.2026135101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.3696929033 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 318330544 ps |
| CPU time | 12.8 seconds |
| Started | Oct 09 10:38:02 AM UTC 24 |
| Finished | Oct 09 10:38:16 AM UTC 24 |
| Peak memory | 261528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696929033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3696929033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2102321081 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1471613521 ps |
| CPU time | 46.2 seconds |
| Started | Oct 09 10:38:04 AM UTC 24 |
| Finished | Oct 09 10:38:52 AM UTC 24 |
| Peak memory | 267532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102321081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.2102321081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.3981405454 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 537751962 ps |
| CPU time | 9.49 seconds |
| Started | Oct 09 10:37:57 AM UTC 24 |
| Finished | Oct 09 10:38:08 AM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981405454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3981405454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.1599762830 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2507736955 ps |
| CPU time | 17.91 seconds |
| Started | Oct 09 10:37:58 AM UTC 24 |
| Finished | Oct 09 10:38:18 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599762830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1599762830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.381027082 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 227495541 ps |
| CPU time | 6.21 seconds |
| Started | Oct 09 10:37:55 AM UTC 24 |
| Finished | Oct 09 10:38:03 AM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381027082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.381027082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.390542131 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 79099828 ps |
| CPU time | 3.58 seconds |
| Started | Oct 09 10:37:55 AM UTC 24 |
| Finished | Oct 09 10:38:00 AM UTC 24 |
| Peak memory | 234700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390542131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.390542131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.3378045617 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3872659636 ps |
| CPU time | 15.76 seconds |
| Started | Oct 09 10:38:05 AM UTC 24 |
| Finished | Oct 09 10:38:22 AM UTC 24 |
| Peak memory | 233448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378045617 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.3378045617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.1497184104 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1479341323 ps |
| CPU time | 11.26 seconds |
| Started | Oct 09 10:38:15 AM UTC 24 |
| Finished | Oct 09 10:38:28 AM UTC 24 |
| Peak memory | 233868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497184104 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.1497184104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.875044758 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 21716760888 ps |
| CPU time | 20.99 seconds |
| Started | Oct 09 10:37:54 AM UTC 24 |
| Finished | Oct 09 10:38:16 AM UTC 24 |
| Peak memory | 231636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875044758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.875044758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.323122201 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 397160175 ps |
| CPU time | 3.49 seconds |
| Started | Oct 09 10:37:53 AM UTC 24 |
| Finished | Oct 09 10:37:57 AM UTC 24 |
| Peak memory | 227336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323122201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.323122201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.2798928391 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 72837503 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 10:37:55 AM UTC 24 |
| Finished | Oct 09 10:37:58 AM UTC 24 |
| Peak memory | 216960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798928391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2798928391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1275697402 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 10684311 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:37:54 AM UTC 24 |
| Finished | Oct 09 10:37:56 AM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275697402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1275697402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.201890638 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 439113161 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 10:37:59 AM UTC 24 |
| Finished | Oct 09 10:38:04 AM UTC 24 |
| Peak memory | 244972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201890638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.201890638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.3585605295 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 46434211 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:38:34 AM UTC 24 |
| Finished | Oct 09 10:38:36 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585605295 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.3585605295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.3948071667 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 995009350 ps |
| CPU time | 7.26 seconds |
| Started | Oct 09 10:38:28 AM UTC 24 |
| Finished | Oct 09 10:38:36 AM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948071667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3948071667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.1166485981 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 107793766 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:38:18 AM UTC 24 |
| Finished | Oct 09 10:38:20 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166485981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1166485981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.3266782552 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 733282922 ps |
| CPU time | 13.43 seconds |
| Started | Oct 09 10:38:31 AM UTC 24 |
| Finished | Oct 09 10:38:46 AM UTC 24 |
| Peak memory | 234732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266782552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3266782552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.695549450 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 6061645035 ps |
| CPU time | 80.29 seconds |
| Started | Oct 09 10:38:32 AM UTC 24 |
| Finished | Oct 09 10:39:54 AM UTC 24 |
| Peak memory | 249296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695549450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.695549450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2266201563 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4875493577 ps |
| CPU time | 73.79 seconds |
| Started | Oct 09 10:38:33 AM UTC 24 |
| Finished | Oct 09 10:39:49 AM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266201563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.2266201563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.195387286 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 156378664 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 10:38:29 AM UTC 24 |
| Finished | Oct 09 10:38:34 AM UTC 24 |
| Peak memory | 229664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195387286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.195387286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.3994444569 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 13814676357 ps |
| CPU time | 160.1 seconds |
| Started | Oct 09 10:38:29 AM UTC 24 |
| Finished | Oct 09 10:41:12 AM UTC 24 |
| Peak memory | 261668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994444569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.3994444569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.2718001008 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 54093135 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 10:38:23 AM UTC 24 |
| Finished | Oct 09 10:38:27 AM UTC 24 |
| Peak memory | 234068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718001008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2718001008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.3962646759 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1592694384 ps |
| CPU time | 6.52 seconds |
| Started | Oct 09 10:38:24 AM UTC 24 |
| Finished | Oct 09 10:38:32 AM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962646759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3962646759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.3572335176 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 188667849 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 10:38:23 AM UTC 24 |
| Finished | Oct 09 10:38:28 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572335176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.3572335176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2714464215 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 31334409 ps |
| CPU time | 3.06 seconds |
| Started | Oct 09 10:38:22 AM UTC 24 |
| Finished | Oct 09 10:38:26 AM UTC 24 |
| Peak memory | 244648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714464215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2714464215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.3392255059 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 236925456 ps |
| CPU time | 8.2 seconds |
| Started | Oct 09 10:38:29 AM UTC 24 |
| Finished | Oct 09 10:38:38 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392255059 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.3392255059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.1614824673 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 96539427269 ps |
| CPU time | 903.39 seconds |
| Started | Oct 09 10:38:34 AM UTC 24 |
| Finished | Oct 09 10:53:49 AM UTC 24 |
| Peak memory | 278028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614824673 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.1614824673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.644921944 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4121149447 ps |
| CPU time | 19.73 seconds |
| Started | Oct 09 10:38:19 AM UTC 24 |
| Finished | Oct 09 10:38:40 AM UTC 24 |
| Peak memory | 231636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644921944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.644921944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.1808027132 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5620349375 ps |
| CPU time | 23.62 seconds |
| Started | Oct 09 10:38:19 AM UTC 24 |
| Finished | Oct 09 10:38:44 AM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808027132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1808027132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.4260667085 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 45061128 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 10:38:21 AM UTC 24 |
| Finished | Oct 09 10:38:23 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260667085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4260667085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.3982743818 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 37188938 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:38:20 AM UTC 24 |
| Finished | Oct 09 10:38:22 AM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982743818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3982743818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.2206189449 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 756980601 ps |
| CPU time | 6 seconds |
| Started | Oct 09 10:38:24 AM UTC 24 |
| Finished | Oct 09 10:38:31 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206189449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2206189449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.2102328635 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 42520925 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:38:56 AM UTC 24 |
| Finished | Oct 09 10:38:58 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102328635 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.2102328635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3477319995 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 502512243 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 10:38:49 AM UTC 24 |
| Finished | Oct 09 10:38:58 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477319995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3477319995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.3169905930 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 25749347 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:38:36 AM UTC 24 |
| Finished | Oct 09 10:38:39 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169905930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3169905930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.4241991007 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 154517368481 ps |
| CPU time | 364.84 seconds |
| Started | Oct 09 10:38:52 AM UTC 24 |
| Finished | Oct 09 10:45:02 AM UTC 24 |
| Peak memory | 284180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241991007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4241991007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3491151301 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 174577631470 ps |
| CPU time | 394.98 seconds |
| Started | Oct 09 10:38:53 AM UTC 24 |
| Finished | Oct 09 10:45:33 AM UTC 24 |
| Peak memory | 276176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491151301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3491151301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.351430272 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 21705378549 ps |
| CPU time | 227.87 seconds |
| Started | Oct 09 10:38:53 AM UTC 24 |
| Finished | Oct 09 10:42:45 AM UTC 24 |
| Peak memory | 263624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351430272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.351430272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.3165404990 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 905608747 ps |
| CPU time | 10.88 seconds |
| Started | Oct 09 10:38:49 AM UTC 24 |
| Finished | Oct 09 10:39:01 AM UTC 24 |
| Peak memory | 249236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165404990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3165404990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1180917225 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4464742497 ps |
| CPU time | 68.63 seconds |
| Started | Oct 09 10:38:51 AM UTC 24 |
| Finished | Oct 09 10:40:01 AM UTC 24 |
| Peak memory | 265552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180917225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.1180917225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.230702975 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 42483192 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:38:44 AM UTC 24 |
| Finished | Oct 09 10:38:49 AM UTC 24 |
| Peak memory | 244968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230702975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.230702975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.3553785192 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2450652426 ps |
| CPU time | 32.46 seconds |
| Started | Oct 09 10:38:45 AM UTC 24 |
| Finished | Oct 09 10:39:19 AM UTC 24 |
| Peak memory | 249360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553785192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3553785192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.2900102225 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2581529757 ps |
| CPU time | 10.92 seconds |
| Started | Oct 09 10:38:43 AM UTC 24 |
| Finished | Oct 09 10:38:55 AM UTC 24 |
| Peak memory | 245076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900102225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.2900102225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.300084231 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 104103711 ps |
| CPU time | 4.95 seconds |
| Started | Oct 09 10:38:43 AM UTC 24 |
| Finished | Oct 09 10:38:49 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300084231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.300084231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.475017999 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1163068073 ps |
| CPU time | 23.94 seconds |
| Started | Oct 09 10:38:52 AM UTC 24 |
| Finished | Oct 09 10:39:17 AM UTC 24 |
| Peak memory | 231452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475017999 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.475017999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.2968032845 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 128706104027 ps |
| CPU time | 106.29 seconds |
| Started | Oct 09 10:38:55 AM UTC 24 |
| Finished | Oct 09 10:40:44 AM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968032845 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.2968032845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.3759509762 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 9284803987 ps |
| CPU time | 11.18 seconds |
| Started | Oct 09 10:38:39 AM UTC 24 |
| Finished | Oct 09 10:38:51 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759509762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3759509762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3873667607 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2317707651 ps |
| CPU time | 11.57 seconds |
| Started | Oct 09 10:38:38 AM UTC 24 |
| Finished | Oct 09 10:38:50 AM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873667607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3873667607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.1977403542 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 57158067 ps |
| CPU time | 1.48 seconds |
| Started | Oct 09 10:38:41 AM UTC 24 |
| Finished | Oct 09 10:38:44 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977403542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1977403542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.4223138321 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 62531201 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 10:38:40 AM UTC 24 |
| Finished | Oct 09 10:38:42 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223138321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4223138321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.1318152459 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3557427541 ps |
| CPU time | 6.26 seconds |
| Started | Oct 09 10:38:46 AM UTC 24 |
| Finished | Oct 09 10:38:54 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318152459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1318152459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.3982747445 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 17487653 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 10:39:35 AM UTC 24 |
| Finished | Oct 09 10:39:37 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982747445 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.3982747445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.4159092801 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1447345124 ps |
| CPU time | 7.3 seconds |
| Started | Oct 09 10:39:18 AM UTC 24 |
| Finished | Oct 09 10:39:26 AM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159092801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4159092801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.2600323881 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 349611956 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:38:56 AM UTC 24 |
| Finished | Oct 09 10:38:59 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600323881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2600323881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.2299144459 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 84742967700 ps |
| CPU time | 131.1 seconds |
| Started | Oct 09 10:39:28 AM UTC 24 |
| Finished | Oct 09 10:41:41 AM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299144459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2299144459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.801125575 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 21972591539 ps |
| CPU time | 55.39 seconds |
| Started | Oct 09 10:39:28 AM UTC 24 |
| Finished | Oct 09 10:40:25 AM UTC 24 |
| Peak memory | 263828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801125575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.801125575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2419132664 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 53987018191 ps |
| CPU time | 403.6 seconds |
| Started | Oct 09 10:39:29 AM UTC 24 |
| Finished | Oct 09 10:46:18 AM UTC 24 |
| Peak memory | 267720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419132664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.2419132664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.1444768357 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 493001586 ps |
| CPU time | 12.33 seconds |
| Started | Oct 09 10:39:20 AM UTC 24 |
| Finished | Oct 09 10:39:34 AM UTC 24 |
| Peak memory | 234856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444768357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1444768357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.309815331 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 25215472186 ps |
| CPU time | 233.11 seconds |
| Started | Oct 09 10:39:22 AM UTC 24 |
| Finished | Oct 09 10:43:19 AM UTC 24 |
| Peak memory | 261508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309815331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.309815331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.687142882 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 263285230 ps |
| CPU time | 6.28 seconds |
| Started | Oct 09 10:39:09 AM UTC 24 |
| Finished | Oct 09 10:39:16 AM UTC 24 |
| Peak memory | 234860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687142882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.687142882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.2672397547 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 9611364597 ps |
| CPU time | 18.51 seconds |
| Started | Oct 09 10:39:17 AM UTC 24 |
| Finished | Oct 09 10:39:37 AM UTC 24 |
| Peak memory | 247184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672397547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2672397547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.414397511 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 941191975 ps |
| CPU time | 10.5 seconds |
| Started | Oct 09 10:39:06 AM UTC 24 |
| Finished | Oct 09 10:39:17 AM UTC 24 |
| Peak memory | 244956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414397511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.414397511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.2471480341 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 30353014591 ps |
| CPU time | 39.06 seconds |
| Started | Oct 09 10:39:03 AM UTC 24 |
| Finished | Oct 09 10:39:43 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471480341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2471480341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.1789504511 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 209847800 ps |
| CPU time | 5.87 seconds |
| Started | Oct 09 10:39:26 AM UTC 24 |
| Finished | Oct 09 10:39:33 AM UTC 24 |
| Peak memory | 231312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789504511 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.1789504511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.395460469 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 33831339194 ps |
| CPU time | 264.42 seconds |
| Started | Oct 09 10:39:35 AM UTC 24 |
| Finished | Oct 09 10:44:03 AM UTC 24 |
| Peak memory | 282068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395460469 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.395460469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.3614110245 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5416978119 ps |
| CPU time | 20.42 seconds |
| Started | Oct 09 10:38:59 AM UTC 24 |
| Finished | Oct 09 10:39:21 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614110245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3614110245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.834561673 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 14525607690 ps |
| CPU time | 24.36 seconds |
| Started | Oct 09 10:38:59 AM UTC 24 |
| Finished | Oct 09 10:39:25 AM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834561673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.834561673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.2132690191 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 118334421 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:39:03 AM UTC 24 |
| Finished | Oct 09 10:39:05 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132690191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2132690191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3757789084 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 19743638 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:38:59 AM UTC 24 |
| Finished | Oct 09 10:39:02 AM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757789084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3757789084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.1294899233 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1893431453 ps |
| CPU time | 8.69 seconds |
| Started | Oct 09 10:39:18 AM UTC 24 |
| Finished | Oct 09 10:39:28 AM UTC 24 |
| Peak memory | 234848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294899233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1294899233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.2895198394 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 10994247 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:39:56 AM UTC 24 |
| Finished | Oct 09 10:39:58 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895198394 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2895198394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3262605094 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 31279894 ps |
| CPU time | 3.02 seconds |
| Started | Oct 09 10:39:48 AM UTC 24 |
| Finished | Oct 09 10:39:52 AM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262605094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3262605094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.449857882 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 24876821 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:39:37 AM UTC 24 |
| Finished | Oct 09 10:39:39 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449857882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.449857882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.2041160268 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 68045996374 ps |
| CPU time | 129.41 seconds |
| Started | Oct 09 10:39:53 AM UTC 24 |
| Finished | Oct 09 10:42:05 AM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041160268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2041160268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.354384096 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3771471576 ps |
| CPU time | 34.15 seconds |
| Started | Oct 09 10:39:53 AM UTC 24 |
| Finished | Oct 09 10:40:29 AM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354384096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.354384096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2950106730 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 83604513188 ps |
| CPU time | 62.37 seconds |
| Started | Oct 09 10:39:54 AM UTC 24 |
| Finished | Oct 09 10:40:58 AM UTC 24 |
| Peak memory | 247120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950106730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.2950106730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.146330238 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 840665786 ps |
| CPU time | 5.99 seconds |
| Started | Oct 09 10:39:50 AM UTC 24 |
| Finished | Oct 09 10:39:57 AM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146330238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.146330238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.972333163 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 59397406 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 10:39:50 AM UTC 24 |
| Finished | Oct 09 10:39:52 AM UTC 24 |
| Peak memory | 226820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972333163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.972333163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.3353549335 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 843124980 ps |
| CPU time | 5.59 seconds |
| Started | Oct 09 10:39:47 AM UTC 24 |
| Finished | Oct 09 10:39:53 AM UTC 24 |
| Peak memory | 245088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353549335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3353549335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.606270229 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2358254878 ps |
| CPU time | 17.05 seconds |
| Started | Oct 09 10:39:47 AM UTC 24 |
| Finished | Oct 09 10:40:05 AM UTC 24 |
| Peak memory | 244968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606270229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.606270229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3934267566 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 265926918 ps |
| CPU time | 6.21 seconds |
| Started | Oct 09 10:39:45 AM UTC 24 |
| Finished | Oct 09 10:39:52 AM UTC 24 |
| Peak memory | 234884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934267566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.3934267566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.2618431577 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 10938972423 ps |
| CPU time | 25.11 seconds |
| Started | Oct 09 10:39:45 AM UTC 24 |
| Finished | Oct 09 10:40:11 AM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618431577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2618431577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2699301114 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 276697387 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 10:39:52 AM UTC 24 |
| Finished | Oct 09 10:39:59 AM UTC 24 |
| Peak memory | 231440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699301114 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.2699301114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.1147882661 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 179874047280 ps |
| CPU time | 501.21 seconds |
| Started | Oct 09 10:39:55 AM UTC 24 |
| Finished | Oct 09 10:48:23 AM UTC 24 |
| Peak memory | 278032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147882661 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.1147882661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.4143790898 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 8216651947 ps |
| CPU time | 36.53 seconds |
| Started | Oct 09 10:39:38 AM UTC 24 |
| Finished | Oct 09 10:40:16 AM UTC 24 |
| Peak memory | 227652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143790898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4143790898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.255331996 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3366328021 ps |
| CPU time | 12.86 seconds |
| Started | Oct 09 10:39:38 AM UTC 24 |
| Finished | Oct 09 10:39:52 AM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255331996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.255331996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.48459660 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 54327523 ps |
| CPU time | 2.61 seconds |
| Started | Oct 09 10:39:43 AM UTC 24 |
| Finished | Oct 09 10:39:47 AM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48459660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.48459660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.584394148 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 39545552 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 10:39:40 AM UTC 24 |
| Finished | Oct 09 10:39:43 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584394148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.584394148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.1248788877 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 10837038854 ps |
| CPU time | 31.19 seconds |
| Started | Oct 09 10:39:47 AM UTC 24 |
| Finished | Oct 09 10:40:19 AM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248788877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1248788877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2987619023 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 43830352 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:40:18 AM UTC 24 |
| Finished | Oct 09 10:40:20 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987619023 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.2987619023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.3111157423 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2658765535 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 10:40:06 AM UTC 24 |
| Finished | Oct 09 10:40:11 AM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111157423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3111157423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.3126044576 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 39309174 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:39:58 AM UTC 24 |
| Finished | Oct 09 10:40:00 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126044576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3126044576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.258889932 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 8837539637 ps |
| CPU time | 12.02 seconds |
| Started | Oct 09 10:40:12 AM UTC 24 |
| Finished | Oct 09 10:40:25 AM UTC 24 |
| Peak memory | 249168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258889932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.258889932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.582981166 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 14936108151 ps |
| CPU time | 130.73 seconds |
| Started | Oct 09 10:40:15 AM UTC 24 |
| Finished | Oct 09 10:42:29 AM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582981166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.582981166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.3260592973 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 169876332 ps |
| CPU time | 6.4 seconds |
| Started | Oct 09 10:40:10 AM UTC 24 |
| Finished | Oct 09 10:40:17 AM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260592973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3260592973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.688324349 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1294773411 ps |
| CPU time | 29.66 seconds |
| Started | Oct 09 10:40:10 AM UTC 24 |
| Finished | Oct 09 10:40:41 AM UTC 24 |
| Peak memory | 261316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688324349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.688324349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.2459919124 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 635749581 ps |
| CPU time | 8.99 seconds |
| Started | Oct 09 10:40:05 AM UTC 24 |
| Finished | Oct 09 10:40:15 AM UTC 24 |
| Peak memory | 245168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459919124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2459919124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.1569012432 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 33973789 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 10:40:05 AM UTC 24 |
| Finished | Oct 09 10:40:09 AM UTC 24 |
| Peak memory | 244632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569012432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1569012432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2552257538 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1192073223 ps |
| CPU time | 9.78 seconds |
| Started | Oct 09 10:40:04 AM UTC 24 |
| Finished | Oct 09 10:40:15 AM UTC 24 |
| Peak memory | 234768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552257538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2552257538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.53143615 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 922974097 ps |
| CPU time | 14.25 seconds |
| Started | Oct 09 10:40:02 AM UTC 24 |
| Finished | Oct 09 10:40:18 AM UTC 24 |
| Peak memory | 261348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53143615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.53143615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.705957517 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 408699249 ps |
| CPU time | 7.21 seconds |
| Started | Oct 09 10:40:12 AM UTC 24 |
| Finished | Oct 09 10:40:21 AM UTC 24 |
| Peak memory | 231188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705957517 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.705957517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.1204885846 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5481652426 ps |
| CPU time | 33.21 seconds |
| Started | Oct 09 10:40:16 AM UTC 24 |
| Finished | Oct 09 10:40:51 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204885846 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.1204885846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.1080692707 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1312334623 ps |
| CPU time | 7.49 seconds |
| Started | Oct 09 10:40:00 AM UTC 24 |
| Finished | Oct 09 10:40:09 AM UTC 24 |
| Peak memory | 231448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080692707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1080692707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.2578535213 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 1544757856 ps |
| CPU time | 3.8 seconds |
| Started | Oct 09 10:39:59 AM UTC 24 |
| Finished | Oct 09 10:40:04 AM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578535213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2578535213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.1558539031 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 44653481 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 10:40:01 AM UTC 24 |
| Finished | Oct 09 10:40:04 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558539031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1558539031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.1906030312 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 203682561 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 10:40:01 AM UTC 24 |
| Finished | Oct 09 10:40:04 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906030312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1906030312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.3797596295 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 186476146 ps |
| CPU time | 6.27 seconds |
| Started | Oct 09 10:40:06 AM UTC 24 |
| Finished | Oct 09 10:40:13 AM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797596295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3797596295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.972421409 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 18372251 ps |
| CPU time | 1 seconds |
| Started | Oct 09 10:40:40 AM UTC 24 |
| Finished | Oct 09 10:40:43 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972421409 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.972421409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.766855384 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2312595212 ps |
| CPU time | 18.52 seconds |
| Started | Oct 09 10:40:27 AM UTC 24 |
| Finished | Oct 09 10:40:47 AM UTC 24 |
| Peak memory | 244968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766855384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.766855384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.4247481959 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 14827514 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:40:19 AM UTC 24 |
| Finished | Oct 09 10:40:21 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247481959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4247481959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2124631957 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 1448993328 ps |
| CPU time | 19.31 seconds |
| Started | Oct 09 10:40:34 AM UTC 24 |
| Finished | Oct 09 10:40:55 AM UTC 24 |
| Peak memory | 234704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124631957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2124631957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.1112368857 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 16343090445 ps |
| CPU time | 158.86 seconds |
| Started | Oct 09 10:40:35 AM UTC 24 |
| Finished | Oct 09 10:43:17 AM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112368857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1112368857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2453946889 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 9947219280 ps |
| CPU time | 63.16 seconds |
| Started | Oct 09 10:40:37 AM UTC 24 |
| Finished | Oct 09 10:41:42 AM UTC 24 |
| Peak memory | 261588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453946889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.2453946889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.206140855 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3940740259 ps |
| CPU time | 42.77 seconds |
| Started | Oct 09 10:40:30 AM UTC 24 |
| Finished | Oct 09 10:41:14 AM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206140855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.206140855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.727993408 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 6848062475 ps |
| CPU time | 20.32 seconds |
| Started | Oct 09 10:40:32 AM UTC 24 |
| Finished | Oct 09 10:40:54 AM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727993408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.727993408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.1309364119 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1323026281 ps |
| CPU time | 5.16 seconds |
| Started | Oct 09 10:40:25 AM UTC 24 |
| Finished | Oct 09 10:40:32 AM UTC 24 |
| Peak memory | 234736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309364119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1309364119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.602271576 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 700993282 ps |
| CPU time | 12.73 seconds |
| Started | Oct 09 10:40:25 AM UTC 24 |
| Finished | Oct 09 10:40:39 AM UTC 24 |
| Peak memory | 234676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602271576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.602271576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2111194482 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1756197190 ps |
| CPU time | 7.75 seconds |
| Started | Oct 09 10:40:24 AM UTC 24 |
| Finished | Oct 09 10:40:33 AM UTC 24 |
| Peak memory | 245132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111194482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.2111194482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2829138042 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4507023489 ps |
| CPU time | 10.6 seconds |
| Started | Oct 09 10:40:22 AM UTC 24 |
| Finished | Oct 09 10:40:34 AM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829138042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2829138042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.2763492053 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 986914368 ps |
| CPU time | 12.17 seconds |
| Started | Oct 09 10:40:33 AM UTC 24 |
| Finished | Oct 09 10:40:46 AM UTC 24 |
| Peak memory | 231184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763492053 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.2763492053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3247170691 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 117392748693 ps |
| CPU time | 668.33 seconds |
| Started | Oct 09 10:40:37 AM UTC 24 |
| Finished | Oct 09 10:51:54 AM UTC 24 |
| Peak memory | 277964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247170691 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.3247170691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.2657844592 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 22915531116 ps |
| CPU time | 35.17 seconds |
| Started | Oct 09 10:40:20 AM UTC 24 |
| Finished | Oct 09 10:40:57 AM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657844592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2657844592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2373454758 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 322369913 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 10:40:19 AM UTC 24 |
| Finished | Oct 09 10:40:25 AM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373454758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2373454758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.1032017130 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 692183158 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:40:21 AM UTC 24 |
| Finished | Oct 09 10:40:25 AM UTC 24 |
| Peak memory | 227352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032017130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1032017130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.2713015803 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 23872244 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:40:21 AM UTC 24 |
| Finished | Oct 09 10:40:23 AM UTC 24 |
| Peak memory | 216144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713015803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2713015803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1759723930 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 637835720 ps |
| CPU time | 7.94 seconds |
| Started | Oct 09 10:40:27 AM UTC 24 |
| Finished | Oct 09 10:40:36 AM UTC 24 |
| Peak memory | 244952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759723930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1759723930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.1929542760 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 68194197 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:40:58 AM UTC 24 |
| Finished | Oct 09 10:41:00 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929542760 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.1929542760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3836231621 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 416770072 ps |
| CPU time | 4.49 seconds |
| Started | Oct 09 10:40:49 AM UTC 24 |
| Finished | Oct 09 10:40:55 AM UTC 24 |
| Peak memory | 234852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836231621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3836231621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.384877798 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 39076371 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:40:42 AM UTC 24 |
| Finished | Oct 09 10:40:44 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384877798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.384877798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2413161177 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 15538504889 ps |
| CPU time | 170.36 seconds |
| Started | Oct 09 10:40:56 AM UTC 24 |
| Finished | Oct 09 10:43:49 AM UTC 24 |
| Peak memory | 267904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413161177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2413161177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3383362668 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 2839138296 ps |
| CPU time | 31.88 seconds |
| Started | Oct 09 10:40:56 AM UTC 24 |
| Finished | Oct 09 10:41:29 AM UTC 24 |
| Peak memory | 244024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383362668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.3383362668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.2658518855 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3403859273 ps |
| CPU time | 14.93 seconds |
| Started | Oct 09 10:40:52 AM UTC 24 |
| Finished | Oct 09 10:41:09 AM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658518855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2658518855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1354454490 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 135067352838 ps |
| CPU time | 537.67 seconds |
| Started | Oct 09 10:40:54 AM UTC 24 |
| Finished | Oct 09 10:49:59 AM UTC 24 |
| Peak memory | 284168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354454490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.1354454490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.2717382671 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2918400413 ps |
| CPU time | 12.06 seconds |
| Started | Oct 09 10:40:48 AM UTC 24 |
| Finished | Oct 09 10:41:01 AM UTC 24 |
| Peak memory | 245020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717382671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2717382671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.2381071289 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 28017018168 ps |
| CPU time | 79.93 seconds |
| Started | Oct 09 10:40:48 AM UTC 24 |
| Finished | Oct 09 10:42:10 AM UTC 24 |
| Peak memory | 245028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381071289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2381071289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2862551188 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 29807899060 ps |
| CPU time | 22.15 seconds |
| Started | Oct 09 10:40:47 AM UTC 24 |
| Finished | Oct 09 10:41:10 AM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862551188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.2862551188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1313251586 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3810088232 ps |
| CPU time | 9.52 seconds |
| Started | Oct 09 10:40:45 AM UTC 24 |
| Finished | Oct 09 10:40:56 AM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313251586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1313251586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.519657889 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3468532384 ps |
| CPU time | 9.77 seconds |
| Started | Oct 09 10:40:55 AM UTC 24 |
| Finished | Oct 09 10:41:06 AM UTC 24 |
| Peak memory | 233480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519657889 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.519657889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.3163121713 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4790886339 ps |
| CPU time | 26.81 seconds |
| Started | Oct 09 10:40:45 AM UTC 24 |
| Finished | Oct 09 10:41:13 AM UTC 24 |
| Peak memory | 227780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163121713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3163121713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3643555975 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 864165914 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 10:40:44 AM UTC 24 |
| Finished | Oct 09 10:40:48 AM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643555975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3643555975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.2553838155 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 328882045 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 10:40:45 AM UTC 24 |
| Finished | Oct 09 10:40:48 AM UTC 24 |
| Peak memory | 227024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553838155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2553838155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2796711694 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 34728908 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:40:45 AM UTC 24 |
| Finished | Oct 09 10:40:47 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796711694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2796711694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.3604886194 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5590556618 ps |
| CPU time | 21.74 seconds |
| Started | Oct 09 10:40:48 AM UTC 24 |
| Finished | Oct 09 10:41:11 AM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604886194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3604886194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.3073553077 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 11514597 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:41:21 AM UTC 24 |
| Finished | Oct 09 10:41:23 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073553077 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.3073553077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.914628644 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 116105583 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 10:41:12 AM UTC 24 |
| Finished | Oct 09 10:41:16 AM UTC 24 |
| Peak memory | 234708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914628644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.914628644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.1799405368 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 22390457 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:40:58 AM UTC 24 |
| Finished | Oct 09 10:41:00 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799405368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1799405368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.800125160 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 49845867733 ps |
| CPU time | 114.07 seconds |
| Started | Oct 09 10:41:15 AM UTC 24 |
| Finished | Oct 09 10:43:12 AM UTC 24 |
| Peak memory | 261524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800125160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.800125160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2684722032 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 11049430866 ps |
| CPU time | 147.39 seconds |
| Started | Oct 09 10:41:17 AM UTC 24 |
| Finished | Oct 09 10:43:46 AM UTC 24 |
| Peak memory | 261844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684722032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2684722032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3294177208 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 8994708775 ps |
| CPU time | 77.93 seconds |
| Started | Oct 09 10:41:18 AM UTC 24 |
| Finished | Oct 09 10:42:37 AM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294177208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.3294177208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.3222599909 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 807301886 ps |
| CPU time | 7.41 seconds |
| Started | Oct 09 10:41:13 AM UTC 24 |
| Finished | Oct 09 10:41:22 AM UTC 24 |
| Peak memory | 234916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222599909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3222599909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3627128565 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 61736329752 ps |
| CPU time | 67.71 seconds |
| Started | Oct 09 10:41:14 AM UTC 24 |
| Finished | Oct 09 10:42:24 AM UTC 24 |
| Peak memory | 267600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627128565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.3627128565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.1370555463 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 547053089 ps |
| CPU time | 11.63 seconds |
| Started | Oct 09 10:41:11 AM UTC 24 |
| Finished | Oct 09 10:41:24 AM UTC 24 |
| Peak memory | 234676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370555463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1370555463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.2766793170 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 101632123 ps |
| CPU time | 3.62 seconds |
| Started | Oct 09 10:41:12 AM UTC 24 |
| Finished | Oct 09 10:41:17 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766793170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2766793170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3150881204 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 325464530 ps |
| CPU time | 12.44 seconds |
| Started | Oct 09 10:41:10 AM UTC 24 |
| Finished | Oct 09 10:41:23 AM UTC 24 |
| Peak memory | 261328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150881204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.3150881204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2117537343 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 66313446 ps |
| CPU time | 2.99 seconds |
| Started | Oct 09 10:41:07 AM UTC 24 |
| Finished | Oct 09 10:41:11 AM UTC 24 |
| Peak memory | 244696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117537343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2117537343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2160856225 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3492075403 ps |
| CPU time | 8.49 seconds |
| Started | Oct 09 10:41:15 AM UTC 24 |
| Finished | Oct 09 10:41:25 AM UTC 24 |
| Peak memory | 229264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160856225 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2160856225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.3284128136 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1496352562 ps |
| CPU time | 15.74 seconds |
| Started | Oct 09 10:41:18 AM UTC 24 |
| Finished | Oct 09 10:41:35 AM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284128136 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.3284128136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.2315708562 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1329772172 ps |
| CPU time | 18.07 seconds |
| Started | Oct 09 10:41:01 AM UTC 24 |
| Finished | Oct 09 10:41:21 AM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315708562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2315708562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1962348576 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 4991524779 ps |
| CPU time | 25.77 seconds |
| Started | Oct 09 10:41:01 AM UTC 24 |
| Finished | Oct 09 10:41:28 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962348576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1962348576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.614229842 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 242629575 ps |
| CPU time | 3.01 seconds |
| Started | Oct 09 10:41:07 AM UTC 24 |
| Finished | Oct 09 10:41:11 AM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614229842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.614229842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2655286792 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 434774105 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 10:41:02 AM UTC 24 |
| Finished | Oct 09 10:41:05 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655286792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2655286792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.258823820 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 521233311 ps |
| CPU time | 3.3 seconds |
| Started | Oct 09 10:41:12 AM UTC 24 |
| Finished | Oct 09 10:41:16 AM UTC 24 |
| Peak memory | 234728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258823820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.258823820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.3297485986 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 13616393 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:41:37 AM UTC 24 |
| Finished | Oct 09 10:41:39 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297485986 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.3297485986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.1903824292 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 248720345 ps |
| CPU time | 4.82 seconds |
| Started | Oct 09 10:41:29 AM UTC 24 |
| Finished | Oct 09 10:41:35 AM UTC 24 |
| Peak memory | 234656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903824292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1903824292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.3143553889 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 112786964 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:41:22 AM UTC 24 |
| Finished | Oct 09 10:41:24 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143553889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3143553889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.1293954785 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 35272554689 ps |
| CPU time | 99.93 seconds |
| Started | Oct 09 10:41:32 AM UTC 24 |
| Finished | Oct 09 10:43:14 AM UTC 24 |
| Peak memory | 263764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293954785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1293954785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.931711764 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 44885981321 ps |
| CPU time | 437.16 seconds |
| Started | Oct 09 10:41:35 AM UTC 24 |
| Finished | Oct 09 10:48:58 AM UTC 24 |
| Peak memory | 278028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931711764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.931711764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.4258386020 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 129436901447 ps |
| CPU time | 253.69 seconds |
| Started | Oct 09 10:41:35 AM UTC 24 |
| Finished | Oct 09 10:45:53 AM UTC 24 |
| Peak memory | 261572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258386020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.4258386020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.2955098046 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2207923232 ps |
| CPU time | 39.46 seconds |
| Started | Oct 09 10:41:29 AM UTC 24 |
| Finished | Oct 09 10:42:10 AM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955098046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2955098046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.916965529 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3954290553 ps |
| CPU time | 18.34 seconds |
| Started | Oct 09 10:41:30 AM UTC 24 |
| Finished | Oct 09 10:41:50 AM UTC 24 |
| Peak memory | 234724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916965529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.916965529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.3941987061 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1228902034 ps |
| CPU time | 15.45 seconds |
| Started | Oct 09 10:41:25 AM UTC 24 |
| Finished | Oct 09 10:41:42 AM UTC 24 |
| Peak memory | 245040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941987061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3941987061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.3458731099 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 105931696 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 10:41:27 AM UTC 24 |
| Finished | Oct 09 10:41:31 AM UTC 24 |
| Peak memory | 233820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458731099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3458731099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3172548087 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 4173704086 ps |
| CPU time | 11.55 seconds |
| Started | Oct 09 10:41:25 AM UTC 24 |
| Finished | Oct 09 10:41:38 AM UTC 24 |
| Peak memory | 245068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172548087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.3172548087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.178801794 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 63415939 ps |
| CPU time | 2.94 seconds |
| Started | Oct 09 10:41:24 AM UTC 24 |
| Finished | Oct 09 10:41:28 AM UTC 24 |
| Peak memory | 244688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178801794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.178801794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.745677939 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1383331837 ps |
| CPU time | 8.76 seconds |
| Started | Oct 09 10:41:30 AM UTC 24 |
| Finished | Oct 09 10:41:40 AM UTC 24 |
| Peak memory | 233340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745677939 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.745677939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.103504118 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 625873418152 ps |
| CPU time | 436.57 seconds |
| Started | Oct 09 10:41:35 AM UTC 24 |
| Finished | Oct 09 10:48:58 AM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103504118 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.103504118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.4008786058 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 829084729 ps |
| CPU time | 3.78 seconds |
| Started | Oct 09 10:41:24 AM UTC 24 |
| Finished | Oct 09 10:41:29 AM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008786058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4008786058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1619411087 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 22375549409 ps |
| CPU time | 13.05 seconds |
| Started | Oct 09 10:41:23 AM UTC 24 |
| Finished | Oct 09 10:41:37 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619411087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1619411087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.317021981 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 66369726 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 10:41:24 AM UTC 24 |
| Finished | Oct 09 10:41:27 AM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317021981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.317021981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3797559447 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 48411617 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:41:24 AM UTC 24 |
| Finished | Oct 09 10:41:26 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797559447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3797559447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.2383231826 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1100955123 ps |
| CPU time | 16.51 seconds |
| Started | Oct 09 10:41:29 AM UTC 24 |
| Finished | Oct 09 10:41:46 AM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383231826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2383231826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.1653912326 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14429612 ps |
| CPU time | 1.06 seconds |
| Started | Oct 09 10:25:20 AM UTC 24 |
| Finished | Oct 09 10:25:23 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653912326 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1653912326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.86078553 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 495573210 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 10:25:05 AM UTC 24 |
| Finished | Oct 09 10:25:10 AM UTC 24 |
| Peak memory | 234668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86078553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.86078553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.1926610369 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 41561062 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:24:45 AM UTC 24 |
| Finished | Oct 09 10:24:48 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926610369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1926610369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.509681753 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 9568575094 ps |
| CPU time | 30.83 seconds |
| Started | Oct 09 10:25:11 AM UTC 24 |
| Finished | Oct 09 10:25:43 AM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509681753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.509681753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1059421323 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 32092623769 ps |
| CPU time | 134.43 seconds |
| Started | Oct 09 10:25:12 AM UTC 24 |
| Finished | Oct 09 10:27:29 AM UTC 24 |
| Peak memory | 280032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059421323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1059421323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.87175780 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9303894113 ps |
| CPU time | 40.11 seconds |
| Started | Oct 09 10:25:07 AM UTC 24 |
| Finished | Oct 09 10:25:49 AM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87175780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.87175780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1229438810 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3470086534 ps |
| CPU time | 15.55 seconds |
| Started | Oct 09 10:25:10 AM UTC 24 |
| Finished | Oct 09 10:25:27 AM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229438810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.1229438810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2144121609 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2647357242 ps |
| CPU time | 18.03 seconds |
| Started | Oct 09 10:24:55 AM UTC 24 |
| Finished | Oct 09 10:25:15 AM UTC 24 |
| Peak memory | 234844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144121609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2144121609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1939362087 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 354441236 ps |
| CPU time | 7.9 seconds |
| Started | Oct 09 10:25:01 AM UTC 24 |
| Finished | Oct 09 10:25:10 AM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939362087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1939362087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.245823825 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1450642872 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 10:24:54 AM UTC 24 |
| Finished | Oct 09 10:25:00 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245823825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.245823825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.293531778 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 896794049 ps |
| CPU time | 10.83 seconds |
| Started | Oct 09 10:24:52 AM UTC 24 |
| Finished | Oct 09 10:25:04 AM UTC 24 |
| Peak memory | 245000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293531778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.293531778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3889206935 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2484603995 ps |
| CPU time | 14.28 seconds |
| Started | Oct 09 10:25:10 AM UTC 24 |
| Finished | Oct 09 10:25:25 AM UTC 24 |
| Peak memory | 233600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889206935 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.3889206935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3494189533 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 93807420 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 10:25:16 AM UTC 24 |
| Finished | Oct 09 10:25:19 AM UTC 24 |
| Peak memory | 257076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494189533 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3494189533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2539714681 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 9491798419 ps |
| CPU time | 62.81 seconds |
| Started | Oct 09 10:24:49 AM UTC 24 |
| Finished | Oct 09 10:25:54 AM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539714681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2539714681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1243733109 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 30872987100 ps |
| CPU time | 37.98 seconds |
| Started | Oct 09 10:24:49 AM UTC 24 |
| Finished | Oct 09 10:25:29 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243733109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1243733109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3400543292 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 13622851 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:24:51 AM UTC 24 |
| Finished | Oct 09 10:24:53 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400543292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3400543292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3539596196 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 56431123 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:24:49 AM UTC 24 |
| Finished | Oct 09 10:24:51 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539596196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3539596196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.2777215146 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 64437445 ps |
| CPU time | 3.29 seconds |
| Started | Oct 09 10:25:04 AM UTC 24 |
| Finished | Oct 09 10:25:09 AM UTC 24 |
| Peak memory | 234376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777215146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2777215146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.3273261354 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 13948525 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:42:06 AM UTC 24 |
| Finished | Oct 09 10:42:08 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273261354 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.3273261354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1246045788 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3106647184 ps |
| CPU time | 8.64 seconds |
| Started | Oct 09 10:41:47 AM UTC 24 |
| Finished | Oct 09 10:41:57 AM UTC 24 |
| Peak memory | 244968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246045788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1246045788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.3540027324 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 39523040 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:41:38 AM UTC 24 |
| Finished | Oct 09 10:41:40 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540027324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3540027324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.2335996349 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 136493434710 ps |
| CPU time | 337.75 seconds |
| Started | Oct 09 10:41:58 AM UTC 24 |
| Finished | Oct 09 10:47:41 AM UTC 24 |
| Peak memory | 261528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335996349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2335996349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.971408968 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 7179231395 ps |
| CPU time | 23.29 seconds |
| Started | Oct 09 10:41:59 AM UTC 24 |
| Finished | Oct 09 10:42:24 AM UTC 24 |
| Peak memory | 229640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971408968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.971408968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1811209976 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 108772434205 ps |
| CPU time | 359.02 seconds |
| Started | Oct 09 10:41:59 AM UTC 24 |
| Finished | Oct 09 10:48:03 AM UTC 24 |
| Peak memory | 278160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811209976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.1811209976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.3351146052 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 726181345 ps |
| CPU time | 7 seconds |
| Started | Oct 09 10:41:50 AM UTC 24 |
| Finished | Oct 09 10:41:58 AM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351146052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3351146052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2834424458 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 78985522193 ps |
| CPU time | 609.75 seconds |
| Started | Oct 09 10:41:51 AM UTC 24 |
| Finished | Oct 09 10:52:08 AM UTC 24 |
| Peak memory | 279880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834424458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.2834424458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.4175150613 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1238791081 ps |
| CPU time | 12.56 seconds |
| Started | Oct 09 10:41:43 AM UTC 24 |
| Finished | Oct 09 10:41:57 AM UTC 24 |
| Peak memory | 245024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175150613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4175150613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.3703585439 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 795853037 ps |
| CPU time | 3.1 seconds |
| Started | Oct 09 10:41:44 AM UTC 24 |
| Finished | Oct 09 10:41:49 AM UTC 24 |
| Peak memory | 233304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703585439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3703585439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2420332422 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 19467862026 ps |
| CPU time | 25.91 seconds |
| Started | Oct 09 10:41:43 AM UTC 24 |
| Finished | Oct 09 10:42:11 AM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420332422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.2420332422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2012357940 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 5614212625 ps |
| CPU time | 14.22 seconds |
| Started | Oct 09 10:41:42 AM UTC 24 |
| Finished | Oct 09 10:41:58 AM UTC 24 |
| Peak memory | 245088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012357940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2012357940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.810170362 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2885492570 ps |
| CPU time | 15.23 seconds |
| Started | Oct 09 10:41:58 AM UTC 24 |
| Finished | Oct 09 10:42:14 AM UTC 24 |
| Peak memory | 229272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810170362 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.810170362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.4044648458 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 39823763448 ps |
| CPU time | 288.52 seconds |
| Started | Oct 09 10:41:59 AM UTC 24 |
| Finished | Oct 09 10:46:52 AM UTC 24 |
| Peak memory | 265684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044648458 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.4044648458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.383630922 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4815851576 ps |
| CPU time | 16.85 seconds |
| Started | Oct 09 10:41:40 AM UTC 24 |
| Finished | Oct 09 10:41:58 AM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383630922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.383630922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.53421194 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 5986672284 ps |
| CPU time | 28.91 seconds |
| Started | Oct 09 10:41:39 AM UTC 24 |
| Finished | Oct 09 10:42:09 AM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53421194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.53421194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.1459404038 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 113671853 ps |
| CPU time | 1.83 seconds |
| Started | Oct 09 10:41:41 AM UTC 24 |
| Finished | Oct 09 10:41:44 AM UTC 24 |
| Peak memory | 227064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459404038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1459404038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1947115723 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 414514024 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 10:41:41 AM UTC 24 |
| Finished | Oct 09 10:41:43 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947115723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1947115723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.693230111 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 7045740605 ps |
| CPU time | 22.43 seconds |
| Started | Oct 09 10:41:44 AM UTC 24 |
| Finished | Oct 09 10:42:08 AM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693230111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.693230111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2810479274 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 18932243 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:42:25 AM UTC 24 |
| Finished | Oct 09 10:42:27 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810479274 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.2810479274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.697459323 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 82865059 ps |
| CPU time | 3.77 seconds |
| Started | Oct 09 10:42:15 AM UTC 24 |
| Finished | Oct 09 10:42:20 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697459323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.697459323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.188307061 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 38991819 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:42:09 AM UTC 24 |
| Finished | Oct 09 10:42:12 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188307061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.188307061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.248127294 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 22813848640 ps |
| CPU time | 187.12 seconds |
| Started | Oct 09 10:42:21 AM UTC 24 |
| Finished | Oct 09 10:45:31 AM UTC 24 |
| Peak memory | 267608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248127294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.248127294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3064208102 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 38384641276 ps |
| CPU time | 174.1 seconds |
| Started | Oct 09 10:42:23 AM UTC 24 |
| Finished | Oct 09 10:45:20 AM UTC 24 |
| Peak memory | 276116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064208102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3064208102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2291270875 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 16009004816 ps |
| CPU time | 211.89 seconds |
| Started | Oct 09 10:42:25 AM UTC 24 |
| Finished | Oct 09 10:46:00 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291270875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.2291270875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.3751024380 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1835923984 ps |
| CPU time | 17.16 seconds |
| Started | Oct 09 10:42:18 AM UTC 24 |
| Finished | Oct 09 10:42:37 AM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751024380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3751024380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.828067526 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 7439530234 ps |
| CPU time | 62.21 seconds |
| Started | Oct 09 10:42:19 AM UTC 24 |
| Finished | Oct 09 10:43:23 AM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828067526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.828067526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.3335898431 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 49809145 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 10:42:14 AM UTC 24 |
| Finished | Oct 09 10:42:19 AM UTC 24 |
| Peak memory | 245084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335898431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3335898431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.1571723803 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1672346462 ps |
| CPU time | 7.54 seconds |
| Started | Oct 09 10:42:15 AM UTC 24 |
| Finished | Oct 09 10:42:24 AM UTC 24 |
| Peak memory | 245028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571723803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1571723803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.573304895 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 3910047667 ps |
| CPU time | 13.01 seconds |
| Started | Oct 09 10:42:13 AM UTC 24 |
| Finished | Oct 09 10:42:27 AM UTC 24 |
| Peak memory | 244960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573304895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.573304895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.4005014603 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 13409926254 ps |
| CPU time | 29.9 seconds |
| Started | Oct 09 10:42:12 AM UTC 24 |
| Finished | Oct 09 10:42:43 AM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005014603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4005014603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3933489970 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 119999622 ps |
| CPU time | 5.09 seconds |
| Started | Oct 09 10:42:20 AM UTC 24 |
| Finished | Oct 09 10:42:27 AM UTC 24 |
| Peak memory | 233416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933489970 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3933489970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1399620282 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 40622175679 ps |
| CPU time | 229.33 seconds |
| Started | Oct 09 10:42:25 AM UTC 24 |
| Finished | Oct 09 10:46:18 AM UTC 24 |
| Peak memory | 263824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399620282 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.1399620282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.3568412876 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1321929284 ps |
| CPU time | 5.84 seconds |
| Started | Oct 09 10:42:11 AM UTC 24 |
| Finished | Oct 09 10:42:17 AM UTC 24 |
| Peak memory | 227648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568412876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3568412876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1901281780 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2464104415 ps |
| CPU time | 9.56 seconds |
| Started | Oct 09 10:42:09 AM UTC 24 |
| Finished | Oct 09 10:42:20 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901281780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1901281780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.4232259457 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 55422706 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 10:42:11 AM UTC 24 |
| Finished | Oct 09 10:42:14 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232259457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4232259457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.763701099 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 81058697 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 10:42:11 AM UTC 24 |
| Finished | Oct 09 10:42:13 AM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763701099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.763701099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.18907790 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 893765732 ps |
| CPU time | 5.36 seconds |
| Started | Oct 09 10:42:15 AM UTC 24 |
| Finished | Oct 09 10:42:22 AM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18907790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.18907790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1501501321 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 12456841 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:42:59 AM UTC 24 |
| Finished | Oct 09 10:43:01 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501501321 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.1501501321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1105714338 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3868605951 ps |
| CPU time | 17.32 seconds |
| Started | Oct 09 10:42:40 AM UTC 24 |
| Finished | Oct 09 10:42:58 AM UTC 24 |
| Peak memory | 234724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105714338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1105714338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.3370347595 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 17087650 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 10:42:28 AM UTC 24 |
| Finished | Oct 09 10:42:30 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370347595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3370347595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2380476296 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 450774492 ps |
| CPU time | 13.03 seconds |
| Started | Oct 09 10:42:46 AM UTC 24 |
| Finished | Oct 09 10:43:00 AM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380476296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2380476296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.577494480 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 44938471974 ps |
| CPU time | 132.69 seconds |
| Started | Oct 09 10:42:46 AM UTC 24 |
| Finished | Oct 09 10:45:01 AM UTC 24 |
| Peak memory | 261648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577494480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.577494480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2809184031 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 184311682276 ps |
| CPU time | 494.78 seconds |
| Started | Oct 09 10:42:50 AM UTC 24 |
| Finished | Oct 09 10:51:11 AM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809184031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.2809184031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1008727044 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2533945881 ps |
| CPU time | 59.69 seconds |
| Started | Oct 09 10:42:41 AM UTC 24 |
| Finished | Oct 09 10:43:43 AM UTC 24 |
| Peak memory | 260940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008727044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1008727044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.1443707745 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 70456686588 ps |
| CPU time | 215.28 seconds |
| Started | Oct 09 10:42:41 AM UTC 24 |
| Finished | Oct 09 10:46:20 AM UTC 24 |
| Peak memory | 277524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443707745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.1443707745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2949960380 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 266954310 ps |
| CPU time | 3.7 seconds |
| Started | Oct 09 10:42:35 AM UTC 24 |
| Finished | Oct 09 10:42:39 AM UTC 24 |
| Peak memory | 239720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949960380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2949960380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.4133208359 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1214758552 ps |
| CPU time | 24.68 seconds |
| Started | Oct 09 10:42:38 AM UTC 24 |
| Finished | Oct 09 10:43:04 AM UTC 24 |
| Peak memory | 247000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133208359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4133208359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1788186873 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2717289703 ps |
| CPU time | 15.4 seconds |
| Started | Oct 09 10:42:33 AM UTC 24 |
| Finished | Oct 09 10:42:49 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788186873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.1788186873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1439931084 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 888723197 ps |
| CPU time | 7.7 seconds |
| Started | Oct 09 10:42:31 AM UTC 24 |
| Finished | Oct 09 10:42:40 AM UTC 24 |
| Peak memory | 245012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439931084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1439931084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2695192761 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 10862773261 ps |
| CPU time | 23.92 seconds |
| Started | Oct 09 10:42:44 AM UTC 24 |
| Finished | Oct 09 10:43:09 AM UTC 24 |
| Peak memory | 233776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695192761 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2695192761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3316440051 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 268395591046 ps |
| CPU time | 219.73 seconds |
| Started | Oct 09 10:42:57 AM UTC 24 |
| Finished | Oct 09 10:46:40 AM UTC 24 |
| Peak memory | 263632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316440051 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.3316440051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.1301777610 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1476570283 ps |
| CPU time | 10.69 seconds |
| Started | Oct 09 10:42:28 AM UTC 24 |
| Finished | Oct 09 10:42:40 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301777610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1301777610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1110397118 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 12116795 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:42:28 AM UTC 24 |
| Finished | Oct 09 10:42:30 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110397118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1110397118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.196199069 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 26270355 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 10:42:31 AM UTC 24 |
| Finished | Oct 09 10:42:34 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196199069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.196199069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3118657597 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 17533556 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:42:29 AM UTC 24 |
| Finished | Oct 09 10:42:32 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118657597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3118657597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2764076801 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 5119637454 ps |
| CPU time | 16.47 seconds |
| Started | Oct 09 10:42:39 AM UTC 24 |
| Finished | Oct 09 10:42:56 AM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764076801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2764076801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1282750930 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 63152318 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:43:19 AM UTC 24 |
| Finished | Oct 09 10:43:21 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282750930 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.1282750930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1641174791 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 7330126352 ps |
| CPU time | 15.53 seconds |
| Started | Oct 09 10:43:13 AM UTC 24 |
| Finished | Oct 09 10:43:30 AM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641174791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1641174791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.57847243 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 19547498 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:43:00 AM UTC 24 |
| Finished | Oct 09 10:43:03 AM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57847243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.57847243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.805640470 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 55185980115 ps |
| CPU time | 453.5 seconds |
| Started | Oct 09 10:43:16 AM UTC 24 |
| Finished | Oct 09 10:50:55 AM UTC 24 |
| Peak memory | 267672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805640470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.805640470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3650725666 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 7605193877 ps |
| CPU time | 60.46 seconds |
| Started | Oct 09 10:43:16 AM UTC 24 |
| Finished | Oct 09 10:44:18 AM UTC 24 |
| Peak memory | 261528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650725666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3650725666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3793772311 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 38038469047 ps |
| CPU time | 352.21 seconds |
| Started | Oct 09 10:43:18 AM UTC 24 |
| Finished | Oct 09 10:49:15 AM UTC 24 |
| Peak memory | 277952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793772311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.3793772311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2260683420 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1542871028 ps |
| CPU time | 10.35 seconds |
| Started | Oct 09 10:43:14 AM UTC 24 |
| Finished | Oct 09 10:43:26 AM UTC 24 |
| Peak memory | 245016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260683420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2260683420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2678471180 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 17066548 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:43:15 AM UTC 24 |
| Finished | Oct 09 10:43:18 AM UTC 24 |
| Peak memory | 226820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678471180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.2678471180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3235972554 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 213727948 ps |
| CPU time | 5.41 seconds |
| Started | Oct 09 10:43:08 AM UTC 24 |
| Finished | Oct 09 10:43:15 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235972554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3235972554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2498519776 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 147105104 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 10:43:10 AM UTC 24 |
| Finished | Oct 09 10:43:14 AM UTC 24 |
| Peak memory | 233304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498519776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2498519776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1266246258 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 243570657 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 10:43:07 AM UTC 24 |
| Finished | Oct 09 10:43:13 AM UTC 24 |
| Peak memory | 234604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266246258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.1266246258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.1073388415 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 1015558368 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:43:07 AM UTC 24 |
| Finished | Oct 09 10:43:12 AM UTC 24 |
| Peak memory | 233744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073388415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1073388415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1039354971 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1779677084 ps |
| CPU time | 9.01 seconds |
| Started | Oct 09 10:43:16 AM UTC 24 |
| Finished | Oct 09 10:43:26 AM UTC 24 |
| Peak memory | 233332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039354971 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.1039354971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.677312866 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 7645852083 ps |
| CPU time | 134.68 seconds |
| Started | Oct 09 10:43:19 AM UTC 24 |
| Finished | Oct 09 10:45:36 AM UTC 24 |
| Peak memory | 282068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677312866 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.677312866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.3006257229 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 9328305060 ps |
| CPU time | 37.22 seconds |
| Started | Oct 09 10:43:01 AM UTC 24 |
| Finished | Oct 09 10:43:41 AM UTC 24 |
| Peak memory | 231768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006257229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3006257229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1389888487 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 9760596364 ps |
| CPU time | 13.01 seconds |
| Started | Oct 09 10:43:00 AM UTC 24 |
| Finished | Oct 09 10:43:15 AM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389888487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1389888487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3590965324 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 73245963 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 10:43:05 AM UTC 24 |
| Finished | Oct 09 10:43:07 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590965324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3590965324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2908013759 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 32254777 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:43:04 AM UTC 24 |
| Finished | Oct 09 10:43:06 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908013759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2908013759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.739177248 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 128678801 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:43:13 AM UTC 24 |
| Finished | Oct 09 10:43:18 AM UTC 24 |
| Peak memory | 234592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739177248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.739177248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.2296193458 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 17170163 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 10:43:50 AM UTC 24 |
| Finished | Oct 09 10:43:52 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296193458 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.2296193458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.266284007 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 1363466369 ps |
| CPU time | 16.57 seconds |
| Started | Oct 09 10:43:31 AM UTC 24 |
| Finished | Oct 09 10:43:49 AM UTC 24 |
| Peak memory | 234664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266284007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.266284007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2185492642 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 15030847 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 10:43:20 AM UTC 24 |
| Finished | Oct 09 10:43:22 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185492642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2185492642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.375366563 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 167050456513 ps |
| CPU time | 218.4 seconds |
| Started | Oct 09 10:43:41 AM UTC 24 |
| Finished | Oct 09 10:47:24 AM UTC 24 |
| Peak memory | 265812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375366563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.375366563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2908644591 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 6963866189 ps |
| CPU time | 65.52 seconds |
| Started | Oct 09 10:43:42 AM UTC 24 |
| Finished | Oct 09 10:44:50 AM UTC 24 |
| Peak memory | 261908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908644591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2908644591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1911103092 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 71124918516 ps |
| CPU time | 361.65 seconds |
| Started | Oct 09 10:43:43 AM UTC 24 |
| Finished | Oct 09 10:49:50 AM UTC 24 |
| Peak memory | 267780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911103092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1911103092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.1475822078 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 576406121 ps |
| CPU time | 14.57 seconds |
| Started | Oct 09 10:43:40 AM UTC 24 |
| Finished | Oct 09 10:43:56 AM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475822078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1475822078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.3546442816 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 8183167762 ps |
| CPU time | 22.41 seconds |
| Started | Oct 09 10:43:28 AM UTC 24 |
| Finished | Oct 09 10:43:52 AM UTC 24 |
| Peak memory | 242152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546442816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3546442816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.4165707790 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 1910422587 ps |
| CPU time | 21.79 seconds |
| Started | Oct 09 10:43:30 AM UTC 24 |
| Finished | Oct 09 10:43:53 AM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165707790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4165707790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.637133819 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1899551847 ps |
| CPU time | 11.17 seconds |
| Started | Oct 09 10:43:27 AM UTC 24 |
| Finished | Oct 09 10:43:39 AM UTC 24 |
| Peak memory | 251140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637133819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.637133819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1938286412 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 613745433 ps |
| CPU time | 11.84 seconds |
| Started | Oct 09 10:43:26 AM UTC 24 |
| Finished | Oct 09 10:43:40 AM UTC 24 |
| Peak memory | 244968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938286412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1938286412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.819642639 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1806147804 ps |
| CPU time | 23.51 seconds |
| Started | Oct 09 10:43:41 AM UTC 24 |
| Finished | Oct 09 10:44:06 AM UTC 24 |
| Peak memory | 233544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819642639 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.819642639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.2889717117 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 4357528371 ps |
| CPU time | 16.08 seconds |
| Started | Oct 09 10:43:23 AM UTC 24 |
| Finished | Oct 09 10:43:41 AM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889717117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2889717117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2493442179 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1239657511 ps |
| CPU time | 5.88 seconds |
| Started | Oct 09 10:43:22 AM UTC 24 |
| Finished | Oct 09 10:43:29 AM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493442179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2493442179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1915099760 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 35696220 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:43:26 AM UTC 24 |
| Finished | Oct 09 10:43:29 AM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915099760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1915099760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3939627590 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 170804556 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 10:43:24 AM UTC 24 |
| Finished | Oct 09 10:43:27 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939627590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3939627590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2164373495 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 15782856921 ps |
| CPU time | 22.86 seconds |
| Started | Oct 09 10:43:31 AM UTC 24 |
| Finished | Oct 09 10:43:55 AM UTC 24 |
| Peak memory | 234976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164373495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2164373495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.1518948260 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 14604965 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:44:18 AM UTC 24 |
| Finished | Oct 09 10:44:21 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518948260 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.1518948260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.2396605087 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 459074536 ps |
| CPU time | 8.25 seconds |
| Started | Oct 09 10:44:07 AM UTC 24 |
| Finished | Oct 09 10:44:16 AM UTC 24 |
| Peak memory | 244904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396605087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2396605087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.2069857219 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 54660027 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:43:50 AM UTC 24 |
| Finished | Oct 09 10:43:52 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069857219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2069857219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.1519152530 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 48696225729 ps |
| CPU time | 26.64 seconds |
| Started | Oct 09 10:44:13 AM UTC 24 |
| Finished | Oct 09 10:44:41 AM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519152530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1519152530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2755765844 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 37724964988 ps |
| CPU time | 353.59 seconds |
| Started | Oct 09 10:44:14 AM UTC 24 |
| Finished | Oct 09 10:50:13 AM UTC 24 |
| Peak memory | 280024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755765844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2755765844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.1998144000 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 13382743294 ps |
| CPU time | 83.26 seconds |
| Started | Oct 09 10:44:15 AM UTC 24 |
| Finished | Oct 09 10:45:40 AM UTC 24 |
| Peak memory | 261640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998144000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.1998144000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.2519067628 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 42351060 ps |
| CPU time | 4.03 seconds |
| Started | Oct 09 10:44:07 AM UTC 24 |
| Finished | Oct 09 10:44:12 AM UTC 24 |
| Peak memory | 244952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519067628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2519067628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2674236234 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 9998748287 ps |
| CPU time | 51.77 seconds |
| Started | Oct 09 10:44:08 AM UTC 24 |
| Finished | Oct 09 10:45:01 AM UTC 24 |
| Peak memory | 265552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674236234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.2674236234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.3506480056 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 326053704 ps |
| CPU time | 8.85 seconds |
| Started | Oct 09 10:43:56 AM UTC 24 |
| Finished | Oct 09 10:44:06 AM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506480056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3506480056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3986990113 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 5685448306 ps |
| CPU time | 46.57 seconds |
| Started | Oct 09 10:43:59 AM UTC 24 |
| Finished | Oct 09 10:44:48 AM UTC 24 |
| Peak memory | 234832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986990113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3986990113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2694240405 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 1944516503 ps |
| CPU time | 8.09 seconds |
| Started | Oct 09 10:43:56 AM UTC 24 |
| Finished | Oct 09 10:44:05 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694240405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.2694240405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.4074133496 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 4099415208 ps |
| CPU time | 20.72 seconds |
| Started | Oct 09 10:43:56 AM UTC 24 |
| Finished | Oct 09 10:44:18 AM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074133496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4074133496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1192318282 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 766041113 ps |
| CPU time | 7.93 seconds |
| Started | Oct 09 10:44:10 AM UTC 24 |
| Finished | Oct 09 10:44:19 AM UTC 24 |
| Peak memory | 231184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192318282 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.1192318282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2176856683 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 627485701 ps |
| CPU time | 18.05 seconds |
| Started | Oct 09 10:44:17 AM UTC 24 |
| Finished | Oct 09 10:44:37 AM UTC 24 |
| Peak memory | 261524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176856683 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.2176856683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3932490674 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2587149990 ps |
| CPU time | 18.58 seconds |
| Started | Oct 09 10:43:53 AM UTC 24 |
| Finished | Oct 09 10:44:13 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932490674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3932490674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3420176413 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 1451977766 ps |
| CPU time | 14.74 seconds |
| Started | Oct 09 10:43:53 AM UTC 24 |
| Finished | Oct 09 10:44:09 AM UTC 24 |
| Peak memory | 227472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420176413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3420176413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.59306229 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 91455986 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 10:43:54 AM UTC 24 |
| Finished | Oct 09 10:43:59 AM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59306229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.59306229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1983550360 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 22552498 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:43:53 AM UTC 24 |
| Finished | Oct 09 10:43:55 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983550360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1983550360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.3992276368 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2344529762 ps |
| CPU time | 8.83 seconds |
| Started | Oct 09 10:44:05 AM UTC 24 |
| Finished | Oct 09 10:44:15 AM UTC 24 |
| Peak memory | 234724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992276368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3992276368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2773560310 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 18437427 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:44:56 AM UTC 24 |
| Finished | Oct 09 10:44:59 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773560310 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.2773560310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3528433734 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 1841431725 ps |
| CPU time | 8.93 seconds |
| Started | Oct 09 10:44:42 AM UTC 24 |
| Finished | Oct 09 10:44:53 AM UTC 24 |
| Peak memory | 244900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528433734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3528433734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.2991155052 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 14670096 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:44:20 AM UTC 24 |
| Finished | Oct 09 10:44:22 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991155052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2991155052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2303668414 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 35633098735 ps |
| CPU time | 282.24 seconds |
| Started | Oct 09 10:44:49 AM UTC 24 |
| Finished | Oct 09 10:49:35 AM UTC 24 |
| Peak memory | 267664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303668414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2303668414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.148691638 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 13618966600 ps |
| CPU time | 111.93 seconds |
| Started | Oct 09 10:44:51 AM UTC 24 |
| Finished | Oct 09 10:46:45 AM UTC 24 |
| Peak memory | 267728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148691638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.148691638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2712322389 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 192988168654 ps |
| CPU time | 201.87 seconds |
| Started | Oct 09 10:44:53 AM UTC 24 |
| Finished | Oct 09 10:48:18 AM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712322389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.2712322389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.1852986334 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 3302659129 ps |
| CPU time | 56.52 seconds |
| Started | Oct 09 10:44:43 AM UTC 24 |
| Finished | Oct 09 10:45:41 AM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852986334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1852986334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.411754499 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 107719775 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 10:44:37 AM UTC 24 |
| Finished | Oct 09 10:44:41 AM UTC 24 |
| Peak memory | 233348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411754499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.411754499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.1490841956 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 36296817 ps |
| CPU time | 3.02 seconds |
| Started | Oct 09 10:44:41 AM UTC 24 |
| Finished | Oct 09 10:44:46 AM UTC 24 |
| Peak memory | 244640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490841956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1490841956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1853650750 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 1162633628 ps |
| CPU time | 14.77 seconds |
| Started | Oct 09 10:44:26 AM UTC 24 |
| Finished | Oct 09 10:44:42 AM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853650750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.1853650750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1291449447 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 5535966994 ps |
| CPU time | 13.23 seconds |
| Started | Oct 09 10:44:26 AM UTC 24 |
| Finished | Oct 09 10:44:40 AM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291449447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1291449447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.4147143736 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 136213607 ps |
| CPU time | 5.78 seconds |
| Started | Oct 09 10:44:47 AM UTC 24 |
| Finished | Oct 09 10:44:54 AM UTC 24 |
| Peak memory | 229392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147143736 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.4147143736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.2211200601 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 4916401224 ps |
| CPU time | 35.94 seconds |
| Started | Oct 09 10:44:54 AM UTC 24 |
| Finished | Oct 09 10:45:32 AM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211200601 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.2211200601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.481394171 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 20471486237 ps |
| CPU time | 20.63 seconds |
| Started | Oct 09 10:44:22 AM UTC 24 |
| Finished | Oct 09 10:44:44 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481394171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.481394171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2998552712 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 30511649 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:44:20 AM UTC 24 |
| Finished | Oct 09 10:44:22 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998552712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2998552712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.2878711750 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 202784585 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 10:44:23 AM UTC 24 |
| Finished | Oct 09 10:44:25 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878711750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2878711750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.4151143029 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 62550841 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:44:23 AM UTC 24 |
| Finished | Oct 09 10:44:25 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151143029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4151143029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.2564622493 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3073363915 ps |
| CPU time | 11.9 seconds |
| Started | Oct 09 10:44:42 AM UTC 24 |
| Finished | Oct 09 10:44:56 AM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564622493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2564622493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.821296144 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 45259250 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:45:33 AM UTC 24 |
| Finished | Oct 09 10:45:35 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821296144 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.821296144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2826116730 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 479985276 ps |
| CPU time | 6.25 seconds |
| Started | Oct 09 10:45:09 AM UTC 24 |
| Finished | Oct 09 10:45:17 AM UTC 24 |
| Peak memory | 234664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826116730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2826116730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3330196118 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 27752981 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:44:57 AM UTC 24 |
| Finished | Oct 09 10:45:00 AM UTC 24 |
| Peak memory | 215720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330196118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3330196118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.1541765959 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 12462634566 ps |
| CPU time | 159.48 seconds |
| Started | Oct 09 10:45:29 AM UTC 24 |
| Finished | Oct 09 10:48:11 AM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541765959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1541765959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.464716155 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 175801209979 ps |
| CPU time | 439.85 seconds |
| Started | Oct 09 10:45:31 AM UTC 24 |
| Finished | Oct 09 10:52:57 AM UTC 24 |
| Peak memory | 277972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464716155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.464716155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2679584731 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 359472534645 ps |
| CPU time | 271.88 seconds |
| Started | Oct 09 10:45:31 AM UTC 24 |
| Finished | Oct 09 10:50:07 AM UTC 24 |
| Peak memory | 274064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679584731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.2679584731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.182221023 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 4370661863 ps |
| CPU time | 27.98 seconds |
| Started | Oct 09 10:45:17 AM UTC 24 |
| Finished | Oct 09 10:45:47 AM UTC 24 |
| Peak memory | 245036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182221023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.182221023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1947971814 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 57473653341 ps |
| CPU time | 164.61 seconds |
| Started | Oct 09 10:45:20 AM UTC 24 |
| Finished | Oct 09 10:48:08 AM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947971814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.1947971814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.844547487 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 2623416135 ps |
| CPU time | 20.26 seconds |
| Started | Oct 09 10:45:06 AM UTC 24 |
| Finished | Oct 09 10:45:27 AM UTC 24 |
| Peak memory | 234736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844547487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.844547487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.783983556 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 27360980108 ps |
| CPU time | 234.43 seconds |
| Started | Oct 09 10:45:06 AM UTC 24 |
| Finished | Oct 09 10:49:04 AM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783983556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.783983556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1822182348 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 9944011498 ps |
| CPU time | 22.75 seconds |
| Started | Oct 09 10:45:06 AM UTC 24 |
| Finished | Oct 09 10:45:30 AM UTC 24 |
| Peak memory | 245132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822182348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.1822182348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.678781821 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 184499966 ps |
| CPU time | 4.5 seconds |
| Started | Oct 09 10:45:03 AM UTC 24 |
| Finished | Oct 09 10:45:08 AM UTC 24 |
| Peak memory | 234724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678781821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.678781821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1401861944 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 3590878008 ps |
| CPU time | 22.49 seconds |
| Started | Oct 09 10:45:23 AM UTC 24 |
| Finished | Oct 09 10:45:46 AM UTC 24 |
| Peak memory | 233340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401861944 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.1401861944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.2440244025 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 122452557469 ps |
| CPU time | 376.81 seconds |
| Started | Oct 09 10:45:32 AM UTC 24 |
| Finished | Oct 09 10:51:54 AM UTC 24 |
| Peak memory | 294352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440244025 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.2440244025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.4197407216 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 700409610 ps |
| CPU time | 3.68 seconds |
| Started | Oct 09 10:45:01 AM UTC 24 |
| Finished | Oct 09 10:45:05 AM UTC 24 |
| Peak memory | 229400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197407216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4197407216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.3965976713 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5634145554 ps |
| CPU time | 7.4 seconds |
| Started | Oct 09 10:44:59 AM UTC 24 |
| Finished | Oct 09 10:45:08 AM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965976713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3965976713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.3635297672 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 16116615 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:45:03 AM UTC 24 |
| Finished | Oct 09 10:45:05 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635297672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3635297672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1987375272 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 48672349 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 10:45:02 AM UTC 24 |
| Finished | Oct 09 10:45:05 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987375272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1987375272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.4069010755 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 1240871716 ps |
| CPU time | 11.12 seconds |
| Started | Oct 09 10:45:09 AM UTC 24 |
| Finished | Oct 09 10:45:21 AM UTC 24 |
| Peak memory | 234660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069010755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4069010755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3539283286 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 14682625 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 10:46:01 AM UTC 24 |
| Finished | Oct 09 10:46:03 AM UTC 24 |
| Peak memory | 213740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539283286 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.3539283286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2363988765 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 110274665 ps |
| CPU time | 4.84 seconds |
| Started | Oct 09 10:45:48 AM UTC 24 |
| Finished | Oct 09 10:45:54 AM UTC 24 |
| Peak memory | 244944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363988765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2363988765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.3054137201 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 18963665 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:45:34 AM UTC 24 |
| Finished | Oct 09 10:45:36 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054137201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3054137201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.197277454 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 199251520643 ps |
| CPU time | 474.21 seconds |
| Started | Oct 09 10:45:54 AM UTC 24 |
| Finished | Oct 09 10:53:55 AM UTC 24 |
| Peak memory | 265544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197277454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.197277454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3574966025 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 71120688867 ps |
| CPU time | 69.53 seconds |
| Started | Oct 09 10:45:54 AM UTC 24 |
| Finished | Oct 09 10:47:05 AM UTC 24 |
| Peak memory | 261640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574966025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3574966025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.722601860 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 69040156940 ps |
| CPU time | 726.67 seconds |
| Started | Oct 09 10:45:54 AM UTC 24 |
| Finished | Oct 09 10:58:11 AM UTC 24 |
| Peak memory | 294412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722601860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.722601860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.3737670638 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5389280857 ps |
| CPU time | 17.43 seconds |
| Started | Oct 09 10:45:50 AM UTC 24 |
| Finished | Oct 09 10:46:09 AM UTC 24 |
| Peak memory | 245080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737670638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3737670638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.701113277 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 1242239997 ps |
| CPU time | 22.63 seconds |
| Started | Oct 09 10:45:51 AM UTC 24 |
| Finished | Oct 09 10:46:15 AM UTC 24 |
| Peak memory | 249092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701113277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.701113277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3916832088 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 1628841942 ps |
| CPU time | 3.85 seconds |
| Started | Oct 09 10:45:45 AM UTC 24 |
| Finished | Oct 09 10:45:50 AM UTC 24 |
| Peak memory | 234780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916832088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3916832088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.3275158879 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 1094535915 ps |
| CPU time | 14.83 seconds |
| Started | Oct 09 10:45:47 AM UTC 24 |
| Finished | Oct 09 10:46:03 AM UTC 24 |
| Peak memory | 234768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275158879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3275158879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1614939172 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 15853644174 ps |
| CPU time | 33.8 seconds |
| Started | Oct 09 10:45:42 AM UTC 24 |
| Finished | Oct 09 10:46:17 AM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614939172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.1614939172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.77625963 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 5148298076 ps |
| CPU time | 7.68 seconds |
| Started | Oct 09 10:45:42 AM UTC 24 |
| Finished | Oct 09 10:45:50 AM UTC 24 |
| Peak memory | 234988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77625963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.77625963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1228932529 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3671515657 ps |
| CPU time | 10.42 seconds |
| Started | Oct 09 10:45:51 AM UTC 24 |
| Finished | Oct 09 10:46:03 AM UTC 24 |
| Peak memory | 233592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228932529 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.1228932529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.934488129 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 848306761 ps |
| CPU time | 11.85 seconds |
| Started | Oct 09 10:45:37 AM UTC 24 |
| Finished | Oct 09 10:45:50 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934488129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.934488129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2817532094 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 17566561249 ps |
| CPU time | 9.57 seconds |
| Started | Oct 09 10:45:36 AM UTC 24 |
| Finished | Oct 09 10:45:47 AM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817532094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2817532094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.4168411645 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 95782976 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 10:45:40 AM UTC 24 |
| Finished | Oct 09 10:45:44 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168411645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.4168411645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2097806318 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 22916235 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 10:45:37 AM UTC 24 |
| Finished | Oct 09 10:45:40 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097806318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2097806318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.4014555390 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 202419865 ps |
| CPU time | 3.49 seconds |
| Started | Oct 09 10:45:48 AM UTC 24 |
| Finished | Oct 09 10:45:53 AM UTC 24 |
| Peak memory | 247144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014555390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4014555390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.1654775122 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 19946521 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:46:27 AM UTC 24 |
| Finished | Oct 09 10:46:29 AM UTC 24 |
| Peak memory | 213740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654775122 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.1654775122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3216948860 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 1190791460 ps |
| CPU time | 8.4 seconds |
| Started | Oct 09 10:46:16 AM UTC 24 |
| Finished | Oct 09 10:46:26 AM UTC 24 |
| Peak memory | 234664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216948860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3216948860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.239580087 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 63701509 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:46:04 AM UTC 24 |
| Finished | Oct 09 10:46:06 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239580087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.239580087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.2577550354 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 187897338309 ps |
| CPU time | 339.88 seconds |
| Started | Oct 09 10:46:20 AM UTC 24 |
| Finished | Oct 09 10:52:05 AM UTC 24 |
| Peak memory | 267608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577550354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2577550354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.4256126636 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 51454572959 ps |
| CPU time | 131.37 seconds |
| Started | Oct 09 10:46:21 AM UTC 24 |
| Finished | Oct 09 10:48:34 AM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256126636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4256126636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1545637860 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 76647037816 ps |
| CPU time | 695.87 seconds |
| Started | Oct 09 10:46:25 AM UTC 24 |
| Finished | Oct 09 10:58:10 AM UTC 24 |
| Peak memory | 273868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545637860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.1545637860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3156409018 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 98750096 ps |
| CPU time | 4.82 seconds |
| Started | Oct 09 10:46:18 AM UTC 24 |
| Finished | Oct 09 10:46:24 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156409018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3156409018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2340289674 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2087551897 ps |
| CPU time | 65.78 seconds |
| Started | Oct 09 10:46:18 AM UTC 24 |
| Finished | Oct 09 10:47:26 AM UTC 24 |
| Peak memory | 261376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340289674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.2340289674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1197806247 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 1436925927 ps |
| CPU time | 7.17 seconds |
| Started | Oct 09 10:46:11 AM UTC 24 |
| Finished | Oct 09 10:46:19 AM UTC 24 |
| Peak memory | 244956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197806247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1197806247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.891358923 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 23916770284 ps |
| CPU time | 76.83 seconds |
| Started | Oct 09 10:46:15 AM UTC 24 |
| Finished | Oct 09 10:47:34 AM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891358923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.891358923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2442697188 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 420440363 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 10:46:11 AM UTC 24 |
| Finished | Oct 09 10:46:15 AM UTC 24 |
| Peak memory | 233260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442697188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.2442697188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3717680204 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 64192226 ps |
| CPU time | 3.03 seconds |
| Started | Oct 09 10:46:10 AM UTC 24 |
| Finished | Oct 09 10:46:14 AM UTC 24 |
| Peak memory | 244648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717680204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3717680204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1573213104 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 90253553 ps |
| CPU time | 5.34 seconds |
| Started | Oct 09 10:46:19 AM UTC 24 |
| Finished | Oct 09 10:46:26 AM UTC 24 |
| Peak memory | 233448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573213104 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.1573213104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1291070822 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 122680008 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:46:27 AM UTC 24 |
| Finished | Oct 09 10:46:29 AM UTC 24 |
| Peak memory | 215600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291070822 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.1291070822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2939182121 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 56241707549 ps |
| CPU time | 26.28 seconds |
| Started | Oct 09 10:46:04 AM UTC 24 |
| Finished | Oct 09 10:46:32 AM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939182121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2939182121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1047631837 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 70512264 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:46:04 AM UTC 24 |
| Finished | Oct 09 10:46:06 AM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047631837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1047631837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.3632922266 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 63036576 ps |
| CPU time | 1.69 seconds |
| Started | Oct 09 10:46:08 AM UTC 24 |
| Finished | Oct 09 10:46:10 AM UTC 24 |
| Peak memory | 217024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632922266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3632922266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2685550258 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 20789094 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:46:07 AM UTC 24 |
| Finished | Oct 09 10:46:10 AM UTC 24 |
| Peak memory | 216080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685550258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2685550258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.3285146890 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 3384161266 ps |
| CPU time | 17.94 seconds |
| Started | Oct 09 10:46:16 AM UTC 24 |
| Finished | Oct 09 10:46:35 AM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285146890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3285146890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2578435174 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 82822953 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:25:52 AM UTC 24 |
| Finished | Oct 09 10:25:54 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578435174 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2578435174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.986859906 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 199750928 ps |
| CPU time | 2.96 seconds |
| Started | Oct 09 10:25:38 AM UTC 24 |
| Finished | Oct 09 10:25:42 AM UTC 24 |
| Peak memory | 244584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986859906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.986859906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.2660474994 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 21089860 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:25:20 AM UTC 24 |
| Finished | Oct 09 10:25:23 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660474994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2660474994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.1609790197 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 40161201405 ps |
| CPU time | 44.94 seconds |
| Started | Oct 09 10:25:44 AM UTC 24 |
| Finished | Oct 09 10:26:30 AM UTC 24 |
| Peak memory | 245080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609790197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1609790197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2404405980 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2144637329 ps |
| CPU time | 44.43 seconds |
| Started | Oct 09 10:25:49 AM UTC 24 |
| Finished | Oct 09 10:26:35 AM UTC 24 |
| Peak memory | 261644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404405980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.2404405980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.66815243 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 431341586 ps |
| CPU time | 14.22 seconds |
| Started | Oct 09 10:25:40 AM UTC 24 |
| Finished | Oct 09 10:25:56 AM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66815243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.66815243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.929760721 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 6668890332 ps |
| CPU time | 36.44 seconds |
| Started | Oct 09 10:25:42 AM UTC 24 |
| Finished | Oct 09 10:26:20 AM UTC 24 |
| Peak memory | 261732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929760721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.929760721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3481946614 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 651426231 ps |
| CPU time | 10.05 seconds |
| Started | Oct 09 10:25:30 AM UTC 24 |
| Finished | Oct 09 10:25:41 AM UTC 24 |
| Peak memory | 234864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481946614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3481946614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2519215943 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2897159406 ps |
| CPU time | 39.93 seconds |
| Started | Oct 09 10:25:35 AM UTC 24 |
| Finished | Oct 09 10:26:16 AM UTC 24 |
| Peak memory | 234728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519215943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2519215943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.4157204753 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 211753389 ps |
| CPU time | 6.25 seconds |
| Started | Oct 09 10:25:30 AM UTC 24 |
| Finished | Oct 09 10:25:37 AM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157204753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.4157204753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2426029008 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 555752357 ps |
| CPU time | 5.34 seconds |
| Started | Oct 09 10:25:28 AM UTC 24 |
| Finished | Oct 09 10:25:34 AM UTC 24 |
| Peak memory | 234724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426029008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2426029008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3531235770 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1234104532 ps |
| CPU time | 6.94 seconds |
| Started | Oct 09 10:25:43 AM UTC 24 |
| Finished | Oct 09 10:25:51 AM UTC 24 |
| Peak memory | 231188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531235770 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.3531235770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.3624670344 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6795880090 ps |
| CPU time | 97.9 seconds |
| Started | Oct 09 10:25:50 AM UTC 24 |
| Finished | Oct 09 10:27:30 AM UTC 24 |
| Peak memory | 267728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624670344 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.3624670344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1331854559 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 22108657824 ps |
| CPU time | 39.7 seconds |
| Started | Oct 09 10:25:27 AM UTC 24 |
| Finished | Oct 09 10:26:08 AM UTC 24 |
| Peak memory | 227784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331854559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1331854559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3820743161 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 20550930 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:25:23 AM UTC 24 |
| Finished | Oct 09 10:25:26 AM UTC 24 |
| Peak memory | 215724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820743161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3820743161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.597931471 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 286200135 ps |
| CPU time | 11.47 seconds |
| Started | Oct 09 10:25:27 AM UTC 24 |
| Finished | Oct 09 10:25:39 AM UTC 24 |
| Peak memory | 227356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597931471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.597931471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.1303312697 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 91019377 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:25:27 AM UTC 24 |
| Finished | Oct 09 10:25:29 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303312697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1303312697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3355792087 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 371404718 ps |
| CPU time | 6.79 seconds |
| Started | Oct 09 10:25:35 AM UTC 24 |
| Finished | Oct 09 10:25:43 AM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355792087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3355792087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.3391239862 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 15506765 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:26:31 AM UTC 24 |
| Finished | Oct 09 10:26:33 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391239862 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3391239862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2527331842 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 817018469 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 10:26:10 AM UTC 24 |
| Finished | Oct 09 10:26:16 AM UTC 24 |
| Peak memory | 234728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527331842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2527331842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2508339874 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 61323946 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 10:25:55 AM UTC 24 |
| Finished | Oct 09 10:25:57 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508339874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2508339874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.2244415945 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3552705584 ps |
| CPU time | 59.41 seconds |
| Started | Oct 09 10:26:18 AM UTC 24 |
| Finished | Oct 09 10:27:20 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244415945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2244415945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2324286148 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 7945183380 ps |
| CPU time | 135.59 seconds |
| Started | Oct 09 10:26:22 AM UTC 24 |
| Finished | Oct 09 10:28:40 AM UTC 24 |
| Peak memory | 263896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324286148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2324286148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1352380563 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1582326829 ps |
| CPU time | 41.15 seconds |
| Started | Oct 09 10:26:16 AM UTC 24 |
| Finished | Oct 09 10:26:59 AM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352380563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1352380563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2448565380 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5384274348 ps |
| CPU time | 29.56 seconds |
| Started | Oct 09 10:26:17 AM UTC 24 |
| Finished | Oct 09 10:26:48 AM UTC 24 |
| Peak memory | 249168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448565380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.2448565380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.2402750367 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 46932414 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 10:26:05 AM UTC 24 |
| Finished | Oct 09 10:26:09 AM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402750367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2402750367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.3763765927 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 6645784445 ps |
| CPU time | 47.54 seconds |
| Started | Oct 09 10:26:09 AM UTC 24 |
| Finished | Oct 09 10:26:58 AM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763765927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3763765927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.4272305308 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4134429808 ps |
| CPU time | 22.72 seconds |
| Started | Oct 09 10:26:03 AM UTC 24 |
| Finished | Oct 09 10:26:27 AM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272305308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.4272305308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1817578587 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 534463534 ps |
| CPU time | 5.02 seconds |
| Started | Oct 09 10:26:02 AM UTC 24 |
| Finished | Oct 09 10:26:08 AM UTC 24 |
| Peak memory | 244992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817578587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1817578587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3410353026 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2959270029 ps |
| CPU time | 18.75 seconds |
| Started | Oct 09 10:26:17 AM UTC 24 |
| Finished | Oct 09 10:26:37 AM UTC 24 |
| Peak memory | 231320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410353026 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.3410353026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.468383104 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 28125142483 ps |
| CPU time | 59.86 seconds |
| Started | Oct 09 10:25:58 AM UTC 24 |
| Finished | Oct 09 10:27:00 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468383104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.468383104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3423720349 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2249681990 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 10:25:56 AM UTC 24 |
| Finished | Oct 09 10:26:02 AM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423720349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3423720349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2653226264 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 209340969 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 10:26:02 AM UTC 24 |
| Finished | Oct 09 10:26:04 AM UTC 24 |
| Peak memory | 215884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653226264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2653226264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2780479286 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 37403592 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 10:25:58 AM UTC 24 |
| Finished | Oct 09 10:26:01 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780479286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2780479286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.2903241665 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 8022356711 ps |
| CPU time | 19.13 seconds |
| Started | Oct 09 10:26:09 AM UTC 24 |
| Finished | Oct 09 10:26:29 AM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903241665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2903241665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.3731364012 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 20244341 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:27:07 AM UTC 24 |
| Finished | Oct 09 10:27:09 AM UTC 24 |
| Peak memory | 215596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731364012 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3731364012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3917033195 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 76419358 ps |
| CPU time | 3.33 seconds |
| Started | Oct 09 10:26:53 AM UTC 24 |
| Finished | Oct 09 10:26:58 AM UTC 24 |
| Peak memory | 234772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917033195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3917033195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.1251950646 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 89592220 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:26:34 AM UTC 24 |
| Finished | Oct 09 10:26:36 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251950646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1251950646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.205877387 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 41620642873 ps |
| CPU time | 124.07 seconds |
| Started | Oct 09 10:26:59 AM UTC 24 |
| Finished | Oct 09 10:29:06 AM UTC 24 |
| Peak memory | 261676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205877387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.205877387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2985731136 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 26533561513 ps |
| CPU time | 328.58 seconds |
| Started | Oct 09 10:26:59 AM UTC 24 |
| Finished | Oct 09 10:32:33 AM UTC 24 |
| Peak memory | 278108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985731136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2985731136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2167204771 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5283510966 ps |
| CPU time | 65.42 seconds |
| Started | Oct 09 10:27:01 AM UTC 24 |
| Finished | Oct 09 10:28:08 AM UTC 24 |
| Peak memory | 261580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167204771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.2167204771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.4130621944 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1304364865 ps |
| CPU time | 14.09 seconds |
| Started | Oct 09 10:26:55 AM UTC 24 |
| Finished | Oct 09 10:27:11 AM UTC 24 |
| Peak memory | 234708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130621944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4130621944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3273627715 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2403164102 ps |
| CPU time | 52.27 seconds |
| Started | Oct 09 10:26:58 AM UTC 24 |
| Finished | Oct 09 10:27:52 AM UTC 24 |
| Peak memory | 261380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273627715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.3273627715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2574016989 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1827365515 ps |
| CPU time | 26.6 seconds |
| Started | Oct 09 10:26:50 AM UTC 24 |
| Finished | Oct 09 10:27:18 AM UTC 24 |
| Peak memory | 234780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574016989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2574016989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.1713540463 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 314469713 ps |
| CPU time | 6.7 seconds |
| Started | Oct 09 10:26:52 AM UTC 24 |
| Finished | Oct 09 10:27:00 AM UTC 24 |
| Peak memory | 234776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713540463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1713540463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2383445700 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 547079037 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 10:26:49 AM UTC 24 |
| Finished | Oct 09 10:26:55 AM UTC 24 |
| Peak memory | 234844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383445700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.2383445700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.293549821 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1945786556 ps |
| CPU time | 16.36 seconds |
| Started | Oct 09 10:26:49 AM UTC 24 |
| Finished | Oct 09 10:27:06 AM UTC 24 |
| Peak memory | 245000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293549821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.293549821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1850046949 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 702822013 ps |
| CPU time | 6.53 seconds |
| Started | Oct 09 10:26:59 AM UTC 24 |
| Finished | Oct 09 10:27:07 AM UTC 24 |
| Peak memory | 231252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850046949 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.1850046949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.3452800875 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3069823411 ps |
| CPU time | 11.76 seconds |
| Started | Oct 09 10:26:38 AM UTC 24 |
| Finished | Oct 09 10:26:52 AM UTC 24 |
| Peak memory | 227716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452800875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3452800875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3585628659 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3910448336 ps |
| CPU time | 13.65 seconds |
| Started | Oct 09 10:26:37 AM UTC 24 |
| Finished | Oct 09 10:26:52 AM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585628659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3585628659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.683802025 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 160230555 ps |
| CPU time | 3.61 seconds |
| Started | Oct 09 10:26:42 AM UTC 24 |
| Finished | Oct 09 10:26:47 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683802025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.683802025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.894839167 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 122138026 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 10:26:39 AM UTC 24 |
| Finished | Oct 09 10:26:42 AM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894839167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.894839167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.791599211 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 505294588 ps |
| CPU time | 4.37 seconds |
| Started | Oct 09 10:26:53 AM UTC 24 |
| Finished | Oct 09 10:26:58 AM UTC 24 |
| Peak memory | 245032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791599211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.791599211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.2629429082 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 13482224 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:27:37 AM UTC 24 |
| Finished | Oct 09 10:27:39 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629429082 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2629429082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1810908306 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 110018629 ps |
| CPU time | 3.53 seconds |
| Started | Oct 09 10:27:22 AM UTC 24 |
| Finished | Oct 09 10:27:26 AM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810908306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1810908306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.2802175871 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 52162181 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 10:27:08 AM UTC 24 |
| Finished | Oct 09 10:27:10 AM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802175871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2802175871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1186085644 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 15107497087 ps |
| CPU time | 167.41 seconds |
| Started | Oct 09 10:27:30 AM UTC 24 |
| Finished | Oct 09 10:30:21 AM UTC 24 |
| Peak memory | 277852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186085644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1186085644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1830919042 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 9595120669 ps |
| CPU time | 170.36 seconds |
| Started | Oct 09 10:27:31 AM UTC 24 |
| Finished | Oct 09 10:30:25 AM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830919042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1830919042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.2836337679 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 6905356635 ps |
| CPU time | 29.51 seconds |
| Started | Oct 09 10:27:25 AM UTC 24 |
| Finished | Oct 09 10:27:56 AM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836337679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2836337679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3790665372 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1961812676 ps |
| CPU time | 8.19 seconds |
| Started | Oct 09 10:27:27 AM UTC 24 |
| Finished | Oct 09 10:27:36 AM UTC 24 |
| Peak memory | 234652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790665372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.3790665372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.487678279 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1786505734 ps |
| CPU time | 14.6 seconds |
| Started | Oct 09 10:27:19 AM UTC 24 |
| Finished | Oct 09 10:27:34 AM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487678279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.487678279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.1728927353 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 8027133605 ps |
| CPU time | 44.17 seconds |
| Started | Oct 09 10:27:21 AM UTC 24 |
| Finished | Oct 09 10:28:06 AM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728927353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1728927353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.510010721 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2636468966 ps |
| CPU time | 15.47 seconds |
| Started | Oct 09 10:27:17 AM UTC 24 |
| Finished | Oct 09 10:27:33 AM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510010721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.510010721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2051988744 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2692218534 ps |
| CPU time | 3.95 seconds |
| Started | Oct 09 10:27:16 AM UTC 24 |
| Finished | Oct 09 10:27:21 AM UTC 24 |
| Peak memory | 245016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051988744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2051988744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1193910467 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2082839443 ps |
| CPU time | 10.56 seconds |
| Started | Oct 09 10:27:27 AM UTC 24 |
| Finished | Oct 09 10:27:39 AM UTC 24 |
| Peak memory | 233348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193910467 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.1193910467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1023481985 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12771861836 ps |
| CPU time | 70.11 seconds |
| Started | Oct 09 10:27:36 AM UTC 24 |
| Finished | Oct 09 10:28:47 AM UTC 24 |
| Peak memory | 263684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023481985 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.1023481985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.309221188 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3002889022 ps |
| CPU time | 22.29 seconds |
| Started | Oct 09 10:27:12 AM UTC 24 |
| Finished | Oct 09 10:27:36 AM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309221188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.309221188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.147655734 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1424703759 ps |
| CPU time | 12.18 seconds |
| Started | Oct 09 10:27:11 AM UTC 24 |
| Finished | Oct 09 10:27:24 AM UTC 24 |
| Peak memory | 227648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147655734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.147655734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.3295120389 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 188529410 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 10:27:16 AM UTC 24 |
| Finished | Oct 09 10:27:20 AM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295120389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3295120389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.562878525 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 147766403 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:27:13 AM UTC 24 |
| Finished | Oct 09 10:27:16 AM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562878525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.562878525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.401462508 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 631667573 ps |
| CPU time | 3.62 seconds |
| Started | Oct 09 10:27:22 AM UTC 24 |
| Finished | Oct 09 10:27:26 AM UTC 24 |
| Peak memory | 234916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401462508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.401462508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3918859565 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 11354580 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:28:09 AM UTC 24 |
| Finished | Oct 09 10:28:11 AM UTC 24 |
| Peak memory | 215656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918859565 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3918859565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1567744918 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 36092035 ps |
| CPU time | 2.5 seconds |
| Started | Oct 09 10:27:55 AM UTC 24 |
| Finished | Oct 09 10:27:59 AM UTC 24 |
| Peak memory | 244908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567744918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1567744918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.29034651 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 15952340 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:27:38 AM UTC 24 |
| Finished | Oct 09 10:27:40 AM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29034651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.29034651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.4091491357 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 8228333394 ps |
| CPU time | 46.83 seconds |
| Started | Oct 09 10:27:59 AM UTC 24 |
| Finished | Oct 09 10:28:48 AM UTC 24 |
| Peak memory | 263516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091491357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4091491357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1179422269 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 22599146703 ps |
| CPU time | 210.01 seconds |
| Started | Oct 09 10:28:00 AM UTC 24 |
| Finished | Oct 09 10:31:34 AM UTC 24 |
| Peak memory | 267732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179422269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1179422269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3216061175 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3669181697 ps |
| CPU time | 24.15 seconds |
| Started | Oct 09 10:28:06 AM UTC 24 |
| Finished | Oct 09 10:28:31 AM UTC 24 |
| Peak memory | 234884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216061175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.3216061175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.491813662 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 17249830599 ps |
| CPU time | 78.2 seconds |
| Started | Oct 09 10:27:56 AM UTC 24 |
| Finished | Oct 09 10:29:16 AM UTC 24 |
| Peak memory | 245040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491813662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.491813662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.4080465243 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 8091120253 ps |
| CPU time | 55.96 seconds |
| Started | Oct 09 10:27:57 AM UTC 24 |
| Finished | Oct 09 10:28:55 AM UTC 24 |
| Peak memory | 261456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080465243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.4080465243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2997188547 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 176787514 ps |
| CPU time | 7.19 seconds |
| Started | Oct 09 10:27:46 AM UTC 24 |
| Finished | Oct 09 10:27:54 AM UTC 24 |
| Peak memory | 244964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997188547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2997188547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3365066408 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 28779809601 ps |
| CPU time | 57.48 seconds |
| Started | Oct 09 10:27:53 AM UTC 24 |
| Finished | Oct 09 10:28:52 AM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365066408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3365066408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.85615350 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1410061209 ps |
| CPU time | 10.61 seconds |
| Started | Oct 09 10:27:43 AM UTC 24 |
| Finished | Oct 09 10:27:55 AM UTC 24 |
| Peak memory | 244960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85615350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.85615350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3187924217 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 8420895137 ps |
| CPU time | 14.26 seconds |
| Started | Oct 09 10:27:41 AM UTC 24 |
| Finished | Oct 09 10:27:57 AM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187924217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3187924217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.808928979 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 89203775 ps |
| CPU time | 6.41 seconds |
| Started | Oct 09 10:27:57 AM UTC 24 |
| Finished | Oct 09 10:28:05 AM UTC 24 |
| Peak memory | 233300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808928979 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.808928979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.1187050877 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 6288150132 ps |
| CPU time | 58.85 seconds |
| Started | Oct 09 10:28:08 AM UTC 24 |
| Finished | Oct 09 10:29:08 AM UTC 24 |
| Peak memory | 235164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187050877 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.1187050877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3556218091 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4011771023 ps |
| CPU time | 34.84 seconds |
| Started | Oct 09 10:27:40 AM UTC 24 |
| Finished | Oct 09 10:28:16 AM UTC 24 |
| Peak memory | 227412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556218091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3556218091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.508650426 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3518951721 ps |
| CPU time | 10.32 seconds |
| Started | Oct 09 10:27:40 AM UTC 24 |
| Finished | Oct 09 10:27:51 AM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508650426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.508650426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1788653318 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 259221336 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 10:27:41 AM UTC 24 |
| Finished | Oct 09 10:27:45 AM UTC 24 |
| Peak memory | 227296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788653318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1788653318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1157984579 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 145106847 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 10:27:40 AM UTC 24 |
| Finished | Oct 09 10:27:43 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157984579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1157984579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.974220338 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4469322055 ps |
| CPU time | 32.84 seconds |
| Started | Oct 09 10:27:53 AM UTC 24 |
| Finished | Oct 09 10:28:27 AM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974220338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.974220338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |