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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.74 98.65 96.80 99.01 89.36 98.51 95.57 99.26


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html

T459 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.2165891568 Oct 12 08:47:43 AM UTC 24 Oct 12 08:47:48 AM UTC 24 108100353 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2494290214 Oct 12 08:41:43 AM UTC 24 Oct 12 08:47:48 AM UTC 24 27970246261 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2980314559 Oct 12 08:47:45 AM UTC 24 Oct 12 08:47:49 AM UTC 24 498895228 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.3996098160 Oct 12 08:47:07 AM UTC 24 Oct 12 08:47:53 AM UTC 24 11737588842 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1720410840 Oct 12 08:42:22 AM UTC 24 Oct 12 08:47:57 AM UTC 24 28680947412 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.1563275220 Oct 12 08:47:57 AM UTC 24 Oct 12 08:48:00 AM UTC 24 13694012 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.2814467516 Oct 12 08:47:25 AM UTC 24 Oct 12 08:48:02 AM UTC 24 2967796210 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.2570358010 Oct 12 08:48:00 AM UTC 24 Oct 12 08:48:03 AM UTC 24 44154130 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.3178190516 Oct 12 08:49:33 AM UTC 24 Oct 12 08:49:39 AM UTC 24 115696914 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.2702251865 Oct 12 08:47:45 AM UTC 24 Oct 12 08:48:07 AM UTC 24 16706880957 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.516520637 Oct 12 08:48:07 AM UTC 24 Oct 12 08:48:09 AM UTC 24 18635811 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.3542357044 Oct 12 08:41:02 AM UTC 24 Oct 12 08:48:11 AM UTC 24 78594037113 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.4275677612 Oct 12 08:47:49 AM UTC 24 Oct 12 08:48:11 AM UTC 24 561443710 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.606064205 Oct 12 08:48:08 AM UTC 24 Oct 12 08:48:11 AM UTC 24 233053586 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.315076723 Oct 12 08:47:48 AM UTC 24 Oct 12 08:48:12 AM UTC 24 2644190852 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3470636813 Oct 12 08:48:12 AM UTC 24 Oct 12 08:48:21 AM UTC 24 1002067126 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2770136060 Oct 12 08:48:11 AM UTC 24 Oct 12 08:48:25 AM UTC 24 615340209 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3205698597 Oct 12 08:48:04 AM UTC 24 Oct 12 08:48:25 AM UTC 24 5469315953 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1350125905 Oct 12 08:47:46 AM UTC 24 Oct 12 08:48:26 AM UTC 24 3949322285 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2541484096 Oct 12 08:48:12 AM UTC 24 Oct 12 08:48:26 AM UTC 24 7930267634 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.531325368 Oct 12 08:48:10 AM UTC 24 Oct 12 08:48:28 AM UTC 24 10496158651 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.1875709004 Oct 12 08:48:22 AM UTC 24 Oct 12 08:48:32 AM UTC 24 470481614 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.1826561143 Oct 12 08:48:26 AM UTC 24 Oct 12 08:48:32 AM UTC 24 512148681 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.1218482029 Oct 12 08:48:33 AM UTC 24 Oct 12 08:48:36 AM UTC 24 25596162 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.3933382140 Oct 12 08:46:44 AM UTC 24 Oct 12 08:48:38 AM UTC 24 5714185591 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.3395100187 Oct 12 08:48:36 AM UTC 24 Oct 12 08:48:39 AM UTC 24 15750945 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2841291033 Oct 12 08:46:24 AM UTC 24 Oct 12 08:48:42 AM UTC 24 135834436639 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.94955540 Oct 12 08:48:40 AM UTC 24 Oct 12 08:48:44 AM UTC 24 196936898 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3996012095 Oct 12 08:48:43 AM UTC 24 Oct 12 08:48:45 AM UTC 24 58647101 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.2449016304 Oct 12 08:48:27 AM UTC 24 Oct 12 08:48:45 AM UTC 24 2670176831 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1272151322 Oct 12 08:46:28 AM UTC 24 Oct 12 08:48:48 AM UTC 24 10536233851 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.55263594 Oct 12 08:48:05 AM UTC 24 Oct 12 08:48:48 AM UTC 24 2340375768 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.3347194761 Oct 12 08:48:45 AM UTC 24 Oct 12 08:48:49 AM UTC 24 2106274939 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.2700120413 Oct 12 08:47:42 AM UTC 24 Oct 12 08:48:52 AM UTC 24 14328837718 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.803469217 Oct 12 08:48:46 AM UTC 24 Oct 12 08:48:53 AM UTC 24 383439933 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.3924133406 Oct 12 08:46:54 AM UTC 24 Oct 12 08:48:56 AM UTC 24 10793827774 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.3251201324 Oct 12 08:48:50 AM UTC 24 Oct 12 08:48:56 AM UTC 24 572960814 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.294835398 Oct 12 08:47:05 AM UTC 24 Oct 12 08:48:57 AM UTC 24 12575479255 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2597919703 Oct 12 08:48:46 AM UTC 24 Oct 12 08:48:59 AM UTC 24 8463354902 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.936431782 Oct 12 08:48:49 AM UTC 24 Oct 12 08:49:00 AM UTC 24 698510955 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.2397181610 Oct 12 08:48:53 AM UTC 24 Oct 12 08:49:02 AM UTC 24 469464044 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.2470192830 Oct 12 08:48:52 AM UTC 24 Oct 12 08:49:06 AM UTC 24 651375274 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.2290113753 Oct 12 08:48:49 AM UTC 24 Oct 12 08:49:07 AM UTC 24 776498288 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.2688312059 Oct 12 08:49:06 AM UTC 24 Oct 12 08:49:08 AM UTC 24 31889124 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.2519397528 Oct 12 08:49:08 AM UTC 24 Oct 12 08:49:10 AM UTC 24 34880411 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2695070152 Oct 12 08:49:09 AM UTC 24 Oct 12 08:49:13 AM UTC 24 1443399845 ps
T485 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1635874828 Oct 12 08:49:13 AM UTC 24 Oct 12 08:49:15 AM UTC 24 23887860 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.3941326712 Oct 12 08:49:14 AM UTC 24 Oct 12 08:49:17 AM UTC 24 69528463 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1102339199 Oct 12 08:48:31 AM UTC 24 Oct 12 08:49:19 AM UTC 24 1840363074 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.1616502097 Oct 12 08:48:42 AM UTC 24 Oct 12 08:49:21 AM UTC 24 6463442412 ps
T486 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2297955869 Oct 12 08:48:58 AM UTC 24 Oct 12 08:49:27 AM UTC 24 2309556128 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.629631804 Oct 12 08:43:46 AM UTC 24 Oct 12 08:49:33 AM UTC 24 36362864020 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.1647650365 Oct 12 08:49:12 AM UTC 24 Oct 12 08:49:34 AM UTC 24 4388448336 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2655837694 Oct 12 08:49:18 AM UTC 24 Oct 12 08:49:35 AM UTC 24 1056421336 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2266016727 Oct 12 08:44:53 AM UTC 24 Oct 12 08:49:36 AM UTC 24 63926923939 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.352598345 Oct 12 08:49:20 AM UTC 24 Oct 12 08:49:38 AM UTC 24 4053581773 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.559200018 Oct 12 08:45:28 AM UTC 24 Oct 12 08:49:38 AM UTC 24 15006391094 ps
T487 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.2547734816 Oct 12 08:49:34 AM UTC 24 Oct 12 08:49:39 AM UTC 24 284479554 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.252131814 Oct 12 08:49:28 AM UTC 24 Oct 12 08:49:39 AM UTC 24 702662242 ps
T488 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.3653158005 Oct 12 08:49:39 AM UTC 24 Oct 12 08:49:41 AM UTC 24 45697837 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3737721727 Oct 12 08:49:16 AM UTC 24 Oct 12 08:49:42 AM UTC 24 5176719346 ps
T489 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.3200363956 Oct 12 08:49:40 AM UTC 24 Oct 12 08:49:42 AM UTC 24 36556304 ps
T490 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1855235229 Oct 12 08:49:37 AM UTC 24 Oct 12 08:49:43 AM UTC 24 90804138 ps
T491 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.368021943 Oct 12 08:49:42 AM UTC 24 Oct 12 08:49:44 AM UTC 24 30898391 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3507433086 Oct 12 08:46:26 AM UTC 24 Oct 12 08:49:46 AM UTC 24 239565865040 ps
T492 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.2355967740 Oct 12 08:49:44 AM UTC 24 Oct 12 08:49:47 AM UTC 24 66673163 ps
T493 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.4193104843 Oct 12 08:49:43 AM UTC 24 Oct 12 08:49:47 AM UTC 24 4078192611 ps
T494 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.921470303 Oct 12 08:49:46 AM UTC 24 Oct 12 08:49:48 AM UTC 24 401213818 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.4287140527 Oct 12 08:49:22 AM UTC 24 Oct 12 08:49:49 AM UTC 24 2987809700 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.4106947769 Oct 12 08:48:12 AM UTC 24 Oct 12 08:49:53 AM UTC 24 7693842147 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3344833950 Oct 12 08:49:49 AM UTC 24 Oct 12 08:49:54 AM UTC 24 107687540 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1235579640 Oct 12 08:49:47 AM UTC 24 Oct 12 08:49:57 AM UTC 24 3754988526 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.1328369424 Oct 12 08:49:48 AM UTC 24 Oct 12 08:50:01 AM UTC 24 639317824 ps
T495 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.3048712319 Oct 12 08:49:53 AM UTC 24 Oct 12 08:50:01 AM UTC 24 776973841 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.475330965 Oct 12 08:41:01 AM UTC 24 Oct 12 08:50:01 AM UTC 24 47264025574 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2272329222 Oct 12 08:46:27 AM UTC 24 Oct 12 08:50:06 AM UTC 24 67237278200 ps
T496 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3404533730 Oct 12 08:47:49 AM UTC 24 Oct 12 08:50:08 AM UTC 24 57280573233 ps
T497 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.3850294677 Oct 12 08:49:46 AM UTC 24 Oct 12 08:50:08 AM UTC 24 10340595755 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.584420477 Oct 12 08:48:27 AM UTC 24 Oct 12 08:50:08 AM UTC 24 7597989750 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3107614223 Oct 12 08:49:50 AM UTC 24 Oct 12 08:50:09 AM UTC 24 1026097472 ps
T498 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1959964837 Oct 12 08:50:09 AM UTC 24 Oct 12 08:50:11 AM UTC 24 18830490 ps
T499 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.523718687 Oct 12 08:50:09 AM UTC 24 Oct 12 08:50:11 AM UTC 24 16044495 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2345103587 Oct 12 08:49:43 AM UTC 24 Oct 12 08:50:14 AM UTC 24 37891171501 ps
T500 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.496030329 Oct 12 08:50:10 AM UTC 24 Oct 12 08:50:14 AM UTC 24 141479153 ps
T501 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1134343841 Oct 12 08:50:12 AM UTC 24 Oct 12 08:50:14 AM UTC 24 11176967 ps
T502 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.2336923621 Oct 12 08:50:12 AM UTC 24 Oct 12 08:50:16 AM UTC 24 51726345 ps
T503 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2078671864 Oct 12 08:49:58 AM UTC 24 Oct 12 08:50:18 AM UTC 24 3670168299 ps
T504 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.801260416 Oct 12 08:50:14 AM UTC 24 Oct 12 08:50:18 AM UTC 24 101036636 ps
T505 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.1930251410 Oct 12 08:50:16 AM UTC 24 Oct 12 08:50:21 AM UTC 24 810345409 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.3793876282 Oct 12 08:46:43 AM UTC 24 Oct 12 08:50:26 AM UTC 24 26845660433 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.3666914526 Oct 12 08:50:19 AM UTC 24 Oct 12 08:50:28 AM UTC 24 1586996124 ps
T506 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2270362094 Oct 12 08:49:01 AM UTC 24 Oct 12 08:50:29 AM UTC 24 37325032017 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.3056326375 Oct 12 08:50:22 AM UTC 24 Oct 12 08:50:31 AM UTC 24 379720051 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.3205965870 Oct 12 08:41:05 AM UTC 24 Oct 12 08:50:33 AM UTC 24 652933334602 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.102329247 Oct 12 08:49:48 AM UTC 24 Oct 12 08:50:34 AM UTC 24 3864956046 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3787272231 Oct 12 08:49:39 AM UTC 24 Oct 12 08:50:34 AM UTC 24 2547752224 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.4192143831 Oct 12 08:47:50 AM UTC 24 Oct 12 08:50:34 AM UTC 24 11037854308 ps
T507 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1826606378 Oct 12 08:50:19 AM UTC 24 Oct 12 08:50:35 AM UTC 24 3229634766 ps
T508 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1773201581 Oct 12 08:50:29 AM UTC 24 Oct 12 08:50:37 AM UTC 24 123289678 ps
T509 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2828391095 Oct 12 08:50:36 AM UTC 24 Oct 12 08:50:38 AM UTC 24 30274419 ps
T510 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.2234576323 Oct 12 08:50:36 AM UTC 24 Oct 12 08:50:38 AM UTC 24 14697317 ps
T511 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.556692528 Oct 12 08:50:39 AM UTC 24 Oct 12 08:50:41 AM UTC 24 20306705 ps
T512 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3188609616 Oct 12 08:49:55 AM UTC 24 Oct 12 08:50:41 AM UTC 24 17842030788 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2351399245 Oct 12 08:48:57 AM UTC 24 Oct 12 08:50:42 AM UTC 24 12452892313 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1114674411 Oct 12 08:45:21 AM UTC 24 Oct 12 08:50:42 AM UTC 24 14035827943 ps
T513 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.3722441494 Oct 12 08:50:39 AM UTC 24 Oct 12 08:50:43 AM UTC 24 162394226 ps
T514 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2790096538 Oct 12 08:47:11 AM UTC 24 Oct 12 08:50:44 AM UTC 24 74614764779 ps
T515 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1464439194 Oct 12 08:50:33 AM UTC 24 Oct 12 08:50:46 AM UTC 24 2874621693 ps
T516 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3545501267 Oct 12 08:50:12 AM UTC 24 Oct 12 08:50:48 AM UTC 24 3299986468 ps
T517 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1013926874 Oct 12 08:50:45 AM UTC 24 Oct 12 08:50:49 AM UTC 24 39266027 ps
T518 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.4227688381 Oct 12 08:50:43 AM UTC 24 Oct 12 08:50:50 AM UTC 24 388479258 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.66027877 Oct 12 08:48:26 AM UTC 24 Oct 12 08:50:50 AM UTC 24 13905100520 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3264655029 Oct 12 08:50:16 AM UTC 24 Oct 12 08:50:52 AM UTC 24 36637750942 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1434963375 Oct 12 08:45:50 AM UTC 24 Oct 12 08:50:53 AM UTC 24 38675930678 ps
T519 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3773877088 Oct 12 08:50:50 AM UTC 24 Oct 12 08:50:57 AM UTC 24 124866648 ps
T520 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.3278585709 Oct 12 08:50:17 AM UTC 24 Oct 12 08:50:58 AM UTC 24 22447558842 ps
T521 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1632648714 Oct 12 08:50:36 AM UTC 24 Oct 12 08:51:00 AM UTC 24 15051477197 ps
T522 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1910990706 Oct 12 08:50:58 AM UTC 24 Oct 12 08:51:01 AM UTC 24 11859325 ps
T523 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2379494583 Oct 12 08:50:58 AM UTC 24 Oct 12 08:51:01 AM UTC 24 23494585 ps
T524 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3993827426 Oct 12 08:51:02 AM UTC 24 Oct 12 08:51:04 AM UTC 24 18802805 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.593865406 Oct 12 08:50:44 AM UTC 24 Oct 12 08:51:04 AM UTC 24 10660888412 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.4087088379 Oct 12 08:50:38 AM UTC 24 Oct 12 08:51:06 AM UTC 24 23418086060 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.454327999 Oct 12 08:50:47 AM UTC 24 Oct 12 08:51:06 AM UTC 24 953058518 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.4004961571 Oct 12 08:50:42 AM UTC 24 Oct 12 08:51:07 AM UTC 24 12135581335 ps
T525 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.1635134553 Oct 12 08:51:05 AM UTC 24 Oct 12 08:51:07 AM UTC 24 30094176 ps
T526 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.945171331 Oct 12 08:50:42 AM UTC 24 Oct 12 08:51:10 AM UTC 24 8738546855 ps
T527 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1711586982 Oct 12 08:51:07 AM UTC 24 Oct 12 08:51:11 AM UTC 24 33297847 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3957185908 Oct 12 08:47:10 AM UTC 24 Oct 12 08:51:12 AM UTC 24 31979389586 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.1205239363 Oct 12 08:45:20 AM UTC 24 Oct 12 08:51:13 AM UTC 24 81437197397 ps
T528 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3392891900 Oct 12 08:51:02 AM UTC 24 Oct 12 08:51:14 AM UTC 24 1050559724 ps
T529 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.342811830 Oct 12 08:51:18 AM UTC 24 Oct 12 08:51:20 AM UTC 24 37813711 ps
T530 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3010294147 Oct 12 08:51:11 AM UTC 24 Oct 12 08:51:15 AM UTC 24 56332700 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.260889754 Oct 12 08:51:08 AM UTC 24 Oct 12 08:51:16 AM UTC 24 764759332 ps
T531 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.4270315012 Oct 12 08:51:07 AM UTC 24 Oct 12 08:51:17 AM UTC 24 207334309 ps
T532 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.3366651710 Oct 12 08:51:02 AM UTC 24 Oct 12 08:51:17 AM UTC 24 628883472 ps
T533 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.1018179169 Oct 12 08:51:18 AM UTC 24 Oct 12 08:51:20 AM UTC 24 16329348 ps
T534 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.488512401 Oct 12 08:51:08 AM UTC 24 Oct 12 08:51:21 AM UTC 24 589975167 ps
T535 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3649868001 Oct 12 08:51:21 AM UTC 24 Oct 12 08:51:24 AM UTC 24 55424203 ps
T536 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1645540915 Oct 12 08:51:14 AM UTC 24 Oct 12 08:51:26 AM UTC 24 1150643056 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.4201745318 Oct 12 08:50:27 AM UTC 24 Oct 12 08:51:27 AM UTC 24 12793271827 ps
T537 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.3006803244 Oct 12 08:51:24 AM UTC 24 Oct 12 08:51:27 AM UTC 24 34388792 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1434947644 Oct 12 08:51:21 AM UTC 24 Oct 12 08:51:29 AM UTC 24 15542297904 ps
T538 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1975320444 Oct 12 08:51:26 AM UTC 24 Oct 12 08:51:30 AM UTC 24 212508516 ps
T539 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.4103504023 Oct 12 08:51:21 AM UTC 24 Oct 12 08:51:31 AM UTC 24 2066764527 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3124637965 Oct 12 08:51:27 AM UTC 24 Oct 12 08:51:34 AM UTC 24 667355693 ps
T540 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.995140469 Oct 12 08:45:56 AM UTC 24 Oct 12 08:51:37 AM UTC 24 30878123209 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2024548996 Oct 12 08:50:31 AM UTC 24 Oct 12 08:51:37 AM UTC 24 5609143008 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2552668023 Oct 12 08:50:51 AM UTC 24 Oct 12 08:51:39 AM UTC 24 7110066933 ps
T541 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2211111759 Oct 12 08:51:31 AM UTC 24 Oct 12 08:51:40 AM UTC 24 757092872 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2622384258 Oct 12 08:51:28 AM UTC 24 Oct 12 08:51:40 AM UTC 24 666163828 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1232878025 Oct 12 08:49:02 AM UTC 24 Oct 12 08:51:42 AM UTC 24 23225219445 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.81448576 Oct 12 08:45:53 AM UTC 24 Oct 12 08:51:43 AM UTC 24 164212597319 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.4025628209 Oct 12 08:51:43 AM UTC 24 Oct 12 08:51:45 AM UTC 24 24191146 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.226682098 Oct 12 08:51:39 AM UTC 24 Oct 12 08:51:46 AM UTC 24 268404307 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2545758483 Oct 12 08:51:44 AM UTC 24 Oct 12 08:51:46 AM UTC 24 29925517 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1369262022 Oct 12 08:51:47 AM UTC 24 Oct 12 08:51:50 AM UTC 24 248368365 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1168789126 Oct 12 08:51:06 AM UTC 24 Oct 12 08:51:51 AM UTC 24 8518354521 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3770081580 Oct 12 08:51:47 AM UTC 24 Oct 12 08:51:52 AM UTC 24 171716706 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.3517825557 Oct 12 08:51:46 AM UTC 24 Oct 12 08:51:52 AM UTC 24 289944644 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3999691835 Oct 12 08:51:12 AM UTC 24 Oct 12 08:51:52 AM UTC 24 1493579858 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.4055739301 Oct 12 08:46:43 AM UTC 24 Oct 12 08:51:54 AM UTC 24 193432333727 ps
T542 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.1319514140 Oct 12 08:51:32 AM UTC 24 Oct 12 08:51:55 AM UTC 24 480792228 ps
T543 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3591185512 Oct 12 08:51:41 AM UTC 24 Oct 12 08:51:55 AM UTC 24 1124561007 ps
T544 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.854024238 Oct 12 08:51:50 AM UTC 24 Oct 12 08:51:56 AM UTC 24 213306234 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2541328491 Oct 12 08:49:40 AM UTC 24 Oct 12 08:51:57 AM UTC 24 32879759765 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.1058970617 Oct 12 08:51:54 AM UTC 24 Oct 12 08:51:58 AM UTC 24 215677266 ps
T545 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1513149007 Oct 12 08:50:01 AM UTC 24 Oct 12 08:51:59 AM UTC 24 56942339111 ps
T546 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3235153243 Oct 12 08:51:56 AM UTC 24 Oct 12 08:52:00 AM UTC 24 71411242 ps
T547 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.2159436777 Oct 12 08:51:51 AM UTC 24 Oct 12 08:52:03 AM UTC 24 14799125218 ps
T548 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.3014197717 Oct 12 08:51:55 AM UTC 24 Oct 12 08:52:05 AM UTC 24 480611614 ps
T549 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1143504303 Oct 12 08:51:56 AM UTC 24 Oct 12 08:52:06 AM UTC 24 525920299 ps
T550 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3495179492 Oct 12 08:51:58 AM UTC 24 Oct 12 08:52:06 AM UTC 24 758293024 ps
T551 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2577235216 Oct 12 08:51:53 AM UTC 24 Oct 12 08:52:06 AM UTC 24 2441104405 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2453160415 Oct 12 08:51:53 AM UTC 24 Oct 12 08:52:07 AM UTC 24 3385675898 ps
T552 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.1528359956 Oct 12 08:52:06 AM UTC 24 Oct 12 08:52:08 AM UTC 24 48946107 ps
T553 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.2347991628 Oct 12 08:52:07 AM UTC 24 Oct 12 08:52:09 AM UTC 24 22114009 ps
T554 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1741763635 Oct 12 08:52:07 AM UTC 24 Oct 12 08:52:10 AM UTC 24 269438845 ps
T555 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.810209470 Oct 12 08:52:08 AM UTC 24 Oct 12 08:52:11 AM UTC 24 318102642 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.127759810 Oct 12 08:51:30 AM UTC 24 Oct 12 08:52:13 AM UTC 24 8349025717 ps
T556 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.3952077862 Oct 12 08:52:07 AM UTC 24 Oct 12 08:52:13 AM UTC 24 2258428996 ps
T557 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2049942643 Oct 12 08:52:09 AM UTC 24 Oct 12 08:52:15 AM UTC 24 1119716288 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.2503419417 Oct 12 08:47:53 AM UTC 24 Oct 12 08:52:15 AM UTC 24 10877959789 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.2304475162 Oct 12 08:52:11 AM UTC 24 Oct 12 08:52:16 AM UTC 24 518404364 ps
T558 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.285276677 Oct 12 08:50:49 AM UTC 24 Oct 12 08:52:16 AM UTC 24 11725687971 ps
T559 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3878417511 Oct 12 08:52:11 AM UTC 24 Oct 12 08:52:18 AM UTC 24 2759212906 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.756872039 Oct 12 08:52:16 AM UTC 24 Oct 12 08:52:20 AM UTC 24 35339554 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3876750745 Oct 12 08:50:53 AM UTC 24 Oct 12 08:52:20 AM UTC 24 4210096098 ps
T560 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3488796993 Oct 12 08:52:17 AM UTC 24 Oct 12 08:52:26 AM UTC 24 1234094846 ps
T561 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.136519726 Oct 12 08:50:43 AM UTC 24 Oct 12 08:52:34 AM UTC 24 31305404398 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1257751659 Oct 12 08:46:25 AM UTC 24 Oct 12 08:52:34 AM UTC 24 179997608213 ps
T562 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.398346841 Oct 12 08:51:28 AM UTC 24 Oct 12 08:52:36 AM UTC 24 12971649732 ps
T563 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.1530372960 Oct 12 08:52:34 AM UTC 24 Oct 12 08:52:36 AM UTC 24 12905931 ps
T564 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1202129788 Oct 12 08:52:35 AM UTC 24 Oct 12 08:52:37 AM UTC 24 56198668 ps
T565 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1624944667 Oct 12 08:52:10 AM UTC 24 Oct 12 08:52:38 AM UTC 24 37942659241 ps
T566 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2598423176 Oct 12 08:52:39 AM UTC 24 Oct 12 08:52:41 AM UTC 24 229846433 ps
T567 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.66523160 Oct 12 08:52:39 AM UTC 24 Oct 12 08:52:41 AM UTC 24 32430634 ps
T568 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1162378588 Oct 12 08:52:42 AM UTC 24 Oct 12 08:52:46 AM UTC 24 32916109 ps
T569 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.2237269537 Oct 12 08:51:59 AM UTC 24 Oct 12 08:52:50 AM UTC 24 14263376128 ps
T570 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.343017553 Oct 12 08:52:47 AM UTC 24 Oct 12 08:52:51 AM UTC 24 182427228 ps
T571 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.1817222839 Oct 12 08:52:38 AM UTC 24 Oct 12 08:52:52 AM UTC 24 3722337602 ps
T572 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1394252988 Oct 12 08:52:13 AM UTC 24 Oct 12 08:52:55 AM UTC 24 12938586538 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.2808490029 Oct 12 08:52:51 AM UTC 24 Oct 12 08:52:57 AM UTC 24 75707746 ps
T573 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.3074790013 Oct 12 08:52:49 AM UTC 24 Oct 12 08:52:59 AM UTC 24 1457560301 ps
T574 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.821011085 Oct 12 08:52:52 AM UTC 24 Oct 12 08:53:01 AM UTC 24 5203582444 ps
T575 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1294057984 Oct 12 08:52:38 AM UTC 24 Oct 12 08:53:04 AM UTC 24 10734719680 ps
T576 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.24013720 Oct 12 08:52:52 AM UTC 24 Oct 12 08:53:06 AM UTC 24 1589622693 ps
T577 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.179322214 Oct 12 08:52:58 AM UTC 24 Oct 12 08:53:08 AM UTC 24 1824253637 ps
T578 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.956307715 Oct 12 08:50:53 AM UTC 24 Oct 12 08:53:09 AM UTC 24 41352497371 ps
T579 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.3323730465 Oct 12 08:53:09 AM UTC 24 Oct 12 08:53:12 AM UTC 24 36313409 ps
T580 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3237552174 Oct 12 08:53:10 AM UTC 24 Oct 12 08:53:13 AM UTC 24 97672316 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.2806453080 Oct 12 08:51:39 AM UTC 24 Oct 12 08:53:15 AM UTC 24 14326519496 ps
T581 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.4127142132 Oct 12 08:53:17 AM UTC 24 Oct 12 08:53:19 AM UTC 24 41822537 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.343085573 Oct 12 08:52:16 AM UTC 24 Oct 12 08:53:19 AM UTC 24 3251856979 ps
T582 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.3180271496 Oct 12 08:53:20 AM UTC 24 Oct 12 08:53:24 AM UTC 24 181638080 ps
T583 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.175679498 Oct 12 08:53:13 AM UTC 24 Oct 12 08:53:27 AM UTC 24 8972914146 ps
T584 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.1776247193 Oct 12 08:52:42 AM UTC 24 Oct 12 08:53:30 AM UTC 24 176502012854 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3189374669 Oct 12 08:51:15 AM UTC 24 Oct 12 08:53:35 AM UTC 24 149746031360 ps
T585 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.1077866586 Oct 12 08:53:31 AM UTC 24 Oct 12 08:53:35 AM UTC 24 110545552 ps
T586 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.337098978 Oct 12 08:53:20 AM UTC 24 Oct 12 08:53:36 AM UTC 24 1998942360 ps
T587 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.898557027 Oct 12 08:52:14 AM UTC 24 Oct 12 08:53:36 AM UTC 24 19264872139 ps
T588 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.2777381377 Oct 12 08:51:16 AM UTC 24 Oct 12 08:53:37 AM UTC 24 201154850220 ps
T589 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.2164959374 Oct 12 08:53:36 AM UTC 24 Oct 12 08:53:41 AM UTC 24 383465581 ps
T590 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1638029530 Oct 12 08:53:36 AM UTC 24 Oct 12 08:53:41 AM UTC 24 175283430 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.1092116173 Oct 12 08:53:25 AM UTC 24 Oct 12 08:53:43 AM UTC 24 6261073390 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2315487504 Oct 12 08:53:28 AM UTC 24 Oct 12 08:53:45 AM UTC 24 2264909322 ps
T591 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2829660147 Oct 12 08:53:38 AM UTC 24 Oct 12 08:53:46 AM UTC 24 229498530 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.4175566715 Oct 12 08:52:18 AM UTC 24 Oct 12 08:53:48 AM UTC 24 17621145066 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1595761172 Oct 12 08:53:07 AM UTC 24 Oct 12 08:53:48 AM UTC 24 11654185995 ps
T592 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3191360003 Oct 12 08:52:21 AM UTC 24 Oct 12 08:53:48 AM UTC 24 3180289711 ps
T593 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.984704723 Oct 12 08:53:47 AM UTC 24 Oct 12 08:53:49 AM UTC 24 13980869 ps
T594 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.3155551236 Oct 12 08:53:48 AM UTC 24 Oct 12 08:53:50 AM UTC 24 17071390 ps
T595 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1971332829 Oct 12 08:50:03 AM UTC 24 Oct 12 08:53:51 AM UTC 24 21703501500 ps
T596 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3815903734 Oct 12 08:53:50 AM UTC 24 Oct 12 08:53:52 AM UTC 24 67752557 ps
T597 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1891222415 Oct 12 08:53:12 AM UTC 24 Oct 12 08:53:53 AM UTC 24 7278276746 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1378932486 Oct 12 08:53:36 AM UTC 24 Oct 12 08:53:54 AM UTC 24 1534654634 ps
T598 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.3800611300 Oct 12 08:53:51 AM UTC 24 Oct 12 08:53:55 AM UTC 24 42404328 ps
T599 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1144727982 Oct 12 08:53:49 AM UTC 24 Oct 12 08:53:56 AM UTC 24 563005626 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.1824878117 Oct 12 08:51:35 AM UTC 24 Oct 12 08:53:56 AM UTC 24 52476581666 ps
T600 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2606296730 Oct 12 08:53:42 AM UTC 24 Oct 12 08:53:57 AM UTC 24 3267674096 ps
T601 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3408217549 Oct 12 08:53:57 AM UTC 24 Oct 12 08:54:02 AM UTC 24 106060597 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.538728935 Oct 12 08:53:00 AM UTC 24 Oct 12 08:54:04 AM UTC 24 7752629160 ps
T602 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.542547818 Oct 12 08:53:37 AM UTC 24 Oct 12 08:54:06 AM UTC 24 2423602509 ps
T603 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3999475733 Oct 12 08:53:52 AM UTC 24 Oct 12 08:54:06 AM UTC 24 5366138756 ps
T604 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1238087185 Oct 12 08:53:56 AM UTC 24 Oct 12 08:54:07 AM UTC 24 632869867 ps
T605 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2859188394 Oct 12 08:50:03 AM UTC 24 Oct 12 08:54:08 AM UTC 24 20772571604 ps
T606 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.563721363 Oct 12 08:54:08 AM UTC 24 Oct 12 08:54:10 AM UTC 24 29342194 ps
T607 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3316818634 Oct 12 08:54:03 AM UTC 24 Oct 12 08:54:10 AM UTC 24 177821632 ps
T608 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.345241204 Oct 12 08:54:09 AM UTC 24 Oct 12 08:54:11 AM UTC 24 158805523 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.2212620835 Oct 12 08:51:41 AM UTC 24 Oct 12 08:54:13 AM UTC 24 235827810163 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.3494545212 Oct 12 08:44:53 AM UTC 24 Oct 12 08:54:13 AM UTC 24 100408160510 ps
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