| T826 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2248327999 |
|
|
Oct 12 08:58:12 AM UTC 24 |
Oct 12 08:58:29 AM UTC 24 |
1327468027 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.3148760015 |
|
|
Oct 12 08:58:20 AM UTC 24 |
Oct 12 08:58:29 AM UTC 24 |
638984623 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1918675412 |
|
|
Oct 12 08:57:31 AM UTC 24 |
Oct 12 08:58:31 AM UTC 24 |
2959393303 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.609125740 |
|
|
Oct 12 08:58:25 AM UTC 24 |
Oct 12 08:58:31 AM UTC 24 |
905408734 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.2031293573 |
|
|
Oct 12 08:58:26 AM UTC 24 |
Oct 12 08:58:33 AM UTC 24 |
1068497505 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.2439753751 |
|
|
Oct 12 08:58:07 AM UTC 24 |
Oct 12 08:58:34 AM UTC 24 |
2104938753 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.611802674 |
|
|
Oct 12 08:58:12 AM UTC 24 |
Oct 12 08:58:35 AM UTC 24 |
7289344282 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.2034831670 |
|
|
Oct 12 08:54:44 AM UTC 24 |
Oct 12 08:58:35 AM UTC 24 |
45633730750 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3068280050 |
|
|
Oct 12 08:51:41 AM UTC 24 |
Oct 12 08:58:36 AM UTC 24 |
37366813586 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.693046341 |
|
|
Oct 12 08:57:46 AM UTC 24 |
Oct 12 08:58:36 AM UTC 24 |
5053859182 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.2950867055 |
|
|
Oct 12 08:58:10 AM UTC 24 |
Oct 12 08:58:37 AM UTC 24 |
2777830038 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2364196964 |
|
|
Oct 12 08:58:10 AM UTC 24 |
Oct 12 08:58:37 AM UTC 24 |
1781365667 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2550657867 |
|
|
Oct 12 08:58:37 AM UTC 24 |
Oct 12 08:58:39 AM UTC 24 |
47991056 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.1153575481 |
|
|
Oct 12 08:58:38 AM UTC 24 |
Oct 12 08:58:40 AM UTC 24 |
37320662 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.575339218 |
|
|
Oct 12 08:58:29 AM UTC 24 |
Oct 12 08:58:41 AM UTC 24 |
4287490880 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.4142034865 |
|
|
Oct 12 08:58:34 AM UTC 24 |
Oct 12 08:58:42 AM UTC 24 |
2620453357 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.438945962 |
|
|
Oct 12 08:58:42 AM UTC 24 |
Oct 12 08:58:44 AM UTC 24 |
41712718 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2995379087 |
|
|
Oct 12 08:58:30 AM UTC 24 |
Oct 12 08:58:44 AM UTC 24 |
692530177 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.403586784 |
|
|
Oct 12 08:58:42 AM UTC 24 |
Oct 12 08:58:44 AM UTC 24 |
62142246 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.601236774 |
|
|
Oct 12 08:58:38 AM UTC 24 |
Oct 12 08:58:49 AM UTC 24 |
1891328407 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.922571138 |
|
|
Oct 12 08:58:27 AM UTC 24 |
Oct 12 08:58:52 AM UTC 24 |
5804748672 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.4220308444 |
|
|
Oct 12 08:58:45 AM UTC 24 |
Oct 12 08:58:53 AM UTC 24 |
3101773879 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1591017878 |
|
|
Oct 12 08:58:49 AM UTC 24 |
Oct 12 08:58:53 AM UTC 24 |
420708817 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.127179016 |
|
|
Oct 12 08:58:45 AM UTC 24 |
Oct 12 08:58:54 AM UTC 24 |
803178945 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.1199360092 |
|
|
Oct 12 08:55:02 AM UTC 24 |
Oct 12 08:58:55 AM UTC 24 |
32623555930 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.2362058437 |
|
|
Oct 12 08:56:52 AM UTC 24 |
Oct 12 08:58:56 AM UTC 24 |
4222301432 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2361076560 |
|
|
Oct 12 08:58:45 AM UTC 24 |
Oct 12 08:58:56 AM UTC 24 |
479907614 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.3123083525 |
|
|
Oct 12 08:58:02 AM UTC 24 |
Oct 12 08:58:58 AM UTC 24 |
3493265989 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.1276334018 |
|
|
Oct 12 08:58:32 AM UTC 24 |
Oct 12 08:58:58 AM UTC 24 |
2233524636 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.2550403516 |
|
|
Oct 12 08:58:57 AM UTC 24 |
Oct 12 08:58:59 AM UTC 24 |
16655829 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3198497827 |
|
|
Oct 12 08:58:06 AM UTC 24 |
Oct 12 08:58:59 AM UTC 24 |
3761138029 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3741615859 |
|
|
Oct 12 08:58:57 AM UTC 24 |
Oct 12 08:58:59 AM UTC 24 |
291954635 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1308062494 |
|
|
Oct 12 08:58:17 AM UTC 24 |
Oct 12 08:59:00 AM UTC 24 |
5287849054 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1126107264 |
|
|
Oct 12 08:58:59 AM UTC 24 |
Oct 12 08:59:01 AM UTC 24 |
26135989 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1478472022 |
|
|
Oct 12 08:59:00 AM UTC 24 |
Oct 12 08:59:03 AM UTC 24 |
182430112 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2475360899 |
|
|
Oct 12 08:59:00 AM UTC 24 |
Oct 12 08:59:03 AM UTC 24 |
48872173 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3289967605 |
|
|
Oct 12 08:58:06 AM UTC 24 |
Oct 12 08:59:04 AM UTC 24 |
23706022168 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.2922196234 |
|
|
Oct 12 08:58:50 AM UTC 24 |
Oct 12 08:59:05 AM UTC 24 |
2206250481 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.948670958 |
|
|
Oct 12 08:59:01 AM UTC 24 |
Oct 12 08:59:06 AM UTC 24 |
201906813 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1997045870 |
|
|
Oct 12 08:58:43 AM UTC 24 |
Oct 12 08:59:07 AM UTC 24 |
25129239723 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3523861448 |
|
|
Oct 12 08:58:17 AM UTC 24 |
Oct 12 08:59:07 AM UTC 24 |
7997540943 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2325580547 |
|
|
Oct 12 08:59:02 AM UTC 24 |
Oct 12 08:59:09 AM UTC 24 |
744958784 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1445065974 |
|
|
Oct 12 08:59:06 AM UTC 24 |
Oct 12 08:59:10 AM UTC 24 |
95406471 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1302080478 |
|
|
Oct 12 08:59:08 AM UTC 24 |
Oct 12 08:59:11 AM UTC 24 |
198387919 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3157586075 |
|
|
Oct 12 08:58:59 AM UTC 24 |
Oct 12 08:59:11 AM UTC 24 |
4117981462 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1168593384 |
|
|
Oct 12 08:59:13 AM UTC 24 |
Oct 12 08:59:15 AM UTC 24 |
32462205 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2223885923 |
|
|
Oct 12 08:58:53 AM UTC 24 |
Oct 12 08:59:15 AM UTC 24 |
5472987961 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3178131370 |
|
|
Oct 12 08:58:53 AM UTC 24 |
Oct 12 08:59:16 AM UTC 24 |
774800506 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1192806903 |
|
|
Oct 12 08:59:08 AM UTC 24 |
Oct 12 08:59:18 AM UTC 24 |
379149984 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.4242286949 |
|
|
Oct 12 08:59:16 AM UTC 24 |
Oct 12 08:59:18 AM UTC 24 |
44315776 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1714020998 |
|
|
Oct 12 08:59:18 AM UTC 24 |
Oct 12 08:59:20 AM UTC 24 |
37756222 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.4069202028 |
|
|
Oct 12 08:59:10 AM UTC 24 |
Oct 12 08:59:20 AM UTC 24 |
391787670 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.428123872 |
|
|
Oct 12 08:59:19 AM UTC 24 |
Oct 12 08:59:21 AM UTC 24 |
32162939 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3145399717 |
|
|
Oct 12 08:59:04 AM UTC 24 |
Oct 12 08:59:22 AM UTC 24 |
1212783735 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2905989623 |
|
|
Oct 12 08:59:05 AM UTC 24 |
Oct 12 08:59:23 AM UTC 24 |
6390887459 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.4251134683 |
|
|
Oct 12 08:57:47 AM UTC 24 |
Oct 12 08:59:25 AM UTC 24 |
5851471705 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2609172228 |
|
|
Oct 12 08:58:36 AM UTC 24 |
Oct 12 08:59:26 AM UTC 24 |
4771380326 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3300242540 |
|
|
Oct 12 08:58:28 AM UTC 24 |
Oct 12 08:59:26 AM UTC 24 |
4735439196 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.77175378 |
|
|
Oct 12 08:59:24 AM UTC 24 |
Oct 12 08:59:29 AM UTC 24 |
2156620465 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2516723147 |
|
|
Oct 12 08:59:05 AM UTC 24 |
Oct 12 08:59:29 AM UTC 24 |
5487915156 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1858470264 |
|
|
Oct 12 08:59:26 AM UTC 24 |
Oct 12 08:59:30 AM UTC 24 |
692386460 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1368667837 |
|
|
Oct 12 08:59:16 AM UTC 24 |
Oct 12 08:59:36 AM UTC 24 |
4561623240 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2214777938 |
|
|
Oct 12 08:59:21 AM UTC 24 |
Oct 12 08:59:39 AM UTC 24 |
6987564870 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1139083366 |
|
|
Oct 12 08:56:05 AM UTC 24 |
Oct 12 08:59:39 AM UTC 24 |
65926668552 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.1167562599 |
|
|
Oct 12 08:59:22 AM UTC 24 |
Oct 12 08:59:41 AM UTC 24 |
6547997721 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1935763362 |
|
|
Oct 12 08:59:21 AM UTC 24 |
Oct 12 08:59:42 AM UTC 24 |
5080007340 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.2520630442 |
|
|
Oct 12 08:59:40 AM UTC 24 |
Oct 12 08:59:42 AM UTC 24 |
11984886 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3240595621 |
|
|
Oct 12 08:59:40 AM UTC 24 |
Oct 12 08:59:42 AM UTC 24 |
73616129 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.2761446720 |
|
|
Oct 12 08:58:45 AM UTC 24 |
Oct 12 08:59:43 AM UTC 24 |
10202221744 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3790382176 |
|
|
Oct 12 08:59:43 AM UTC 24 |
Oct 12 08:59:45 AM UTC 24 |
36594641 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.944359715 |
|
|
Oct 12 08:58:55 AM UTC 24 |
Oct 12 08:59:46 AM UTC 24 |
3447639516 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.479423653 |
|
|
Oct 12 08:59:17 AM UTC 24 |
Oct 12 08:59:46 AM UTC 24 |
4408930399 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.470439570 |
|
|
Oct 12 08:59:42 AM UTC 24 |
Oct 12 08:59:47 AM UTC 24 |
528443174 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.700682896 |
|
|
Oct 12 08:56:22 AM UTC 24 |
Oct 12 08:59:49 AM UTC 24 |
53774736473 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.4162412852 |
|
|
Oct 12 08:59:07 AM UTC 24 |
Oct 12 08:59:49 AM UTC 24 |
5102837709 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.359171444 |
|
|
Oct 12 08:54:08 AM UTC 24 |
Oct 12 08:59:50 AM UTC 24 |
126052462797 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3299796409 |
|
|
Oct 12 08:59:43 AM UTC 24 |
Oct 12 08:59:50 AM UTC 24 |
87185025 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1289375854 |
|
|
Oct 12 08:59:44 AM UTC 24 |
Oct 12 08:59:51 AM UTC 24 |
209552709 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3902216607 |
|
|
Oct 12 08:59:27 AM UTC 24 |
Oct 12 08:59:53 AM UTC 24 |
4776148574 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.264697053 |
|
|
Oct 12 08:59:50 AM UTC 24 |
Oct 12 08:59:54 AM UTC 24 |
432928760 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.1512193833 |
|
|
Oct 12 08:59:29 AM UTC 24 |
Oct 12 08:59:56 AM UTC 24 |
4675007513 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.234438127 |
|
|
Oct 12 08:58:36 AM UTC 24 |
Oct 12 08:59:59 AM UTC 24 |
55545909257 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.3677105644 |
|
|
Oct 12 08:59:57 AM UTC 24 |
Oct 12 09:00:00 AM UTC 24 |
112711500 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3986958119 |
|
|
Oct 12 08:59:46 AM UTC 24 |
Oct 12 09:00:01 AM UTC 24 |
976456139 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.93729336 |
|
|
Oct 12 08:59:24 AM UTC 24 |
Oct 12 09:00:01 AM UTC 24 |
6975331908 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3991030924 |
|
|
Oct 12 08:59:59 AM UTC 24 |
Oct 12 09:00:01 AM UTC 24 |
36502161 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1103715869 |
|
|
Oct 12 08:59:51 AM UTC 24 |
Oct 12 09:00:02 AM UTC 24 |
1162771533 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2066990291 |
|
|
Oct 12 08:59:51 AM UTC 24 |
Oct 12 09:00:03 AM UTC 24 |
4812686832 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3191205512 |
|
|
Oct 12 08:59:43 AM UTC 24 |
Oct 12 09:00:03 AM UTC 24 |
1801742131 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.4095665627 |
|
|
Oct 12 09:00:01 AM UTC 24 |
Oct 12 09:00:07 AM UTC 24 |
19390570 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2978512909 |
|
|
Oct 12 09:00:03 AM UTC 24 |
Oct 12 09:00:08 AM UTC 24 |
23952737 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.301309706 |
|
|
Oct 12 08:59:46 AM UTC 24 |
Oct 12 09:00:08 AM UTC 24 |
4788761065 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.2849163181 |
|
|
Oct 12 08:59:00 AM UTC 24 |
Oct 12 09:00:08 AM UTC 24 |
38108960255 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2813595731 |
|
|
Oct 12 08:59:47 AM UTC 24 |
Oct 12 09:00:08 AM UTC 24 |
3133776689 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2972601523 |
|
|
Oct 12 09:00:01 AM UTC 24 |
Oct 12 09:00:11 AM UTC 24 |
721517544 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2882961942 |
|
|
Oct 12 09:00:09 AM UTC 24 |
Oct 12 09:00:14 AM UTC 24 |
76562286 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1025184135 |
|
|
Oct 12 09:00:08 AM UTC 24 |
Oct 12 09:00:15 AM UTC 24 |
296961002 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1489321583 |
|
|
Oct 12 08:59:30 AM UTC 24 |
Oct 12 09:00:16 AM UTC 24 |
7859474035 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2142368576 |
|
|
Oct 12 08:58:12 AM UTC 24 |
Oct 12 09:00:18 AM UTC 24 |
13612389307 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3351575269 |
|
|
Oct 12 09:00:12 AM UTC 24 |
Oct 12 09:00:18 AM UTC 24 |
437545001 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3278798309 |
|
|
Oct 12 09:00:07 AM UTC 24 |
Oct 12 09:00:19 AM UTC 24 |
1781852465 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.3949741764 |
|
|
Oct 12 09:00:17 AM UTC 24 |
Oct 12 09:00:20 AM UTC 24 |
138847731 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2748654049 |
|
|
Oct 12 09:00:15 AM UTC 24 |
Oct 12 09:00:20 AM UTC 24 |
161502319 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3555998835 |
|
|
Oct 12 09:00:18 AM UTC 24 |
Oct 12 09:00:20 AM UTC 24 |
19685203 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3697227314 |
|
|
Oct 12 09:00:18 AM UTC 24 |
Oct 12 09:00:20 AM UTC 24 |
20468942 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1676382009 |
|
|
Oct 12 09:00:09 AM UTC 24 |
Oct 12 09:00:21 AM UTC 24 |
1701611041 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.3899273492 |
|
|
Oct 12 09:00:08 AM UTC 24 |
Oct 12 09:00:23 AM UTC 24 |
2642350266 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.2879230596 |
|
|
Oct 12 08:58:04 AM UTC 24 |
Oct 12 09:00:23 AM UTC 24 |
96869328329 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1918220131 |
|
|
Oct 12 09:00:21 AM UTC 24 |
Oct 12 09:00:24 AM UTC 24 |
96185811 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.4220488546 |
|
|
Oct 12 09:00:21 AM UTC 24 |
Oct 12 09:00:24 AM UTC 24 |
33730781 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.319264756 |
|
|
Oct 12 09:00:09 AM UTC 24 |
Oct 12 09:00:24 AM UTC 24 |
1040283411 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2330140950 |
|
|
Oct 12 09:00:07 AM UTC 24 |
Oct 12 09:00:24 AM UTC 24 |
916863203 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1980064004 |
|
|
Oct 12 08:57:30 AM UTC 24 |
Oct 12 09:00:24 AM UTC 24 |
86696935313 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2941580507 |
|
|
Oct 12 08:57:15 AM UTC 24 |
Oct 12 09:00:25 AM UTC 24 |
9495647828 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.4103151223 |
|
|
Oct 12 09:00:20 AM UTC 24 |
Oct 12 09:00:26 AM UTC 24 |
594210043 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2933854961 |
|
|
Oct 12 09:00:23 AM UTC 24 |
Oct 12 09:00:29 AM UTC 24 |
1278294042 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1673930633 |
|
|
Oct 12 09:00:25 AM UTC 24 |
Oct 12 09:00:29 AM UTC 24 |
236360029 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3194014776 |
|
|
Oct 12 09:00:25 AM UTC 24 |
Oct 12 09:00:30 AM UTC 24 |
401517201 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.31519605 |
|
|
Oct 12 08:59:29 AM UTC 24 |
Oct 12 09:00:32 AM UTC 24 |
21300590600 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.4106023601 |
|
|
Oct 12 08:59:52 AM UTC 24 |
Oct 12 09:00:32 AM UTC 24 |
3897549734 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.4098150120 |
|
|
Oct 12 09:00:32 AM UTC 24 |
Oct 12 09:00:34 AM UTC 24 |
60388971 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.1674763162 |
|
|
Oct 12 09:00:33 AM UTC 24 |
Oct 12 09:00:35 AM UTC 24 |
28007811 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2207922486 |
|
|
Oct 12 09:00:33 AM UTC 24 |
Oct 12 09:00:35 AM UTC 24 |
34961555 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1550915540 |
|
|
Oct 12 09:00:25 AM UTC 24 |
Oct 12 09:00:36 AM UTC 24 |
1986321815 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.1635298657 |
|
|
Oct 12 09:00:25 AM UTC 24 |
Oct 12 09:00:36 AM UTC 24 |
5451582939 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.1201876130 |
|
|
Oct 12 09:00:24 AM UTC 24 |
Oct 12 09:00:36 AM UTC 24 |
3905514324 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1345124578 |
|
|
Oct 12 09:00:36 AM UTC 24 |
Oct 12 09:00:38 AM UTC 24 |
96596079 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.184416702 |
|
|
Oct 12 09:00:22 AM UTC 24 |
Oct 12 09:00:39 AM UTC 24 |
5767980620 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.952911308 |
|
|
Oct 12 09:00:36 AM UTC 24 |
Oct 12 09:00:41 AM UTC 24 |
106887549 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3221263060 |
|
|
Oct 12 09:00:37 AM UTC 24 |
Oct 12 09:00:42 AM UTC 24 |
33347685 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.650531358 |
|
|
Oct 12 09:00:03 AM UTC 24 |
Oct 12 09:00:42 AM UTC 24 |
2930292590 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2429345906 |
|
|
Oct 12 09:00:37 AM UTC 24 |
Oct 12 09:00:44 AM UTC 24 |
200943974 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2974878211 |
|
|
Oct 12 08:59:51 AM UTC 24 |
Oct 12 09:00:45 AM UTC 24 |
15571538066 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1944771036 |
|
|
Oct 12 09:00:39 AM UTC 24 |
Oct 12 09:00:46 AM UTC 24 |
267881745 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.725344209 |
|
|
Oct 12 09:00:37 AM UTC 24 |
Oct 12 09:00:46 AM UTC 24 |
1850491372 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2168919419 |
|
|
Oct 12 09:00:43 AM UTC 24 |
Oct 12 09:00:47 AM UTC 24 |
38158583 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.722564545 |
|
|
Oct 12 09:00:48 AM UTC 24 |
Oct 12 09:00:51 AM UTC 24 |
157353404 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.4147304534 |
|
|
Oct 12 09:00:39 AM UTC 24 |
Oct 12 09:00:51 AM UTC 24 |
1862474128 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2548659124 |
|
|
Oct 12 09:00:45 AM UTC 24 |
Oct 12 09:00:53 AM UTC 24 |
646361020 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.2250295008 |
|
|
Oct 12 09:00:51 AM UTC 24 |
Oct 12 09:00:54 AM UTC 24 |
23854867 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3092757784 |
|
|
Oct 12 09:00:42 AM UTC 24 |
Oct 12 09:00:54 AM UTC 24 |
1978575615 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3931043339 |
|
|
Oct 12 09:00:53 AM UTC 24 |
Oct 12 09:00:55 AM UTC 24 |
114144168 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3855064302 |
|
|
Oct 12 09:00:55 AM UTC 24 |
Oct 12 09:00:57 AM UTC 24 |
107106663 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.3491493855 |
|
|
Oct 12 09:00:56 AM UTC 24 |
Oct 12 09:00:58 AM UTC 24 |
40189218 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3768019752 |
|
|
Oct 12 08:57:30 AM UTC 24 |
Oct 12 09:00:59 AM UTC 24 |
83550369031 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.193238663 |
|
|
Oct 12 09:00:21 AM UTC 24 |
Oct 12 09:01:00 AM UTC 24 |
70426943549 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3119944840 |
|
|
Oct 12 08:57:27 AM UTC 24 |
Oct 12 09:01:00 AM UTC 24 |
353607523992 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.3391287273 |
|
|
Oct 12 08:52:27 AM UTC 24 |
Oct 12 09:01:01 AM UTC 24 |
55532728377 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.3178606317 |
|
|
Oct 12 09:00:35 AM UTC 24 |
Oct 12 09:01:02 AM UTC 24 |
2633530378 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3793798550 |
|
|
Oct 12 09:01:03 AM UTC 24 |
Oct 12 09:01:07 AM UTC 24 |
79628277 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.3088642870 |
|
|
Oct 12 09:00:59 AM UTC 24 |
Oct 12 09:01:07 AM UTC 24 |
2900122004 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1940188635 |
|
|
Oct 12 09:01:00 AM UTC 24 |
Oct 12 09:01:07 AM UTC 24 |
2569995812 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.1411857478 |
|
|
Oct 12 09:01:00 AM UTC 24 |
Oct 12 09:01:07 AM UTC 24 |
743985557 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3772006374 |
|
|
Oct 12 09:00:58 AM UTC 24 |
Oct 12 09:01:09 AM UTC 24 |
1537948814 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1717724395 |
|
|
Oct 12 09:01:02 AM UTC 24 |
Oct 12 09:01:10 AM UTC 24 |
739017755 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1260756060 |
|
|
Oct 12 09:00:55 AM UTC 24 |
Oct 12 09:01:11 AM UTC 24 |
2789396905 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3169369566 |
|
|
Oct 12 09:00:54 AM UTC 24 |
Oct 12 09:01:11 AM UTC 24 |
1663578563 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3474273464 |
|
|
Oct 12 08:58:56 AM UTC 24 |
Oct 12 09:01:12 AM UTC 24 |
24608171219 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1634977801 |
|
|
Oct 12 09:01:00 AM UTC 24 |
Oct 12 09:01:13 AM UTC 24 |
2623430058 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.280731261 |
|
|
Oct 12 09:01:11 AM UTC 24 |
Oct 12 09:01:14 AM UTC 24 |
602799143 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.794339760 |
|
|
Oct 12 09:01:12 AM UTC 24 |
Oct 12 09:01:14 AM UTC 24 |
12962238 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2809596077 |
|
|
Oct 12 08:59:54 AM UTC 24 |
Oct 12 09:01:17 AM UTC 24 |
17778704395 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1700897495 |
|
|
Oct 12 09:00:30 AM UTC 24 |
Oct 12 09:01:17 AM UTC 24 |
4355384697 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1445267782 |
|
|
Oct 12 08:57:47 AM UTC 24 |
Oct 12 09:01:18 AM UTC 24 |
139488995678 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.4193148204 |
|
|
Oct 12 09:01:08 AM UTC 24 |
Oct 12 09:01:19 AM UTC 24 |
721940479 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3125830484 |
|
|
Oct 12 09:00:15 AM UTC 24 |
Oct 12 09:01:22 AM UTC 24 |
12104567417 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2821321289 |
|
|
Oct 12 08:57:15 AM UTC 24 |
Oct 12 09:01:35 AM UTC 24 |
50055560637 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2509537603 |
|
|
Oct 12 09:00:25 AM UTC 24 |
Oct 12 09:01:38 AM UTC 24 |
12800131649 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.830700312 |
|
|
Oct 12 09:01:08 AM UTC 24 |
Oct 12 09:01:40 AM UTC 24 |
3303893392 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.1300724423 |
|
|
Oct 12 08:50:07 AM UTC 24 |
Oct 12 09:01:44 AM UTC 24 |
140235537776 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3113965485 |
|
|
Oct 12 08:58:35 AM UTC 24 |
Oct 12 09:01:45 AM UTC 24 |
53535210167 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.1429222714 |
|
|
Oct 12 09:00:25 AM UTC 24 |
Oct 12 09:01:49 AM UTC 24 |
18128511050 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3750994996 |
|
|
Oct 12 08:59:12 AM UTC 24 |
Oct 12 09:01:53 AM UTC 24 |
30860511399 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1573260908 |
|
|
Oct 12 08:55:53 AM UTC 24 |
Oct 12 09:01:56 AM UTC 24 |
132116514811 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2560842937 |
|
|
Oct 12 08:58:33 AM UTC 24 |
Oct 12 09:01:59 AM UTC 24 |
16191619668 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.375261566 |
|
|
Oct 12 09:01:10 AM UTC 24 |
Oct 12 09:02:04 AM UTC 24 |
2991008542 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1994855066 |
|
|
Oct 12 08:55:20 AM UTC 24 |
Oct 12 09:02:09 AM UTC 24 |
167656762758 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.958340920 |
|
|
Oct 12 09:00:44 AM UTC 24 |
Oct 12 09:02:11 AM UTC 24 |
39229961107 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3001456297 |
|
|
Oct 12 08:59:55 AM UTC 24 |
Oct 12 09:02:15 AM UTC 24 |
12179993017 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2685384921 |
|
|
Oct 12 08:56:52 AM UTC 24 |
Oct 12 09:02:20 AM UTC 24 |
27198152765 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.4021666905 |
|
|
Oct 12 08:59:27 AM UTC 24 |
Oct 12 09:02:24 AM UTC 24 |
45627330170 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.29514426 |
|
|
Oct 12 09:00:16 AM UTC 24 |
Oct 12 09:02:31 AM UTC 24 |
36728304864 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.1777392722 |
|
|
Oct 12 08:55:21 AM UTC 24 |
Oct 12 09:02:37 AM UTC 24 |
44098741499 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.3984408316 |
|
|
Oct 12 08:43:05 AM UTC 24 |
Oct 12 09:02:57 AM UTC 24 |
764142275333 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4292148891 |
|
|
Oct 12 08:59:30 AM UTC 24 |
Oct 12 09:03:02 AM UTC 24 |
21804839097 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3996846391 |
|
|
Oct 12 08:56:27 AM UTC 24 |
Oct 12 09:03:18 AM UTC 24 |
37037778138 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.490707415 |
|
|
Oct 12 08:58:17 AM UTC 24 |
Oct 12 09:03:46 AM UTC 24 |
123581951895 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1233416292 |
|
|
Oct 12 08:57:31 AM UTC 24 |
Oct 12 09:03:46 AM UTC 24 |
37650233425 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2161210541 |
|
|
Oct 12 09:01:08 AM UTC 24 |
Oct 12 09:03:48 AM UTC 24 |
14480371600 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2469618021 |
|
|
Oct 12 08:58:56 AM UTC 24 |
Oct 12 09:03:53 AM UTC 24 |
55613376027 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.2765617914 |
|
|
Oct 12 08:59:10 AM UTC 24 |
Oct 12 09:03:59 AM UTC 24 |
156844377563 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3521891511 |
|
|
Oct 12 09:00:27 AM UTC 24 |
Oct 12 09:04:03 AM UTC 24 |
52884236969 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.4120849213 |
|
|
Oct 12 08:55:20 AM UTC 24 |
Oct 12 09:04:07 AM UTC 24 |
104048710801 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3056082256 |
|
|
Oct 12 08:57:46 AM UTC 24 |
Oct 12 09:04:19 AM UTC 24 |
45018375757 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2082732660 |
|
|
Oct 12 09:00:46 AM UTC 24 |
Oct 12 09:04:47 AM UTC 24 |
147931721105 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1146369865 |
|
|
Oct 12 08:57:49 AM UTC 24 |
Oct 12 09:05:02 AM UTC 24 |
140779257452 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.1575641534 |
|
|
Oct 12 09:00:47 AM UTC 24 |
Oct 12 09:05:09 AM UTC 24 |
75184180710 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3689279695 |
|
|
Oct 12 09:00:26 AM UTC 24 |
Oct 12 09:05:11 AM UTC 24 |
36929406448 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.249121334 |
|
|
Oct 12 09:00:11 AM UTC 24 |
Oct 12 09:05:38 AM UTC 24 |
94736050104 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3618104706 |
|
|
Oct 12 09:00:47 AM UTC 24 |
Oct 12 09:06:16 AM UTC 24 |
32502932622 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3330232551 |
|
|
Oct 12 09:00:29 AM UTC 24 |
Oct 12 09:06:18 AM UTC 24 |
115417162508 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.4145278550 |
|
|
Oct 12 08:55:40 AM UTC 24 |
Oct 12 09:06:27 AM UTC 24 |
346158429876 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.4106300266 |
|
|
Oct 12 09:01:09 AM UTC 24 |
Oct 12 09:06:30 AM UTC 24 |
25417928873 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3494404227 |
|
|
Oct 12 08:59:12 AM UTC 24 |
Oct 12 09:08:55 AM UTC 24 |
162850693237 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.3070137852 |
|
|
Oct 12 08:58:37 AM UTC 24 |
Oct 12 09:13:10 AM UTC 24 |
87121949169 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2109180805 |
|
|
Oct 12 08:59:38 AM UTC 24 |
Oct 12 09:16:50 AM UTC 24 |
101258304710 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3022494701 |
|
|
Oct 12 09:01:13 AM UTC 24 |
Oct 12 09:01:16 AM UTC 24 |
19124392 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1372708365 |
|
|
Oct 12 09:01:15 AM UTC 24 |
Oct 12 09:01:17 AM UTC 24 |
16268810 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.4066831306 |
|
|
Oct 12 09:01:12 AM UTC 24 |
Oct 12 09:01:18 AM UTC 24 |
155896993 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3461088605 |
|
|
Oct 12 09:01:16 AM UTC 24 |
Oct 12 09:01:19 AM UTC 24 |
55898754 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.214319787 |
|
|
Oct 12 09:01:17 AM UTC 24 |
Oct 12 09:01:19 AM UTC 24 |
59774444 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3380395908 |
|
|
Oct 12 09:01:18 AM UTC 24 |
Oct 12 09:01:21 AM UTC 24 |
129972343 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.706968562 |
|
|
Oct 12 09:01:19 AM UTC 24 |
Oct 12 09:01:23 AM UTC 24 |
139758746 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3212415482 |
|
|
Oct 12 09:01:20 AM UTC 24 |
Oct 12 09:01:23 AM UTC 24 |
18055402 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2742629461 |
|
|
Oct 12 09:01:21 AM UTC 24 |
Oct 12 09:01:24 AM UTC 24 |
11065783 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.409463754 |
|
|
Oct 12 09:01:19 AM UTC 24 |
Oct 12 09:01:24 AM UTC 24 |
669119518 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1000337276 |
|
|
Oct 12 09:01:23 AM UTC 24 |
Oct 12 09:01:26 AM UTC 24 |
25427172 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3844075460 |
|
|
Oct 12 09:01:24 AM UTC 24 |
Oct 12 09:01:26 AM UTC 24 |
48020390 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2030430715 |
|
|
Oct 12 09:01:20 AM UTC 24 |
Oct 12 09:01:27 AM UTC 24 |
56284826 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.453296475 |
|
|
Oct 12 09:01:24 AM UTC 24 |
Oct 12 09:01:28 AM UTC 24 |
76842579 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3843659310 |
|
|
Oct 12 09:01:20 AM UTC 24 |
Oct 12 09:01:29 AM UTC 24 |
634662581 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.954574625 |
|
|
Oct 12 09:01:13 AM UTC 24 |
Oct 12 09:01:31 AM UTC 24 |
572321791 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3391535944 |
|
|
Oct 12 09:01:30 AM UTC 24 |
Oct 12 09:01:33 AM UTC 24 |
25192014 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3003685755 |
|
|
Oct 12 09:01:27 AM UTC 24 |
Oct 12 09:01:33 AM UTC 24 |
582183713 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2350144987 |
|
|
Oct 12 09:01:27 AM UTC 24 |
Oct 12 09:01:33 AM UTC 24 |
582527689 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.4021006285 |
|
|
Oct 12 09:01:31 AM UTC 24 |
Oct 12 09:01:34 AM UTC 24 |
56271518 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.4176883570 |
|
|
Oct 12 09:01:28 AM UTC 24 |
Oct 12 09:01:36 AM UTC 24 |
1899500209 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3089328427 |
|
|
Oct 12 09:01:34 AM UTC 24 |
Oct 12 09:01:37 AM UTC 24 |
231394833 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3143276192 |
|
|
Oct 12 09:01:34 AM UTC 24 |
Oct 12 09:01:37 AM UTC 24 |
42687714 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2523680281 |
|
|
Oct 12 09:01:34 AM UTC 24 |
Oct 12 09:01:37 AM UTC 24 |
86653963 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2436194261 |
|
|
Oct 12 09:01:18 AM UTC 24 |
Oct 12 09:01:39 AM UTC 24 |
214371401 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2746976591 |
|
|
Oct 12 09:01:39 AM UTC 24 |
Oct 12 09:01:42 AM UTC 24 |
46655047 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1621491300 |
|
|
Oct 12 09:01:39 AM UTC 24 |
Oct 12 09:01:42 AM UTC 24 |
13011155 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1602042893 |
|
|
Oct 12 09:01:37 AM UTC 24 |
Oct 12 09:01:42 AM UTC 24 |
100602731 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1116952973 |
|
|
Oct 12 09:01:37 AM UTC 24 |
Oct 12 09:01:43 AM UTC 24 |
101437531 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.4207755693 |
|
|
Oct 12 09:01:41 AM UTC 24 |
Oct 12 09:01:44 AM UTC 24 |
81345494 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.3477312337 |
|
|
Oct 12 09:01:37 AM UTC 24 |
Oct 12 09:01:44 AM UTC 24 |
380476941 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1880040840 |
|
|
Oct 12 09:01:43 AM UTC 24 |
Oct 12 09:01:46 AM UTC 24 |
34266829 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.41652434 |
|
|
Oct 12 09:01:43 AM UTC 24 |
Oct 12 09:01:46 AM UTC 24 |
42094953 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2846508693 |
|
|
Oct 12 09:01:25 AM UTC 24 |
Oct 12 09:01:47 AM UTC 24 |
1226077325 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2159347025 |
|
|
Oct 12 09:01:46 AM UTC 24 |
Oct 12 09:01:49 AM UTC 24 |
19948596 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1442982932 |
|
|
Oct 12 09:01:46 AM UTC 24 |
Oct 12 09:01:49 AM UTC 24 |
11714035 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.861100137 |
|
|
Oct 12 09:01:45 AM UTC 24 |
Oct 12 09:01:49 AM UTC 24 |
190077104 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1980773243 |
|
|
Oct 12 09:01:29 AM UTC 24 |
Oct 12 09:01:49 AM UTC 24 |
1144101870 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3816222803 |
|
|
Oct 12 09:01:45 AM UTC 24 |
Oct 12 09:01:51 AM UTC 24 |
273951553 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.2178054009 |
|
|
Oct 12 09:01:36 AM UTC 24 |
Oct 12 09:01:51 AM UTC 24 |
1569736019 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1618044306 |
|
|
Oct 12 09:01:38 AM UTC 24 |
Oct 12 09:01:52 AM UTC 24 |
377743358 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1898238968 |
|
|
Oct 12 09:01:49 AM UTC 24 |
Oct 12 09:01:52 AM UTC 24 |
165576253 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2813932259 |
|
|
Oct 12 09:01:50 AM UTC 24 |
Oct 12 09:01:52 AM UTC 24 |
36150179 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1622328327 |
|
|
Oct 12 09:01:50 AM UTC 24 |
Oct 12 09:01:53 AM UTC 24 |
123827399 ps |