| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.74 | 98.65 | 96.80 | 99.01 | 89.36 | 98.51 | 95.57 | 99.26 |
| T115 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.602445181 | Oct 12 09:01:45 AM UTC 24 | Oct 12 09:01:53 AM UTC 24 | 1280001632 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3835503274 | Oct 12 09:01:46 AM UTC 24 | Oct 12 09:01:54 AM UTC 24 | 2106833211 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4264080680 | Oct 12 09:01:50 AM UTC 24 | Oct 12 09:01:55 AM UTC 24 | 677999876 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.2734911758 | Oct 12 09:01:53 AM UTC 24 | Oct 12 09:01:55 AM UTC 24 | 43440966 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3411072705 | Oct 12 09:01:52 AM UTC 24 | Oct 12 09:01:56 AM UTC 24 | 185146933 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1558814633 | Oct 12 09:01:18 AM UTC 24 | Oct 12 09:02:03 AM UTC 24 | 5876408672 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4222595862 | Oct 12 09:01:43 AM UTC 24 | Oct 12 09:01:57 AM UTC 24 | 5048789334 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.487254284 | Oct 12 09:01:54 AM UTC 24 | Oct 12 09:01:57 AM UTC 24 | 83019433 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2314888308 | Oct 12 09:01:53 AM UTC 24 | Oct 12 09:01:57 AM UTC 24 | 216460384 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.2202308280 | Oct 12 09:01:52 AM UTC 24 | Oct 12 09:01:58 AM UTC 24 | 913425493 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1159936758 | Oct 12 09:01:56 AM UTC 24 | Oct 12 09:01:58 AM UTC 24 | 29174896 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.127539389 | Oct 12 09:01:55 AM UTC 24 | Oct 12 09:01:58 AM UTC 24 | 105809813 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1288458199 | Oct 12 09:01:53 AM UTC 24 | Oct 12 09:01:58 AM UTC 24 | 48841564 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1911703079 | Oct 12 09:01:35 AM UTC 24 | Oct 12 09:01:58 AM UTC 24 | 1460080141 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2598655243 | Oct 12 09:01:56 AM UTC 24 | Oct 12 09:01:59 AM UTC 24 | 79955129 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3681468439 | Oct 12 09:01:25 AM UTC 24 | Oct 12 09:02:00 AM UTC 24 | 1222132569 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2080464762 | Oct 12 09:01:57 AM UTC 24 | Oct 12 09:02:01 AM UTC 24 | 44603746 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1987177535 | Oct 12 09:01:58 AM UTC 24 | Oct 12 09:02:01 AM UTC 24 | 38305077 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.906165606 | Oct 12 09:01:57 AM UTC 24 | Oct 12 09:02:01 AM UTC 24 | 28152442 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.2573941020 | Oct 12 09:01:44 AM UTC 24 | Oct 12 09:02:01 AM UTC 24 | 735261577 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3006419800 | Oct 12 09:01:58 AM UTC 24 | Oct 12 09:02:01 AM UTC 24 | 61468445 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1156545035 | Oct 12 09:01:59 AM UTC 24 | Oct 12 09:02:02 AM UTC 24 | 471049514 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2343627660 | Oct 12 09:02:00 AM UTC 24 | Oct 12 09:02:02 AM UTC 24 | 113583640 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1960717028 | Oct 12 09:02:00 AM UTC 24 | Oct 12 09:02:03 AM UTC 24 | 110641131 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2143226445 | Oct 12 09:02:00 AM UTC 24 | Oct 12 09:02:04 AM UTC 24 | 164727620 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1072078664 | Oct 12 09:01:58 AM UTC 24 | Oct 12 09:02:04 AM UTC 24 | 736739286 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.2858432708 | Oct 12 09:01:56 AM UTC 24 | Oct 12 09:02:08 AM UTC 24 | 355722654 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3793683810 | Oct 12 09:02:02 AM UTC 24 | Oct 12 09:02:05 AM UTC 24 | 31366035 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.1372541285 | Oct 12 09:02:00 AM UTC 24 | Oct 12 09:02:05 AM UTC 24 | 1054991615 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3785337920 | Oct 12 09:02:02 AM UTC 24 | Oct 12 09:02:05 AM UTC 24 | 54743883 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1541051182 | Oct 12 09:02:01 AM UTC 24 | Oct 12 09:02:06 AM UTC 24 | 251073900 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3908805610 | Oct 12 09:02:02 AM UTC 24 | Oct 12 09:02:06 AM UTC 24 | 156134162 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2063950756 | Oct 12 09:02:05 AM UTC 24 | Oct 12 09:02:07 AM UTC 24 | 191046035 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3181342427 | Oct 12 09:02:04 AM UTC 24 | Oct 12 09:02:08 AM UTC 24 | 72103399 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2472032462 | Oct 12 09:02:04 AM UTC 24 | Oct 12 09:02:07 AM UTC 24 | 47113982 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2376236800 | Oct 12 09:02:05 AM UTC 24 | Oct 12 09:02:08 AM UTC 24 | 70487882 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1840252711 | Oct 12 09:02:02 AM UTC 24 | Oct 12 09:02:09 AM UTC 24 | 319507753 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1688394631 | Oct 12 09:02:05 AM UTC 24 | Oct 12 09:02:09 AM UTC 24 | 91150502 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3730928649 | Oct 12 09:02:07 AM UTC 24 | Oct 12 09:02:09 AM UTC 24 | 11699305 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.661367373 | Oct 12 09:02:04 AM UTC 24 | Oct 12 09:02:10 AM UTC 24 | 185705735 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.332610584 | Oct 12 09:02:07 AM UTC 24 | Oct 12 09:02:11 AM UTC 24 | 48831169 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2163914412 | Oct 12 09:01:53 AM UTC 24 | Oct 12 09:02:11 AM UTC 24 | 536577425 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.113874499 | Oct 12 09:02:08 AM UTC 24 | Oct 12 09:02:11 AM UTC 24 | 28660311 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.929822618 | Oct 12 09:02:02 AM UTC 24 | Oct 12 09:02:29 AM UTC 24 | 3407861049 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.941253256 | Oct 12 09:02:08 AM UTC 24 | Oct 12 09:02:12 AM UTC 24 | 599723309 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2888541537 | Oct 12 09:02:10 AM UTC 24 | Oct 12 09:02:12 AM UTC 24 | 27533600 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2681117840 | Oct 12 09:02:07 AM UTC 24 | Oct 12 09:02:12 AM UTC 24 | 206187796 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2987795115 | Oct 12 09:02:05 AM UTC 24 | Oct 12 09:02:13 AM UTC 24 | 161547458 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.273924211 | Oct 12 09:02:04 AM UTC 24 | Oct 12 09:02:13 AM UTC 24 | 272337798 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3239045039 | Oct 12 09:02:12 AM UTC 24 | Oct 12 09:02:14 AM UTC 24 | 36726512 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2314383149 | Oct 12 09:02:10 AM UTC 24 | Oct 12 09:02:14 AM UTC 24 | 54801500 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.51434220 | Oct 12 09:02:10 AM UTC 24 | Oct 12 09:02:14 AM UTC 24 | 209342025 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4233173117 | Oct 12 09:02:10 AM UTC 24 | Oct 12 09:02:14 AM UTC 24 | 94831840 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.865728551 | Oct 12 09:01:50 AM UTC 24 | Oct 12 09:02:14 AM UTC 24 | 6778434917 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2601736187 | Oct 12 09:02:10 AM UTC 24 | Oct 12 09:02:15 AM UTC 24 | 575303585 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1307314906 | Oct 12 09:02:12 AM UTC 24 | Oct 12 09:02:15 AM UTC 24 | 53588354 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3216936080 | Oct 12 09:02:12 AM UTC 24 | Oct 12 09:02:15 AM UTC 24 | 272936940 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4126889439 | Oct 12 09:02:10 AM UTC 24 | Oct 12 09:02:15 AM UTC 24 | 146711523 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3424338440 | Oct 12 09:02:13 AM UTC 24 | Oct 12 09:02:15 AM UTC 24 | 23018924 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.321025508 | Oct 12 09:02:12 AM UTC 24 | Oct 12 09:02:15 AM UTC 24 | 52056575 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2718203579 | Oct 12 09:01:58 AM UTC 24 | Oct 12 09:02:17 AM UTC 24 | 806141749 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1758028951 | Oct 12 09:02:13 AM UTC 24 | Oct 12 09:02:17 AM UTC 24 | 109858897 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2485342241 | Oct 12 09:02:15 AM UTC 24 | Oct 12 09:02:17 AM UTC 24 | 14930724 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2739238274 | Oct 12 09:02:15 AM UTC 24 | Oct 12 09:02:18 AM UTC 24 | 18678075 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.4056745457 | Oct 12 09:02:15 AM UTC 24 | Oct 12 09:02:18 AM UTC 24 | 56784400 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3348669579 | Oct 12 09:02:13 AM UTC 24 | Oct 12 09:02:18 AM UTC 24 | 57833176 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3578132880 | Oct 12 09:02:15 AM UTC 24 | Oct 12 09:02:19 AM UTC 24 | 159078590 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2383330920 | Oct 12 09:02:17 AM UTC 24 | Oct 12 09:02:19 AM UTC 24 | 26214844 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2304895633 | Oct 12 09:02:17 AM UTC 24 | Oct 12 09:02:20 AM UTC 24 | 452043822 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2753469568 | Oct 12 09:02:16 AM UTC 24 | Oct 12 09:02:20 AM UTC 24 | 148646919 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3056313486 | Oct 12 09:02:13 AM UTC 24 | Oct 12 09:02:30 AM UTC 24 | 2231644127 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1757271119 | Oct 12 09:02:17 AM UTC 24 | Oct 12 09:02:20 AM UTC 24 | 52283840 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.673567471 | Oct 12 09:02:07 AM UTC 24 | Oct 12 09:02:20 AM UTC 24 | 876070311 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.467241018 | Oct 12 09:02:18 AM UTC 24 | Oct 12 09:02:20 AM UTC 24 | 36127539 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3872455046 | Oct 12 09:02:17 AM UTC 24 | Oct 12 09:02:20 AM UTC 24 | 94780903 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2783065234 | Oct 12 09:02:15 AM UTC 24 | Oct 12 09:02:21 AM UTC 24 | 100858221 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3904520838 | Oct 12 09:02:17 AM UTC 24 | Oct 12 09:02:21 AM UTC 24 | 70289036 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2879485422 | Oct 12 09:02:00 AM UTC 24 | Oct 12 09:02:21 AM UTC 24 | 6991671414 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.828087492 | Oct 12 09:01:50 AM UTC 24 | Oct 12 09:02:21 AM UTC 24 | 537919753 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.295939848 | Oct 12 09:02:18 AM UTC 24 | Oct 12 09:02:22 AM UTC 24 | 65976190 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3776165093 | Oct 12 09:02:17 AM UTC 24 | Oct 12 09:02:22 AM UTC 24 | 101776250 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1258636062 | Oct 12 09:02:18 AM UTC 24 | Oct 12 09:02:24 AM UTC 24 | 1280116780 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2466898186 | Oct 12 09:02:27 AM UTC 24 | Oct 12 09:02:29 AM UTC 24 | 50930766 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.4040699273 | Oct 12 09:02:27 AM UTC 24 | Oct 12 09:02:29 AM UTC 24 | 36641332 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2838017309 | Oct 12 09:02:27 AM UTC 24 | Oct 12 09:02:29 AM UTC 24 | 32653864 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2014881632 | Oct 12 09:02:12 AM UTC 24 | Oct 12 09:02:30 AM UTC 24 | 1231779908 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1525962189 | Oct 12 09:02:20 AM UTC 24 | Oct 12 09:02:24 AM UTC 24 | 1403433422 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1591976646 | Oct 12 09:02:22 AM UTC 24 | Oct 12 09:02:24 AM UTC 24 | 46244731 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1814848358 | Oct 12 09:02:22 AM UTC 24 | Oct 12 09:02:24 AM UTC 24 | 52509168 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2563657635 | Oct 12 09:02:22 AM UTC 24 | Oct 12 09:02:24 AM UTC 24 | 21257490 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.68270933 | Oct 12 09:02:20 AM UTC 24 | Oct 12 09:02:25 AM UTC 24 | 192918863 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.931100263 | Oct 12 09:02:23 AM UTC 24 | Oct 12 09:02:25 AM UTC 24 | 55728148 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1134376156 | Oct 12 09:02:22 AM UTC 24 | Oct 12 09:02:26 AM UTC 24 | 394553662 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1072907071 | Oct 12 09:02:24 AM UTC 24 | Oct 12 09:02:26 AM UTC 24 | 16015815 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2696284878 | Oct 12 09:02:24 AM UTC 24 | Oct 12 09:02:26 AM UTC 24 | 154395285 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3074719030 | Oct 12 09:02:20 AM UTC 24 | Oct 12 09:02:26 AM UTC 24 | 1132854074 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2500959461 | Oct 12 09:02:22 AM UTC 24 | Oct 12 09:02:27 AM UTC 24 | 681288133 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.103863162 | Oct 12 09:02:22 AM UTC 24 | Oct 12 09:02:27 AM UTC 24 | 221369665 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1456211881 | Oct 12 09:02:25 AM UTC 24 | Oct 12 09:02:27 AM UTC 24 | 16512513 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.864859462 | Oct 12 09:02:25 AM UTC 24 | Oct 12 09:02:27 AM UTC 24 | 33855610 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4202489059 | Oct 12 09:02:25 AM UTC 24 | Oct 12 09:02:27 AM UTC 24 | 25908539 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3491942717 | Oct 12 09:02:25 AM UTC 24 | Oct 12 09:02:27 AM UTC 24 | 28392267 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.188178523 | Oct 12 09:02:25 AM UTC 24 | Oct 12 09:02:28 AM UTC 24 | 13097477 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2705041587 | Oct 12 09:02:26 AM UTC 24 | Oct 12 09:02:28 AM UTC 24 | 16339002 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1986388293 | Oct 12 09:02:23 AM UTC 24 | Oct 12 09:02:28 AM UTC 24 | 595500237 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.254488540 | Oct 12 09:02:23 AM UTC 24 | Oct 12 09:02:28 AM UTC 24 | 206654772 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3840312590 | Oct 12 09:02:22 AM UTC 24 | Oct 12 09:02:29 AM UTC 24 | 193003151 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.668423681 | Oct 12 09:02:27 AM UTC 24 | Oct 12 09:02:29 AM UTC 24 | 12103867 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1077021388 | Oct 12 09:02:27 AM UTC 24 | Oct 12 09:02:29 AM UTC 24 | 13547770 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2184421440 | Oct 12 09:02:27 AM UTC 24 | Oct 12 09:02:29 AM UTC 24 | 64296873 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2629315585 | Oct 12 09:02:20 AM UTC 24 | Oct 12 09:02:30 AM UTC 24 | 107499850 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.515769104 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 17583151 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1976293726 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 41919065 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3191981194 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 14686214 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1708958965 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 26806626 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2159964061 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 22748078 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3836107002 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 71049120 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3477655917 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 19392811 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1963433347 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 13111762 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2036972769 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 93538963 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1187660520 | Oct 12 09:02:29 AM UTC 24 | Oct 12 09:02:31 AM UTC 24 | 28925721 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3369240864 | Oct 12 09:02:17 AM UTC 24 | Oct 12 09:02:32 AM UTC 24 | 237162084 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2891845876 | Oct 12 09:02:31 AM UTC 24 | Oct 12 09:02:33 AM UTC 24 | 12245713 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.671359363 | Oct 12 09:02:31 AM UTC 24 | Oct 12 09:02:33 AM UTC 24 | 53872908 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2227632680 | Oct 12 09:02:31 AM UTC 24 | Oct 12 09:02:33 AM UTC 24 | 12710905 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3916012630 | Oct 12 09:02:31 AM UTC 24 | Oct 12 09:02:33 AM UTC 24 | 44346828 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1465415852 | Oct 12 09:02:10 AM UTC 24 | Oct 12 09:02:33 AM UTC 24 | 3469108279 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1172600957 | Oct 12 09:02:31 AM UTC 24 | Oct 12 09:02:33 AM UTC 24 | 43306489 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.517288398 | Oct 12 09:02:18 AM UTC 24 | Oct 12 09:02:33 AM UTC 24 | 2256311107 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1793876510 | Oct 12 09:02:15 AM UTC 24 | Oct 12 09:02:37 AM UTC 24 | 825583496 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.757049392 | Oct 12 09:02:22 AM UTC 24 | Oct 12 09:02:40 AM UTC 24 | 2978010054 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2424048480 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 140381481 ps |
| CPU time | 4.68 seconds |
| Started | Oct 12 08:38:26 AM UTC 24 |
| Finished | Oct 12 08:38:32 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424048480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2424048480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2469420963 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 23037667439 ps |
| CPU time | 111.35 seconds |
| Started | Oct 12 08:38:57 AM UTC 24 |
| Finished | Oct 12 08:40:51 AM UTC 24 |
| Peak memory | 245944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469420963 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.2469420963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1555504181 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 27715614748 ps |
| CPU time | 181.01 seconds |
| Started | Oct 12 08:38:55 AM UTC 24 |
| Finished | Oct 12 08:41:59 AM UTC 24 |
| Peak memory | 252300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555504181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1555504181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.908834159 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3330467781 ps |
| CPU time | 24.01 seconds |
| Started | Oct 12 08:38:21 AM UTC 24 |
| Finished | Oct 12 08:38:46 AM UTC 24 |
| Peak memory | 232488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908834159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.908834159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.957494655 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 25223338676 ps |
| CPU time | 119.11 seconds |
| Started | Oct 12 08:38:46 AM UTC 24 |
| Finished | Oct 12 08:40:47 AM UTC 24 |
| Peak memory | 282768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957494655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.957494655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3003685755 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 582183713 ps |
| CPU time | 4.41 seconds |
| Started | Oct 12 09:01:27 AM UTC 24 |
| Finished | Oct 12 09:01:33 AM UTC 24 |
| Peak memory | 226604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3003685755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.spi_device_csr_mem_rw_with_rand_reset.3003685755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.4207525507 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 16832114554 ps |
| CPU time | 113.07 seconds |
| Started | Oct 12 08:43:51 AM UTC 24 |
| Finished | Oct 12 08:45:46 AM UTC 24 |
| Peak memory | 268436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207525507 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.4207525507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2630706598 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 162655865 ps |
| CPU time | 6.61 seconds |
| Started | Oct 12 08:38:47 AM UTC 24 |
| Finished | Oct 12 08:38:55 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630706598 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.2630706598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1720410840 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 28680947412 ps |
| CPU time | 329.83 seconds |
| Started | Oct 12 08:42:22 AM UTC 24 |
| Finished | Oct 12 08:47:57 AM UTC 24 |
| Peak memory | 268460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720410840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.1720410840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.852811863 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 15885737 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 08:38:18 AM UTC 24 |
| Finished | Oct 12 08:38:20 AM UTC 24 |
| Peak memory | 226200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852811863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.852811863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.825159560 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 46037862931 ps |
| CPU time | 196.9 seconds |
| Started | Oct 12 08:38:55 AM UTC 24 |
| Finished | Oct 12 08:42:15 AM UTC 24 |
| Peak memory | 268472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825159560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.825159560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2494290214 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 27970246261 ps |
| CPU time | 359.78 seconds |
| Started | Oct 12 08:41:43 AM UTC 24 |
| Finished | Oct 12 08:47:48 AM UTC 24 |
| Peak memory | 278772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494290214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2494290214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.3494545212 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 100408160510 ps |
| CPU time | 553.11 seconds |
| Started | Oct 12 08:44:53 AM UTC 24 |
| Finished | Oct 12 08:54:13 AM UTC 24 |
| Peak memory | 274836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494545212 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.3494545212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3674994973 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 43075635 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 08:38:58 AM UTC 24 |
| Finished | Oct 12 08:39:01 AM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674994973 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3674994973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.2503419417 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 10877959789 ps |
| CPU time | 257.82 seconds |
| Started | Oct 12 08:47:53 AM UTC 24 |
| Finished | Oct 12 08:52:15 AM UTC 24 |
| Peak memory | 278676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503419417 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.2503419417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.3542357044 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 78594037113 ps |
| CPU time | 423.16 seconds |
| Started | Oct 12 08:41:02 AM UTC 24 |
| Finished | Oct 12 08:48:11 AM UTC 24 |
| Peak memory | 268444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542357044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.3542357044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.475330965 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 47264025574 ps |
| CPU time | 533.68 seconds |
| Started | Oct 12 08:41:01 AM UTC 24 |
| Finished | Oct 12 08:50:01 AM UTC 24 |
| Peak memory | 282912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475330965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.475330965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3550475851 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 176147975091 ps |
| CPU time | 232.88 seconds |
| Started | Oct 12 08:41:41 AM UTC 24 |
| Finished | Oct 12 08:45:37 AM UTC 24 |
| Peak memory | 268400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550475851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.3550475851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.954574625 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 572321791 ps |
| CPU time | 16.37 seconds |
| Started | Oct 12 09:01:13 AM UTC 24 |
| Finished | Oct 12 09:01:31 AM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954574625 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.954574625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2024548996 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5609143008 ps |
| CPU time | 64.25 seconds |
| Started | Oct 12 08:50:31 AM UTC 24 |
| Finished | Oct 12 08:51:37 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024548996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2024548996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2143226445 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 164727620 ps |
| CPU time | 3.15 seconds |
| Started | Oct 12 09:02:00 AM UTC 24 |
| Finished | Oct 12 09:02:04 AM UTC 24 |
| Peak memory | 225016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143226445 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2143226445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3143276192 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 42687714 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 09:01:34 AM UTC 24 |
| Finished | Oct 12 09:01:37 AM UTC 24 |
| Peak memory | 213116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143276192 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.3143276192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.4175566715 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 17621145066 ps |
| CPU time | 87.7 seconds |
| Started | Oct 12 08:52:18 AM UTC 24 |
| Finished | Oct 12 08:53:48 AM UTC 24 |
| Peak memory | 276592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175566715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4175566715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1232878025 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 23225219445 ps |
| CPU time | 156.9 seconds |
| Started | Oct 12 08:49:02 AM UTC 24 |
| Finished | Oct 12 08:51:42 AM UTC 24 |
| Peak memory | 295092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232878025 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.1232878025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.2739884739 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10391323775 ps |
| CPU time | 37.06 seconds |
| Started | Oct 12 08:40:20 AM UTC 24 |
| Finished | Oct 12 08:40:59 AM UTC 24 |
| Peak memory | 232556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739884739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2739884739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1039155406 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 65267612021 ps |
| CPU time | 356.63 seconds |
| Started | Oct 12 08:51:17 AM UTC 24 |
| Finished | Oct 12 08:57:19 AM UTC 24 |
| Peak memory | 297140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039155406 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.1039155406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.77707460 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 496139717 ps |
| CPU time | 3.8 seconds |
| Started | Oct 12 08:38:32 AM UTC 24 |
| Finished | Oct 12 08:38:37 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77707460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.77707460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.3205965870 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 652933334602 ps |
| CPU time | 560.25 seconds |
| Started | Oct 12 08:41:05 AM UTC 24 |
| Finished | Oct 12 08:50:33 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205965870 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.3205965870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3068280050 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 37366813586 ps |
| CPU time | 410.05 seconds |
| Started | Oct 12 08:51:41 AM UTC 24 |
| Finished | Oct 12 08:58:36 AM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068280050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.3068280050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.2040464715 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 16103580557 ps |
| CPU time | 178.01 seconds |
| Started | Oct 12 08:54:25 AM UTC 24 |
| Finished | Oct 12 08:57:26 AM UTC 24 |
| Peak memory | 262448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040464715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2040464715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.3698775696 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13816172 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:39:02 AM UTC 24 |
| Finished | Oct 12 08:39:04 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698775696 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3698775696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.217555999 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3305535154 ps |
| CPU time | 37.83 seconds |
| Started | Oct 12 08:39:45 AM UTC 24 |
| Finished | Oct 12 08:40:24 AM UTC 24 |
| Peak memory | 235628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217555999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.217555999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3957185908 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 31979389586 ps |
| CPU time | 238.76 seconds |
| Started | Oct 12 08:47:10 AM UTC 24 |
| Finished | Oct 12 08:51:12 AM UTC 24 |
| Peak memory | 266420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957185908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3957185908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.796680145 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 6022341428 ps |
| CPU time | 46.63 seconds |
| Started | Oct 12 08:42:14 AM UTC 24 |
| Finished | Oct 12 08:43:02 AM UTC 24 |
| Peak memory | 266356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796680145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.796680145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.3477312337 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 380476941 ps |
| CPU time | 6.17 seconds |
| Started | Oct 12 09:01:37 AM UTC 24 |
| Finished | Oct 12 09:01:44 AM UTC 24 |
| Peak memory | 224756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477312337 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3477312337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.4145278550 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 346158429876 ps |
| CPU time | 639.34 seconds |
| Started | Oct 12 08:55:40 AM UTC 24 |
| Finished | Oct 12 09:06:27 AM UTC 24 |
| Peak memory | 295264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145278550 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.4145278550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.2362058437 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4222301432 ps |
| CPU time | 121.67 seconds |
| Started | Oct 12 08:56:52 AM UTC 24 |
| Finished | Oct 12 08:58:56 AM UTC 24 |
| Peak memory | 266412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362058437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.2362058437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3489238573 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4827654204 ps |
| CPU time | 65.36 seconds |
| Started | Oct 12 08:43:03 AM UTC 24 |
| Finished | Oct 12 08:44:10 AM UTC 24 |
| Peak memory | 268656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489238573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3489238573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.717684105 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2967961344 ps |
| CPU time | 45.71 seconds |
| Started | Oct 12 08:46:50 AM UTC 24 |
| Finished | Oct 12 08:47:37 AM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717684105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.717684105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.4193287346 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 188703099 ps |
| CPU time | 9.69 seconds |
| Started | Oct 12 08:55:34 AM UTC 24 |
| Finished | Oct 12 08:55:45 AM UTC 24 |
| Peak memory | 235480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193287346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4193287346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.1146369865 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 140779257452 ps |
| CPU time | 426.53 seconds |
| Started | Oct 12 08:57:49 AM UTC 24 |
| Finished | Oct 12 09:05:02 AM UTC 24 |
| Peak memory | 278712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146369865 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.1146369865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2351399245 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 12452892313 ps |
| CPU time | 103.6 seconds |
| Started | Oct 12 08:48:57 AM UTC 24 |
| Finished | Oct 12 08:50:42 AM UTC 24 |
| Peak memory | 268408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351399245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.2351399245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2014881632 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1231779908 ps |
| CPU time | 17.01 seconds |
| Started | Oct 12 09:02:12 AM UTC 24 |
| Finished | Oct 12 09:02:30 AM UTC 24 |
| Peak memory | 224744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014881632 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.2014881632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.517288398 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2256311107 ps |
| CPU time | 13.46 seconds |
| Started | Oct 12 09:02:18 AM UTC 24 |
| Finished | Oct 12 09:02:33 AM UTC 24 |
| Peak memory | 224832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517288398 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.517288398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.31519605 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 21300590600 ps |
| CPU time | 60.96 seconds |
| Started | Oct 12 08:59:29 AM UTC 24 |
| Finished | Oct 12 09:00:32 AM UTC 24 |
| Peak memory | 264600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31519605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.31519605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3139448399 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1851322354 ps |
| CPU time | 8.84 seconds |
| Started | Oct 12 08:39:18 AM UTC 24 |
| Finished | Oct 12 08:39:28 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139448399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3139448399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3640423044 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 20700025311 ps |
| CPU time | 67.04 seconds |
| Started | Oct 12 08:45:40 AM UTC 24 |
| Finished | Oct 12 08:46:49 AM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640423044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3640423044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1257751659 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 179997608213 ps |
| CPU time | 363.89 seconds |
| Started | Oct 12 08:46:25 AM UTC 24 |
| Finished | Oct 12 08:52:34 AM UTC 24 |
| Peak memory | 268428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257751659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1257751659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3507433086 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 239565865040 ps |
| CPU time | 195.81 seconds |
| Started | Oct 12 08:46:26 AM UTC 24 |
| Finished | Oct 12 08:49:46 AM UTC 24 |
| Peak memory | 262348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507433086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3507433086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.929455296 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 924606557 ps |
| CPU time | 12.96 seconds |
| Started | Oct 12 08:46:23 AM UTC 24 |
| Finished | Oct 12 08:46:37 AM UTC 24 |
| Peak memory | 235540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929455296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.929455296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.3780684542 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 63249174393 ps |
| CPU time | 422.23 seconds |
| Started | Oct 12 08:50:29 AM UTC 24 |
| Finished | Oct 12 08:57:37 AM UTC 24 |
| Peak memory | 276560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780684542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3780684542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.2165944996 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 10114840473 ps |
| CPU time | 24.03 seconds |
| Started | Oct 12 08:53:54 AM UTC 24 |
| Finished | Oct 12 08:54:19 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165944996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2165944996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3996846391 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 37037778138 ps |
| CPU time | 404.95 seconds |
| Started | Oct 12 08:56:27 AM UTC 24 |
| Finished | Oct 12 09:03:18 AM UTC 24 |
| Peak memory | 280932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996846391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3996846391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2441269994 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1051526033 ps |
| CPU time | 5.39 seconds |
| Started | Oct 12 08:46:37 AM UTC 24 |
| Finished | Oct 12 08:46:44 AM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441269994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2441269994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1258636062 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 1280116780 ps |
| CPU time | 4.38 seconds |
| Started | Oct 12 09:02:18 AM UTC 24 |
| Finished | Oct 12 09:02:24 AM UTC 24 |
| Peak memory | 226724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258636062 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.1258636062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.726700694 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 69166264 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 08:38:15 AM UTC 24 |
| Finished | Oct 12 08:38:17 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726700694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.726700694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2436194261 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 214371401 ps |
| CPU time | 19.59 seconds |
| Started | Oct 12 09:01:18 AM UTC 24 |
| Finished | Oct 12 09:01:39 AM UTC 24 |
| Peak memory | 214412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436194261 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.2436194261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1558814633 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5876408672 ps |
| CPU time | 43.52 seconds |
| Started | Oct 12 09:01:18 AM UTC 24 |
| Finished | Oct 12 09:02:03 AM UTC 24 |
| Peak memory | 225048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558814633 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.1558814633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.214319787 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 59774444 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 09:01:17 AM UTC 24 |
| Finished | Oct 12 09:01:19 AM UTC 24 |
| Peak memory | 213404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214319787 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.214319787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.409463754 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 669119518 ps |
| CPU time | 3.61 seconds |
| Started | Oct 12 09:01:19 AM UTC 24 |
| Finished | Oct 12 09:01:24 AM UTC 24 |
| Peak memory | 226740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=409463754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.spi_device_csr_mem_rw_with_rand_reset.409463754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3380395908 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 129972343 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 09:01:18 AM UTC 24 |
| Finished | Oct 12 09:01:21 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380395908 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3380395908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3022494701 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 19124392 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 09:01:13 AM UTC 24 |
| Finished | Oct 12 09:01:16 AM UTC 24 |
| Peak memory | 212312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022494701 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3022494701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3461088605 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 55898754 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 09:01:16 AM UTC 24 |
| Finished | Oct 12 09:01:19 AM UTC 24 |
| Peak memory | 225004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461088605 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.3461088605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1372708365 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 16268810 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 09:01:15 AM UTC 24 |
| Finished | Oct 12 09:01:17 AM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372708365 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.1372708365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.706968562 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 139758746 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 09:01:19 AM UTC 24 |
| Finished | Oct 12 09:01:23 AM UTC 24 |
| Peak memory | 224656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706968562 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.706968562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.4066831306 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 155896993 ps |
| CPU time | 5.22 seconds |
| Started | Oct 12 09:01:12 AM UTC 24 |
| Finished | Oct 12 09:01:18 AM UTC 24 |
| Peak memory | 224888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066831306 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4066831306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2846508693 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1226077325 ps |
| CPU time | 21.16 seconds |
| Started | Oct 12 09:01:25 AM UTC 24 |
| Finished | Oct 12 09:01:47 AM UTC 24 |
| Peak memory | 224652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846508693 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.2846508693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3681468439 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 1222132569 ps |
| CPU time | 33.56 seconds |
| Started | Oct 12 09:01:25 AM UTC 24 |
| Finished | Oct 12 09:02:00 AM UTC 24 |
| Peak memory | 214352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681468439 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.3681468439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3844075460 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 48020390 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 09:01:24 AM UTC 24 |
| Finished | Oct 12 09:01:26 AM UTC 24 |
| Peak memory | 213116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844075460 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.3844075460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.453296475 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 76842579 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 09:01:24 AM UTC 24 |
| Finished | Oct 12 09:01:28 AM UTC 24 |
| Peak memory | 214484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453296475 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.453296475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3212415482 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 18055402 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 09:01:20 AM UTC 24 |
| Finished | Oct 12 09:01:23 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212415482 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3212415482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1000337276 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 25427172 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 09:01:23 AM UTC 24 |
| Finished | Oct 12 09:01:26 AM UTC 24 |
| Peak memory | 224900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000337276 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.1000337276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2742629461 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 11065783 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 09:01:21 AM UTC 24 |
| Finished | Oct 12 09:01:24 AM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742629461 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.2742629461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2350144987 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 582527689 ps |
| CPU time | 4.84 seconds |
| Started | Oct 12 09:01:27 AM UTC 24 |
| Finished | Oct 12 09:01:33 AM UTC 24 |
| Peak memory | 224668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350144987 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand ing.2350144987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2030430715 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 56284826 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 09:01:20 AM UTC 24 |
| Finished | Oct 12 09:01:27 AM UTC 24 |
| Peak memory | 224656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030430715 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2030430715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3843659310 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 634662581 ps |
| CPU time | 7.5 seconds |
| Started | Oct 12 09:01:20 AM UTC 24 |
| Finished | Oct 12 09:01:29 AM UTC 24 |
| Peak memory | 224904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843659310 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.3843659310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1688394631 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 91150502 ps |
| CPU time | 2.5 seconds |
| Started | Oct 12 09:02:05 AM UTC 24 |
| Finished | Oct 12 09:02:09 AM UTC 24 |
| Peak memory | 224976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1688394631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.spi_device_csr_mem_rw_with_rand_reset.1688394631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2376236800 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 70487882 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 09:02:05 AM UTC 24 |
| Finished | Oct 12 09:02:08 AM UTC 24 |
| Peak memory | 223296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376236800 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.2376236800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2063950756 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 191046035 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 09:02:05 AM UTC 24 |
| Finished | Oct 12 09:02:07 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063950756 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.2063950756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2987795115 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 161547458 ps |
| CPU time | 6.19 seconds |
| Started | Oct 12 09:02:05 AM UTC 24 |
| Finished | Oct 12 09:02:13 AM UTC 24 |
| Peak memory | 224948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987795115 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstan ding.2987795115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.3181342427 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 72103399 ps |
| CPU time | 2.91 seconds |
| Started | Oct 12 09:02:04 AM UTC 24 |
| Finished | Oct 12 09:02:08 AM UTC 24 |
| Peak memory | 224664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181342427 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.3181342427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.273924211 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 272337798 ps |
| CPU time | 7.72 seconds |
| Started | Oct 12 09:02:04 AM UTC 24 |
| Finished | Oct 12 09:02:13 AM UTC 24 |
| Peak memory | 224644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273924211 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.273924211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.941253256 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 599723309 ps |
| CPU time | 2.63 seconds |
| Started | Oct 12 09:02:08 AM UTC 24 |
| Finished | Oct 12 09:02:12 AM UTC 24 |
| Peak memory | 226796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=941253256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.spi_device_csr_mem_rw_with_rand_reset.941253256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.332610584 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 48831169 ps |
| CPU time | 2.74 seconds |
| Started | Oct 12 09:02:07 AM UTC 24 |
| Finished | Oct 12 09:02:11 AM UTC 24 |
| Peak memory | 224636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332610584 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.332610584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3730928649 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 11699305 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 09:02:07 AM UTC 24 |
| Finished | Oct 12 09:02:09 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730928649 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.3730928649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.113874499 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 28660311 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 09:02:08 AM UTC 24 |
| Finished | Oct 12 09:02:11 AM UTC 24 |
| Peak memory | 223560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113874499 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstand ing.113874499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.2681117840 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 206187796 ps |
| CPU time | 4.28 seconds |
| Started | Oct 12 09:02:07 AM UTC 24 |
| Finished | Oct 12 09:02:12 AM UTC 24 |
| Peak memory | 226724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681117840 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.2681117840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.673567471 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 876070311 ps |
| CPU time | 12.25 seconds |
| Started | Oct 12 09:02:07 AM UTC 24 |
| Finished | Oct 12 09:02:20 AM UTC 24 |
| Peak memory | 224748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673567471 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.673567471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4126889439 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 146711523 ps |
| CPU time | 3.51 seconds |
| Started | Oct 12 09:02:10 AM UTC 24 |
| Finished | Oct 12 09:02:15 AM UTC 24 |
| Peak memory | 226676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4126889439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.spi_device_csr_mem_rw_with_rand_reset.4126889439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4233173117 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 94831840 ps |
| CPU time | 3.12 seconds |
| Started | Oct 12 09:02:10 AM UTC 24 |
| Finished | Oct 12 09:02:14 AM UTC 24 |
| Peak memory | 214416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233173117 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.4233173117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2888541537 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 27533600 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 09:02:10 AM UTC 24 |
| Finished | Oct 12 09:02:12 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888541537 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2888541537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2314383149 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 54801500 ps |
| CPU time | 2.82 seconds |
| Started | Oct 12 09:02:10 AM UTC 24 |
| Finished | Oct 12 09:02:14 AM UTC 24 |
| Peak memory | 214416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314383149 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan ding.2314383149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2601736187 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 575303585 ps |
| CPU time | 3.58 seconds |
| Started | Oct 12 09:02:10 AM UTC 24 |
| Finished | Oct 12 09:02:15 AM UTC 24 |
| Peak memory | 224940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601736187 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.2601736187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1465415852 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 3469108279 ps |
| CPU time | 21.53 seconds |
| Started | Oct 12 09:02:10 AM UTC 24 |
| Finished | Oct 12 09:02:33 AM UTC 24 |
| Peak memory | 226824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465415852 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.1465415852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.321025508 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 52056575 ps |
| CPU time | 2.49 seconds |
| Started | Oct 12 09:02:12 AM UTC 24 |
| Finished | Oct 12 09:02:15 AM UTC 24 |
| Peak memory | 226704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=321025508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.spi_device_csr_mem_rw_with_rand_reset.321025508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1307314906 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 53588354 ps |
| CPU time | 2 seconds |
| Started | Oct 12 09:02:12 AM UTC 24 |
| Finished | Oct 12 09:02:15 AM UTC 24 |
| Peak memory | 213056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307314906 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.1307314906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3239045039 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 36726512 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 09:02:12 AM UTC 24 |
| Finished | Oct 12 09:02:14 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239045039 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.3239045039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3216936080 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 272936940 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 09:02:12 AM UTC 24 |
| Finished | Oct 12 09:02:15 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216936080 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstan ding.3216936080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.51434220 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 209342025 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 09:02:10 AM UTC 24 |
| Finished | Oct 12 09:02:14 AM UTC 24 |
| Peak memory | 224976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51434220 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.51434220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2783065234 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 100858221 ps |
| CPU time | 4.73 seconds |
| Started | Oct 12 09:02:15 AM UTC 24 |
| Finished | Oct 12 09:02:21 AM UTC 24 |
| Peak memory | 228792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2783065234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.spi_device_csr_mem_rw_with_rand_reset.2783065234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1758028951 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 109858897 ps |
| CPU time | 2.58 seconds |
| Started | Oct 12 09:02:13 AM UTC 24 |
| Finished | Oct 12 09:02:17 AM UTC 24 |
| Peak memory | 224596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758028951 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.1758028951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3424338440 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 23018924 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 09:02:13 AM UTC 24 |
| Finished | Oct 12 09:02:15 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424338440 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.3424338440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3578132880 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 159078590 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 09:02:15 AM UTC 24 |
| Finished | Oct 12 09:02:19 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578132880 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstan ding.3578132880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3348669579 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 57833176 ps |
| CPU time | 4.03 seconds |
| Started | Oct 12 09:02:13 AM UTC 24 |
| Finished | Oct 12 09:02:18 AM UTC 24 |
| Peak memory | 226812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348669579 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.3348669579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.3056313486 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 2231644127 ps |
| CPU time | 15.51 seconds |
| Started | Oct 12 09:02:13 AM UTC 24 |
| Finished | Oct 12 09:02:30 AM UTC 24 |
| Peak memory | 226884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056313486 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.3056313486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1757271119 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 52283840 ps |
| CPU time | 2.55 seconds |
| Started | Oct 12 09:02:17 AM UTC 24 |
| Finished | Oct 12 09:02:20 AM UTC 24 |
| Peak memory | 226744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1757271119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.spi_device_csr_mem_rw_with_rand_reset.1757271119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2739238274 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 18678075 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 09:02:15 AM UTC 24 |
| Finished | Oct 12 09:02:18 AM UTC 24 |
| Peak memory | 223336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739238274 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.2739238274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2485342241 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 14930724 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 09:02:15 AM UTC 24 |
| Finished | Oct 12 09:02:17 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485342241 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2485342241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2753469568 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 148646919 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 09:02:16 AM UTC 24 |
| Finished | Oct 12 09:02:20 AM UTC 24 |
| Peak memory | 224524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753469568 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstan ding.2753469568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.4056745457 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 56784400 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 09:02:15 AM UTC 24 |
| Finished | Oct 12 09:02:18 AM UTC 24 |
| Peak memory | 225092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056745457 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.4056745457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1793876510 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 825583496 ps |
| CPU time | 20.64 seconds |
| Started | Oct 12 09:02:15 AM UTC 24 |
| Finished | Oct 12 09:02:37 AM UTC 24 |
| Peak memory | 224688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793876510 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.1793876510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3872455046 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 94780903 ps |
| CPU time | 2.5 seconds |
| Started | Oct 12 09:02:17 AM UTC 24 |
| Finished | Oct 12 09:02:20 AM UTC 24 |
| Peak memory | 224824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3872455046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.spi_device_csr_mem_rw_with_rand_reset.3872455046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3904520838 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 70289036 ps |
| CPU time | 3.49 seconds |
| Started | Oct 12 09:02:17 AM UTC 24 |
| Finished | Oct 12 09:02:21 AM UTC 24 |
| Peak memory | 214392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904520838 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.3904520838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2383330920 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 26214844 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 09:02:17 AM UTC 24 |
| Finished | Oct 12 09:02:19 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383330920 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.2383330920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3776165093 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 101776250 ps |
| CPU time | 4.21 seconds |
| Started | Oct 12 09:02:17 AM UTC 24 |
| Finished | Oct 12 09:02:22 AM UTC 24 |
| Peak memory | 224876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776165093 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstan ding.3776165093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2304895633 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 452043822 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 09:02:17 AM UTC 24 |
| Finished | Oct 12 09:02:20 AM UTC 24 |
| Peak memory | 223360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304895633 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.2304895633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3369240864 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 237162084 ps |
| CPU time | 13.99 seconds |
| Started | Oct 12 09:02:17 AM UTC 24 |
| Finished | Oct 12 09:02:32 AM UTC 24 |
| Peak memory | 224812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369240864 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.3369240864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.68270933 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 192918863 ps |
| CPU time | 4.19 seconds |
| Started | Oct 12 09:02:20 AM UTC 24 |
| Finished | Oct 12 09:02:25 AM UTC 24 |
| Peak memory | 229044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=68270933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 17.spi_device_csr_mem_rw_with_rand_reset.68270933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.295939848 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 65976190 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 09:02:18 AM UTC 24 |
| Finished | Oct 12 09:02:22 AM UTC 24 |
| Peak memory | 224948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295939848 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.295939848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.467241018 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 36127539 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 09:02:18 AM UTC 24 |
| Finished | Oct 12 09:02:20 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467241018 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.467241018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1525962189 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 1403433422 ps |
| CPU time | 2.9 seconds |
| Started | Oct 12 09:02:20 AM UTC 24 |
| Finished | Oct 12 09:02:24 AM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525962189 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan ding.1525962189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2500959461 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 681288133 ps |
| CPU time | 3.78 seconds |
| Started | Oct 12 09:02:22 AM UTC 24 |
| Finished | Oct 12 09:02:27 AM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2500959461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.spi_device_csr_mem_rw_with_rand_reset.2500959461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2563657635 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 21257490 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 09:02:22 AM UTC 24 |
| Finished | Oct 12 09:02:24 AM UTC 24 |
| Peak memory | 223296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563657635 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.2563657635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1591976646 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 46244731 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 09:02:22 AM UTC 24 |
| Finished | Oct 12 09:02:24 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591976646 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.1591976646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.103863162 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 221369665 ps |
| CPU time | 4.46 seconds |
| Started | Oct 12 09:02:22 AM UTC 24 |
| Finished | Oct 12 09:02:27 AM UTC 24 |
| Peak memory | 224688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103863162 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstand ing.103863162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3074719030 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 1132854074 ps |
| CPU time | 4.95 seconds |
| Started | Oct 12 09:02:20 AM UTC 24 |
| Finished | Oct 12 09:02:26 AM UTC 24 |
| Peak memory | 224968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074719030 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3074719030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2629315585 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 107499850 ps |
| CPU time | 8.97 seconds |
| Started | Oct 12 09:02:20 AM UTC 24 |
| Finished | Oct 12 09:02:30 AM UTC 24 |
| Peak memory | 224744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629315585 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.2629315585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.254488540 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 206654772 ps |
| CPU time | 3.58 seconds |
| Started | Oct 12 09:02:23 AM UTC 24 |
| Finished | Oct 12 09:02:28 AM UTC 24 |
| Peak memory | 226680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=254488540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.spi_device_csr_mem_rw_with_rand_reset.254488540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.1134376156 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 394553662 ps |
| CPU time | 2.63 seconds |
| Started | Oct 12 09:02:22 AM UTC 24 |
| Finished | Oct 12 09:02:26 AM UTC 24 |
| Peak memory | 224572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134376156 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.1134376156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1814848358 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 52509168 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 09:02:22 AM UTC 24 |
| Finished | Oct 12 09:02:24 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814848358 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.1814848358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1986388293 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 595500237 ps |
| CPU time | 3.42 seconds |
| Started | Oct 12 09:02:23 AM UTC 24 |
| Finished | Oct 12 09:02:28 AM UTC 24 |
| Peak memory | 224660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986388293 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstan ding.1986388293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3840312590 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 193003151 ps |
| CPU time | 5.64 seconds |
| Started | Oct 12 09:02:22 AM UTC 24 |
| Finished | Oct 12 09:02:29 AM UTC 24 |
| Peak memory | 225016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840312590 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.3840312590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.757049392 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 2978010054 ps |
| CPU time | 16.47 seconds |
| Started | Oct 12 09:02:22 AM UTC 24 |
| Finished | Oct 12 09:02:40 AM UTC 24 |
| Peak memory | 226780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757049392 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.757049392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.2178054009 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1569736019 ps |
| CPU time | 14.24 seconds |
| Started | Oct 12 09:01:36 AM UTC 24 |
| Finished | Oct 12 09:01:51 AM UTC 24 |
| Peak memory | 224660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178054009 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.2178054009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1911703079 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 1460080141 ps |
| CPU time | 22.47 seconds |
| Started | Oct 12 09:01:35 AM UTC 24 |
| Finished | Oct 12 09:01:58 AM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911703079 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.1911703079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1116952973 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 101437531 ps |
| CPU time | 4.71 seconds |
| Started | Oct 12 09:01:37 AM UTC 24 |
| Finished | Oct 12 09:01:43 AM UTC 24 |
| Peak memory | 226696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1116952973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.spi_device_csr_mem_rw_with_rand_reset.1116952973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3089328427 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 231394833 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 09:01:34 AM UTC 24 |
| Finished | Oct 12 09:01:37 AM UTC 24 |
| Peak memory | 223288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089328427 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3089328427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3391535944 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 25192014 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 09:01:30 AM UTC 24 |
| Finished | Oct 12 09:01:33 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391535944 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3391535944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2523680281 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 86653963 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 09:01:34 AM UTC 24 |
| Finished | Oct 12 09:01:37 AM UTC 24 |
| Peak memory | 224684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523680281 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.2523680281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.4021006285 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 56271518 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 09:01:31 AM UTC 24 |
| Finished | Oct 12 09:01:34 AM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021006285 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.4021006285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1602042893 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 100602731 ps |
| CPU time | 3.81 seconds |
| Started | Oct 12 09:01:37 AM UTC 24 |
| Finished | Oct 12 09:01:42 AM UTC 24 |
| Peak memory | 224600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602042893 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand ing.1602042893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.4176883570 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1899500209 ps |
| CPU time | 6.67 seconds |
| Started | Oct 12 09:01:28 AM UTC 24 |
| Finished | Oct 12 09:01:36 AM UTC 24 |
| Peak memory | 226780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176883570 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4176883570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1980773243 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1144101870 ps |
| CPU time | 18.55 seconds |
| Started | Oct 12 09:01:29 AM UTC 24 |
| Finished | Oct 12 09:01:49 AM UTC 24 |
| Peak memory | 224748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980773243 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.1980773243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.931100263 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 55728148 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 09:02:23 AM UTC 24 |
| Finished | Oct 12 09:02:25 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931100263 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.931100263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1072907071 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 16015815 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 09:02:24 AM UTC 24 |
| Finished | Oct 12 09:02:26 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072907071 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.1072907071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2696284878 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 154395285 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 09:02:24 AM UTC 24 |
| Finished | Oct 12 09:02:26 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696284878 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.2696284878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.864859462 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 33855610 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 09:02:25 AM UTC 24 |
| Finished | Oct 12 09:02:27 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864859462 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.864859462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.4202489059 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 25908539 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 09:02:25 AM UTC 24 |
| Finished | Oct 12 09:02:27 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202489059 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.4202489059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3491942717 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 28392267 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 09:02:25 AM UTC 24 |
| Finished | Oct 12 09:02:27 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491942717 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3491942717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.188178523 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 13097477 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 09:02:25 AM UTC 24 |
| Finished | Oct 12 09:02:28 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188178523 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.188178523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1456211881 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 16512513 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 09:02:25 AM UTC 24 |
| Finished | Oct 12 09:02:27 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456211881 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.1456211881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.2705041587 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 16339002 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 09:02:26 AM UTC 24 |
| Finished | Oct 12 09:02:28 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705041587 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.2705041587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.4040699273 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 36641332 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 09:02:27 AM UTC 24 |
| Finished | Oct 12 09:02:29 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040699273 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.4040699273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.2573941020 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 735261577 ps |
| CPU time | 15.39 seconds |
| Started | Oct 12 09:01:44 AM UTC 24 |
| Finished | Oct 12 09:02:01 AM UTC 24 |
| Peak memory | 227004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573941020 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.2573941020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4222595862 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 5048789334 ps |
| CPU time | 12.38 seconds |
| Started | Oct 12 09:01:43 AM UTC 24 |
| Finished | Oct 12 09:01:57 AM UTC 24 |
| Peak memory | 224984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222595862 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.4222595862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1880040840 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 34266829 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 09:01:43 AM UTC 24 |
| Finished | Oct 12 09:01:46 AM UTC 24 |
| Peak memory | 213116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880040840 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.1880040840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3816222803 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 273951553 ps |
| CPU time | 4.88 seconds |
| Started | Oct 12 09:01:45 AM UTC 24 |
| Finished | Oct 12 09:01:51 AM UTC 24 |
| Peak memory | 226696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3816222803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.spi_device_csr_mem_rw_with_rand_reset.3816222803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.41652434 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 42094953 ps |
| CPU time | 2.02 seconds |
| Started | Oct 12 09:01:43 AM UTC 24 |
| Finished | Oct 12 09:01:46 AM UTC 24 |
| Peak memory | 214328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41652434 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.41652434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1621491300 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 13011155 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 09:01:39 AM UTC 24 |
| Finished | Oct 12 09:01:42 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621491300 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1621491300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.4207755693 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 81345494 ps |
| CPU time | 2.63 seconds |
| Started | Oct 12 09:01:41 AM UTC 24 |
| Finished | Oct 12 09:01:44 AM UTC 24 |
| Peak memory | 224652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207755693 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.4207755693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.2746976591 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 46655047 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 09:01:39 AM UTC 24 |
| Finished | Oct 12 09:01:42 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746976591 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.2746976591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.861100137 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 190077104 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 09:01:45 AM UTC 24 |
| Finished | Oct 12 09:01:49 AM UTC 24 |
| Peak memory | 224580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861100137 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.861100137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1618044306 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 377743358 ps |
| CPU time | 12.56 seconds |
| Started | Oct 12 09:01:38 AM UTC 24 |
| Finished | Oct 12 09:01:52 AM UTC 24 |
| Peak memory | 224944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618044306 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1618044306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2838017309 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 32653864 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 09:02:27 AM UTC 24 |
| Finished | Oct 12 09:02:29 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838017309 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.2838017309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2466898186 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 50930766 ps |
| CPU time | 1 seconds |
| Started | Oct 12 09:02:27 AM UTC 24 |
| Finished | Oct 12 09:02:29 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466898186 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.2466898186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.668423681 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 12103867 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 09:02:27 AM UTC 24 |
| Finished | Oct 12 09:02:29 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668423681 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.668423681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1077021388 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 13547770 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 09:02:27 AM UTC 24 |
| Finished | Oct 12 09:02:29 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077021388 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.1077021388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2184421440 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 64296873 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 09:02:27 AM UTC 24 |
| Finished | Oct 12 09:02:29 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184421440 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.2184421440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1708958965 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 26806626 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708958965 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.1708958965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2159964061 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 22748078 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159964061 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.2159964061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3191981194 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 14686214 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191981194 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3191981194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.515769104 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 17583151 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515769104 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.515769104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.1976293726 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 41919065 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976293726 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.1976293726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.865728551 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 6778434917 ps |
| CPU time | 23.11 seconds |
| Started | Oct 12 09:01:50 AM UTC 24 |
| Finished | Oct 12 09:02:14 AM UTC 24 |
| Peak memory | 224728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865728551 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.865728551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.828087492 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 537919753 ps |
| CPU time | 30.21 seconds |
| Started | Oct 12 09:01:50 AM UTC 24 |
| Finished | Oct 12 09:02:21 AM UTC 24 |
| Peak memory | 214372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828087492 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.828087492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2813932259 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 36150179 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 09:01:50 AM UTC 24 |
| Finished | Oct 12 09:01:52 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813932259 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.2813932259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3411072705 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 185146933 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 09:01:52 AM UTC 24 |
| Finished | Oct 12 09:01:56 AM UTC 24 |
| Peak memory | 224656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3411072705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.spi_device_csr_mem_rw_with_rand_reset.3411072705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1622328327 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 123827399 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 09:01:50 AM UTC 24 |
| Finished | Oct 12 09:01:53 AM UTC 24 |
| Peak memory | 223328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622328327 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1622328327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1442982932 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 11714035 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 09:01:46 AM UTC 24 |
| Finished | Oct 12 09:01:49 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442982932 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1442982932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1898238968 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 165576253 ps |
| CPU time | 2.57 seconds |
| Started | Oct 12 09:01:49 AM UTC 24 |
| Finished | Oct 12 09:01:52 AM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898238968 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.1898238968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2159347025 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 19948596 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 09:01:46 AM UTC 24 |
| Finished | Oct 12 09:01:49 AM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159347025 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.2159347025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4264080680 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 677999876 ps |
| CPU time | 4.12 seconds |
| Started | Oct 12 09:01:50 AM UTC 24 |
| Finished | Oct 12 09:01:55 AM UTC 24 |
| Peak memory | 224600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264080680 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstand ing.4264080680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.602445181 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1280001632 ps |
| CPU time | 6.25 seconds |
| Started | Oct 12 09:01:45 AM UTC 24 |
| Finished | Oct 12 09:01:53 AM UTC 24 |
| Peak memory | 224920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602445181 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.602445181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3835503274 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 2106833211 ps |
| CPU time | 6.79 seconds |
| Started | Oct 12 09:01:46 AM UTC 24 |
| Finished | Oct 12 09:01:54 AM UTC 24 |
| Peak memory | 226952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835503274 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.3835503274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3836107002 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 71049120 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836107002 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.3836107002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2036972769 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 93538963 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036972769 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.2036972769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3477655917 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 19392811 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477655917 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3477655917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1963433347 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 13111762 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963433347 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1963433347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1187660520 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 28925721 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 09:02:29 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187660520 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.1187660520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.671359363 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 53872908 ps |
| CPU time | 0.89 seconds |
| Started | Oct 12 09:02:31 AM UTC 24 |
| Finished | Oct 12 09:02:33 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671359363 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.671359363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2891845876 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 12245713 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 09:02:31 AM UTC 24 |
| Finished | Oct 12 09:02:33 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891845876 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.2891845876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2227632680 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 12710905 ps |
| CPU time | 0.87 seconds |
| Started | Oct 12 09:02:31 AM UTC 24 |
| Finished | Oct 12 09:02:33 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227632680 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.2227632680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1172600957 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 43306489 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 09:02:31 AM UTC 24 |
| Finished | Oct 12 09:02:33 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172600957 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.1172600957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3916012630 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 44346828 ps |
| CPU time | 0.92 seconds |
| Started | Oct 12 09:02:31 AM UTC 24 |
| Finished | Oct 12 09:02:33 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916012630 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.3916012630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.487254284 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 83019433 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 09:01:54 AM UTC 24 |
| Finished | Oct 12 09:01:57 AM UTC 24 |
| Peak memory | 226768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=487254284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.spi_device_csr_mem_rw_with_rand_reset.487254284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2314888308 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 216460384 ps |
| CPU time | 2.57 seconds |
| Started | Oct 12 09:01:53 AM UTC 24 |
| Finished | Oct 12 09:01:57 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314888308 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2314888308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.2734911758 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 43440966 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 09:01:53 AM UTC 24 |
| Finished | Oct 12 09:01:55 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734911758 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2734911758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1288458199 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 48841564 ps |
| CPU time | 3.79 seconds |
| Started | Oct 12 09:01:53 AM UTC 24 |
| Finished | Oct 12 09:01:58 AM UTC 24 |
| Peak memory | 224856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288458199 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstand ing.1288458199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.2202308280 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 913425493 ps |
| CPU time | 4.41 seconds |
| Started | Oct 12 09:01:52 AM UTC 24 |
| Finished | Oct 12 09:01:58 AM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202308280 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2202308280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2163914412 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 536577425 ps |
| CPU time | 16.37 seconds |
| Started | Oct 12 09:01:53 AM UTC 24 |
| Finished | Oct 12 09:02:11 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163914412 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.2163914412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2080464762 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 44603746 ps |
| CPU time | 2.31 seconds |
| Started | Oct 12 09:01:57 AM UTC 24 |
| Finished | Oct 12 09:02:01 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2080464762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.spi_device_csr_mem_rw_with_rand_reset.2080464762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2598655243 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 79955129 ps |
| CPU time | 1.92 seconds |
| Started | Oct 12 09:01:56 AM UTC 24 |
| Finished | Oct 12 09:01:59 AM UTC 24 |
| Peak memory | 213048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598655243 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2598655243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1159936758 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 29174896 ps |
| CPU time | 0.9 seconds |
| Started | Oct 12 09:01:56 AM UTC 24 |
| Finished | Oct 12 09:01:58 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159936758 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1159936758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.906165606 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 28152442 ps |
| CPU time | 2.64 seconds |
| Started | Oct 12 09:01:57 AM UTC 24 |
| Finished | Oct 12 09:02:01 AM UTC 24 |
| Peak memory | 224448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906165606 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.906165606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.127539389 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 105809813 ps |
| CPU time | 2.56 seconds |
| Started | Oct 12 09:01:55 AM UTC 24 |
| Finished | Oct 12 09:01:58 AM UTC 24 |
| Peak memory | 224764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127539389 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.127539389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.2858432708 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 355722654 ps |
| CPU time | 11.3 seconds |
| Started | Oct 12 09:01:56 AM UTC 24 |
| Finished | Oct 12 09:02:08 AM UTC 24 |
| Peak memory | 224944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858432708 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.2858432708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1960717028 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 110641131 ps |
| CPU time | 2.31 seconds |
| Started | Oct 12 09:02:00 AM UTC 24 |
| Finished | Oct 12 09:02:03 AM UTC 24 |
| Peak memory | 224852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1960717028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.spi_device_csr_mem_rw_with_rand_reset.1960717028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3006419800 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 61468445 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 09:01:58 AM UTC 24 |
| Finished | Oct 12 09:02:01 AM UTC 24 |
| Peak memory | 223340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006419800 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3006419800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1987177535 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 38305077 ps |
| CPU time | 1 seconds |
| Started | Oct 12 09:01:58 AM UTC 24 |
| Finished | Oct 12 09:02:01 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987177535 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1987177535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1156545035 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 471049514 ps |
| CPU time | 2.39 seconds |
| Started | Oct 12 09:01:59 AM UTC 24 |
| Finished | Oct 12 09:02:02 AM UTC 24 |
| Peak memory | 224584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156545035 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand ing.1156545035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1072078664 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 736739286 ps |
| CPU time | 4.73 seconds |
| Started | Oct 12 09:01:58 AM UTC 24 |
| Finished | Oct 12 09:02:04 AM UTC 24 |
| Peak memory | 224824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072078664 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1072078664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2718203579 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 806141749 ps |
| CPU time | 16.76 seconds |
| Started | Oct 12 09:01:58 AM UTC 24 |
| Finished | Oct 12 09:02:17 AM UTC 24 |
| Peak memory | 224704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718203579 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.2718203579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3908805610 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 156134162 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 09:02:02 AM UTC 24 |
| Finished | Oct 12 09:02:06 AM UTC 24 |
| Peak memory | 232772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3908805610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.spi_device_csr_mem_rw_with_rand_reset.3908805610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.1372541285 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1054991615 ps |
| CPU time | 3.45 seconds |
| Started | Oct 12 09:02:00 AM UTC 24 |
| Finished | Oct 12 09:02:05 AM UTC 24 |
| Peak memory | 224628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372541285 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1372541285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2343627660 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 113583640 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 09:02:00 AM UTC 24 |
| Finished | Oct 12 09:02:02 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343627660 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2343627660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1541051182 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 251073900 ps |
| CPU time | 3.42 seconds |
| Started | Oct 12 09:02:01 AM UTC 24 |
| Finished | Oct 12 09:02:06 AM UTC 24 |
| Peak memory | 224576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541051182 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand ing.1541051182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2879485422 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 6991671414 ps |
| CPU time | 19.94 seconds |
| Started | Oct 12 09:02:00 AM UTC 24 |
| Finished | Oct 12 09:02:21 AM UTC 24 |
| Peak memory | 224872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879485422 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.2879485422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2472032462 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 47113982 ps |
| CPU time | 2.42 seconds |
| Started | Oct 12 09:02:04 AM UTC 24 |
| Finished | Oct 12 09:02:07 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2472032462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.spi_device_csr_mem_rw_with_rand_reset.2472032462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3785337920 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 54743883 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 09:02:02 AM UTC 24 |
| Finished | Oct 12 09:02:05 AM UTC 24 |
| Peak memory | 213048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785337920 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3785337920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3793683810 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 31366035 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 09:02:02 AM UTC 24 |
| Finished | Oct 12 09:02:05 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793683810 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3793683810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.661367373 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 185705735 ps |
| CPU time | 5.25 seconds |
| Started | Oct 12 09:02:04 AM UTC 24 |
| Finished | Oct 12 09:02:10 AM UTC 24 |
| Peak memory | 224572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661367373 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.661367373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.1840252711 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 319507753 ps |
| CPU time | 5.4 seconds |
| Started | Oct 12 09:02:02 AM UTC 24 |
| Finished | Oct 12 09:02:09 AM UTC 24 |
| Peak memory | 224760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840252711 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1840252711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.929822618 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3407861049 ps |
| CPU time | 25.56 seconds |
| Started | Oct 12 09:02:02 AM UTC 24 |
| Finished | Oct 12 09:02:29 AM UTC 24 |
| Peak memory | 226864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929822618 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.929822618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2961118043 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 149290575 ps |
| CPU time | 3.29 seconds |
| Started | Oct 12 08:38:41 AM UTC 24 |
| Finished | Oct 12 08:38:45 AM UTC 24 |
| Peak memory | 245940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961118043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2961118043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1338032484 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 50701522748 ps |
| CPU time | 216.89 seconds |
| Started | Oct 12 08:38:49 AM UTC 24 |
| Finished | Oct 12 08:42:29 AM UTC 24 |
| Peak memory | 264316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338032484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1338032484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.2110784685 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1805553080 ps |
| CPU time | 14.96 seconds |
| Started | Oct 12 08:38:46 AM UTC 24 |
| Finished | Oct 12 08:39:02 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110784685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2110784685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.745774811 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1280692201 ps |
| CPU time | 14.99 seconds |
| Started | Oct 12 08:38:39 AM UTC 24 |
| Finished | Oct 12 08:38:55 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745774811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.745774811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.978871977 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5131220662 ps |
| CPU time | 17.83 seconds |
| Started | Oct 12 08:38:29 AM UTC 24 |
| Finished | Oct 12 08:38:48 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978871977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.978871977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3171751402 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 197047531 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 08:38:18 AM UTC 24 |
| Finished | Oct 12 08:38:21 AM UTC 24 |
| Peak memory | 217036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171751402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3171751402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.4158538648 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 90070067 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 08:38:25 AM UTC 24 |
| Finished | Oct 12 08:38:29 AM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158538648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4158538648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1474033762 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 116372322 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 08:38:22 AM UTC 24 |
| Finished | Oct 12 08:38:24 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474033762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1474033762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.217727029 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4454606233 ps |
| CPU time | 17.92 seconds |
| Started | Oct 12 08:38:39 AM UTC 24 |
| Finished | Oct 12 08:38:58 AM UTC 24 |
| Peak memory | 262224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217727029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.217727029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.4255012017 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 55255074 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 08:40:15 AM UTC 24 |
| Finished | Oct 12 08:40:17 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255012017 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4255012017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.3078260192 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 123222749 ps |
| CPU time | 3.23 seconds |
| Started | Oct 12 08:39:42 AM UTC 24 |
| Finished | Oct 12 08:39:46 AM UTC 24 |
| Peak memory | 245940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078260192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3078260192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1446206815 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 36915935 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 08:39:03 AM UTC 24 |
| Finished | Oct 12 08:39:05 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446206815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1446206815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.3417066384 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 24945457 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 08:40:00 AM UTC 24 |
| Finished | Oct 12 08:40:03 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417066384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3417066384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2413344490 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 119105571082 ps |
| CPU time | 320.37 seconds |
| Started | Oct 12 08:40:03 AM UTC 24 |
| Finished | Oct 12 08:45:28 AM UTC 24 |
| Peak memory | 268468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413344490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2413344490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.377857314 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 48188106108 ps |
| CPU time | 268.96 seconds |
| Started | Oct 12 08:40:05 AM UTC 24 |
| Finished | Oct 12 08:44:37 AM UTC 24 |
| Peak memory | 252076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377857314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.377857314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2975995976 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 17738395651 ps |
| CPU time | 81.08 seconds |
| Started | Oct 12 08:39:47 AM UTC 24 |
| Finished | Oct 12 08:41:10 AM UTC 24 |
| Peak memory | 268432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975995976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.2975995976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.988783510 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 713707937 ps |
| CPU time | 5.8 seconds |
| Started | Oct 12 08:39:30 AM UTC 24 |
| Finished | Oct 12 08:39:37 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988783510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.988783510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3740972238 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 775582100 ps |
| CPU time | 5.06 seconds |
| Started | Oct 12 08:39:35 AM UTC 24 |
| Finished | Oct 12 08:39:41 AM UTC 24 |
| Peak memory | 245900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740972238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3740972238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1865906278 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1334008361 ps |
| CPU time | 8.31 seconds |
| Started | Oct 12 08:39:24 AM UTC 24 |
| Finished | Oct 12 08:39:34 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865906278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.1865906278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2531228617 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2846846885 ps |
| CPU time | 12.72 seconds |
| Started | Oct 12 08:39:50 AM UTC 24 |
| Finished | Oct 12 08:40:04 AM UTC 24 |
| Peak memory | 234320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531228617 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.2531228617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4019912874 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 290000255 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 08:40:14 AM UTC 24 |
| Finished | Oct 12 08:40:17 AM UTC 24 |
| Peak memory | 258728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019912874 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4019912874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.375010850 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 220643189 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 08:40:12 AM UTC 24 |
| Finished | Oct 12 08:40:14 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375010850 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.375010850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.2324622821 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 346152213 ps |
| CPU time | 6.96 seconds |
| Started | Oct 12 08:39:08 AM UTC 24 |
| Finished | Oct 12 08:39:16 AM UTC 24 |
| Peak memory | 228268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324622821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2324622821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1975291193 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2330376535 ps |
| CPU time | 6.82 seconds |
| Started | Oct 12 08:39:06 AM UTC 24 |
| Finished | Oct 12 08:39:14 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975291193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1975291193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3210115454 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1092363845 ps |
| CPU time | 4.98 seconds |
| Started | Oct 12 08:39:17 AM UTC 24 |
| Finished | Oct 12 08:39:23 AM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210115454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3210115454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3025074057 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 42099121 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:39:15 AM UTC 24 |
| Finished | Oct 12 08:39:17 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025074057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3025074057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3089397268 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 5628024382 ps |
| CPU time | 9.9 seconds |
| Started | Oct 12 08:39:38 AM UTC 24 |
| Finished | Oct 12 08:39:49 AM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089397268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3089397268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.4026315045 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 117530349 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:46:03 AM UTC 24 |
| Finished | Oct 12 08:46:05 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026315045 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.4026315045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.4109182376 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 683478155 ps |
| CPU time | 6.84 seconds |
| Started | Oct 12 08:45:44 AM UTC 24 |
| Finished | Oct 12 08:45:52 AM UTC 24 |
| Peak memory | 235600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109182376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4109182376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.47431110 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 19851421 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 08:45:29 AM UTC 24 |
| Finished | Oct 12 08:45:31 AM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47431110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.47431110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1045794275 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 6809673274 ps |
| CPU time | 14.11 seconds |
| Started | Oct 12 08:45:53 AM UTC 24 |
| Finished | Oct 12 08:46:08 AM UTC 24 |
| Peak memory | 252208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045794275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1045794275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.81448576 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 164212597319 ps |
| CPU time | 344.83 seconds |
| Started | Oct 12 08:45:53 AM UTC 24 |
| Finished | Oct 12 08:51:43 AM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81448576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.81448576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.190672070 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 9530761783 ps |
| CPU time | 27.44 seconds |
| Started | Oct 12 08:45:54 AM UTC 24 |
| Finished | Oct 12 08:46:23 AM UTC 24 |
| Peak memory | 230424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190672070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.190672070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1315924407 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1850997842 ps |
| CPU time | 13.83 seconds |
| Started | Oct 12 08:45:47 AM UTC 24 |
| Finished | Oct 12 08:46:02 AM UTC 24 |
| Peak memory | 262224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315924407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1315924407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1434963375 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 38675930678 ps |
| CPU time | 298.6 seconds |
| Started | Oct 12 08:45:50 AM UTC 24 |
| Finished | Oct 12 08:50:53 AM UTC 24 |
| Peak memory | 268596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434963375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.1434963375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.445178097 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 536112883 ps |
| CPU time | 9.35 seconds |
| Started | Oct 12 08:45:39 AM UTC 24 |
| Finished | Oct 12 08:45:49 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445178097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.445178097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1689010498 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 10644604260 ps |
| CPU time | 33.42 seconds |
| Started | Oct 12 08:45:39 AM UTC 24 |
| Finished | Oct 12 08:46:13 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689010498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1689010498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1051919614 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1388332772 ps |
| CPU time | 18.43 seconds |
| Started | Oct 12 08:45:36 AM UTC 24 |
| Finished | Oct 12 08:45:56 AM UTC 24 |
| Peak memory | 245820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051919614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.1051919614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.2050366648 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 555112216 ps |
| CPU time | 6.69 seconds |
| Started | Oct 12 08:45:35 AM UTC 24 |
| Finished | Oct 12 08:45:43 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050366648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2050366648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3711962474 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1297357630 ps |
| CPU time | 17.58 seconds |
| Started | Oct 12 08:45:50 AM UTC 24 |
| Finished | Oct 12 08:46:09 AM UTC 24 |
| Peak memory | 234184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711962474 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.3711962474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.995140469 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 30878123209 ps |
| CPU time | 336.11 seconds |
| Started | Oct 12 08:45:56 AM UTC 24 |
| Finished | Oct 12 08:51:37 AM UTC 24 |
| Peak memory | 268660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995140469 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.995140469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.4233997133 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 18926330205 ps |
| CPU time | 56.5 seconds |
| Started | Oct 12 08:45:32 AM UTC 24 |
| Finished | Oct 12 08:46:30 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233997133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4233997133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.1704768543 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 721051724 ps |
| CPU time | 4.97 seconds |
| Started | Oct 12 08:45:32 AM UTC 24 |
| Finished | Oct 12 08:45:38 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704768543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1704768543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1390158640 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 44262869 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 08:45:33 AM UTC 24 |
| Finished | Oct 12 08:45:35 AM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390158640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1390158640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.4283935580 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 272128570 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 08:45:32 AM UTC 24 |
| Finished | Oct 12 08:45:35 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283935580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4283935580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.2414820831 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 14851768 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:46:30 AM UTC 24 |
| Finished | Oct 12 08:46:32 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414820831 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.2414820831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2385465067 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 376643087 ps |
| CPU time | 5.16 seconds |
| Started | Oct 12 08:46:20 AM UTC 24 |
| Finished | Oct 12 08:46:26 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385465067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2385465067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.4006529671 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 92250098 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 08:46:06 AM UTC 24 |
| Finished | Oct 12 08:46:08 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006529671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4006529671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2272329222 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 67237278200 ps |
| CPU time | 214.67 seconds |
| Started | Oct 12 08:46:27 AM UTC 24 |
| Finished | Oct 12 08:50:06 AM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272329222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.2272329222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2841291033 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 135834436639 ps |
| CPU time | 135.42 seconds |
| Started | Oct 12 08:46:24 AM UTC 24 |
| Finished | Oct 12 08:48:42 AM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841291033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.2841291033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1881275252 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 556908226 ps |
| CPU time | 7.24 seconds |
| Started | Oct 12 08:46:13 AM UTC 24 |
| Finished | Oct 12 08:46:22 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881275252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1881275252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1242119817 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 985672469 ps |
| CPU time | 15.75 seconds |
| Started | Oct 12 08:46:15 AM UTC 24 |
| Finished | Oct 12 08:46:32 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242119817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1242119817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1862443212 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1091178943 ps |
| CPU time | 8.78 seconds |
| Started | Oct 12 08:46:13 AM UTC 24 |
| Finished | Oct 12 08:46:24 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862443212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.1862443212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3527350857 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2509851336 ps |
| CPU time | 14.54 seconds |
| Started | Oct 12 08:46:12 AM UTC 24 |
| Finished | Oct 12 08:46:28 AM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527350857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3527350857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.425199846 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 873822269 ps |
| CPU time | 11.16 seconds |
| Started | Oct 12 08:46:24 AM UTC 24 |
| Finished | Oct 12 08:46:37 AM UTC 24 |
| Peak memory | 234192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425199846 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.425199846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1272151322 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 10536233851 ps |
| CPU time | 137.02 seconds |
| Started | Oct 12 08:46:28 AM UTC 24 |
| Finished | Oct 12 08:48:48 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272151322 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.1272151322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.708238539 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1903250401 ps |
| CPU time | 2.23 seconds |
| Started | Oct 12 08:46:09 AM UTC 24 |
| Finished | Oct 12 08:46:12 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708238539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.708238539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3088699242 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 9518687245 ps |
| CPU time | 13.64 seconds |
| Started | Oct 12 08:46:09 AM UTC 24 |
| Finished | Oct 12 08:46:24 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088699242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3088699242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.4837955 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 135324967 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 08:46:10 AM UTC 24 |
| Finished | Oct 12 08:46:13 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4837955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_dev ice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4837955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1519574847 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 62770571 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 08:46:10 AM UTC 24 |
| Finished | Oct 12 08:46:13 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519574847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1519574847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.2235391538 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2200029568 ps |
| CPU time | 9.87 seconds |
| Started | Oct 12 08:46:15 AM UTC 24 |
| Finished | Oct 12 08:46:26 AM UTC 24 |
| Peak memory | 247864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235391538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2235391538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.143289492 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 40445435 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:46:45 AM UTC 24 |
| Finished | Oct 12 08:46:47 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143289492 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.143289492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.3816039765 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1766012784 ps |
| CPU time | 10.43 seconds |
| Started | Oct 12 08:46:40 AM UTC 24 |
| Finished | Oct 12 08:46:51 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816039765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3816039765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1807667441 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 20100266 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:46:31 AM UTC 24 |
| Finished | Oct 12 08:46:33 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807667441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1807667441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.3793876282 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 26845660433 ps |
| CPU time | 219.82 seconds |
| Started | Oct 12 08:46:43 AM UTC 24 |
| Finished | Oct 12 08:50:26 AM UTC 24 |
| Peak memory | 252072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793876282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3793876282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.4055739301 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 193432333727 ps |
| CPU time | 306.91 seconds |
| Started | Oct 12 08:46:43 AM UTC 24 |
| Finished | Oct 12 08:51:54 AM UTC 24 |
| Peak memory | 262328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055739301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4055739301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.3933382140 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5714185591 ps |
| CPU time | 110.86 seconds |
| Started | Oct 12 08:46:44 AM UTC 24 |
| Finished | Oct 12 08:48:38 AM UTC 24 |
| Peak memory | 278708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933382140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.3933382140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.2782231633 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 10560999086 ps |
| CPU time | 28.03 seconds |
| Started | Oct 12 08:46:40 AM UTC 24 |
| Finished | Oct 12 08:47:09 AM UTC 24 |
| Peak memory | 250196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782231633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2782231633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.106974597 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 12121801023 ps |
| CPU time | 53.27 seconds |
| Started | Oct 12 08:46:41 AM UTC 24 |
| Finished | Oct 12 08:47:36 AM UTC 24 |
| Peak memory | 247928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106974597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.106974597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.3762475575 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1502986093 ps |
| CPU time | 10.8 seconds |
| Started | Oct 12 08:46:39 AM UTC 24 |
| Finished | Oct 12 08:46:50 AM UTC 24 |
| Peak memory | 247832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762475575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3762475575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2886311477 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 450419089 ps |
| CPU time | 4.13 seconds |
| Started | Oct 12 08:46:37 AM UTC 24 |
| Finished | Oct 12 08:46:43 AM UTC 24 |
| Peak memory | 246004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886311477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.2886311477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2825069862 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1278218816 ps |
| CPU time | 3.71 seconds |
| Started | Oct 12 08:46:37 AM UTC 24 |
| Finished | Oct 12 08:46:42 AM UTC 24 |
| Peak memory | 235684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825069862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2825069862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3866190298 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 658620063 ps |
| CPU time | 6.15 seconds |
| Started | Oct 12 08:46:43 AM UTC 24 |
| Finished | Oct 12 08:46:50 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866190298 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.3866190298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.1974296232 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 14872481077 ps |
| CPU time | 57.93 seconds |
| Started | Oct 12 08:46:44 AM UTC 24 |
| Finished | Oct 12 08:47:44 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974296232 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.1974296232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.918642419 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 36925978 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 08:46:34 AM UTC 24 |
| Finished | Oct 12 08:46:36 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918642419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.918642419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.151948192 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2467514885 ps |
| CPU time | 9.32 seconds |
| Started | Oct 12 08:46:33 AM UTC 24 |
| Finished | Oct 12 08:46:43 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151948192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.151948192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.239409899 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 14236605 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 08:46:36 AM UTC 24 |
| Finished | Oct 12 08:46:38 AM UTC 24 |
| Peak memory | 217004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239409899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.239409899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2377169261 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 118485906 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 08:46:34 AM UTC 24 |
| Finished | Oct 12 08:46:36 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377169261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2377169261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3916624344 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 39167381158 ps |
| CPU time | 61.15 seconds |
| Started | Oct 12 08:46:39 AM UTC 24 |
| Finished | Oct 12 08:47:41 AM UTC 24 |
| Peak memory | 264332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916624344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3916624344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.372009827 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 95998506 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 08:47:15 AM UTC 24 |
| Finished | Oct 12 08:47:17 AM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372009827 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.372009827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1131833787 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 95371206 ps |
| CPU time | 2.93 seconds |
| Started | Oct 12 08:47:00 AM UTC 24 |
| Finished | Oct 12 08:47:04 AM UTC 24 |
| Peak memory | 235596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131833787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1131833787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3211135384 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 67423474 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 08:46:47 AM UTC 24 |
| Finished | Oct 12 08:46:49 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211135384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3211135384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.3996098160 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 11737588842 ps |
| CPU time | 44.15 seconds |
| Started | Oct 12 08:47:07 AM UTC 24 |
| Finished | Oct 12 08:47:53 AM UTC 24 |
| Peak memory | 264304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996098160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3996098160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2790096538 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 74614764779 ps |
| CPU time | 209.81 seconds |
| Started | Oct 12 08:47:11 AM UTC 24 |
| Finished | Oct 12 08:50:44 AM UTC 24 |
| Peak memory | 268496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790096538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.2790096538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.1335900201 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 261749990 ps |
| CPU time | 12.4 seconds |
| Started | Oct 12 08:47:01 AM UTC 24 |
| Finished | Oct 12 08:47:14 AM UTC 24 |
| Peak memory | 242804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335900201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1335900201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.294835398 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 12575479255 ps |
| CPU time | 109.69 seconds |
| Started | Oct 12 08:47:05 AM UTC 24 |
| Finished | Oct 12 08:48:57 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294835398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.294835398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.1390184377 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1106807032 ps |
| CPU time | 14.35 seconds |
| Started | Oct 12 08:46:54 AM UTC 24 |
| Finished | Oct 12 08:47:10 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390184377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1390184377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.3924133406 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 10793827774 ps |
| CPU time | 118.81 seconds |
| Started | Oct 12 08:46:54 AM UTC 24 |
| Finished | Oct 12 08:48:56 AM UTC 24 |
| Peak memory | 246036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924133406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3924133406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2218964054 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 154988713 ps |
| CPU time | 6.35 seconds |
| Started | Oct 12 08:46:52 AM UTC 24 |
| Finished | Oct 12 08:47:00 AM UTC 24 |
| Peak memory | 235540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218964054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.2218964054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.260465108 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2182623498 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 08:46:51 AM UTC 24 |
| Finished | Oct 12 08:46:59 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260465108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.260465108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2121547180 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1361147493 ps |
| CPU time | 14.68 seconds |
| Started | Oct 12 08:47:06 AM UTC 24 |
| Finished | Oct 12 08:47:22 AM UTC 24 |
| Peak memory | 234184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121547180 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.2121547180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.21573028 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 214850940524 ps |
| CPU time | 657.75 seconds |
| Started | Oct 12 08:47:15 AM UTC 24 |
| Finished | Oct 12 08:58:21 AM UTC 24 |
| Peak memory | 284916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21573028 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.21573028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3647689575 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1320386909 ps |
| CPU time | 4.83 seconds |
| Started | Oct 12 08:46:50 AM UTC 24 |
| Finished | Oct 12 08:46:56 AM UTC 24 |
| Peak memory | 228176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647689575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3647689575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.2651233095 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 56466233 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 08:46:51 AM UTC 24 |
| Finished | Oct 12 08:46:53 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651233095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2651233095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.421780947 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 131978581 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 08:46:51 AM UTC 24 |
| Finished | Oct 12 08:46:53 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421780947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.421780947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.573456621 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3625745760 ps |
| CPU time | 8.74 seconds |
| Started | Oct 12 08:46:56 AM UTC 24 |
| Finished | Oct 12 08:47:06 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573456621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.573456621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.1563275220 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 13694012 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:47:57 AM UTC 24 |
| Finished | Oct 12 08:48:00 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563275220 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.1563275220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.2702251865 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 16706880957 ps |
| CPU time | 20.77 seconds |
| Started | Oct 12 08:47:45 AM UTC 24 |
| Finished | Oct 12 08:48:07 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702251865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2702251865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.2862201161 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 58783055 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:47:18 AM UTC 24 |
| Finished | Oct 12 08:47:21 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862201161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2862201161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.4275677612 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 561443710 ps |
| CPU time | 20.36 seconds |
| Started | Oct 12 08:47:49 AM UTC 24 |
| Finished | Oct 12 08:48:11 AM UTC 24 |
| Peak memory | 245936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275677612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4275677612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3404533730 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 57280573233 ps |
| CPU time | 135.86 seconds |
| Started | Oct 12 08:47:49 AM UTC 24 |
| Finished | Oct 12 08:50:08 AM UTC 24 |
| Peak memory | 264444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404533730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3404533730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.4192143831 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 11037854308 ps |
| CPU time | 161.27 seconds |
| Started | Oct 12 08:47:50 AM UTC 24 |
| Finished | Oct 12 08:50:34 AM UTC 24 |
| Peak memory | 278972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192143831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.4192143831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2980314559 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 498895228 ps |
| CPU time | 3.81 seconds |
| Started | Oct 12 08:47:45 AM UTC 24 |
| Finished | Oct 12 08:47:49 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980314559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2980314559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1350125905 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3949322285 ps |
| CPU time | 38.39 seconds |
| Started | Oct 12 08:47:46 AM UTC 24 |
| Finished | Oct 12 08:48:26 AM UTC 24 |
| Peak memory | 262264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350125905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.1350125905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.2383903544 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 270323504 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 08:47:42 AM UTC 24 |
| Finished | Oct 12 08:47:47 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383903544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2383903544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.2700120413 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 14328837718 ps |
| CPU time | 67.49 seconds |
| Started | Oct 12 08:47:42 AM UTC 24 |
| Finished | Oct 12 08:48:52 AM UTC 24 |
| Peak memory | 262232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700120413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2700120413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2258464180 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 477184440 ps |
| CPU time | 4.66 seconds |
| Started | Oct 12 08:47:38 AM UTC 24 |
| Finished | Oct 12 08:47:44 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258464180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.2258464180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.388127588 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 402806863 ps |
| CPU time | 7.66 seconds |
| Started | Oct 12 08:47:36 AM UTC 24 |
| Finished | Oct 12 08:47:45 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388127588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.388127588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.315076723 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2644190852 ps |
| CPU time | 22.67 seconds |
| Started | Oct 12 08:47:48 AM UTC 24 |
| Finished | Oct 12 08:48:12 AM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315076723 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.315076723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.2814467516 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2967796210 ps |
| CPU time | 36.39 seconds |
| Started | Oct 12 08:47:25 AM UTC 24 |
| Finished | Oct 12 08:48:02 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814467516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2814467516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2263850515 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5032340177 ps |
| CPU time | 19.27 seconds |
| Started | Oct 12 08:47:23 AM UTC 24 |
| Finished | Oct 12 08:47:43 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263850515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2263850515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.2906794106 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 499201462 ps |
| CPU time | 7.17 seconds |
| Started | Oct 12 08:47:33 AM UTC 24 |
| Finished | Oct 12 08:47:41 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906794106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2906794106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.835831365 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 176291340 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 08:47:30 AM UTC 24 |
| Finished | Oct 12 08:47:32 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835831365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.835831365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.2165891568 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 108100353 ps |
| CPU time | 2.98 seconds |
| Started | Oct 12 08:47:43 AM UTC 24 |
| Finished | Oct 12 08:47:48 AM UTC 24 |
| Peak memory | 235188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165891568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2165891568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.1218482029 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 25596162 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:48:33 AM UTC 24 |
| Finished | Oct 12 08:48:36 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218482029 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.1218482029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.1875709004 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 470481614 ps |
| CPU time | 8.14 seconds |
| Started | Oct 12 08:48:22 AM UTC 24 |
| Finished | Oct 12 08:48:32 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875709004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1875709004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.2570358010 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 44154130 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 08:48:00 AM UTC 24 |
| Finished | Oct 12 08:48:03 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570358010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2570358010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.584420477 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 7597989750 ps |
| CPU time | 99.33 seconds |
| Started | Oct 12 08:48:27 AM UTC 24 |
| Finished | Oct 12 08:50:08 AM UTC 24 |
| Peak memory | 262288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584420477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.584420477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.886288193 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 35980623311 ps |
| CPU time | 382.06 seconds |
| Started | Oct 12 08:48:29 AM UTC 24 |
| Finished | Oct 12 08:54:56 AM UTC 24 |
| Peak memory | 268436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886288193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.886288193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1102339199 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1840363074 ps |
| CPU time | 46.57 seconds |
| Started | Oct 12 08:48:31 AM UTC 24 |
| Finished | Oct 12 08:49:19 AM UTC 24 |
| Peak memory | 260240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102339199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.1102339199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.1826561143 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 512148681 ps |
| CPU time | 5.23 seconds |
| Started | Oct 12 08:48:26 AM UTC 24 |
| Finished | Oct 12 08:48:32 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826561143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1826561143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.66027877 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 13905100520 ps |
| CPU time | 142.2 seconds |
| Started | Oct 12 08:48:26 AM UTC 24 |
| Finished | Oct 12 08:50:50 AM UTC 24 |
| Peak memory | 252016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66027877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.66027877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3470636813 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1002067126 ps |
| CPU time | 8.09 seconds |
| Started | Oct 12 08:48:12 AM UTC 24 |
| Finished | Oct 12 08:48:21 AM UTC 24 |
| Peak memory | 242660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470636813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3470636813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.4106947769 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 7693842147 ps |
| CPU time | 98.07 seconds |
| Started | Oct 12 08:48:12 AM UTC 24 |
| Finished | Oct 12 08:49:53 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106947769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4106947769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2770136060 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 615340209 ps |
| CPU time | 12.78 seconds |
| Started | Oct 12 08:48:11 AM UTC 24 |
| Finished | Oct 12 08:48:25 AM UTC 24 |
| Peak memory | 245832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770136060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.2770136060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.531325368 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 10496158651 ps |
| CPU time | 16.48 seconds |
| Started | Oct 12 08:48:10 AM UTC 24 |
| Finished | Oct 12 08:48:28 AM UTC 24 |
| Peak memory | 246136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531325368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.531325368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.2449016304 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2670176831 ps |
| CPU time | 16.98 seconds |
| Started | Oct 12 08:48:27 AM UTC 24 |
| Finished | Oct 12 08:48:45 AM UTC 24 |
| Peak memory | 234524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449016304 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.2449016304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.1285630125 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 245564027950 ps |
| CPU time | 368.93 seconds |
| Started | Oct 12 08:48:32 AM UTC 24 |
| Finished | Oct 12 08:54:46 AM UTC 24 |
| Peak memory | 268460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285630125 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.1285630125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.55263594 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2340375768 ps |
| CPU time | 42.14 seconds |
| Started | Oct 12 08:48:05 AM UTC 24 |
| Finished | Oct 12 08:48:48 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55263594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.55263594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3205698597 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 5469315953 ps |
| CPU time | 20 seconds |
| Started | Oct 12 08:48:04 AM UTC 24 |
| Finished | Oct 12 08:48:25 AM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205698597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3205698597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.606064205 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 233053586 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 08:48:08 AM UTC 24 |
| Finished | Oct 12 08:48:11 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606064205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.606064205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.516520637 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 18635811 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:48:07 AM UTC 24 |
| Finished | Oct 12 08:48:09 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516520637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.516520637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2541484096 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 7930267634 ps |
| CPU time | 12.47 seconds |
| Started | Oct 12 08:48:12 AM UTC 24 |
| Finished | Oct 12 08:48:26 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541484096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2541484096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.2688312059 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 31889124 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:49:06 AM UTC 24 |
| Finished | Oct 12 08:49:08 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688312059 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.2688312059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.2470192830 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 651375274 ps |
| CPU time | 12.09 seconds |
| Started | Oct 12 08:48:52 AM UTC 24 |
| Finished | Oct 12 08:49:06 AM UTC 24 |
| Peak memory | 245972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470192830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2470192830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.3395100187 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 15750945 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 08:48:36 AM UTC 24 |
| Finished | Oct 12 08:48:39 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395100187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3395100187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.1581956568 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 621752328406 ps |
| CPU time | 355.92 seconds |
| Started | Oct 12 08:48:58 AM UTC 24 |
| Finished | Oct 12 08:54:58 AM UTC 24 |
| Peak memory | 266564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581956568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1581956568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2646875381 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 67887049348 ps |
| CPU time | 331.68 seconds |
| Started | Oct 12 08:49:00 AM UTC 24 |
| Finished | Oct 12 08:54:36 AM UTC 24 |
| Peak memory | 268472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646875381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2646875381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2270362094 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 37325032017 ps |
| CPU time | 85.98 seconds |
| Started | Oct 12 08:49:01 AM UTC 24 |
| Finished | Oct 12 08:50:29 AM UTC 24 |
| Peak memory | 262240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270362094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2270362094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.2397181610 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 469464044 ps |
| CPU time | 6.97 seconds |
| Started | Oct 12 08:48:53 AM UTC 24 |
| Finished | Oct 12 08:49:02 AM UTC 24 |
| Peak memory | 235700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397181610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2397181610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.2290113753 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 776498288 ps |
| CPU time | 16.68 seconds |
| Started | Oct 12 08:48:49 AM UTC 24 |
| Finished | Oct 12 08:49:07 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290113753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2290113753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.936431782 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 698510955 ps |
| CPU time | 9.22 seconds |
| Started | Oct 12 08:48:49 AM UTC 24 |
| Finished | Oct 12 08:49:00 AM UTC 24 |
| Peak memory | 245776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936431782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.936431782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.803469217 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 383439933 ps |
| CPU time | 5.93 seconds |
| Started | Oct 12 08:48:46 AM UTC 24 |
| Finished | Oct 12 08:48:53 AM UTC 24 |
| Peak memory | 235648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803469217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.803469217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2597919703 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 8463354902 ps |
| CPU time | 11.84 seconds |
| Started | Oct 12 08:48:46 AM UTC 24 |
| Finished | Oct 12 08:48:59 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597919703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2597919703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2297955869 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2309556128 ps |
| CPU time | 27.92 seconds |
| Started | Oct 12 08:48:58 AM UTC 24 |
| Finished | Oct 12 08:49:27 AM UTC 24 |
| Peak memory | 232332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297955869 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.2297955869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.1616502097 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 6463442412 ps |
| CPU time | 38.4 seconds |
| Started | Oct 12 08:48:42 AM UTC 24 |
| Finished | Oct 12 08:49:21 AM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616502097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1616502097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.94955540 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 196936898 ps |
| CPU time | 3.35 seconds |
| Started | Oct 12 08:48:40 AM UTC 24 |
| Finished | Oct 12 08:48:44 AM UTC 24 |
| Peak memory | 217916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94955540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.94955540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.3347194761 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2106274939 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 08:48:45 AM UTC 24 |
| Finished | Oct 12 08:48:49 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347194761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3347194761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3996012095 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 58647101 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:48:43 AM UTC 24 |
| Finished | Oct 12 08:48:45 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996012095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3996012095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.3251201324 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 572960814 ps |
| CPU time | 5.02 seconds |
| Started | Oct 12 08:48:50 AM UTC 24 |
| Finished | Oct 12 08:48:56 AM UTC 24 |
| Peak memory | 240628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251201324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3251201324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.3200363956 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 36556304 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:49:40 AM UTC 24 |
| Finished | Oct 12 08:49:42 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200363956 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3200363956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.3178190516 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 115696914 ps |
| CPU time | 4.83 seconds |
| Started | Oct 12 08:49:33 AM UTC 24 |
| Finished | Oct 12 08:49:39 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178190516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3178190516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.2519397528 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 34880411 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 08:49:08 AM UTC 24 |
| Finished | Oct 12 08:49:10 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519397528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2519397528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.3653158005 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 45697837 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:49:39 AM UTC 24 |
| Finished | Oct 12 08:49:41 AM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653158005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3653158005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3787272231 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2547752224 ps |
| CPU time | 53.9 seconds |
| Started | Oct 12 08:49:39 AM UTC 24 |
| Finished | Oct 12 08:50:34 AM UTC 24 |
| Peak memory | 262132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787272231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3787272231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.4020234598 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 216819308562 ps |
| CPU time | 396.11 seconds |
| Started | Oct 12 08:49:40 AM UTC 24 |
| Finished | Oct 12 08:56:21 AM UTC 24 |
| Peak memory | 268460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020234598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.4020234598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.2547734816 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 284479554 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 08:49:34 AM UTC 24 |
| Finished | Oct 12 08:49:39 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547734816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2547734816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.3801596972 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 94350441617 ps |
| CPU time | 378.98 seconds |
| Started | Oct 12 08:49:35 AM UTC 24 |
| Finished | Oct 12 08:55:59 AM UTC 24 |
| Peak memory | 264532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801596972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.3801596972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.352598345 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4053581773 ps |
| CPU time | 16.63 seconds |
| Started | Oct 12 08:49:20 AM UTC 24 |
| Finished | Oct 12 08:49:38 AM UTC 24 |
| Peak memory | 246040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352598345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.352598345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.4287140527 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2987809700 ps |
| CPU time | 25.07 seconds |
| Started | Oct 12 08:49:22 AM UTC 24 |
| Finished | Oct 12 08:49:49 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287140527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4287140527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2655837694 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1056421336 ps |
| CPU time | 15.61 seconds |
| Started | Oct 12 08:49:18 AM UTC 24 |
| Finished | Oct 12 08:49:35 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655837694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.2655837694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3737721727 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 5176719346 ps |
| CPU time | 24.63 seconds |
| Started | Oct 12 08:49:16 AM UTC 24 |
| Finished | Oct 12 08:49:42 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737721727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3737721727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1855235229 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 90804138 ps |
| CPU time | 5.26 seconds |
| Started | Oct 12 08:49:37 AM UTC 24 |
| Finished | Oct 12 08:49:43 AM UTC 24 |
| Peak memory | 234344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855235229 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.1855235229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2541328491 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 32879759765 ps |
| CPU time | 134.61 seconds |
| Started | Oct 12 08:49:40 AM UTC 24 |
| Finished | Oct 12 08:51:57 AM UTC 24 |
| Peak memory | 282792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541328491 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.2541328491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.1647650365 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4388448336 ps |
| CPU time | 21.16 seconds |
| Started | Oct 12 08:49:12 AM UTC 24 |
| Finished | Oct 12 08:49:34 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647650365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1647650365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2695070152 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1443399845 ps |
| CPU time | 2.35 seconds |
| Started | Oct 12 08:49:09 AM UTC 24 |
| Finished | Oct 12 08:49:13 AM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695070152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2695070152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.3941326712 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 69528463 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 08:49:14 AM UTC 24 |
| Finished | Oct 12 08:49:17 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941326712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3941326712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1635874828 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 23887860 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 08:49:13 AM UTC 24 |
| Finished | Oct 12 08:49:15 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635874828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1635874828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.252131814 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 702662242 ps |
| CPU time | 9.87 seconds |
| Started | Oct 12 08:49:28 AM UTC 24 |
| Finished | Oct 12 08:49:39 AM UTC 24 |
| Peak memory | 245972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252131814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.252131814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1959964837 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 18830490 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:50:09 AM UTC 24 |
| Finished | Oct 12 08:50:11 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959964837 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.1959964837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3107614223 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1026097472 ps |
| CPU time | 16.91 seconds |
| Started | Oct 12 08:49:50 AM UTC 24 |
| Finished | Oct 12 08:50:09 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107614223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3107614223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.368021943 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 30898391 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:49:42 AM UTC 24 |
| Finished | Oct 12 08:49:44 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368021943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.368021943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1513149007 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 56942339111 ps |
| CPU time | 114.76 seconds |
| Started | Oct 12 08:50:01 AM UTC 24 |
| Finished | Oct 12 08:51:59 AM UTC 24 |
| Peak memory | 252036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513149007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1513149007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2859188394 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 20772571604 ps |
| CPU time | 241.92 seconds |
| Started | Oct 12 08:50:03 AM UTC 24 |
| Finished | Oct 12 08:54:08 AM UTC 24 |
| Peak memory | 266648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859188394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2859188394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1971332829 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 21703501500 ps |
| CPU time | 224.92 seconds |
| Started | Oct 12 08:50:03 AM UTC 24 |
| Finished | Oct 12 08:53:51 AM UTC 24 |
| Peak memory | 274600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971332829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.1971332829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.3048712319 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 776973841 ps |
| CPU time | 6.7 seconds |
| Started | Oct 12 08:49:53 AM UTC 24 |
| Finished | Oct 12 08:50:01 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048712319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3048712319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3188609616 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 17842030788 ps |
| CPU time | 44.49 seconds |
| Started | Oct 12 08:49:55 AM UTC 24 |
| Finished | Oct 12 08:50:41 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188609616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.3188609616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.1328369424 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 639317824 ps |
| CPU time | 10.96 seconds |
| Started | Oct 12 08:49:48 AM UTC 24 |
| Finished | Oct 12 08:50:01 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328369424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1328369424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.102329247 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3864956046 ps |
| CPU time | 43.1 seconds |
| Started | Oct 12 08:49:48 AM UTC 24 |
| Finished | Oct 12 08:50:34 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102329247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.102329247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1235579640 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3754988526 ps |
| CPU time | 9.5 seconds |
| Started | Oct 12 08:49:47 AM UTC 24 |
| Finished | Oct 12 08:49:57 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235579640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.1235579640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.3850294677 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 10340595755 ps |
| CPU time | 20.7 seconds |
| Started | Oct 12 08:49:46 AM UTC 24 |
| Finished | Oct 12 08:50:08 AM UTC 24 |
| Peak memory | 235828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850294677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3850294677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2078671864 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3670168299 ps |
| CPU time | 18.09 seconds |
| Started | Oct 12 08:49:58 AM UTC 24 |
| Finished | Oct 12 08:50:18 AM UTC 24 |
| Peak memory | 234468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078671864 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.2078671864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.1300724423 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 140235537776 ps |
| CPU time | 688.48 seconds |
| Started | Oct 12 08:50:07 AM UTC 24 |
| Finished | Oct 12 09:01:44 AM UTC 24 |
| Peak memory | 280752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300724423 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.1300724423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2345103587 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 37891171501 ps |
| CPU time | 29.11 seconds |
| Started | Oct 12 08:49:43 AM UTC 24 |
| Finished | Oct 12 08:50:14 AM UTC 24 |
| Peak memory | 228188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345103587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2345103587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.4193104843 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 4078192611 ps |
| CPU time | 3.07 seconds |
| Started | Oct 12 08:49:43 AM UTC 24 |
| Finished | Oct 12 08:49:47 AM UTC 24 |
| Peak memory | 217460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193104843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4193104843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.921470303 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 401213818 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 08:49:46 AM UTC 24 |
| Finished | Oct 12 08:49:48 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921470303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.921470303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.2355967740 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 66673163 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 08:49:44 AM UTC 24 |
| Finished | Oct 12 08:49:47 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355967740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2355967740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3344833950 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 107687540 ps |
| CPU time | 3.47 seconds |
| Started | Oct 12 08:49:49 AM UTC 24 |
| Finished | Oct 12 08:49:54 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344833950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3344833950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.2234576323 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 14697317 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:50:36 AM UTC 24 |
| Finished | Oct 12 08:50:38 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234576323 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.2234576323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1826606378 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 3229634766 ps |
| CPU time | 14.82 seconds |
| Started | Oct 12 08:50:19 AM UTC 24 |
| Finished | Oct 12 08:50:35 AM UTC 24 |
| Peak memory | 235664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826606378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1826606378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.523718687 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 16044495 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 08:50:09 AM UTC 24 |
| Finished | Oct 12 08:50:11 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523718687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.523718687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1464439194 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2874621693 ps |
| CPU time | 11.14 seconds |
| Started | Oct 12 08:50:33 AM UTC 24 |
| Finished | Oct 12 08:50:46 AM UTC 24 |
| Peak memory | 249960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464439194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.1464439194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.3056326375 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 379720051 ps |
| CPU time | 7.77 seconds |
| Started | Oct 12 08:50:22 AM UTC 24 |
| Finished | Oct 12 08:50:31 AM UTC 24 |
| Peak memory | 245968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056326375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3056326375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.4201745318 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 12793271827 ps |
| CPU time | 58.01 seconds |
| Started | Oct 12 08:50:27 AM UTC 24 |
| Finished | Oct 12 08:51:27 AM UTC 24 |
| Peak memory | 262448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201745318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.4201745318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.1930251410 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 810345409 ps |
| CPU time | 4.87 seconds |
| Started | Oct 12 08:50:16 AM UTC 24 |
| Finished | Oct 12 08:50:21 AM UTC 24 |
| Peak memory | 245828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930251410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1930251410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.3278585709 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 22447558842 ps |
| CPU time | 39.66 seconds |
| Started | Oct 12 08:50:17 AM UTC 24 |
| Finished | Oct 12 08:50:58 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278585709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3278585709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3264655029 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 36637750942 ps |
| CPU time | 35.3 seconds |
| Started | Oct 12 08:50:16 AM UTC 24 |
| Finished | Oct 12 08:50:52 AM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264655029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.3264655029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.801260416 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 101036636 ps |
| CPU time | 2.88 seconds |
| Started | Oct 12 08:50:14 AM UTC 24 |
| Finished | Oct 12 08:50:18 AM UTC 24 |
| Peak memory | 234656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801260416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.801260416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1773201581 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 123289678 ps |
| CPU time | 6.48 seconds |
| Started | Oct 12 08:50:29 AM UTC 24 |
| Finished | Oct 12 08:50:37 AM UTC 24 |
| Peak memory | 234236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773201581 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1773201581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.754175009 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 39377144676 ps |
| CPU time | 314.64 seconds |
| Started | Oct 12 08:50:35 AM UTC 24 |
| Finished | Oct 12 08:55:54 AM UTC 24 |
| Peak memory | 285044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754175009 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.754175009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3545501267 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3299986468 ps |
| CPU time | 34.31 seconds |
| Started | Oct 12 08:50:12 AM UTC 24 |
| Finished | Oct 12 08:50:48 AM UTC 24 |
| Peak memory | 228392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545501267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3545501267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.496030329 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 141479153 ps |
| CPU time | 3.04 seconds |
| Started | Oct 12 08:50:10 AM UTC 24 |
| Finished | Oct 12 08:50:14 AM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496030329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.496030329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.2336923621 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 51726345 ps |
| CPU time | 2.31 seconds |
| Started | Oct 12 08:50:12 AM UTC 24 |
| Finished | Oct 12 08:50:16 AM UTC 24 |
| Peak memory | 228268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336923621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2336923621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1134343841 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 11176967 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:50:12 AM UTC 24 |
| Finished | Oct 12 08:50:14 AM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134343841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1134343841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.3666914526 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1586996124 ps |
| CPU time | 8.02 seconds |
| Started | Oct 12 08:50:19 AM UTC 24 |
| Finished | Oct 12 08:50:28 AM UTC 24 |
| Peak memory | 235596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666914526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3666914526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.2223713199 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 37848090 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 08:41:15 AM UTC 24 |
| Finished | Oct 12 08:41:18 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223713199 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2223713199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.419984584 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2379364325 ps |
| CPU time | 3.92 seconds |
| Started | Oct 12 08:40:46 AM UTC 24 |
| Finished | Oct 12 08:40:51 AM UTC 24 |
| Peak memory | 235664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419984584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.419984584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.2395607274 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 57754569 ps |
| CPU time | 0.94 seconds |
| Started | Oct 12 08:40:17 AM UTC 24 |
| Finished | Oct 12 08:40:19 AM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395607274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2395607274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.2490341189 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 30171899149 ps |
| CPU time | 179.34 seconds |
| Started | Oct 12 08:40:59 AM UTC 24 |
| Finished | Oct 12 08:44:02 AM UTC 24 |
| Peak memory | 266384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490341189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2490341189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4271533183 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1252223961 ps |
| CPU time | 25.23 seconds |
| Started | Oct 12 08:40:48 AM UTC 24 |
| Finished | Oct 12 08:41:15 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271533183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4271533183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1240336489 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 21699911230 ps |
| CPU time | 170.3 seconds |
| Started | Oct 12 08:40:52 AM UTC 24 |
| Finished | Oct 12 08:43:45 AM UTC 24 |
| Peak memory | 268628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240336489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.1240336489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.924356668 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4496566552 ps |
| CPU time | 5.99 seconds |
| Started | Oct 12 08:40:27 AM UTC 24 |
| Finished | Oct 12 08:40:34 AM UTC 24 |
| Peak memory | 235588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924356668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.924356668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.1054684659 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 14283971328 ps |
| CPU time | 64.17 seconds |
| Started | Oct 12 08:40:33 AM UTC 24 |
| Finished | Oct 12 08:41:39 AM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054684659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1054684659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.4209184932 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 7894840840 ps |
| CPU time | 37.4 seconds |
| Started | Oct 12 08:40:26 AM UTC 24 |
| Finished | Oct 12 08:41:05 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209184932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.4209184932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3175821846 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1545125311 ps |
| CPU time | 5.74 seconds |
| Started | Oct 12 08:40:25 AM UTC 24 |
| Finished | Oct 12 08:40:32 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175821846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3175821846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3482856355 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3914840794 ps |
| CPU time | 6.21 seconds |
| Started | Oct 12 08:40:52 AM UTC 24 |
| Finished | Oct 12 08:41:00 AM UTC 24 |
| Peak memory | 234320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482856355 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.3482856355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3340880636 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 203552053 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 08:41:11 AM UTC 24 |
| Finished | Oct 12 08:41:14 AM UTC 24 |
| Peak memory | 259808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340880636 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3340880636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2729346515 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 10725512 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:40:18 AM UTC 24 |
| Finished | Oct 12 08:40:20 AM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729346515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2729346515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.150461230 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 144865506 ps |
| CPU time | 2.99 seconds |
| Started | Oct 12 08:40:21 AM UTC 24 |
| Finished | Oct 12 08:40:25 AM UTC 24 |
| Peak memory | 228296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150461230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.150461230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2203245 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 69327473 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 08:40:21 AM UTC 24 |
| Finished | Oct 12 08:40:24 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2203245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3412333116 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4777571848 ps |
| CPU time | 9.43 seconds |
| Started | Oct 12 08:40:35 AM UTC 24 |
| Finished | Oct 12 08:40:46 AM UTC 24 |
| Peak memory | 248088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412333116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3412333116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1910990706 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 11859325 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:50:58 AM UTC 24 |
| Finished | Oct 12 08:51:01 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910990706 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.1910990706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1013926874 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 39266027 ps |
| CPU time | 3.47 seconds |
| Started | Oct 12 08:50:45 AM UTC 24 |
| Finished | Oct 12 08:50:49 AM UTC 24 |
| Peak memory | 245756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013926874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1013926874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2828391095 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 30274419 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:50:36 AM UTC 24 |
| Finished | Oct 12 08:50:38 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828391095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2828391095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.3315437238 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 100825092957 ps |
| CPU time | 236.5 seconds |
| Started | Oct 12 08:50:51 AM UTC 24 |
| Finished | Oct 12 08:54:51 AM UTC 24 |
| Peak memory | 264304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315437238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3315437238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2552668023 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 7110066933 ps |
| CPU time | 46.95 seconds |
| Started | Oct 12 08:50:51 AM UTC 24 |
| Finished | Oct 12 08:51:39 AM UTC 24 |
| Peak memory | 246136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552668023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2552668023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3876750745 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4210096098 ps |
| CPU time | 85.52 seconds |
| Started | Oct 12 08:50:53 AM UTC 24 |
| Finished | Oct 12 08:52:20 AM UTC 24 |
| Peak memory | 278708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876750745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.3876750745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.454327999 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 953058518 ps |
| CPU time | 17.77 seconds |
| Started | Oct 12 08:50:47 AM UTC 24 |
| Finished | Oct 12 08:51:06 AM UTC 24 |
| Peak memory | 235700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454327999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.454327999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.285276677 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 11725687971 ps |
| CPU time | 85.17 seconds |
| Started | Oct 12 08:50:49 AM UTC 24 |
| Finished | Oct 12 08:52:16 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285276677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.285276677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.4227688381 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 388479258 ps |
| CPU time | 5.17 seconds |
| Started | Oct 12 08:50:43 AM UTC 24 |
| Finished | Oct 12 08:50:50 AM UTC 24 |
| Peak memory | 245804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227688381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4227688381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.136519726 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 31305404398 ps |
| CPU time | 107.91 seconds |
| Started | Oct 12 08:50:43 AM UTC 24 |
| Finished | Oct 12 08:52:34 AM UTC 24 |
| Peak memory | 245888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136519726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.136519726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.945171331 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 8738546855 ps |
| CPU time | 26.93 seconds |
| Started | Oct 12 08:50:42 AM UTC 24 |
| Finished | Oct 12 08:51:10 AM UTC 24 |
| Peak memory | 245884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945171331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.945171331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.4004961571 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 12135581335 ps |
| CPU time | 23.64 seconds |
| Started | Oct 12 08:50:42 AM UTC 24 |
| Finished | Oct 12 08:51:07 AM UTC 24 |
| Peak memory | 262268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004961571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4004961571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3773877088 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 124866648 ps |
| CPU time | 6.09 seconds |
| Started | Oct 12 08:50:50 AM UTC 24 |
| Finished | Oct 12 08:50:57 AM UTC 24 |
| Peak memory | 234336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773877088 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.3773877088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.956307715 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 41352497371 ps |
| CPU time | 133.57 seconds |
| Started | Oct 12 08:50:53 AM UTC 24 |
| Finished | Oct 12 08:53:09 AM UTC 24 |
| Peak memory | 278680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956307715 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.956307715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.4087088379 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 23418086060 ps |
| CPU time | 26.32 seconds |
| Started | Oct 12 08:50:38 AM UTC 24 |
| Finished | Oct 12 08:51:06 AM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087088379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4087088379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1632648714 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 15051477197 ps |
| CPU time | 23.06 seconds |
| Started | Oct 12 08:50:36 AM UTC 24 |
| Finished | Oct 12 08:51:00 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632648714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1632648714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.3722441494 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 162394226 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 08:50:39 AM UTC 24 |
| Finished | Oct 12 08:50:43 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722441494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3722441494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.556692528 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 20306705 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:50:39 AM UTC 24 |
| Finished | Oct 12 08:50:41 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556692528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.556692528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.593865406 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 10660888412 ps |
| CPU time | 19.7 seconds |
| Started | Oct 12 08:50:44 AM UTC 24 |
| Finished | Oct 12 08:51:04 AM UTC 24 |
| Peak memory | 235728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593865406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.593865406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.342811830 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 37813711 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 08:51:18 AM UTC 24 |
| Finished | Oct 12 08:51:20 AM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342811830 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.342811830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3010294147 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 56332700 ps |
| CPU time | 3.19 seconds |
| Started | Oct 12 08:51:11 AM UTC 24 |
| Finished | Oct 12 08:51:15 AM UTC 24 |
| Peak memory | 245972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010294147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3010294147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2379494583 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 23494585 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 08:50:58 AM UTC 24 |
| Finished | Oct 12 08:51:01 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379494583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2379494583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.3280889315 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 357984229124 ps |
| CPU time | 223.74 seconds |
| Started | Oct 12 08:51:14 AM UTC 24 |
| Finished | Oct 12 08:55:01 AM UTC 24 |
| Peak memory | 278728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280889315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3280889315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3189374669 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 149746031360 ps |
| CPU time | 137.69 seconds |
| Started | Oct 12 08:51:15 AM UTC 24 |
| Finished | Oct 12 08:53:35 AM UTC 24 |
| Peak memory | 262528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189374669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3189374669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.2777381377 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 201154850220 ps |
| CPU time | 138.94 seconds |
| Started | Oct 12 08:51:16 AM UTC 24 |
| Finished | Oct 12 08:53:37 AM UTC 24 |
| Peak memory | 262480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777381377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.2777381377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3999691835 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1493579858 ps |
| CPU time | 38.42 seconds |
| Started | Oct 12 08:51:12 AM UTC 24 |
| Finished | Oct 12 08:51:52 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999691835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3999691835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2447163250 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 57704151909 ps |
| CPU time | 356.09 seconds |
| Started | Oct 12 08:51:14 AM UTC 24 |
| Finished | Oct 12 08:57:14 AM UTC 24 |
| Peak memory | 262256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447163250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.2447163250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1711586982 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 33297847 ps |
| CPU time | 3.21 seconds |
| Started | Oct 12 08:51:07 AM UTC 24 |
| Finished | Oct 12 08:51:11 AM UTC 24 |
| Peak memory | 245460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711586982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1711586982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.488512401 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 589975167 ps |
| CPU time | 11.58 seconds |
| Started | Oct 12 08:51:08 AM UTC 24 |
| Finished | Oct 12 08:51:21 AM UTC 24 |
| Peak memory | 235604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488512401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.488512401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.4270315012 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 207334309 ps |
| CPU time | 8.61 seconds |
| Started | Oct 12 08:51:07 AM UTC 24 |
| Finished | Oct 12 08:51:17 AM UTC 24 |
| Peak memory | 247860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270315012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.4270315012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1168789126 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 8518354521 ps |
| CPU time | 43.42 seconds |
| Started | Oct 12 08:51:06 AM UTC 24 |
| Finished | Oct 12 08:51:51 AM UTC 24 |
| Peak memory | 245872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168789126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1168789126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1645540915 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1150643056 ps |
| CPU time | 11.38 seconds |
| Started | Oct 12 08:51:14 AM UTC 24 |
| Finished | Oct 12 08:51:26 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645540915 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.1645540915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.3366651710 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 628883472 ps |
| CPU time | 14.71 seconds |
| Started | Oct 12 08:51:02 AM UTC 24 |
| Finished | Oct 12 08:51:17 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366651710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3366651710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3392891900 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1050559724 ps |
| CPU time | 10.96 seconds |
| Started | Oct 12 08:51:02 AM UTC 24 |
| Finished | Oct 12 08:51:14 AM UTC 24 |
| Peak memory | 228172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392891900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3392891900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.1635134553 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 30094176 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 08:51:05 AM UTC 24 |
| Finished | Oct 12 08:51:07 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635134553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1635134553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3993827426 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 18802805 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:51:02 AM UTC 24 |
| Finished | Oct 12 08:51:04 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993827426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3993827426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.260889754 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 764759332 ps |
| CPU time | 6.31 seconds |
| Started | Oct 12 08:51:08 AM UTC 24 |
| Finished | Oct 12 08:51:16 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260889754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.260889754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.4025628209 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 24191146 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:51:43 AM UTC 24 |
| Finished | Oct 12 08:51:45 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025628209 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.4025628209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2211111759 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 757092872 ps |
| CPU time | 7.23 seconds |
| Started | Oct 12 08:51:31 AM UTC 24 |
| Finished | Oct 12 08:51:40 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211111759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2211111759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.1018179169 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 16329348 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:51:18 AM UTC 24 |
| Finished | Oct 12 08:51:20 AM UTC 24 |
| Peak memory | 216596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018179169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1018179169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.2806453080 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 14326519496 ps |
| CPU time | 94.64 seconds |
| Started | Oct 12 08:51:39 AM UTC 24 |
| Finished | Oct 12 08:53:15 AM UTC 24 |
| Peak memory | 268552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806453080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2806453080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3591185512 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1124561007 ps |
| CPU time | 13.17 seconds |
| Started | Oct 12 08:51:41 AM UTC 24 |
| Finished | Oct 12 08:51:55 AM UTC 24 |
| Peak memory | 245856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591185512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3591185512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.1319514140 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 480792228 ps |
| CPU time | 21.43 seconds |
| Started | Oct 12 08:51:32 AM UTC 24 |
| Finished | Oct 12 08:51:55 AM UTC 24 |
| Peak memory | 252180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319514140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1319514140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.1824878117 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 52476581666 ps |
| CPU time | 138.29 seconds |
| Started | Oct 12 08:51:35 AM UTC 24 |
| Finished | Oct 12 08:53:56 AM UTC 24 |
| Peak memory | 266552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824878117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.1824878117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2622384258 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 666163828 ps |
| CPU time | 10.75 seconds |
| Started | Oct 12 08:51:28 AM UTC 24 |
| Finished | Oct 12 08:51:40 AM UTC 24 |
| Peak memory | 235524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622384258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2622384258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.398346841 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 12971649732 ps |
| CPU time | 66.66 seconds |
| Started | Oct 12 08:51:28 AM UTC 24 |
| Finished | Oct 12 08:52:36 AM UTC 24 |
| Peak memory | 245824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398346841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.398346841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.3124637965 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 667355693 ps |
| CPU time | 6.26 seconds |
| Started | Oct 12 08:51:27 AM UTC 24 |
| Finished | Oct 12 08:51:34 AM UTC 24 |
| Peak memory | 235520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124637965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.3124637965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1975320444 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 212508516 ps |
| CPU time | 3.48 seconds |
| Started | Oct 12 08:51:26 AM UTC 24 |
| Finished | Oct 12 08:51:30 AM UTC 24 |
| Peak memory | 245768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975320444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1975320444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.226682098 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 268404307 ps |
| CPU time | 5.99 seconds |
| Started | Oct 12 08:51:39 AM UTC 24 |
| Finished | Oct 12 08:51:46 AM UTC 24 |
| Peak memory | 234196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226682098 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.226682098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.2212620835 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 235827810163 ps |
| CPU time | 149.39 seconds |
| Started | Oct 12 08:51:41 AM UTC 24 |
| Finished | Oct 12 08:54:13 AM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212620835 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.2212620835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1434947644 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 15542297904 ps |
| CPU time | 7.02 seconds |
| Started | Oct 12 08:51:21 AM UTC 24 |
| Finished | Oct 12 08:51:29 AM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434947644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1434947644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.4103504023 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2066764527 ps |
| CPU time | 8.96 seconds |
| Started | Oct 12 08:51:21 AM UTC 24 |
| Finished | Oct 12 08:51:31 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103504023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4103504023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.3006803244 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 34388792 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 08:51:24 AM UTC 24 |
| Finished | Oct 12 08:51:27 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006803244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3006803244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3649868001 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 55424203 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 08:51:21 AM UTC 24 |
| Finished | Oct 12 08:51:24 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649868001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3649868001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.127759810 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8349025717 ps |
| CPU time | 41.23 seconds |
| Started | Oct 12 08:51:30 AM UTC 24 |
| Finished | Oct 12 08:52:13 AM UTC 24 |
| Peak memory | 235892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127759810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.127759810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.1528359956 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 48946107 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 08:52:06 AM UTC 24 |
| Finished | Oct 12 08:52:08 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528359956 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.1528359956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3235153243 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 71411242 ps |
| CPU time | 2.81 seconds |
| Started | Oct 12 08:51:56 AM UTC 24 |
| Finished | Oct 12 08:52:00 AM UTC 24 |
| Peak memory | 245944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235153243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3235153243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2545758483 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 29925517 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:51:44 AM UTC 24 |
| Finished | Oct 12 08:51:46 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545758483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2545758483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.2237269537 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 14263376128 ps |
| CPU time | 49.43 seconds |
| Started | Oct 12 08:51:59 AM UTC 24 |
| Finished | Oct 12 08:52:50 AM UTC 24 |
| Peak memory | 249968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237269537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2237269537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.2770564793 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 321221827652 ps |
| CPU time | 285.13 seconds |
| Started | Oct 12 08:52:00 AM UTC 24 |
| Finished | Oct 12 08:56:50 AM UTC 24 |
| Peak memory | 282744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770564793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2770564793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1622296393 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 16071008067 ps |
| CPU time | 189.76 seconds |
| Started | Oct 12 08:52:00 AM UTC 24 |
| Finished | Oct 12 08:55:13 AM UTC 24 |
| Peak memory | 264372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622296393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.1622296393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1143504303 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 525920299 ps |
| CPU time | 8.57 seconds |
| Started | Oct 12 08:51:56 AM UTC 24 |
| Finished | Oct 12 08:52:06 AM UTC 24 |
| Peak memory | 262224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143504303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1143504303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.332388979 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 179576749454 ps |
| CPU time | 201.86 seconds |
| Started | Oct 12 08:51:57 AM UTC 24 |
| Finished | Oct 12 08:55:22 AM UTC 24 |
| Peak memory | 264436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332388979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.332388979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2577235216 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2441104405 ps |
| CPU time | 12.12 seconds |
| Started | Oct 12 08:51:53 AM UTC 24 |
| Finished | Oct 12 08:52:06 AM UTC 24 |
| Peak memory | 235824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577235216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2577235216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.1058970617 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 215677266 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 08:51:54 AM UTC 24 |
| Finished | Oct 12 08:51:58 AM UTC 24 |
| Peak memory | 235760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058970617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1058970617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2453160415 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3385675898 ps |
| CPU time | 13.1 seconds |
| Started | Oct 12 08:51:53 AM UTC 24 |
| Finished | Oct 12 08:52:07 AM UTC 24 |
| Peak memory | 245824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453160415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.2453160415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.2159436777 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 14799125218 ps |
| CPU time | 10.27 seconds |
| Started | Oct 12 08:51:51 AM UTC 24 |
| Finished | Oct 12 08:52:03 AM UTC 24 |
| Peak memory | 245884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159436777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2159436777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3495179492 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 758293024 ps |
| CPU time | 6.4 seconds |
| Started | Oct 12 08:51:58 AM UTC 24 |
| Finished | Oct 12 08:52:06 AM UTC 24 |
| Peak memory | 234224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495179492 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.3495179492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.782791771 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 54689055215 ps |
| CPU time | 143.18 seconds |
| Started | Oct 12 08:52:03 AM UTC 24 |
| Finished | Oct 12 08:54:29 AM UTC 24 |
| Peak memory | 252084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782791771 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.782791771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3770081580 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 171716706 ps |
| CPU time | 3.09 seconds |
| Started | Oct 12 08:51:47 AM UTC 24 |
| Finished | Oct 12 08:51:52 AM UTC 24 |
| Peak memory | 228116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770081580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3770081580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.3517825557 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 289944644 ps |
| CPU time | 4.5 seconds |
| Started | Oct 12 08:51:46 AM UTC 24 |
| Finished | Oct 12 08:51:52 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517825557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3517825557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.854024238 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 213306234 ps |
| CPU time | 4.14 seconds |
| Started | Oct 12 08:51:50 AM UTC 24 |
| Finished | Oct 12 08:51:56 AM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854024238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.854024238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1369262022 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 248368365 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 08:51:47 AM UTC 24 |
| Finished | Oct 12 08:51:50 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369262022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1369262022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.3014197717 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 480611614 ps |
| CPU time | 8.66 seconds |
| Started | Oct 12 08:51:55 AM UTC 24 |
| Finished | Oct 12 08:52:05 AM UTC 24 |
| Peak memory | 249972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014197717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3014197717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.1530372960 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 12905931 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:52:34 AM UTC 24 |
| Finished | Oct 12 08:52:36 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530372960 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.1530372960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.756872039 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 35339554 ps |
| CPU time | 3.16 seconds |
| Started | Oct 12 08:52:16 AM UTC 24 |
| Finished | Oct 12 08:52:20 AM UTC 24 |
| Peak memory | 245784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756872039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.756872039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.2347991628 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 22114009 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:52:07 AM UTC 24 |
| Finished | Oct 12 08:52:09 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347991628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2347991628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3191360003 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 3180289711 ps |
| CPU time | 85.46 seconds |
| Started | Oct 12 08:52:21 AM UTC 24 |
| Finished | Oct 12 08:53:48 AM UTC 24 |
| Peak memory | 262360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191360003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3191360003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2443637543 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 18060209481 ps |
| CPU time | 129.79 seconds |
| Started | Oct 12 08:52:21 AM UTC 24 |
| Finished | Oct 12 08:54:33 AM UTC 24 |
| Peak memory | 268480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443637543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.2443637543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.343085573 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3251856979 ps |
| CPU time | 62.01 seconds |
| Started | Oct 12 08:52:16 AM UTC 24 |
| Finished | Oct 12 08:53:19 AM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343085573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.343085573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2056629045 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 29048000525 ps |
| CPU time | 274.95 seconds |
| Started | Oct 12 08:52:17 AM UTC 24 |
| Finished | Oct 12 08:56:55 AM UTC 24 |
| Peak memory | 266344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056629045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2056629045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.2304475162 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 518404364 ps |
| CPU time | 3.5 seconds |
| Started | Oct 12 08:52:11 AM UTC 24 |
| Finished | Oct 12 08:52:16 AM UTC 24 |
| Peak memory | 245800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304475162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2304475162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1394252988 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 12938586538 ps |
| CPU time | 40.51 seconds |
| Started | Oct 12 08:52:13 AM UTC 24 |
| Finished | Oct 12 08:52:55 AM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394252988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1394252988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3878417511 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2759212906 ps |
| CPU time | 5.19 seconds |
| Started | Oct 12 08:52:11 AM UTC 24 |
| Finished | Oct 12 08:52:18 AM UTC 24 |
| Peak memory | 235604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878417511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.3878417511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1624944667 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 37942659241 ps |
| CPU time | 26.58 seconds |
| Started | Oct 12 08:52:10 AM UTC 24 |
| Finished | Oct 12 08:52:38 AM UTC 24 |
| Peak memory | 242716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624944667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1624944667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3488796993 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1234094846 ps |
| CPU time | 8.6 seconds |
| Started | Oct 12 08:52:17 AM UTC 24 |
| Finished | Oct 12 08:52:26 AM UTC 24 |
| Peak memory | 232064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488796993 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.3488796993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.3391287273 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 55532728377 ps |
| CPU time | 507.33 seconds |
| Started | Oct 12 08:52:27 AM UTC 24 |
| Finished | Oct 12 09:01:01 AM UTC 24 |
| Peak memory | 282804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391287273 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.3391287273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.3952077862 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2258428996 ps |
| CPU time | 5.31 seconds |
| Started | Oct 12 08:52:07 AM UTC 24 |
| Finished | Oct 12 08:52:13 AM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952077862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3952077862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1741763635 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 269438845 ps |
| CPU time | 2.44 seconds |
| Started | Oct 12 08:52:07 AM UTC 24 |
| Finished | Oct 12 08:52:10 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741763635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1741763635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2049942643 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1119716288 ps |
| CPU time | 4.71 seconds |
| Started | Oct 12 08:52:09 AM UTC 24 |
| Finished | Oct 12 08:52:15 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049942643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2049942643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.810209470 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 318102642 ps |
| CPU time | 1.56 seconds |
| Started | Oct 12 08:52:08 AM UTC 24 |
| Finished | Oct 12 08:52:11 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810209470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.810209470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.898557027 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 19264872139 ps |
| CPU time | 79.97 seconds |
| Started | Oct 12 08:52:14 AM UTC 24 |
| Finished | Oct 12 08:53:36 AM UTC 24 |
| Peak memory | 245852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898557027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.898557027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.3323730465 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 36313409 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:53:09 AM UTC 24 |
| Finished | Oct 12 08:53:12 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323730465 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.3323730465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.821011085 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5203582444 ps |
| CPU time | 7.49 seconds |
| Started | Oct 12 08:52:52 AM UTC 24 |
| Finished | Oct 12 08:53:01 AM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821011085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.821011085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1202129788 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 56198668 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 08:52:35 AM UTC 24 |
| Finished | Oct 12 08:52:37 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202129788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1202129788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.538728935 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7752629160 ps |
| CPU time | 62.86 seconds |
| Started | Oct 12 08:53:00 AM UTC 24 |
| Finished | Oct 12 08:54:04 AM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538728935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.538728935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3605183613 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 16495938413 ps |
| CPU time | 147.85 seconds |
| Started | Oct 12 08:53:02 AM UTC 24 |
| Finished | Oct 12 08:55:33 AM UTC 24 |
| Peak memory | 276860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605183613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3605183613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.993849582 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 56158796759 ps |
| CPU time | 251.65 seconds |
| Started | Oct 12 08:53:05 AM UTC 24 |
| Finished | Oct 12 08:57:20 AM UTC 24 |
| Peak memory | 264564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993849582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.993849582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.24013720 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1589622693 ps |
| CPU time | 12.62 seconds |
| Started | Oct 12 08:52:52 AM UTC 24 |
| Finished | Oct 12 08:53:06 AM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24013720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.24013720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.107394866 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 16408644263 ps |
| CPU time | 104.58 seconds |
| Started | Oct 12 08:52:57 AM UTC 24 |
| Finished | Oct 12 08:54:43 AM UTC 24 |
| Peak memory | 266360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107394866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.107394866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.343017553 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 182427228 ps |
| CPU time | 3.07 seconds |
| Started | Oct 12 08:52:47 AM UTC 24 |
| Finished | Oct 12 08:52:51 AM UTC 24 |
| Peak memory | 240276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343017553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.343017553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.3074790013 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1457560301 ps |
| CPU time | 8.47 seconds |
| Started | Oct 12 08:52:49 AM UTC 24 |
| Finished | Oct 12 08:52:59 AM UTC 24 |
| Peak memory | 235604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074790013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3074790013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1162378588 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 32916109 ps |
| CPU time | 2.94 seconds |
| Started | Oct 12 08:52:42 AM UTC 24 |
| Finished | Oct 12 08:52:46 AM UTC 24 |
| Peak memory | 245492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162378588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.1162378588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.1776247193 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 176502012854 ps |
| CPU time | 46.95 seconds |
| Started | Oct 12 08:52:42 AM UTC 24 |
| Finished | Oct 12 08:53:30 AM UTC 24 |
| Peak memory | 247924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776247193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1776247193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.179322214 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1824253637 ps |
| CPU time | 8.86 seconds |
| Started | Oct 12 08:52:58 AM UTC 24 |
| Finished | Oct 12 08:53:08 AM UTC 24 |
| Peak memory | 234280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179322214 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.179322214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1595761172 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 11654185995 ps |
| CPU time | 39.64 seconds |
| Started | Oct 12 08:53:07 AM UTC 24 |
| Finished | Oct 12 08:53:48 AM UTC 24 |
| Peak memory | 262328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595761172 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1595761172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.1817222839 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3722337602 ps |
| CPU time | 13.12 seconds |
| Started | Oct 12 08:52:38 AM UTC 24 |
| Finished | Oct 12 08:52:52 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817222839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1817222839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1294057984 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 10734719680 ps |
| CPU time | 24.84 seconds |
| Started | Oct 12 08:52:38 AM UTC 24 |
| Finished | Oct 12 08:53:04 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294057984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1294057984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.66523160 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 32430634 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 08:52:39 AM UTC 24 |
| Finished | Oct 12 08:52:41 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66523160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.66523160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2598423176 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 229846433 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 08:52:39 AM UTC 24 |
| Finished | Oct 12 08:52:41 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598423176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2598423176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.2808490029 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 75707746 ps |
| CPU time | 4.73 seconds |
| Started | Oct 12 08:52:51 AM UTC 24 |
| Finished | Oct 12 08:52:57 AM UTC 24 |
| Peak memory | 245944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808490029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2808490029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.984704723 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 13980869 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 08:53:47 AM UTC 24 |
| Finished | Oct 12 08:53:49 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984704723 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.984704723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1638029530 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 175283430 ps |
| CPU time | 3.52 seconds |
| Started | Oct 12 08:53:36 AM UTC 24 |
| Finished | Oct 12 08:53:41 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638029530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1638029530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3237552174 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 97672316 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 08:53:10 AM UTC 24 |
| Finished | Oct 12 08:53:13 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237552174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3237552174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.3129822105 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1094748216 ps |
| CPU time | 35.85 seconds |
| Started | Oct 12 08:53:42 AM UTC 24 |
| Finished | Oct 12 08:54:19 AM UTC 24 |
| Peak memory | 268528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129822105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3129822105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2606296730 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3267674096 ps |
| CPU time | 13.9 seconds |
| Started | Oct 12 08:53:42 AM UTC 24 |
| Finished | Oct 12 08:53:57 AM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606296730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2606296730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.497351727 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2372138701 ps |
| CPU time | 57.69 seconds |
| Started | Oct 12 08:53:44 AM UTC 24 |
| Finished | Oct 12 08:54:43 AM UTC 24 |
| Peak memory | 245940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497351727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.497351727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1378932486 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1534654634 ps |
| CPU time | 16.24 seconds |
| Started | Oct 12 08:53:36 AM UTC 24 |
| Finished | Oct 12 08:53:54 AM UTC 24 |
| Peak memory | 252144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378932486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1378932486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.542547818 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2423602509 ps |
| CPU time | 27.29 seconds |
| Started | Oct 12 08:53:37 AM UTC 24 |
| Finished | Oct 12 08:54:06 AM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542547818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.542547818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2315487504 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2264909322 ps |
| CPU time | 15.59 seconds |
| Started | Oct 12 08:53:28 AM UTC 24 |
| Finished | Oct 12 08:53:45 AM UTC 24 |
| Peak memory | 235632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315487504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2315487504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.1077866586 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 110545552 ps |
| CPU time | 3.05 seconds |
| Started | Oct 12 08:53:31 AM UTC 24 |
| Finished | Oct 12 08:53:35 AM UTC 24 |
| Peak memory | 245520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077866586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1077866586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.1092116173 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 6261073390 ps |
| CPU time | 16.64 seconds |
| Started | Oct 12 08:53:25 AM UTC 24 |
| Finished | Oct 12 08:53:43 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092116173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.1092116173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.337098978 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1998942360 ps |
| CPU time | 14.58 seconds |
| Started | Oct 12 08:53:20 AM UTC 24 |
| Finished | Oct 12 08:53:36 AM UTC 24 |
| Peak memory | 262168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337098978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.337098978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2829660147 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 229498530 ps |
| CPU time | 6.68 seconds |
| Started | Oct 12 08:53:38 AM UTC 24 |
| Finished | Oct 12 08:53:46 AM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829660147 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2829660147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2186506944 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1944425285 ps |
| CPU time | 42.07 seconds |
| Started | Oct 12 08:53:46 AM UTC 24 |
| Finished | Oct 12 08:54:29 AM UTC 24 |
| Peak memory | 268536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186506944 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2186506944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.175679498 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 8972914146 ps |
| CPU time | 12.24 seconds |
| Started | Oct 12 08:53:13 AM UTC 24 |
| Finished | Oct 12 08:53:27 AM UTC 24 |
| Peak memory | 232404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175679498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.175679498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1891222415 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 7278276746 ps |
| CPU time | 38.76 seconds |
| Started | Oct 12 08:53:12 AM UTC 24 |
| Finished | Oct 12 08:53:53 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891222415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1891222415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.3180271496 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 181638080 ps |
| CPU time | 3.52 seconds |
| Started | Oct 12 08:53:20 AM UTC 24 |
| Finished | Oct 12 08:53:24 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180271496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3180271496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.4127142132 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 41822537 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 08:53:17 AM UTC 24 |
| Finished | Oct 12 08:53:19 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127142132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4127142132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.2164959374 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 383465581 ps |
| CPU time | 3.29 seconds |
| Started | Oct 12 08:53:36 AM UTC 24 |
| Finished | Oct 12 08:53:41 AM UTC 24 |
| Peak memory | 245488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164959374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2164959374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.563721363 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 29342194 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 08:54:08 AM UTC 24 |
| Finished | Oct 12 08:54:10 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563721363 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.563721363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.861789743 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 8006617265 ps |
| CPU time | 22.57 seconds |
| Started | Oct 12 08:53:57 AM UTC 24 |
| Finished | Oct 12 08:54:21 AM UTC 24 |
| Peak memory | 245900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861789743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.861789743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.3155551236 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 17071390 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 08:53:48 AM UTC 24 |
| Finished | Oct 12 08:53:50 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155551236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3155551236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.1496729402 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 118062315641 ps |
| CPU time | 177.6 seconds |
| Started | Oct 12 08:54:04 AM UTC 24 |
| Finished | Oct 12 08:57:05 AM UTC 24 |
| Peak memory | 264524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496729402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1496729402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.3968609833 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 10957807552 ps |
| CPU time | 62.32 seconds |
| Started | Oct 12 08:54:05 AM UTC 24 |
| Finished | Oct 12 08:55:09 AM UTC 24 |
| Peak memory | 262520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968609833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3968609833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.4156979555 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8928535357 ps |
| CPU time | 70.88 seconds |
| Started | Oct 12 08:54:07 AM UTC 24 |
| Finished | Oct 12 08:55:19 AM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156979555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.4156979555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3408217549 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 106060597 ps |
| CPU time | 4.2 seconds |
| Started | Oct 12 08:53:57 AM UTC 24 |
| Finished | Oct 12 08:54:02 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408217549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3408217549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.614495213 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 37051392545 ps |
| CPU time | 235.59 seconds |
| Started | Oct 12 08:53:58 AM UTC 24 |
| Finished | Oct 12 08:57:57 AM UTC 24 |
| Peak memory | 262480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614495213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.614495213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.1728262555 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 75886045828 ps |
| CPU time | 41.47 seconds |
| Started | Oct 12 08:53:55 AM UTC 24 |
| Finished | Oct 12 08:54:38 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728262555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1728262555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1639122908 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 18665321892 ps |
| CPU time | 23.93 seconds |
| Started | Oct 12 08:53:54 AM UTC 24 |
| Finished | Oct 12 08:54:19 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639122908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.1639122908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3999475733 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 5366138756 ps |
| CPU time | 12.72 seconds |
| Started | Oct 12 08:53:52 AM UTC 24 |
| Finished | Oct 12 08:54:06 AM UTC 24 |
| Peak memory | 245896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999475733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3999475733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.3316818634 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 177821632 ps |
| CPU time | 6.11 seconds |
| Started | Oct 12 08:54:03 AM UTC 24 |
| Finished | Oct 12 08:54:10 AM UTC 24 |
| Peak memory | 232328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316818634 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.3316818634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.359171444 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 126052462797 ps |
| CPU time | 338.21 seconds |
| Started | Oct 12 08:54:08 AM UTC 24 |
| Finished | Oct 12 08:59:50 AM UTC 24 |
| Peak memory | 276660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359171444 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.359171444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1904614254 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 6928819853 ps |
| CPU time | 33.14 seconds |
| Started | Oct 12 08:53:49 AM UTC 24 |
| Finished | Oct 12 08:54:24 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904614254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1904614254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1144727982 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 563005626 ps |
| CPU time | 5.59 seconds |
| Started | Oct 12 08:53:49 AM UTC 24 |
| Finished | Oct 12 08:53:56 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144727982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1144727982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.3800611300 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 42404328 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 08:53:51 AM UTC 24 |
| Finished | Oct 12 08:53:55 AM UTC 24 |
| Peak memory | 228176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800611300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3800611300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3815903734 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 67752557 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 08:53:50 AM UTC 24 |
| Finished | Oct 12 08:53:52 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815903734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3815903734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1238087185 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 632869867 ps |
| CPU time | 10.33 seconds |
| Started | Oct 12 08:53:56 AM UTC 24 |
| Finished | Oct 12 08:54:07 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238087185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1238087185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.685008343 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 14696085 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 08:54:30 AM UTC 24 |
| Finished | Oct 12 08:54:33 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685008343 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.685008343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.2367035199 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 733374221 ps |
| CPU time | 13.2 seconds |
| Started | Oct 12 08:54:20 AM UTC 24 |
| Finished | Oct 12 08:54:34 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367035199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2367035199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.345241204 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 158805523 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 08:54:09 AM UTC 24 |
| Finished | Oct 12 08:54:11 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345241204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.345241204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2036085045 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 26849526807 ps |
| CPU time | 132.88 seconds |
| Started | Oct 12 08:54:27 AM UTC 24 |
| Finished | Oct 12 08:56:42 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036085045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2036085045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3243394300 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 70505163024 ps |
| CPU time | 140.24 seconds |
| Started | Oct 12 08:54:28 AM UTC 24 |
| Finished | Oct 12 08:56:51 AM UTC 24 |
| Peak memory | 252304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243394300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.3243394300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.3059269801 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 812933165 ps |
| CPU time | 20.64 seconds |
| Started | Oct 12 08:54:20 AM UTC 24 |
| Finished | Oct 12 08:54:42 AM UTC 24 |
| Peak memory | 248052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059269801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3059269801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.484923177 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 9280312732 ps |
| CPU time | 149.39 seconds |
| Started | Oct 12 08:54:22 AM UTC 24 |
| Finished | Oct 12 08:56:54 AM UTC 24 |
| Peak memory | 284820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484923177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.484923177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.3493818545 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 446167067 ps |
| CPU time | 8.93 seconds |
| Started | Oct 12 08:54:17 AM UTC 24 |
| Finished | Oct 12 08:54:27 AM UTC 24 |
| Peak memory | 235560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493818545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3493818545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.391809510 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 11568995159 ps |
| CPU time | 30.2 seconds |
| Started | Oct 12 08:54:20 AM UTC 24 |
| Finished | Oct 12 08:54:51 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391809510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.391809510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.1141522650 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 710739565 ps |
| CPU time | 10.35 seconds |
| Started | Oct 12 08:54:15 AM UTC 24 |
| Finished | Oct 12 08:54:27 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141522650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.1141522650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.4095649420 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 282655580 ps |
| CPU time | 3.08 seconds |
| Started | Oct 12 08:54:14 AM UTC 24 |
| Finished | Oct 12 08:54:18 AM UTC 24 |
| Peak memory | 230012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095649420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4095649420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.4153927290 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 251721519 ps |
| CPU time | 7.86 seconds |
| Started | Oct 12 08:54:25 AM UTC 24 |
| Finished | Oct 12 08:54:34 AM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153927290 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.4153927290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.4083732402 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 15012656651 ps |
| CPU time | 24.79 seconds |
| Started | Oct 12 08:54:30 AM UTC 24 |
| Finished | Oct 12 08:54:57 AM UTC 24 |
| Peak memory | 252152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083732402 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.4083732402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.161729610 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 10512869693 ps |
| CPU time | 52.77 seconds |
| Started | Oct 12 08:54:11 AM UTC 24 |
| Finished | Oct 12 08:55:05 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161729610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.161729610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3245272720 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3936859471 ps |
| CPU time | 21.31 seconds |
| Started | Oct 12 08:54:11 AM UTC 24 |
| Finished | Oct 12 08:54:33 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245272720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3245272720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.2422951712 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 252409730 ps |
| CPU time | 1.92 seconds |
| Started | Oct 12 08:54:14 AM UTC 24 |
| Finished | Oct 12 08:54:17 AM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422951712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2422951712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.2597221668 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 18284965 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:54:12 AM UTC 24 |
| Finished | Oct 12 08:54:14 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597221668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2597221668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.2266186023 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 496457682 ps |
| CPU time | 3.91 seconds |
| Started | Oct 12 08:54:20 AM UTC 24 |
| Finished | Oct 12 08:54:25 AM UTC 24 |
| Peak memory | 235564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266186023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2266186023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.3761730987 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 20163976 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 08:54:52 AM UTC 24 |
| Finished | Oct 12 08:54:55 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761730987 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.3761730987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.2340130571 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 3738960862 ps |
| CPU time | 18.01 seconds |
| Started | Oct 12 08:54:39 AM UTC 24 |
| Finished | Oct 12 08:54:59 AM UTC 24 |
| Peak memory | 235632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340130571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2340130571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.353850982 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 14538501 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 08:54:34 AM UTC 24 |
| Finished | Oct 12 08:54:36 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353850982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.353850982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.3018496500 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 27946542677 ps |
| CPU time | 125.87 seconds |
| Started | Oct 12 08:54:47 AM UTC 24 |
| Finished | Oct 12 08:56:56 AM UTC 24 |
| Peak memory | 264300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018496500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3018496500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1586511097 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 5780812451 ps |
| CPU time | 81.13 seconds |
| Started | Oct 12 08:54:47 AM UTC 24 |
| Finished | Oct 12 08:56:11 AM UTC 24 |
| Peak memory | 268468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586511097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1586511097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1110173230 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4651134934 ps |
| CPU time | 59.12 seconds |
| Started | Oct 12 08:54:51 AM UTC 24 |
| Finished | Oct 12 08:55:52 AM UTC 24 |
| Peak memory | 262304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110173230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.1110173230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.160675785 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 547012815 ps |
| CPU time | 6.11 seconds |
| Started | Oct 12 08:54:43 AM UTC 24 |
| Finished | Oct 12 08:54:50 AM UTC 24 |
| Peak memory | 235596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160675785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.160675785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.2034831670 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 45633730750 ps |
| CPU time | 228.06 seconds |
| Started | Oct 12 08:54:44 AM UTC 24 |
| Finished | Oct 12 08:58:35 AM UTC 24 |
| Peak memory | 262264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034831670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.2034831670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.3071077654 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 5618802936 ps |
| CPU time | 22.77 seconds |
| Started | Oct 12 08:54:38 AM UTC 24 |
| Finished | Oct 12 08:55:02 AM UTC 24 |
| Peak memory | 246068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071077654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3071077654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.3264175626 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 9713348062 ps |
| CPU time | 36.13 seconds |
| Started | Oct 12 08:54:38 AM UTC 24 |
| Finished | Oct 12 08:55:16 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264175626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3264175626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1113101044 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 880755998 ps |
| CPU time | 8.33 seconds |
| Started | Oct 12 08:54:37 AM UTC 24 |
| Finished | Oct 12 08:54:46 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113101044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.1113101044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3186540875 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 5321909913 ps |
| CPU time | 22.28 seconds |
| Started | Oct 12 08:54:37 AM UTC 24 |
| Finished | Oct 12 08:55:01 AM UTC 24 |
| Peak memory | 235536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186540875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3186540875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2410004437 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3439285606 ps |
| CPU time | 11.73 seconds |
| Started | Oct 12 08:54:44 AM UTC 24 |
| Finished | Oct 12 08:54:57 AM UTC 24 |
| Peak memory | 234276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410004437 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.2410004437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3186141948 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 297896166 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 08:54:52 AM UTC 24 |
| Finished | Oct 12 08:54:55 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186141948 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3186141948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.906275138 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 3477604180 ps |
| CPU time | 19.33 seconds |
| Started | Oct 12 08:54:35 AM UTC 24 |
| Finished | Oct 12 08:54:55 AM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906275138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.906275138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.2167471560 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 325505418 ps |
| CPU time | 2.58 seconds |
| Started | Oct 12 08:54:35 AM UTC 24 |
| Finished | Oct 12 08:54:38 AM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167471560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2167471560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.666890156 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 52695873 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 08:54:35 AM UTC 24 |
| Finished | Oct 12 08:54:38 AM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666890156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.666890156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2880917991 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 71285356 ps |
| CPU time | 1.45 seconds |
| Started | Oct 12 08:54:35 AM UTC 24 |
| Finished | Oct 12 08:54:37 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880917991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2880917991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.276014292 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 10103884906 ps |
| CPU time | 12.76 seconds |
| Started | Oct 12 08:54:38 AM UTC 24 |
| Finished | Oct 12 08:54:52 AM UTC 24 |
| Peak memory | 235608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276014292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.276014292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3954485765 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 13924560 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:41:53 AM UTC 24 |
| Finished | Oct 12 08:41:55 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954485765 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3954485765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2677988478 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 319807226 ps |
| CPU time | 8.69 seconds |
| Started | Oct 12 08:41:39 AM UTC 24 |
| Finished | Oct 12 08:41:48 AM UTC 24 |
| Peak memory | 235504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677988478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2677988478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.178514390 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 79944459 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:41:15 AM UTC 24 |
| Finished | Oct 12 08:41:18 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178514390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.178514390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3338647770 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 6368970498 ps |
| CPU time | 128.25 seconds |
| Started | Oct 12 08:41:43 AM UTC 24 |
| Finished | Oct 12 08:43:54 AM UTC 24 |
| Peak memory | 262460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338647770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3338647770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1929875415 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 7587526453 ps |
| CPU time | 73.59 seconds |
| Started | Oct 12 08:41:47 AM UTC 24 |
| Finished | Oct 12 08:43:03 AM UTC 24 |
| Peak memory | 235660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929875415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.1929875415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.16056764 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 689473150 ps |
| CPU time | 5.8 seconds |
| Started | Oct 12 08:41:40 AM UTC 24 |
| Finished | Oct 12 08:41:47 AM UTC 24 |
| Peak memory | 245832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16056764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.16056764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.216383289 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 9860769091 ps |
| CPU time | 34.29 seconds |
| Started | Oct 12 08:41:28 AM UTC 24 |
| Finished | Oct 12 08:42:04 AM UTC 24 |
| Peak memory | 246044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216383289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.216383289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3053394791 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4929833459 ps |
| CPU time | 17.26 seconds |
| Started | Oct 12 08:41:30 AM UTC 24 |
| Finished | Oct 12 08:41:49 AM UTC 24 |
| Peak memory | 249988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053394791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3053394791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2495053285 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1847527057 ps |
| CPU time | 10.01 seconds |
| Started | Oct 12 08:41:28 AM UTC 24 |
| Finished | Oct 12 08:41:39 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495053285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.2495053285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3818240952 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 272424712 ps |
| CPU time | 11.59 seconds |
| Started | Oct 12 08:41:28 AM UTC 24 |
| Finished | Oct 12 08:41:41 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818240952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3818240952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3433459221 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4979521165 ps |
| CPU time | 10.06 seconds |
| Started | Oct 12 08:41:42 AM UTC 24 |
| Finished | Oct 12 08:41:53 AM UTC 24 |
| Peak memory | 234256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433459221 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.3433459221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2199950093 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 139413778 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 08:41:50 AM UTC 24 |
| Finished | Oct 12 08:41:53 AM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199950093 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2199950093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.321769076 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 39630509409 ps |
| CPU time | 104.6 seconds |
| Started | Oct 12 08:41:49 AM UTC 24 |
| Finished | Oct 12 08:43:36 AM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321769076 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.321769076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1706108252 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 835676479 ps |
| CPU time | 6.41 seconds |
| Started | Oct 12 08:41:20 AM UTC 24 |
| Finished | Oct 12 08:41:27 AM UTC 24 |
| Peak memory | 230288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706108252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1706108252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1666540062 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1719446504 ps |
| CPU time | 6.34 seconds |
| Started | Oct 12 08:41:20 AM UTC 24 |
| Finished | Oct 12 08:41:27 AM UTC 24 |
| Peak memory | 228264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666540062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1666540062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1036947333 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 27792375 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 08:41:25 AM UTC 24 |
| Finished | Oct 12 08:41:27 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036947333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1036947333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2932997633 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 72409359 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 08:41:22 AM UTC 24 |
| Finished | Oct 12 08:41:24 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932997633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2932997633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1355797548 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 132703945 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 08:41:34 AM UTC 24 |
| Finished | Oct 12 08:41:38 AM UTC 24 |
| Peak memory | 235604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355797548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1355797548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.1489564815 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 12918124 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:55:06 AM UTC 24 |
| Finished | Oct 12 08:55:09 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489564815 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.1489564815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.670589925 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3810796175 ps |
| CPU time | 28.6 seconds |
| Started | Oct 12 08:55:00 AM UTC 24 |
| Finished | Oct 12 08:55:31 AM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670589925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.670589925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.2562277315 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 23861051 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:54:53 AM UTC 24 |
| Finished | Oct 12 08:54:56 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562277315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2562277315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.3500731568 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3993492492 ps |
| CPU time | 33.29 seconds |
| Started | Oct 12 08:55:03 AM UTC 24 |
| Finished | Oct 12 08:55:38 AM UTC 24 |
| Peak memory | 262248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500731568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3500731568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1870378129 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 158023500045 ps |
| CPU time | 102.51 seconds |
| Started | Oct 12 08:55:04 AM UTC 24 |
| Finished | Oct 12 08:56:49 AM UTC 24 |
| Peak memory | 262432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870378129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1870378129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.670601249 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 7471367272 ps |
| CPU time | 67.25 seconds |
| Started | Oct 12 08:55:04 AM UTC 24 |
| Finished | Oct 12 08:56:13 AM UTC 24 |
| Peak memory | 278928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670601249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.670601249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.1544808547 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 77805265 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 08:55:00 AM UTC 24 |
| Finished | Oct 12 08:55:05 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544808547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1544808547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.1199360092 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 32623555930 ps |
| CPU time | 230.14 seconds |
| Started | Oct 12 08:55:02 AM UTC 24 |
| Finished | Oct 12 08:58:55 AM UTC 24 |
| Peak memory | 262460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199360092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.1199360092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.3738798057 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 813025765 ps |
| CPU time | 6.36 seconds |
| Started | Oct 12 08:54:58 AM UTC 24 |
| Finished | Oct 12 08:55:06 AM UTC 24 |
| Peak memory | 245828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738798057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3738798057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.2896057791 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 335841503 ps |
| CPU time | 3.07 seconds |
| Started | Oct 12 08:54:59 AM UTC 24 |
| Finished | Oct 12 08:55:03 AM UTC 24 |
| Peak memory | 235604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896057791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2896057791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1031275311 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 203303525 ps |
| CPU time | 3.66 seconds |
| Started | Oct 12 08:54:58 AM UTC 24 |
| Finished | Oct 12 08:55:03 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031275311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1031275311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3687904138 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 441732887 ps |
| CPU time | 7.09 seconds |
| Started | Oct 12 08:54:57 AM UTC 24 |
| Finished | Oct 12 08:55:05 AM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687904138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3687904138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.804441966 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 140438384 ps |
| CPU time | 5.41 seconds |
| Started | Oct 12 08:55:02 AM UTC 24 |
| Finished | Oct 12 08:55:08 AM UTC 24 |
| Peak memory | 230288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804441966 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.804441966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.4207214492 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 6803377255 ps |
| CPU time | 83.98 seconds |
| Started | Oct 12 08:55:05 AM UTC 24 |
| Finished | Oct 12 08:56:31 AM UTC 24 |
| Peak memory | 268500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207214492 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.4207214492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3094012300 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 6854432059 ps |
| CPU time | 26.37 seconds |
| Started | Oct 12 08:54:57 AM UTC 24 |
| Finished | Oct 12 08:55:25 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094012300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3094012300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.1648465672 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2629336936 ps |
| CPU time | 17.04 seconds |
| Started | Oct 12 08:54:56 AM UTC 24 |
| Finished | Oct 12 08:55:14 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648465672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1648465672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.1397125972 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 24623768 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 08:54:57 AM UTC 24 |
| Finished | Oct 12 08:54:59 AM UTC 24 |
| Peak memory | 216480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397125972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1397125972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1897382681 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 31709226 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 08:54:57 AM UTC 24 |
| Finished | Oct 12 08:54:59 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897382681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1897382681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.3637081874 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 152350198 ps |
| CPU time | 3.61 seconds |
| Started | Oct 12 08:54:59 AM UTC 24 |
| Finished | Oct 12 08:55:04 AM UTC 24 |
| Peak memory | 235460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637081874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3637081874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.1612101791 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 29528731 ps |
| CPU time | 0.93 seconds |
| Started | Oct 12 08:55:22 AM UTC 24 |
| Finished | Oct 12 08:55:24 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612101791 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.1612101791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1899308275 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 38004564 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 08:55:14 AM UTC 24 |
| Finished | Oct 12 08:55:18 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899308275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1899308275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.4230146457 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 29765677 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:55:06 AM UTC 24 |
| Finished | Oct 12 08:55:09 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230146457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4230146457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.1625954035 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 59681991 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 08:55:19 AM UTC 24 |
| Finished | Oct 12 08:55:21 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625954035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1625954035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1994855066 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 167656762758 ps |
| CPU time | 403.69 seconds |
| Started | Oct 12 08:55:20 AM UTC 24 |
| Finished | Oct 12 09:02:09 AM UTC 24 |
| Peak memory | 264372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994855066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1994855066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.4120849213 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 104048710801 ps |
| CPU time | 520.91 seconds |
| Started | Oct 12 08:55:20 AM UTC 24 |
| Finished | Oct 12 09:04:07 AM UTC 24 |
| Peak memory | 268460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120849213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.4120849213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.2392337043 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1747912629 ps |
| CPU time | 11.77 seconds |
| Started | Oct 12 08:55:15 AM UTC 24 |
| Finished | Oct 12 08:55:28 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392337043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2392337043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.238541572 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 13657846692 ps |
| CPU time | 98.89 seconds |
| Started | Oct 12 08:55:16 AM UTC 24 |
| Finished | Oct 12 08:56:57 AM UTC 24 |
| Peak memory | 252216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238541572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.238541572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.611859597 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 799898484 ps |
| CPU time | 4.82 seconds |
| Started | Oct 12 08:55:11 AM UTC 24 |
| Finished | Oct 12 08:55:17 AM UTC 24 |
| Peak memory | 245976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611859597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.611859597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.2049242668 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1016648586 ps |
| CPU time | 14.9 seconds |
| Started | Oct 12 08:55:12 AM UTC 24 |
| Finished | Oct 12 08:55:28 AM UTC 24 |
| Peak memory | 245784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049242668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2049242668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1317480856 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 3449010459 ps |
| CPU time | 6.72 seconds |
| Started | Oct 12 08:55:11 AM UTC 24 |
| Finished | Oct 12 08:55:19 AM UTC 24 |
| Peak memory | 235776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317480856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1317480856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.3955014107 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 291441237 ps |
| CPU time | 7.74 seconds |
| Started | Oct 12 08:55:10 AM UTC 24 |
| Finished | Oct 12 08:55:19 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955014107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3955014107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.2988896228 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 363418785 ps |
| CPU time | 6.12 seconds |
| Started | Oct 12 08:55:17 AM UTC 24 |
| Finished | Oct 12 08:55:25 AM UTC 24 |
| Peak memory | 234152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988896228 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.2988896228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.1777392722 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 44098741499 ps |
| CPU time | 430.05 seconds |
| Started | Oct 12 08:55:21 AM UTC 24 |
| Finished | Oct 12 09:02:37 AM UTC 24 |
| Peak memory | 268492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777392722 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.1777392722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.626020632 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 22292840490 ps |
| CPU time | 31.16 seconds |
| Started | Oct 12 08:55:06 AM UTC 24 |
| Finished | Oct 12 08:55:39 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626020632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.626020632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.358358598 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 218233901 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 08:55:06 AM UTC 24 |
| Finished | Oct 12 08:55:10 AM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358358598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.358358598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.4019033213 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 487246774 ps |
| CPU time | 2.52 seconds |
| Started | Oct 12 08:55:10 AM UTC 24 |
| Finished | Oct 12 08:55:13 AM UTC 24 |
| Peak memory | 228252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019033213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4019033213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.3161526553 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 21350764 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 08:55:08 AM UTC 24 |
| Finished | Oct 12 08:55:11 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161526553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3161526553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.21508102 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2966820660 ps |
| CPU time | 19.64 seconds |
| Started | Oct 12 08:55:14 AM UTC 24 |
| Finished | Oct 12 08:55:35 AM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21508102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.21508102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.2270664470 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 14216442 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 08:55:41 AM UTC 24 |
| Finished | Oct 12 08:55:43 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270664470 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.2270664470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3614755825 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3482870652 ps |
| CPU time | 12.04 seconds |
| Started | Oct 12 08:55:32 AM UTC 24 |
| Finished | Oct 12 08:55:45 AM UTC 24 |
| Peak memory | 245940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614755825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3614755825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.2769429117 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 14316814 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 08:55:23 AM UTC 24 |
| Finished | Oct 12 08:55:25 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769429117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2769429117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.3445495192 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2548988280 ps |
| CPU time | 27.44 seconds |
| Started | Oct 12 08:55:36 AM UTC 24 |
| Finished | Oct 12 08:56:05 AM UTC 24 |
| Peak memory | 264316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445495192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3445495192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1021823894 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 13141191013 ps |
| CPU time | 125 seconds |
| Started | Oct 12 08:55:37 AM UTC 24 |
| Finished | Oct 12 08:57:45 AM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021823894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1021823894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2290740417 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 4286248421 ps |
| CPU time | 118.48 seconds |
| Started | Oct 12 08:55:38 AM UTC 24 |
| Finished | Oct 12 08:57:39 AM UTC 24 |
| Peak memory | 278964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290740417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.2290740417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.110596341 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 41093121183 ps |
| CPU time | 47.9 seconds |
| Started | Oct 12 08:55:35 AM UTC 24 |
| Finished | Oct 12 08:56:25 AM UTC 24 |
| Peak memory | 264532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110596341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.110596341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.1386621741 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 516969879 ps |
| CPU time | 4.78 seconds |
| Started | Oct 12 08:55:29 AM UTC 24 |
| Finished | Oct 12 08:55:35 AM UTC 24 |
| Peak memory | 244732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386621741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1386621741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.1297551144 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1574531298 ps |
| CPU time | 9.77 seconds |
| Started | Oct 12 08:55:30 AM UTC 24 |
| Finished | Oct 12 08:55:41 AM UTC 24 |
| Peak memory | 262416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297551144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1297551144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.4258498512 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2170012142 ps |
| CPU time | 6.19 seconds |
| Started | Oct 12 08:55:29 AM UTC 24 |
| Finished | Oct 12 08:55:36 AM UTC 24 |
| Peak memory | 245744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258498512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.4258498512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.3440674449 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1307338780 ps |
| CPU time | 15.88 seconds |
| Started | Oct 12 08:55:26 AM UTC 24 |
| Finished | Oct 12 08:55:44 AM UTC 24 |
| Peak memory | 246004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440674449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3440674449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1082395682 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2072814598 ps |
| CPU time | 12.81 seconds |
| Started | Oct 12 08:55:36 AM UTC 24 |
| Finished | Oct 12 08:55:50 AM UTC 24 |
| Peak memory | 234144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082395682 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.1082395682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.3736767469 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2595268156 ps |
| CPU time | 13.93 seconds |
| Started | Oct 12 08:55:25 AM UTC 24 |
| Finished | Oct 12 08:55:40 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736767469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3736767469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.9444770 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1755995906 ps |
| CPU time | 9.92 seconds |
| Started | Oct 12 08:55:25 AM UTC 24 |
| Finished | Oct 12 08:55:36 AM UTC 24 |
| Peak memory | 228116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9444770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.9444770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.2679350959 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 45543340 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 08:55:26 AM UTC 24 |
| Finished | Oct 12 08:55:29 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679350959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2679350959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1109048180 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 70151523 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 08:55:25 AM UTC 24 |
| Finished | Oct 12 08:55:28 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109048180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1109048180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.394613116 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 531369275 ps |
| CPU time | 9.07 seconds |
| Started | Oct 12 08:55:30 AM UTC 24 |
| Finished | Oct 12 08:55:40 AM UTC 24 |
| Peak memory | 245832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394613116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.394613116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.581876323 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 13125746 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 08:56:06 AM UTC 24 |
| Finished | Oct 12 08:56:08 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581876323 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.581876323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.403474643 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4002997356 ps |
| CPU time | 16.33 seconds |
| Started | Oct 12 08:55:52 AM UTC 24 |
| Finished | Oct 12 08:56:09 AM UTC 24 |
| Peak memory | 235608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403474643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.403474643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.1374800890 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 48929056 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 08:55:42 AM UTC 24 |
| Finished | Oct 12 08:55:44 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374800890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1374800890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.4279062261 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 13188550014 ps |
| CPU time | 130.8 seconds |
| Started | Oct 12 08:55:54 AM UTC 24 |
| Finished | Oct 12 08:58:07 AM UTC 24 |
| Peak memory | 268420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279062261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4279062261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1581598987 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 9233452105 ps |
| CPU time | 91.77 seconds |
| Started | Oct 12 08:55:55 AM UTC 24 |
| Finished | Oct 12 08:57:29 AM UTC 24 |
| Peak memory | 268512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581598987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1581598987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3860513562 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 7371687982 ps |
| CPU time | 115.42 seconds |
| Started | Oct 12 08:56:00 AM UTC 24 |
| Finished | Oct 12 08:57:58 AM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860513562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.3860513562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.3229014475 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 15586946489 ps |
| CPU time | 46.46 seconds |
| Started | Oct 12 08:55:53 AM UTC 24 |
| Finished | Oct 12 08:56:41 AM UTC 24 |
| Peak memory | 245932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229014475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3229014475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1573260908 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 132116514811 ps |
| CPU time | 357.98 seconds |
| Started | Oct 12 08:55:53 AM UTC 24 |
| Finished | Oct 12 09:01:56 AM UTC 24 |
| Peak memory | 268392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573260908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.1573260908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.2263934257 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 400951015 ps |
| CPU time | 3.23 seconds |
| Started | Oct 12 08:55:48 AM UTC 24 |
| Finished | Oct 12 08:55:53 AM UTC 24 |
| Peak memory | 235436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263934257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2263934257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3089088758 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 514415785 ps |
| CPU time | 3.24 seconds |
| Started | Oct 12 08:55:49 AM UTC 24 |
| Finished | Oct 12 08:55:53 AM UTC 24 |
| Peak memory | 235244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089088758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3089088758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.2078989170 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1108292243 ps |
| CPU time | 4.49 seconds |
| Started | Oct 12 08:55:46 AM UTC 24 |
| Finished | Oct 12 08:55:52 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078989170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.2078989170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.248186354 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 296787365 ps |
| CPU time | 3.49 seconds |
| Started | Oct 12 08:55:46 AM UTC 24 |
| Finished | Oct 12 08:55:51 AM UTC 24 |
| Peak memory | 235460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248186354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.248186354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.25121905 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1826690068 ps |
| CPU time | 14.79 seconds |
| Started | Oct 12 08:55:54 AM UTC 24 |
| Finished | Oct 12 08:56:10 AM UTC 24 |
| Peak memory | 234192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25121905 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.25121905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1139083366 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 65926668552 ps |
| CPU time | 210.65 seconds |
| Started | Oct 12 08:56:05 AM UTC 24 |
| Finished | Oct 12 08:59:39 AM UTC 24 |
| Peak memory | 285036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139083366 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1139083366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.1400926168 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1878814422 ps |
| CPU time | 37.84 seconds |
| Started | Oct 12 08:55:44 AM UTC 24 |
| Finished | Oct 12 08:56:23 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400926168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1400926168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1148683312 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 15787210912 ps |
| CPU time | 21.61 seconds |
| Started | Oct 12 08:55:42 AM UTC 24 |
| Finished | Oct 12 08:56:05 AM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148683312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1148683312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.52266090 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 28947222 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 08:55:45 AM UTC 24 |
| Finished | Oct 12 08:55:48 AM UTC 24 |
| Peak memory | 228204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52266090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.52266090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3415248306 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 67959708 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 08:55:45 AM UTC 24 |
| Finished | Oct 12 08:55:47 AM UTC 24 |
| Peak memory | 216476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415248306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3415248306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.484153245 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 25269500687 ps |
| CPU time | 40.33 seconds |
| Started | Oct 12 08:55:52 AM UTC 24 |
| Finished | Oct 12 08:56:33 AM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484153245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.484153245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.4252127813 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 47398922 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 08:56:31 AM UTC 24 |
| Finished | Oct 12 08:56:33 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252127813 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.4252127813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3145940736 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1585796690 ps |
| CPU time | 16.02 seconds |
| Started | Oct 12 08:56:22 AM UTC 24 |
| Finished | Oct 12 08:56:40 AM UTC 24 |
| Peak memory | 245512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145940736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3145940736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.3158426230 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 20042508 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 08:56:09 AM UTC 24 |
| Finished | Oct 12 08:56:12 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158426230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3158426230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.3494120921 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 9622073578 ps |
| CPU time | 92.21 seconds |
| Started | Oct 12 08:56:26 AM UTC 24 |
| Finished | Oct 12 08:58:00 AM UTC 24 |
| Peak memory | 268420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494120921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3494120921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.668539451 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 18246447011 ps |
| CPU time | 95.44 seconds |
| Started | Oct 12 08:56:28 AM UTC 24 |
| Finished | Oct 12 08:58:05 AM UTC 24 |
| Peak memory | 278716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668539451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.668539451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.4115186079 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 774202298 ps |
| CPU time | 6.84 seconds |
| Started | Oct 12 08:56:22 AM UTC 24 |
| Finished | Oct 12 08:56:30 AM UTC 24 |
| Peak memory | 245644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115186079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4115186079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.700682896 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 53774736473 ps |
| CPU time | 203.29 seconds |
| Started | Oct 12 08:56:22 AM UTC 24 |
| Finished | Oct 12 08:59:49 AM UTC 24 |
| Peak memory | 278860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700682896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.700682896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.3722396159 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 147010202 ps |
| CPU time | 5.66 seconds |
| Started | Oct 12 08:56:15 AM UTC 24 |
| Finished | Oct 12 08:56:22 AM UTC 24 |
| Peak memory | 230292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722396159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3722396159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.840432758 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 370814553 ps |
| CPU time | 8.87 seconds |
| Started | Oct 12 08:56:16 AM UTC 24 |
| Finished | Oct 12 08:56:26 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840432758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.840432758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1972273984 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 14159932701 ps |
| CPU time | 11.8 seconds |
| Started | Oct 12 08:56:14 AM UTC 24 |
| Finished | Oct 12 08:56:27 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972273984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.1972273984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.4065588656 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 600229044 ps |
| CPU time | 6.58 seconds |
| Started | Oct 12 08:56:14 AM UTC 24 |
| Finished | Oct 12 08:56:22 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065588656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4065588656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.338781197 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 272018246 ps |
| CPU time | 5.41 seconds |
| Started | Oct 12 08:56:24 AM UTC 24 |
| Finished | Oct 12 08:56:30 AM UTC 24 |
| Peak memory | 230228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338781197 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.338781197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.1265477544 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 11938146844 ps |
| CPU time | 92.8 seconds |
| Started | Oct 12 08:56:31 AM UTC 24 |
| Finished | Oct 12 08:58:06 AM UTC 24 |
| Peak memory | 278676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265477544 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.1265477544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.1819051146 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 33658994 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 08:56:11 AM UTC 24 |
| Finished | Oct 12 08:56:13 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819051146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1819051146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3679700112 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 296259608 ps |
| CPU time | 3.66 seconds |
| Started | Oct 12 08:56:11 AM UTC 24 |
| Finished | Oct 12 08:56:15 AM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679700112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3679700112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.1309787142 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 55661150 ps |
| CPU time | 1.57 seconds |
| Started | Oct 12 08:56:13 AM UTC 24 |
| Finished | Oct 12 08:56:15 AM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309787142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1309787142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2959318025 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 16706089 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 08:56:12 AM UTC 24 |
| Finished | Oct 12 08:56:14 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959318025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2959318025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.1153451646 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 8133506223 ps |
| CPU time | 44.58 seconds |
| Started | Oct 12 08:56:16 AM UTC 24 |
| Finished | Oct 12 08:57:02 AM UTC 24 |
| Peak memory | 262224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153451646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1153451646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2588128603 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 39090543 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 08:56:52 AM UTC 24 |
| Finished | Oct 12 08:56:54 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588128603 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.2588128603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1968941017 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 94857595 ps |
| CPU time | 4.39 seconds |
| Started | Oct 12 08:56:45 AM UTC 24 |
| Finished | Oct 12 08:56:51 AM UTC 24 |
| Peak memory | 245744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968941017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1968941017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.4036902493 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 107686908 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 08:56:32 AM UTC 24 |
| Finished | Oct 12 08:56:35 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036902493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4036902493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2228119826 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4605751296 ps |
| CPU time | 16.46 seconds |
| Started | Oct 12 08:56:51 AM UTC 24 |
| Finished | Oct 12 08:57:08 AM UTC 24 |
| Peak memory | 235632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228119826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2228119826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2128221390 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 2391340551 ps |
| CPU time | 36.76 seconds |
| Started | Oct 12 08:56:51 AM UTC 24 |
| Finished | Oct 12 08:57:29 AM UTC 24 |
| Peak memory | 247988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128221390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2128221390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.459408109 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 8198149488 ps |
| CPU time | 52.09 seconds |
| Started | Oct 12 08:56:46 AM UTC 24 |
| Finished | Oct 12 08:57:40 AM UTC 24 |
| Peak memory | 252236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459408109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.459408109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.1460729875 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 10205313876 ps |
| CPU time | 85.65 seconds |
| Started | Oct 12 08:56:48 AM UTC 24 |
| Finished | Oct 12 08:58:16 AM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460729875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.1460729875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3433319067 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 388708786 ps |
| CPU time | 6.32 seconds |
| Started | Oct 12 08:56:42 AM UTC 24 |
| Finished | Oct 12 08:56:49 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433319067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3433319067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.2158471818 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5024301997 ps |
| CPU time | 73.46 seconds |
| Started | Oct 12 08:56:43 AM UTC 24 |
| Finished | Oct 12 08:57:58 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158471818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2158471818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2345357721 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 76964347 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 08:56:42 AM UTC 24 |
| Finished | Oct 12 08:56:45 AM UTC 24 |
| Peak memory | 234840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345357721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2345357721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.1412304555 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 148687368 ps |
| CPU time | 2.53 seconds |
| Started | Oct 12 08:56:41 AM UTC 24 |
| Finished | Oct 12 08:56:44 AM UTC 24 |
| Peak memory | 235376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412304555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1412304555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3794632787 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 78376346 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 08:56:49 AM UTC 24 |
| Finished | Oct 12 08:56:55 AM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794632787 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.3794632787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2685384921 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 27198152765 ps |
| CPU time | 323.11 seconds |
| Started | Oct 12 08:56:52 AM UTC 24 |
| Finished | Oct 12 09:02:20 AM UTC 24 |
| Peak memory | 285012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685384921 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2685384921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.600251988 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 29226711807 ps |
| CPU time | 59.81 seconds |
| Started | Oct 12 08:56:34 AM UTC 24 |
| Finished | Oct 12 08:57:36 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600251988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.600251988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3816776762 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1789311513 ps |
| CPU time | 5.89 seconds |
| Started | Oct 12 08:56:34 AM UTC 24 |
| Finished | Oct 12 08:56:41 AM UTC 24 |
| Peak memory | 228168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816776762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3816776762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.836364557 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 136733772 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 08:56:38 AM UTC 24 |
| Finished | Oct 12 08:56:41 AM UTC 24 |
| Peak memory | 228408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836364557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.836364557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3520306146 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 35691839 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 08:56:35 AM UTC 24 |
| Finished | Oct 12 08:56:37 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520306146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3520306146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.2812532665 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 100531024 ps |
| CPU time | 3.04 seconds |
| Started | Oct 12 08:56:43 AM UTC 24 |
| Finished | Oct 12 08:56:47 AM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812532665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2812532665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.3976432521 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 11798969 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:57:16 AM UTC 24 |
| Finished | Oct 12 08:57:18 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976432521 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.3976432521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2636266871 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1144143783 ps |
| CPU time | 9.09 seconds |
| Started | Oct 12 08:57:03 AM UTC 24 |
| Finished | Oct 12 08:57:13 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636266871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2636266871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.2119575698 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 30553215 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 08:56:55 AM UTC 24 |
| Finished | Oct 12 08:56:57 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119575698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2119575698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.105712299 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4333689223 ps |
| CPU time | 21.19 seconds |
| Started | Oct 12 08:57:09 AM UTC 24 |
| Finished | Oct 12 08:57:32 AM UTC 24 |
| Peak memory | 247916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105712299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.105712299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2941580507 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 9495647828 ps |
| CPU time | 187.81 seconds |
| Started | Oct 12 08:57:15 AM UTC 24 |
| Finished | Oct 12 09:00:25 AM UTC 24 |
| Peak memory | 280736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941580507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2941580507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2821321289 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 50055560637 ps |
| CPU time | 256.47 seconds |
| Started | Oct 12 08:57:15 AM UTC 24 |
| Finished | Oct 12 09:01:35 AM UTC 24 |
| Peak memory | 262344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821321289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.2821321289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.2172126709 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 191993139 ps |
| CPU time | 6.01 seconds |
| Started | Oct 12 08:57:06 AM UTC 24 |
| Finished | Oct 12 08:57:13 AM UTC 24 |
| Peak memory | 235520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172126709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2172126709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2503071374 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 2183258789 ps |
| CPU time | 17.69 seconds |
| Started | Oct 12 08:57:06 AM UTC 24 |
| Finished | Oct 12 08:57:25 AM UTC 24 |
| Peak memory | 235752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503071374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.2503071374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.3897750311 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1092199596 ps |
| CPU time | 17.26 seconds |
| Started | Oct 12 08:56:59 AM UTC 24 |
| Finished | Oct 12 08:57:17 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897750311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3897750311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.876914655 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 6322563917 ps |
| CPU time | 71.14 seconds |
| Started | Oct 12 08:57:00 AM UTC 24 |
| Finished | Oct 12 08:58:13 AM UTC 24 |
| Peak memory | 246012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876914655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.876914655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2985333434 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 396065432 ps |
| CPU time | 5.37 seconds |
| Started | Oct 12 08:56:59 AM UTC 24 |
| Finished | Oct 12 08:57:05 AM UTC 24 |
| Peak memory | 246068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985333434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.2985333434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2565760829 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 25319856735 ps |
| CPU time | 20 seconds |
| Started | Oct 12 08:56:58 AM UTC 24 |
| Finished | Oct 12 08:57:20 AM UTC 24 |
| Peak memory | 246064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565760829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2565760829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.2119568371 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4473091073 ps |
| CPU time | 7.92 seconds |
| Started | Oct 12 08:57:08 AM UTC 24 |
| Finished | Oct 12 08:57:17 AM UTC 24 |
| Peak memory | 234276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119568371 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.2119568371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3165596970 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 57453337 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 08:57:15 AM UTC 24 |
| Finished | Oct 12 08:57:17 AM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165596970 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.3165596970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.818880942 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 6063832559 ps |
| CPU time | 35.92 seconds |
| Started | Oct 12 08:56:56 AM UTC 24 |
| Finished | Oct 12 08:57:34 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818880942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.818880942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1293786740 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 2139177121 ps |
| CPU time | 11.07 seconds |
| Started | Oct 12 08:56:55 AM UTC 24 |
| Finished | Oct 12 08:57:07 AM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293786740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1293786740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.4196151357 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1639137059 ps |
| CPU time | 4.93 seconds |
| Started | Oct 12 08:56:56 AM UTC 24 |
| Finished | Oct 12 08:57:02 AM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196151357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4196151357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3433081241 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 135050993 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 08:56:56 AM UTC 24 |
| Finished | Oct 12 08:56:59 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433081241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3433081241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1460043519 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1851372203 ps |
| CPU time | 9.83 seconds |
| Started | Oct 12 08:57:03 AM UTC 24 |
| Finished | Oct 12 08:57:14 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460043519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1460043519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.2653397532 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 53469747 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 08:57:33 AM UTC 24 |
| Finished | Oct 12 08:57:35 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653397532 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.2653397532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.836368310 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 51816989 ps |
| CPU time | 3.52 seconds |
| Started | Oct 12 08:57:26 AM UTC 24 |
| Finished | Oct 12 08:57:30 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836368310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.836368310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.2726530893 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 53608141 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:57:18 AM UTC 24 |
| Finished | Oct 12 08:57:20 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726530893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2726530893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1980064004 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 86696935313 ps |
| CPU time | 171.29 seconds |
| Started | Oct 12 08:57:30 AM UTC 24 |
| Finished | Oct 12 09:00:24 AM UTC 24 |
| Peak memory | 268392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980064004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1980064004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3768019752 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 83550369031 ps |
| CPU time | 205.67 seconds |
| Started | Oct 12 08:57:30 AM UTC 24 |
| Finished | Oct 12 09:00:59 AM UTC 24 |
| Peak memory | 266428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768019752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3768019752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1918675412 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2959393303 ps |
| CPU time | 57.78 seconds |
| Started | Oct 12 08:57:31 AM UTC 24 |
| Finished | Oct 12 08:58:31 AM UTC 24 |
| Peak memory | 262332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918675412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1918675412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.3156659129 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2478634125 ps |
| CPU time | 42.45 seconds |
| Started | Oct 12 08:57:27 AM UTC 24 |
| Finished | Oct 12 08:58:11 AM UTC 24 |
| Peak memory | 250000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156659129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3156659129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3119944840 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 353607523992 ps |
| CPU time | 209.39 seconds |
| Started | Oct 12 08:57:27 AM UTC 24 |
| Finished | Oct 12 09:01:00 AM UTC 24 |
| Peak memory | 262264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119944840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.3119944840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.2943956131 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5098816903 ps |
| CPU time | 7.55 seconds |
| Started | Oct 12 08:57:21 AM UTC 24 |
| Finished | Oct 12 08:57:30 AM UTC 24 |
| Peak memory | 235632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943956131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2943956131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.80225063 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4165959145 ps |
| CPU time | 37.3 seconds |
| Started | Oct 12 08:57:23 AM UTC 24 |
| Finished | Oct 12 08:58:01 AM UTC 24 |
| Peak memory | 262548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80225063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.80225063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.470319973 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 10742280087 ps |
| CPU time | 21.79 seconds |
| Started | Oct 12 08:57:21 AM UTC 24 |
| Finished | Oct 12 08:57:44 AM UTC 24 |
| Peak memory | 246068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470319973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.470319973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1573882601 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 177515156 ps |
| CPU time | 5 seconds |
| Started | Oct 12 08:57:20 AM UTC 24 |
| Finished | Oct 12 08:57:26 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573882601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1573882601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1114569314 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 315655729 ps |
| CPU time | 5.54 seconds |
| Started | Oct 12 08:57:30 AM UTC 24 |
| Finished | Oct 12 08:57:37 AM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114569314 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1114569314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1233416292 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 37650233425 ps |
| CPU time | 369.44 seconds |
| Started | Oct 12 08:57:31 AM UTC 24 |
| Finished | Oct 12 09:03:46 AM UTC 24 |
| Peak memory | 266416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233416292 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.1233416292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.1244589209 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 5430447042 ps |
| CPU time | 19.63 seconds |
| Started | Oct 12 08:57:18 AM UTC 24 |
| Finished | Oct 12 08:57:39 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244589209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1244589209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.833628456 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 6055639132 ps |
| CPU time | 31.72 seconds |
| Started | Oct 12 08:57:18 AM UTC 24 |
| Finished | Oct 12 08:57:51 AM UTC 24 |
| Peak memory | 228216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833628456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.833628456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.933968834 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 268825693 ps |
| CPU time | 3.91 seconds |
| Started | Oct 12 08:57:19 AM UTC 24 |
| Finished | Oct 12 08:57:24 AM UTC 24 |
| Peak memory | 228324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933968834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.933968834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.3381553495 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 171236207 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 08:57:19 AM UTC 24 |
| Finished | Oct 12 08:57:22 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381553495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3381553495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.2677097680 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 48656301 ps |
| CPU time | 3.34 seconds |
| Started | Oct 12 08:57:25 AM UTC 24 |
| Finished | Oct 12 08:57:29 AM UTC 24 |
| Peak memory | 245508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677097680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2677097680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.2067033842 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 12567920 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:57:51 AM UTC 24 |
| Finished | Oct 12 08:57:53 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067033842 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.2067033842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2660555394 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 120791957 ps |
| CPU time | 5.08 seconds |
| Started | Oct 12 08:57:42 AM UTC 24 |
| Finished | Oct 12 08:57:49 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660555394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2660555394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.2815461124 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 34036561 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 08:57:35 AM UTC 24 |
| Finished | Oct 12 08:57:37 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815461124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2815461124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3056082256 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 45018375757 ps |
| CPU time | 388.14 seconds |
| Started | Oct 12 08:57:46 AM UTC 24 |
| Finished | Oct 12 09:04:19 AM UTC 24 |
| Peak memory | 278668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056082256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3056082256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.4251134683 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 5851471705 ps |
| CPU time | 96.32 seconds |
| Started | Oct 12 08:57:47 AM UTC 24 |
| Finished | Oct 12 08:59:25 AM UTC 24 |
| Peak memory | 268388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251134683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4251134683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1445267782 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 139488995678 ps |
| CPU time | 207.73 seconds |
| Started | Oct 12 08:57:47 AM UTC 24 |
| Finished | Oct 12 09:01:18 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445267782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.1445267782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.2545751471 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 278817704 ps |
| CPU time | 5.86 seconds |
| Started | Oct 12 08:57:44 AM UTC 24 |
| Finished | Oct 12 08:57:51 AM UTC 24 |
| Peak memory | 232600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545751471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2545751471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.693046341 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5053859182 ps |
| CPU time | 49.23 seconds |
| Started | Oct 12 08:57:46 AM UTC 24 |
| Finished | Oct 12 08:58:36 AM UTC 24 |
| Peak memory | 262256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693046341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.693046341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.803848478 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 2059244935 ps |
| CPU time | 4.9 seconds |
| Started | Oct 12 08:57:40 AM UTC 24 |
| Finished | Oct 12 08:57:46 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803848478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.803848478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.934956270 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 595852269 ps |
| CPU time | 13.17 seconds |
| Started | Oct 12 08:57:41 AM UTC 24 |
| Finished | Oct 12 08:57:56 AM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934956270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.934956270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3257575299 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 72474100 ps |
| CPU time | 3.45 seconds |
| Started | Oct 12 08:57:40 AM UTC 24 |
| Finished | Oct 12 08:57:45 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257575299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.3257575299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2659028069 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 26071138101 ps |
| CPU time | 21.84 seconds |
| Started | Oct 12 08:57:38 AM UTC 24 |
| Finished | Oct 12 08:58:01 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659028069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2659028069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2112694707 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 289666926 ps |
| CPU time | 6.91 seconds |
| Started | Oct 12 08:57:46 AM UTC 24 |
| Finished | Oct 12 08:57:54 AM UTC 24 |
| Peak memory | 234316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112694707 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2112694707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1634708209 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3546701247 ps |
| CPU time | 22.12 seconds |
| Started | Oct 12 08:57:37 AM UTC 24 |
| Finished | Oct 12 08:58:00 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634708209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1634708209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3760019686 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 643036869 ps |
| CPU time | 4.28 seconds |
| Started | Oct 12 08:57:36 AM UTC 24 |
| Finished | Oct 12 08:57:41 AM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760019686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3760019686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.1191698863 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 167361335 ps |
| CPU time | 3.54 seconds |
| Started | Oct 12 08:57:38 AM UTC 24 |
| Finished | Oct 12 08:57:43 AM UTC 24 |
| Peak memory | 228296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191698863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1191698863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2443082926 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 24729199 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 08:57:38 AM UTC 24 |
| Finished | Oct 12 08:57:40 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443082926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2443082926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.3901478666 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 596780078 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 08:57:41 AM UTC 24 |
| Finished | Oct 12 08:57:46 AM UTC 24 |
| Peak memory | 235792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901478666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3901478666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.3369652177 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 64292149 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 08:58:07 AM UTC 24 |
| Finished | Oct 12 08:58:09 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369652177 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.3369652177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.3316641239 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 60077622 ps |
| CPU time | 3.49 seconds |
| Started | Oct 12 08:58:01 AM UTC 24 |
| Finished | Oct 12 08:58:06 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316641239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3316641239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.3154467412 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 181048430 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:57:52 AM UTC 24 |
| Finished | Oct 12 08:57:54 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154467412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3154467412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.2879230596 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 96869328329 ps |
| CPU time | 136.59 seconds |
| Started | Oct 12 08:58:04 AM UTC 24 |
| Finished | Oct 12 09:00:23 AM UTC 24 |
| Peak memory | 262476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879230596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2879230596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3289967605 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 23706022168 ps |
| CPU time | 56.3 seconds |
| Started | Oct 12 08:58:06 AM UTC 24 |
| Finished | Oct 12 08:59:04 AM UTC 24 |
| Peak memory | 262524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289967605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3289967605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3198497827 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 3761138029 ps |
| CPU time | 52.07 seconds |
| Started | Oct 12 08:58:06 AM UTC 24 |
| Finished | Oct 12 08:58:59 AM UTC 24 |
| Peak memory | 268468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198497827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.3198497827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.535038443 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 41686712 ps |
| CPU time | 3.93 seconds |
| Started | Oct 12 08:58:01 AM UTC 24 |
| Finished | Oct 12 08:58:06 AM UTC 24 |
| Peak memory | 245748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535038443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.535038443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.3123083525 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 3493265989 ps |
| CPU time | 53.72 seconds |
| Started | Oct 12 08:58:02 AM UTC 24 |
| Finished | Oct 12 08:58:58 AM UTC 24 |
| Peak memory | 262256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123083525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.3123083525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.3286747068 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 32062671 ps |
| CPU time | 3.25 seconds |
| Started | Oct 12 08:57:59 AM UTC 24 |
| Finished | Oct 12 08:58:03 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286747068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3286747068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.2788534828 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2451909731 ps |
| CPU time | 18.2 seconds |
| Started | Oct 12 08:57:59 AM UTC 24 |
| Finished | Oct 12 08:58:18 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788534828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2788534828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.806359007 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 220559461 ps |
| CPU time | 4.61 seconds |
| Started | Oct 12 08:57:59 AM UTC 24 |
| Finished | Oct 12 08:58:04 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806359007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.806359007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3167648690 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 676149700 ps |
| CPU time | 5.11 seconds |
| Started | Oct 12 08:57:59 AM UTC 24 |
| Finished | Oct 12 08:58:05 AM UTC 24 |
| Peak memory | 235704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167648690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3167648690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1184224257 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 175288046 ps |
| CPU time | 4.25 seconds |
| Started | Oct 12 08:58:02 AM UTC 24 |
| Finished | Oct 12 08:58:08 AM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184224257 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.1184224257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.3309264488 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 54902162 ps |
| CPU time | 1.79 seconds |
| Started | Oct 12 08:58:06 AM UTC 24 |
| Finished | Oct 12 08:58:08 AM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309264488 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.3309264488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.569337994 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4918885017 ps |
| CPU time | 12.83 seconds |
| Started | Oct 12 08:57:54 AM UTC 24 |
| Finished | Oct 12 08:58:08 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569337994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.569337994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3452848743 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2061177543 ps |
| CPU time | 9.13 seconds |
| Started | Oct 12 08:57:54 AM UTC 24 |
| Finished | Oct 12 08:58:05 AM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452848743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3452848743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.492927027 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 63617943 ps |
| CPU time | 2.01 seconds |
| Started | Oct 12 08:57:57 AM UTC 24 |
| Finished | Oct 12 08:58:00 AM UTC 24 |
| Peak memory | 228372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492927027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.492927027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3660838217 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 12937846 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:57:56 AM UTC 24 |
| Finished | Oct 12 08:57:58 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660838217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3660838217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.2453285719 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 4865636861 ps |
| CPU time | 5.58 seconds |
| Started | Oct 12 08:58:00 AM UTC 24 |
| Finished | Oct 12 08:58:07 AM UTC 24 |
| Peak memory | 235660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453285719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2453285719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.668643119 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 29865716 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:42:29 AM UTC 24 |
| Finished | Oct 12 08:42:31 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668643119 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.668643119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3122959249 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 144065722 ps |
| CPU time | 3.43 seconds |
| Started | Oct 12 08:42:13 AM UTC 24 |
| Finished | Oct 12 08:42:17 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122959249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3122959249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.3081741476 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 179698593 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 08:41:54 AM UTC 24 |
| Finished | Oct 12 08:41:56 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081741476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3081741476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.3101565224 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 24845816800 ps |
| CPU time | 207.61 seconds |
| Started | Oct 12 08:42:18 AM UTC 24 |
| Finished | Oct 12 08:45:49 AM UTC 24 |
| Peak memory | 264384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101565224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3101565224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.4214676383 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 27314396 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 08:42:19 AM UTC 24 |
| Finished | Oct 12 08:42:21 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214676383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4214676383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3898976367 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 8537704274 ps |
| CPU time | 12.85 seconds |
| Started | Oct 12 08:42:13 AM UTC 24 |
| Finished | Oct 12 08:42:27 AM UTC 24 |
| Peak memory | 235660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898976367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3898976367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1896665931 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 504686847 ps |
| CPU time | 6.04 seconds |
| Started | Oct 12 08:42:05 AM UTC 24 |
| Finished | Oct 12 08:42:13 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896665931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1896665931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1985335567 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 398047843 ps |
| CPU time | 5.05 seconds |
| Started | Oct 12 08:42:06 AM UTC 24 |
| Finished | Oct 12 08:42:12 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985335567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1985335567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3735417540 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 569176231 ps |
| CPU time | 7.61 seconds |
| Started | Oct 12 08:42:03 AM UTC 24 |
| Finished | Oct 12 08:42:12 AM UTC 24 |
| Peak memory | 235540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735417540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.3735417540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.4039483634 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 350394433 ps |
| CPU time | 6.02 seconds |
| Started | Oct 12 08:42:00 AM UTC 24 |
| Finished | Oct 12 08:42:07 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039483634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4039483634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.550326096 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1476881440 ps |
| CPU time | 10.94 seconds |
| Started | Oct 12 08:42:16 AM UTC 24 |
| Finished | Oct 12 08:42:28 AM UTC 24 |
| Peak memory | 232088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550326096 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.550326096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.2697202101 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 406183645 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 08:42:29 AM UTC 24 |
| Finished | Oct 12 08:42:31 AM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697202101 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2697202101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2181042236 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 42002528 ps |
| CPU time | 1.42 seconds |
| Started | Oct 12 08:42:27 AM UTC 24 |
| Finished | Oct 12 08:42:30 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181042236 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.2181042236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2509369734 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 6959022728 ps |
| CPU time | 19.8 seconds |
| Started | Oct 12 08:41:57 AM UTC 24 |
| Finished | Oct 12 08:42:18 AM UTC 24 |
| Peak memory | 232464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509369734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2509369734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2288226150 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4779034078 ps |
| CPU time | 7.31 seconds |
| Started | Oct 12 08:41:56 AM UTC 24 |
| Finished | Oct 12 08:42:04 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288226150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2288226150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3661594444 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 18773398 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 08:42:00 AM UTC 24 |
| Finished | Oct 12 08:42:02 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661594444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3661594444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3153637309 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 67662569 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 08:41:57 AM UTC 24 |
| Finished | Oct 12 08:41:59 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153637309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3153637309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1258492914 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1930932320 ps |
| CPU time | 17.74 seconds |
| Started | Oct 12 08:42:09 AM UTC 24 |
| Finished | Oct 12 08:42:28 AM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258492914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1258492914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.527703353 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 12461217 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 08:58:18 AM UTC 24 |
| Finished | Oct 12 08:58:21 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527703353 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.527703353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.611802674 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 7289344282 ps |
| CPU time | 21.85 seconds |
| Started | Oct 12 08:58:12 AM UTC 24 |
| Finished | Oct 12 08:58:35 AM UTC 24 |
| Peak memory | 246012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611802674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.611802674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.2188613194 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 19149644 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 08:58:07 AM UTC 24 |
| Finished | Oct 12 08:58:09 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188613194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2188613194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.266552405 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 7558306560 ps |
| CPU time | 8.63 seconds |
| Started | Oct 12 08:58:17 AM UTC 24 |
| Finished | Oct 12 08:58:27 AM UTC 24 |
| Peak memory | 247944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266552405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.266552405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.490707415 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 123581951895 ps |
| CPU time | 323.41 seconds |
| Started | Oct 12 08:58:17 AM UTC 24 |
| Finished | Oct 12 09:03:46 AM UTC 24 |
| Peak memory | 284544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490707415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.490707415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1308062494 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5287849054 ps |
| CPU time | 40.91 seconds |
| Started | Oct 12 08:58:17 AM UTC 24 |
| Finished | Oct 12 08:59:00 AM UTC 24 |
| Peak memory | 268448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308062494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.1308062494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2248327999 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1327468027 ps |
| CPU time | 15.73 seconds |
| Started | Oct 12 08:58:12 AM UTC 24 |
| Finished | Oct 12 08:58:29 AM UTC 24 |
| Peak memory | 245772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248327999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2248327999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2142368576 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 13612389307 ps |
| CPU time | 123.37 seconds |
| Started | Oct 12 08:58:12 AM UTC 24 |
| Finished | Oct 12 09:00:18 AM UTC 24 |
| Peak memory | 268396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142368576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.2142368576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.558071624 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 727674201 ps |
| CPU time | 5.23 seconds |
| Started | Oct 12 08:58:10 AM UTC 24 |
| Finished | Oct 12 08:58:16 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558071624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.558071624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.2950867055 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2777830038 ps |
| CPU time | 26.29 seconds |
| Started | Oct 12 08:58:10 AM UTC 24 |
| Finished | Oct 12 08:58:37 AM UTC 24 |
| Peak memory | 245900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950867055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2950867055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2364196964 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1781365667 ps |
| CPU time | 26.45 seconds |
| Started | Oct 12 08:58:10 AM UTC 24 |
| Finished | Oct 12 08:58:37 AM UTC 24 |
| Peak memory | 262192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364196964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.2364196964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2241678805 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 796469494 ps |
| CPU time | 7.69 seconds |
| Started | Oct 12 08:58:08 AM UTC 24 |
| Finished | Oct 12 08:58:17 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241678805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2241678805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2467674877 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 153719331 ps |
| CPU time | 4.94 seconds |
| Started | Oct 12 08:58:13 AM UTC 24 |
| Finished | Oct 12 08:58:19 AM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467674877 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.2467674877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3523861448 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 7997540943 ps |
| CPU time | 47.84 seconds |
| Started | Oct 12 08:58:17 AM UTC 24 |
| Finished | Oct 12 08:59:07 AM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523861448 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.3523861448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.2439753751 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2104938753 ps |
| CPU time | 26.05 seconds |
| Started | Oct 12 08:58:07 AM UTC 24 |
| Finished | Oct 12 08:58:34 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439753751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2439753751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1369095211 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 3737997966 ps |
| CPU time | 8 seconds |
| Started | Oct 12 08:58:07 AM UTC 24 |
| Finished | Oct 12 08:58:16 AM UTC 24 |
| Peak memory | 228524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369095211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1369095211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3782509720 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 377750013 ps |
| CPU time | 6.79 seconds |
| Started | Oct 12 08:58:08 AM UTC 24 |
| Finished | Oct 12 08:58:16 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782509720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3782509720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.18728720 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 278518468 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 08:58:08 AM UTC 24 |
| Finished | Oct 12 08:58:11 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18728720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.18728720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.1571743420 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 19527521666 ps |
| CPU time | 15.44 seconds |
| Started | Oct 12 08:58:10 AM UTC 24 |
| Finished | Oct 12 08:58:26 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571743420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1571743420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2550657867 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 47991056 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:58:37 AM UTC 24 |
| Finished | Oct 12 08:58:39 AM UTC 24 |
| Peak memory | 214532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550657867 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.2550657867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2995379087 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 692530177 ps |
| CPU time | 12.06 seconds |
| Started | Oct 12 08:58:30 AM UTC 24 |
| Finished | Oct 12 08:58:44 AM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995379087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2995379087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1481652338 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 17411037 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 08:58:20 AM UTC 24 |
| Finished | Oct 12 08:58:22 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481652338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1481652338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3113965485 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 53535210167 ps |
| CPU time | 186.86 seconds |
| Started | Oct 12 08:58:35 AM UTC 24 |
| Finished | Oct 12 09:01:45 AM UTC 24 |
| Peak memory | 264492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113965485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3113965485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.234438127 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 55545909257 ps |
| CPU time | 80.57 seconds |
| Started | Oct 12 08:58:36 AM UTC 24 |
| Finished | Oct 12 08:59:59 AM UTC 24 |
| Peak memory | 262320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234438127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.234438127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2609172228 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4771380326 ps |
| CPU time | 48.04 seconds |
| Started | Oct 12 08:58:36 AM UTC 24 |
| Finished | Oct 12 08:59:26 AM UTC 24 |
| Peak memory | 264332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609172228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.2609172228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.1276334018 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2233524636 ps |
| CPU time | 24.52 seconds |
| Started | Oct 12 08:58:32 AM UTC 24 |
| Finished | Oct 12 08:58:58 AM UTC 24 |
| Peak memory | 248144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276334018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1276334018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2560842937 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 16191619668 ps |
| CPU time | 202.79 seconds |
| Started | Oct 12 08:58:33 AM UTC 24 |
| Finished | Oct 12 09:01:59 AM UTC 24 |
| Peak memory | 278648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560842937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2560842937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.922571138 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 5804748672 ps |
| CPU time | 23.44 seconds |
| Started | Oct 12 08:58:27 AM UTC 24 |
| Finished | Oct 12 08:58:52 AM UTC 24 |
| Peak memory | 246132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922571138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.922571138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3300242540 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 4735439196 ps |
| CPU time | 56.22 seconds |
| Started | Oct 12 08:58:28 AM UTC 24 |
| Finished | Oct 12 08:59:26 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300242540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3300242540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.2031293573 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1068497505 ps |
| CPU time | 5.43 seconds |
| Started | Oct 12 08:58:26 AM UTC 24 |
| Finished | Oct 12 08:58:33 AM UTC 24 |
| Peak memory | 235520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031293573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.2031293573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.609125740 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 905408734 ps |
| CPU time | 4.88 seconds |
| Started | Oct 12 08:58:25 AM UTC 24 |
| Finished | Oct 12 08:58:31 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609125740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.609125740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.4142034865 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2620453357 ps |
| CPU time | 7.07 seconds |
| Started | Oct 12 08:58:34 AM UTC 24 |
| Finished | Oct 12 08:58:42 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142034865 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.4142034865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.3070137852 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 87121949169 ps |
| CPU time | 862.25 seconds |
| Started | Oct 12 08:58:37 AM UTC 24 |
| Finished | Oct 12 09:13:10 AM UTC 24 |
| Peak memory | 285112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070137852 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.3070137852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.3935259792 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4554735211 ps |
| CPU time | 21.24 seconds |
| Started | Oct 12 08:58:22 AM UTC 24 |
| Finished | Oct 12 08:58:44 AM UTC 24 |
| Peak memory | 232660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935259792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3935259792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.3148760015 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 638984623 ps |
| CPU time | 8.44 seconds |
| Started | Oct 12 08:58:20 AM UTC 24 |
| Finished | Oct 12 08:58:29 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148760015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3148760015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.2812313378 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 224019322 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 08:58:23 AM UTC 24 |
| Finished | Oct 12 08:58:26 AM UTC 24 |
| Peak memory | 216984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812313378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2812313378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3746534137 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 54814738 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 08:58:22 AM UTC 24 |
| Finished | Oct 12 08:58:24 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746534137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3746534137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.575339218 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4287490880 ps |
| CPU time | 9.75 seconds |
| Started | Oct 12 08:58:29 AM UTC 24 |
| Finished | Oct 12 08:58:41 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575339218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.575339218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.2550403516 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 16655829 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:58:57 AM UTC 24 |
| Finished | Oct 12 08:58:59 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550403516 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.2550403516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1591017878 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 420708817 ps |
| CPU time | 3.3 seconds |
| Started | Oct 12 08:58:49 AM UTC 24 |
| Finished | Oct 12 08:58:53 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591017878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1591017878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.1153575481 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 37320662 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 08:58:38 AM UTC 24 |
| Finished | Oct 12 08:58:40 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153575481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1153575481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.944359715 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 3447639516 ps |
| CPU time | 49.56 seconds |
| Started | Oct 12 08:58:55 AM UTC 24 |
| Finished | Oct 12 08:59:46 AM UTC 24 |
| Peak memory | 246068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944359715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.944359715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2469618021 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 55613376027 ps |
| CPU time | 292.97 seconds |
| Started | Oct 12 08:58:56 AM UTC 24 |
| Finished | Oct 12 09:03:53 AM UTC 24 |
| Peak memory | 266452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469618021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2469618021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3474273464 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 24608171219 ps |
| CPU time | 134.15 seconds |
| Started | Oct 12 08:58:56 AM UTC 24 |
| Finished | Oct 12 09:01:12 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474273464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.3474273464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.2922196234 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2206250481 ps |
| CPU time | 13.17 seconds |
| Started | Oct 12 08:58:50 AM UTC 24 |
| Finished | Oct 12 08:59:05 AM UTC 24 |
| Peak memory | 235824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922196234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2922196234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3178131370 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 774800506 ps |
| CPU time | 20.99 seconds |
| Started | Oct 12 08:58:53 AM UTC 24 |
| Finished | Oct 12 08:59:16 AM UTC 24 |
| Peak memory | 252080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178131370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.3178131370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.127179016 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 803178945 ps |
| CPU time | 8.3 seconds |
| Started | Oct 12 08:58:45 AM UTC 24 |
| Finished | Oct 12 08:58:54 AM UTC 24 |
| Peak memory | 245804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127179016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.127179016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.2761446720 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 10202221744 ps |
| CPU time | 56.65 seconds |
| Started | Oct 12 08:58:45 AM UTC 24 |
| Finished | Oct 12 08:59:43 AM UTC 24 |
| Peak memory | 264340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761446720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2761446720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2361076560 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 479907614 ps |
| CPU time | 10.21 seconds |
| Started | Oct 12 08:58:45 AM UTC 24 |
| Finished | Oct 12 08:58:56 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361076560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.2361076560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1997045870 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 25129239723 ps |
| CPU time | 22.72 seconds |
| Started | Oct 12 08:58:43 AM UTC 24 |
| Finished | Oct 12 08:59:07 AM UTC 24 |
| Peak memory | 246012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997045870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1997045870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2223885923 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 5472987961 ps |
| CPU time | 20.59 seconds |
| Started | Oct 12 08:58:53 AM UTC 24 |
| Finished | Oct 12 08:59:15 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223885923 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2223885923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3741615859 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 291954635 ps |
| CPU time | 1.46 seconds |
| Started | Oct 12 08:58:57 AM UTC 24 |
| Finished | Oct 12 08:58:59 AM UTC 24 |
| Peak memory | 216884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741615859 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.3741615859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.1310350205 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3706536347 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 08:58:40 AM UTC 24 |
| Finished | Oct 12 08:58:48 AM UTC 24 |
| Peak memory | 232464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310350205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1310350205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.601236774 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1891328407 ps |
| CPU time | 9.92 seconds |
| Started | Oct 12 08:58:38 AM UTC 24 |
| Finished | Oct 12 08:58:49 AM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601236774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.601236774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.403586784 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 62142246 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 08:58:42 AM UTC 24 |
| Finished | Oct 12 08:58:44 AM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403586784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.403586784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.438945962 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 41712718 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 08:58:42 AM UTC 24 |
| Finished | Oct 12 08:58:44 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438945962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.438945962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.4220308444 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3101773879 ps |
| CPU time | 6.51 seconds |
| Started | Oct 12 08:58:45 AM UTC 24 |
| Finished | Oct 12 08:58:53 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220308444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4220308444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1168593384 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 32462205 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 08:59:13 AM UTC 24 |
| Finished | Oct 12 08:59:15 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168593384 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.1168593384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1445065974 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 95406471 ps |
| CPU time | 3.2 seconds |
| Started | Oct 12 08:59:06 AM UTC 24 |
| Finished | Oct 12 08:59:10 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445065974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1445065974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1126107264 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 26135989 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:58:59 AM UTC 24 |
| Finished | Oct 12 08:59:01 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126107264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1126107264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.2765617914 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 156844377563 ps |
| CPU time | 285.03 seconds |
| Started | Oct 12 08:59:10 AM UTC 24 |
| Finished | Oct 12 09:03:59 AM UTC 24 |
| Peak memory | 262348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765617914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2765617914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.4069202028 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 391787670 ps |
| CPU time | 8.9 seconds |
| Started | Oct 12 08:59:10 AM UTC 24 |
| Finished | Oct 12 08:59:20 AM UTC 24 |
| Peak memory | 230428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069202028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4069202028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3494404227 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 162850693237 ps |
| CPU time | 575.65 seconds |
| Started | Oct 12 08:59:12 AM UTC 24 |
| Finished | Oct 12 09:08:55 AM UTC 24 |
| Peak memory | 268468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494404227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.3494404227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.4162412852 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 5102837709 ps |
| CPU time | 41.1 seconds |
| Started | Oct 12 08:59:07 AM UTC 24 |
| Finished | Oct 12 08:59:49 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162412852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4162412852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1302080478 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 198387919 ps |
| CPU time | 1.61 seconds |
| Started | Oct 12 08:59:08 AM UTC 24 |
| Finished | Oct 12 08:59:11 AM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302080478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1302080478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3145399717 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1212783735 ps |
| CPU time | 17.67 seconds |
| Started | Oct 12 08:59:04 AM UTC 24 |
| Finished | Oct 12 08:59:22 AM UTC 24 |
| Peak memory | 245776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145399717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3145399717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2516723147 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 5487915156 ps |
| CPU time | 23.12 seconds |
| Started | Oct 12 08:59:05 AM UTC 24 |
| Finished | Oct 12 08:59:29 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516723147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2516723147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2325580547 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 744958784 ps |
| CPU time | 5.35 seconds |
| Started | Oct 12 08:59:02 AM UTC 24 |
| Finished | Oct 12 08:59:09 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325580547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.2325580547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.948670958 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 201906813 ps |
| CPU time | 3.32 seconds |
| Started | Oct 12 08:59:01 AM UTC 24 |
| Finished | Oct 12 08:59:06 AM UTC 24 |
| Peak memory | 235444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948670958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.948670958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1192806903 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 379149984 ps |
| CPU time | 8.41 seconds |
| Started | Oct 12 08:59:08 AM UTC 24 |
| Finished | Oct 12 08:59:18 AM UTC 24 |
| Peak memory | 234404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192806903 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.1192806903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3750994996 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 30860511399 ps |
| CPU time | 158.82 seconds |
| Started | Oct 12 08:59:12 AM UTC 24 |
| Finished | Oct 12 09:01:53 AM UTC 24 |
| Peak memory | 278704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750994996 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.3750994996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.2849163181 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 38108960255 ps |
| CPU time | 66.11 seconds |
| Started | Oct 12 08:59:00 AM UTC 24 |
| Finished | Oct 12 09:00:08 AM UTC 24 |
| Peak memory | 228372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849163181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2849163181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3157586075 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 4117981462 ps |
| CPU time | 11.26 seconds |
| Started | Oct 12 08:58:59 AM UTC 24 |
| Finished | Oct 12 08:59:11 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157586075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3157586075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2475360899 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 48872173 ps |
| CPU time | 2.18 seconds |
| Started | Oct 12 08:59:00 AM UTC 24 |
| Finished | Oct 12 08:59:03 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475360899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2475360899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1478472022 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 182430112 ps |
| CPU time | 1.94 seconds |
| Started | Oct 12 08:59:00 AM UTC 24 |
| Finished | Oct 12 08:59:03 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478472022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1478472022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2905989623 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 6390887459 ps |
| CPU time | 16.89 seconds |
| Started | Oct 12 08:59:05 AM UTC 24 |
| Finished | Oct 12 08:59:23 AM UTC 24 |
| Peak memory | 245896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905989623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2905989623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.2520630442 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 11984886 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 08:59:40 AM UTC 24 |
| Finished | Oct 12 08:59:42 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520630442 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.2520630442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1858470264 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 692386460 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 08:59:26 AM UTC 24 |
| Finished | Oct 12 08:59:30 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858470264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1858470264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.4242286949 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 44315776 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 08:59:16 AM UTC 24 |
| Finished | Oct 12 08:59:18 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242286949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4242286949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1489321583 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 7859474035 ps |
| CPU time | 43.95 seconds |
| Started | Oct 12 08:59:30 AM UTC 24 |
| Finished | Oct 12 09:00:16 AM UTC 24 |
| Peak memory | 262548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489321583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1489321583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4292148891 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 21804839097 ps |
| CPU time | 208.07 seconds |
| Started | Oct 12 08:59:30 AM UTC 24 |
| Finished | Oct 12 09:03:02 AM UTC 24 |
| Peak memory | 268488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292148891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.4292148891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3902216607 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 4776148574 ps |
| CPU time | 24.47 seconds |
| Started | Oct 12 08:59:27 AM UTC 24 |
| Finished | Oct 12 08:59:53 AM UTC 24 |
| Peak memory | 250004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902216607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3902216607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.4021666905 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 45627330170 ps |
| CPU time | 174.53 seconds |
| Started | Oct 12 08:59:27 AM UTC 24 |
| Finished | Oct 12 09:02:24 AM UTC 24 |
| Peak memory | 266360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021666905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.4021666905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.1167562599 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 6547997721 ps |
| CPU time | 17.07 seconds |
| Started | Oct 12 08:59:22 AM UTC 24 |
| Finished | Oct 12 08:59:41 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167562599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1167562599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.93729336 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 6975331908 ps |
| CPU time | 36.31 seconds |
| Started | Oct 12 08:59:24 AM UTC 24 |
| Finished | Oct 12 09:00:01 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93729336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.93729336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1935763362 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 5080007340 ps |
| CPU time | 19.13 seconds |
| Started | Oct 12 08:59:21 AM UTC 24 |
| Finished | Oct 12 08:59:42 AM UTC 24 |
| Peak memory | 252212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935763362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.1935763362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2214777938 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 6987564870 ps |
| CPU time | 16.51 seconds |
| Started | Oct 12 08:59:21 AM UTC 24 |
| Finished | Oct 12 08:59:39 AM UTC 24 |
| Peak memory | 235736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214777938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2214777938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.1512193833 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 4675007513 ps |
| CPU time | 25.87 seconds |
| Started | Oct 12 08:59:29 AM UTC 24 |
| Finished | Oct 12 08:59:56 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512193833 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.1512193833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2109180805 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 101258304710 ps |
| CPU time | 1019.82 seconds |
| Started | Oct 12 08:59:38 AM UTC 24 |
| Finished | Oct 12 09:16:50 AM UTC 24 |
| Peak memory | 299388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109180805 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.2109180805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.479423653 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 4408930399 ps |
| CPU time | 27.71 seconds |
| Started | Oct 12 08:59:17 AM UTC 24 |
| Finished | Oct 12 08:59:46 AM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479423653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.479423653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1368667837 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 4561623240 ps |
| CPU time | 19.47 seconds |
| Started | Oct 12 08:59:16 AM UTC 24 |
| Finished | Oct 12 08:59:36 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368667837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1368667837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.428123872 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 32162939 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 08:59:19 AM UTC 24 |
| Finished | Oct 12 08:59:21 AM UTC 24 |
| Peak memory | 216828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428123872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.428123872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1714020998 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 37756222 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 08:59:18 AM UTC 24 |
| Finished | Oct 12 08:59:20 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714020998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1714020998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.77175378 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2156620465 ps |
| CPU time | 3.93 seconds |
| Started | Oct 12 08:59:24 AM UTC 24 |
| Finished | Oct 12 08:59:29 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77175378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.77175378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3991030924 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 36502161 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:59:59 AM UTC 24 |
| Finished | Oct 12 09:00:01 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991030924 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.3991030924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.264697053 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 432928760 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 08:59:50 AM UTC 24 |
| Finished | Oct 12 08:59:54 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264697053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.264697053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3240595621 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 73616129 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 08:59:40 AM UTC 24 |
| Finished | Oct 12 08:59:42 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240595621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3240595621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.4106023601 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3897549734 ps |
| CPU time | 38.39 seconds |
| Started | Oct 12 08:59:52 AM UTC 24 |
| Finished | Oct 12 09:00:32 AM UTC 24 |
| Peak memory | 252228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106023601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4106023601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2809596077 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 17778704395 ps |
| CPU time | 80.46 seconds |
| Started | Oct 12 08:59:54 AM UTC 24 |
| Finished | Oct 12 09:01:17 AM UTC 24 |
| Peak memory | 262580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809596077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2809596077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.3001456297 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 12179993017 ps |
| CPU time | 137.67 seconds |
| Started | Oct 12 08:59:55 AM UTC 24 |
| Finished | Oct 12 09:02:15 AM UTC 24 |
| Peak memory | 278736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001456297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.3001456297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1103715869 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 1162771533 ps |
| CPU time | 10.29 seconds |
| Started | Oct 12 08:59:51 AM UTC 24 |
| Finished | Oct 12 09:00:02 AM UTC 24 |
| Peak memory | 262188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103715869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1103715869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2974878211 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 15571538066 ps |
| CPU time | 52.14 seconds |
| Started | Oct 12 08:59:51 AM UTC 24 |
| Finished | Oct 12 09:00:45 AM UTC 24 |
| Peak memory | 262320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974878211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.2974878211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.301309706 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 4788761065 ps |
| CPU time | 20.37 seconds |
| Started | Oct 12 08:59:46 AM UTC 24 |
| Finished | Oct 12 09:00:08 AM UTC 24 |
| Peak memory | 235668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301309706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.301309706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2813595731 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 3133776689 ps |
| CPU time | 19.66 seconds |
| Started | Oct 12 08:59:47 AM UTC 24 |
| Finished | Oct 12 09:00:08 AM UTC 24 |
| Peak memory | 246012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813595731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2813595731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3986958119 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 976456139 ps |
| CPU time | 13.5 seconds |
| Started | Oct 12 08:59:46 AM UTC 24 |
| Finished | Oct 12 09:00:01 AM UTC 24 |
| Peak memory | 245784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986958119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.3986958119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1289375854 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 209552709 ps |
| CPU time | 5.34 seconds |
| Started | Oct 12 08:59:44 AM UTC 24 |
| Finished | Oct 12 08:59:51 AM UTC 24 |
| Peak memory | 246068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289375854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1289375854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2066990291 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 4812686832 ps |
| CPU time | 10.78 seconds |
| Started | Oct 12 08:59:51 AM UTC 24 |
| Finished | Oct 12 09:00:03 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066990291 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.2066990291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.3677105644 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 112711500 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 08:59:57 AM UTC 24 |
| Finished | Oct 12 09:00:00 AM UTC 24 |
| Peak memory | 217028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677105644 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.3677105644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3191205512 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 1801742131 ps |
| CPU time | 18.68 seconds |
| Started | Oct 12 08:59:43 AM UTC 24 |
| Finished | Oct 12 09:00:03 AM UTC 24 |
| Peak memory | 228268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191205512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3191205512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.470439570 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 528443174 ps |
| CPU time | 4.44 seconds |
| Started | Oct 12 08:59:42 AM UTC 24 |
| Finished | Oct 12 08:59:47 AM UTC 24 |
| Peak memory | 228176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470439570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.470439570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3299796409 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 87185025 ps |
| CPU time | 6.2 seconds |
| Started | Oct 12 08:59:43 AM UTC 24 |
| Finished | Oct 12 08:59:50 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299796409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3299796409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3790382176 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 36594641 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 08:59:43 AM UTC 24 |
| Finished | Oct 12 08:59:45 AM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790382176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3790382176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.3570583994 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2488463183 ps |
| CPU time | 20.94 seconds |
| Started | Oct 12 08:59:49 AM UTC 24 |
| Finished | Oct 12 09:00:11 AM UTC 24 |
| Peak memory | 235664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570583994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3570583994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3555998835 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 19685203 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 09:00:18 AM UTC 24 |
| Finished | Oct 12 09:00:20 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555998835 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.3555998835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2882961942 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 76562286 ps |
| CPU time | 3.36 seconds |
| Started | Oct 12 09:00:09 AM UTC 24 |
| Finished | Oct 12 09:00:14 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882961942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2882961942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.4095665627 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 19390570 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 09:00:01 AM UTC 24 |
| Finished | Oct 12 09:00:07 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095665627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4095665627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2748654049 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 161502319 ps |
| CPU time | 4.16 seconds |
| Started | Oct 12 09:00:15 AM UTC 24 |
| Finished | Oct 12 09:00:20 AM UTC 24 |
| Peak memory | 247948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748654049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2748654049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3125830484 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 12104567417 ps |
| CPU time | 65.46 seconds |
| Started | Oct 12 09:00:15 AM UTC 24 |
| Finished | Oct 12 09:01:22 AM UTC 24 |
| Peak memory | 266616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125830484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3125830484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.29514426 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 36728304864 ps |
| CPU time | 132.08 seconds |
| Started | Oct 12 09:00:16 AM UTC 24 |
| Finished | Oct 12 09:02:31 AM UTC 24 |
| Peak memory | 252076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29514426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.29514426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.319264756 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 1040283411 ps |
| CPU time | 13.43 seconds |
| Started | Oct 12 09:00:09 AM UTC 24 |
| Finished | Oct 12 09:00:24 AM UTC 24 |
| Peak memory | 262416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319264756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.319264756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.249121334 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 94736050104 ps |
| CPU time | 321.77 seconds |
| Started | Oct 12 09:00:11 AM UTC 24 |
| Finished | Oct 12 09:05:38 AM UTC 24 |
| Peak memory | 282772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249121334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.249121334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1025184135 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 296961002 ps |
| CPU time | 5.54 seconds |
| Started | Oct 12 09:00:08 AM UTC 24 |
| Finished | Oct 12 09:00:15 AM UTC 24 |
| Peak memory | 244692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025184135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1025184135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.3899273492 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2642350266 ps |
| CPU time | 13.86 seconds |
| Started | Oct 12 09:00:08 AM UTC 24 |
| Finished | Oct 12 09:00:23 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899273492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3899273492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3278798309 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 1781852465 ps |
| CPU time | 10.97 seconds |
| Started | Oct 12 09:00:07 AM UTC 24 |
| Finished | Oct 12 09:00:19 AM UTC 24 |
| Peak memory | 264472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278798309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.3278798309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2330140950 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 916863203 ps |
| CPU time | 16.1 seconds |
| Started | Oct 12 09:00:07 AM UTC 24 |
| Finished | Oct 12 09:00:24 AM UTC 24 |
| Peak memory | 235700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330140950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2330140950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3351575269 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 437545001 ps |
| CPU time | 4.92 seconds |
| Started | Oct 12 09:00:12 AM UTC 24 |
| Finished | Oct 12 09:00:18 AM UTC 24 |
| Peak memory | 234124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351575269 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.3351575269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.3949741764 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 138847731 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 09:00:17 AM UTC 24 |
| Finished | Oct 12 09:00:20 AM UTC 24 |
| Peak memory | 216848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949741764 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.3949741764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.650531358 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2930292590 ps |
| CPU time | 35.85 seconds |
| Started | Oct 12 09:00:03 AM UTC 24 |
| Finished | Oct 12 09:00:42 AM UTC 24 |
| Peak memory | 232656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650531358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.650531358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2972601523 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 721517544 ps |
| CPU time | 4.08 seconds |
| Started | Oct 12 09:00:01 AM UTC 24 |
| Finished | Oct 12 09:00:11 AM UTC 24 |
| Peak memory | 228176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972601523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2972601523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3634913089 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 248642701 ps |
| CPU time | 5.75 seconds |
| Started | Oct 12 09:00:07 AM UTC 24 |
| Finished | Oct 12 09:00:14 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634913089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3634913089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2978512909 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 23952737 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 09:00:03 AM UTC 24 |
| Finished | Oct 12 09:00:08 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978512909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2978512909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1676382009 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 1701611041 ps |
| CPU time | 10.59 seconds |
| Started | Oct 12 09:00:09 AM UTC 24 |
| Finished | Oct 12 09:00:21 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676382009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1676382009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.4098150120 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 60388971 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 09:00:32 AM UTC 24 |
| Finished | Oct 12 09:00:34 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098150120 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.4098150120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3194014776 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 401517201 ps |
| CPU time | 4.32 seconds |
| Started | Oct 12 09:00:25 AM UTC 24 |
| Finished | Oct 12 09:00:30 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194014776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3194014776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3697227314 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 20468942 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 09:00:18 AM UTC 24 |
| Finished | Oct 12 09:00:20 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697227314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3697227314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3689279695 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 36929406448 ps |
| CPU time | 281.15 seconds |
| Started | Oct 12 09:00:26 AM UTC 24 |
| Finished | Oct 12 09:05:11 AM UTC 24 |
| Peak memory | 266348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689279695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3689279695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3521891511 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 52884236969 ps |
| CPU time | 212.11 seconds |
| Started | Oct 12 09:00:27 AM UTC 24 |
| Finished | Oct 12 09:04:03 AM UTC 24 |
| Peak memory | 268660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521891511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3521891511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3330232551 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 115417162508 ps |
| CPU time | 343.82 seconds |
| Started | Oct 12 09:00:29 AM UTC 24 |
| Finished | Oct 12 09:06:18 AM UTC 24 |
| Peak memory | 278688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330232551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.3330232551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1673930633 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 236360029 ps |
| CPU time | 3.38 seconds |
| Started | Oct 12 09:00:25 AM UTC 24 |
| Finished | Oct 12 09:00:29 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673930633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1673930633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2509537603 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 12800131649 ps |
| CPU time | 71.57 seconds |
| Started | Oct 12 09:00:25 AM UTC 24 |
| Finished | Oct 12 09:01:38 AM UTC 24 |
| Peak memory | 278668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509537603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.2509537603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.1201876130 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 3905514324 ps |
| CPU time | 11.71 seconds |
| Started | Oct 12 09:00:24 AM UTC 24 |
| Finished | Oct 12 09:00:36 AM UTC 24 |
| Peak memory | 245872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201876130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1201876130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.1429222714 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 18128511050 ps |
| CPU time | 81.92 seconds |
| Started | Oct 12 09:00:25 AM UTC 24 |
| Finished | Oct 12 09:01:49 AM UTC 24 |
| Peak memory | 249976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429222714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1429222714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2933854961 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 1278294042 ps |
| CPU time | 5.17 seconds |
| Started | Oct 12 09:00:23 AM UTC 24 |
| Finished | Oct 12 09:00:29 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933854961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2933854961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.184416702 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5767980620 ps |
| CPU time | 16.2 seconds |
| Started | Oct 12 09:00:22 AM UTC 24 |
| Finished | Oct 12 09:00:39 AM UTC 24 |
| Peak memory | 245908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184416702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.184416702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1550915540 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 1986321815 ps |
| CPU time | 9.23 seconds |
| Started | Oct 12 09:00:25 AM UTC 24 |
| Finished | Oct 12 09:00:36 AM UTC 24 |
| Peak memory | 234144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550915540 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.1550915540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1700897495 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 4355384697 ps |
| CPU time | 44.77 seconds |
| Started | Oct 12 09:00:30 AM UTC 24 |
| Finished | Oct 12 09:01:17 AM UTC 24 |
| Peak memory | 252080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700897495 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.1700897495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.193238663 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 70426943549 ps |
| CPU time | 36.85 seconds |
| Started | Oct 12 09:00:21 AM UTC 24 |
| Finished | Oct 12 09:01:00 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193238663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.193238663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.4103151223 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 594210043 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 09:00:20 AM UTC 24 |
| Finished | Oct 12 09:00:26 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103151223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4103151223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.4220488546 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 33730781 ps |
| CPU time | 1.48 seconds |
| Started | Oct 12 09:00:21 AM UTC 24 |
| Finished | Oct 12 09:00:24 AM UTC 24 |
| Peak memory | 228456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220488546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4220488546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1918220131 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 96185811 ps |
| CPU time | 1.24 seconds |
| Started | Oct 12 09:00:21 AM UTC 24 |
| Finished | Oct 12 09:00:24 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918220131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1918220131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.1635298657 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 5451582939 ps |
| CPU time | 10.37 seconds |
| Started | Oct 12 09:00:25 AM UTC 24 |
| Finished | Oct 12 09:00:36 AM UTC 24 |
| Peak memory | 249972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635298657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1635298657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.2250295008 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 23854867 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 09:00:51 AM UTC 24 |
| Finished | Oct 12 09:00:54 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250295008 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.2250295008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3092757784 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 1978575615 ps |
| CPU time | 11.27 seconds |
| Started | Oct 12 09:00:42 AM UTC 24 |
| Finished | Oct 12 09:00:54 AM UTC 24 |
| Peak memory | 235708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092757784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3092757784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.1674763162 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 28007811 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 09:00:33 AM UTC 24 |
| Finished | Oct 12 09:00:35 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674763162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1674763162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2082732660 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 147931721105 ps |
| CPU time | 237.45 seconds |
| Started | Oct 12 09:00:46 AM UTC 24 |
| Finished | Oct 12 09:04:47 AM UTC 24 |
| Peak memory | 278852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082732660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2082732660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.1575641534 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 75184180710 ps |
| CPU time | 257.53 seconds |
| Started | Oct 12 09:00:47 AM UTC 24 |
| Finished | Oct 12 09:05:09 AM UTC 24 |
| Peak memory | 278900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575641534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1575641534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3618104706 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 32502932622 ps |
| CPU time | 323.67 seconds |
| Started | Oct 12 09:00:47 AM UTC 24 |
| Finished | Oct 12 09:06:16 AM UTC 24 |
| Peak memory | 278712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618104706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.3618104706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2168919419 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 38158583 ps |
| CPU time | 3.71 seconds |
| Started | Oct 12 09:00:43 AM UTC 24 |
| Finished | Oct 12 09:00:47 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168919419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2168919419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.958340920 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 39229961107 ps |
| CPU time | 84.67 seconds |
| Started | Oct 12 09:00:44 AM UTC 24 |
| Finished | Oct 12 09:02:11 AM UTC 24 |
| Peak memory | 264504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958340920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.958340920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3221263060 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 33347685 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 09:00:37 AM UTC 24 |
| Finished | Oct 12 09:00:42 AM UTC 24 |
| Peak memory | 245512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221263060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3221263060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1944771036 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 267881745 ps |
| CPU time | 5.25 seconds |
| Started | Oct 12 09:00:39 AM UTC 24 |
| Finished | Oct 12 09:00:46 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944771036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1944771036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.725344209 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 1850491372 ps |
| CPU time | 7.92 seconds |
| Started | Oct 12 09:00:37 AM UTC 24 |
| Finished | Oct 12 09:00:46 AM UTC 24 |
| Peak memory | 245744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725344209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.725344209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2429345906 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 200943974 ps |
| CPU time | 6 seconds |
| Started | Oct 12 09:00:37 AM UTC 24 |
| Finished | Oct 12 09:00:44 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429345906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2429345906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2548659124 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 646361020 ps |
| CPU time | 7.01 seconds |
| Started | Oct 12 09:00:45 AM UTC 24 |
| Finished | Oct 12 09:00:53 AM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548659124 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.2548659124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.722564545 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 157353404 ps |
| CPU time | 1.51 seconds |
| Started | Oct 12 09:00:48 AM UTC 24 |
| Finished | Oct 12 09:00:51 AM UTC 24 |
| Peak memory | 216948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722564545 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.722564545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.3178606317 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2633530378 ps |
| CPU time | 25.32 seconds |
| Started | Oct 12 09:00:35 AM UTC 24 |
| Finished | Oct 12 09:01:02 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178606317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3178606317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2207922486 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 34961555 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 09:00:33 AM UTC 24 |
| Finished | Oct 12 09:00:35 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207922486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2207922486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.952911308 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 106887549 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 09:00:36 AM UTC 24 |
| Finished | Oct 12 09:00:41 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952911308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.952911308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1345124578 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 96596079 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 09:00:36 AM UTC 24 |
| Finished | Oct 12 09:00:38 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345124578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1345124578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.4147304534 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 1862474128 ps |
| CPU time | 10.55 seconds |
| Started | Oct 12 09:00:39 AM UTC 24 |
| Finished | Oct 12 09:00:51 AM UTC 24 |
| Peak memory | 245748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147304534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4147304534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.794339760 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 12962238 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 09:01:12 AM UTC 24 |
| Finished | Oct 12 09:01:14 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794339760 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.794339760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1717724395 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 739017755 ps |
| CPU time | 6.94 seconds |
| Started | Oct 12 09:01:02 AM UTC 24 |
| Finished | Oct 12 09:01:10 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717724395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1717724395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3931043339 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 114144168 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 09:00:53 AM UTC 24 |
| Finished | Oct 12 09:00:55 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931043339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3931043339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.830700312 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3303893392 ps |
| CPU time | 30.71 seconds |
| Started | Oct 12 09:01:08 AM UTC 24 |
| Finished | Oct 12 09:01:40 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830700312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.830700312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.4106300266 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 25417928873 ps |
| CPU time | 316.35 seconds |
| Started | Oct 12 09:01:09 AM UTC 24 |
| Finished | Oct 12 09:06:30 AM UTC 24 |
| Peak memory | 280748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106300266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4106300266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.375261566 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2991008542 ps |
| CPU time | 52.09 seconds |
| Started | Oct 12 09:01:10 AM UTC 24 |
| Finished | Oct 12 09:02:04 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375261566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.375261566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3793798550 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 79628277 ps |
| CPU time | 3.49 seconds |
| Started | Oct 12 09:01:03 AM UTC 24 |
| Finished | Oct 12 09:01:07 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793798550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3793798550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2161210541 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 14480371600 ps |
| CPU time | 157.74 seconds |
| Started | Oct 12 09:01:08 AM UTC 24 |
| Finished | Oct 12 09:03:48 AM UTC 24 |
| Peak memory | 266552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161210541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.2161210541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1940188635 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 2569995812 ps |
| CPU time | 5.94 seconds |
| Started | Oct 12 09:01:00 AM UTC 24 |
| Finished | Oct 12 09:01:07 AM UTC 24 |
| Peak memory | 245872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940188635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1940188635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.1411857478 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 743985557 ps |
| CPU time | 6.12 seconds |
| Started | Oct 12 09:01:00 AM UTC 24 |
| Finished | Oct 12 09:01:07 AM UTC 24 |
| Peak memory | 235644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411857478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1411857478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.3088642870 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2900122004 ps |
| CPU time | 6.91 seconds |
| Started | Oct 12 09:00:59 AM UTC 24 |
| Finished | Oct 12 09:01:07 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088642870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.3088642870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3772006374 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 1537948814 ps |
| CPU time | 9.97 seconds |
| Started | Oct 12 09:00:58 AM UTC 24 |
| Finished | Oct 12 09:01:09 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772006374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3772006374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.4193148204 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 721940479 ps |
| CPU time | 10.06 seconds |
| Started | Oct 12 09:01:08 AM UTC 24 |
| Finished | Oct 12 09:01:19 AM UTC 24 |
| Peak memory | 234212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193148204 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.4193148204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.280731261 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 602799143 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 09:01:11 AM UTC 24 |
| Finished | Oct 12 09:01:14 AM UTC 24 |
| Peak memory | 216792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280731261 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.280731261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1260756060 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2789396905 ps |
| CPU time | 15.24 seconds |
| Started | Oct 12 09:00:55 AM UTC 24 |
| Finished | Oct 12 09:01:11 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260756060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1260756060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3169369566 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 1663578563 ps |
| CPU time | 16.57 seconds |
| Started | Oct 12 09:00:54 AM UTC 24 |
| Finished | Oct 12 09:01:11 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169369566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3169369566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.3491493855 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 40189218 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 09:00:56 AM UTC 24 |
| Finished | Oct 12 09:00:58 AM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491493855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3491493855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3855064302 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 107106663 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 09:00:55 AM UTC 24 |
| Finished | Oct 12 09:00:57 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855064302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3855064302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1634977801 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2623430058 ps |
| CPU time | 11.36 seconds |
| Started | Oct 12 09:01:00 AM UTC 24 |
| Finished | Oct 12 09:01:13 AM UTC 24 |
| Peak memory | 246128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634977801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1634977801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2673409929 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 14703493 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:43:05 AM UTC 24 |
| Finished | Oct 12 08:43:07 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673409929 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2673409929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.4138800779 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 414425242 ps |
| CPU time | 6.67 seconds |
| Started | Oct 12 08:42:50 AM UTC 24 |
| Finished | Oct 12 08:42:58 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138800779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4138800779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.836900452 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 16347323 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 08:42:30 AM UTC 24 |
| Finished | Oct 12 08:42:32 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836900452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.836900452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.1198471655 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 29039242698 ps |
| CPU time | 88.72 seconds |
| Started | Oct 12 08:43:00 AM UTC 24 |
| Finished | Oct 12 08:44:31 AM UTC 24 |
| Peak memory | 268440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198471655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1198471655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.1488421533 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 117983032870 ps |
| CPU time | 119.47 seconds |
| Started | Oct 12 08:43:03 AM UTC 24 |
| Finished | Oct 12 08:45:05 AM UTC 24 |
| Peak memory | 262520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488421533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.1488421533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3010468998 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2814351450 ps |
| CPU time | 10.96 seconds |
| Started | Oct 12 08:42:50 AM UTC 24 |
| Finished | Oct 12 08:43:02 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010468998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3010468998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1346950676 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 11647112925 ps |
| CPU time | 35.5 seconds |
| Started | Oct 12 08:42:50 AM UTC 24 |
| Finished | Oct 12 08:43:27 AM UTC 24 |
| Peak memory | 245872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346950676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.1346950676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.2912151059 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1080367749 ps |
| CPU time | 9.99 seconds |
| Started | Oct 12 08:42:39 AM UTC 24 |
| Finished | Oct 12 08:42:50 AM UTC 24 |
| Peak memory | 245916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912151059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2912151059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.4145076136 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 42777459979 ps |
| CPU time | 136.95 seconds |
| Started | Oct 12 08:42:40 AM UTC 24 |
| Finished | Oct 12 08:44:59 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145076136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4145076136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2183659092 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 5207239715 ps |
| CPU time | 11.93 seconds |
| Started | Oct 12 08:42:36 AM UTC 24 |
| Finished | Oct 12 08:42:49 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183659092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.2183659092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1787511671 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1878763397 ps |
| CPU time | 7.99 seconds |
| Started | Oct 12 08:42:36 AM UTC 24 |
| Finished | Oct 12 08:42:45 AM UTC 24 |
| Peak memory | 245996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787511671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1787511671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.353164173 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 442701220 ps |
| CPU time | 6.6 seconds |
| Started | Oct 12 08:42:55 AM UTC 24 |
| Finished | Oct 12 08:43:03 AM UTC 24 |
| Peak memory | 234224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353164173 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.353164173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.3984408316 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 764142275333 ps |
| CPU time | 1178.2 seconds |
| Started | Oct 12 08:43:05 AM UTC 24 |
| Finished | Oct 12 09:02:57 AM UTC 24 |
| Peak memory | 278688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984408316 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.3984408316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1184621158 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 24546212726 ps |
| CPU time | 39.55 seconds |
| Started | Oct 12 08:42:32 AM UTC 24 |
| Finished | Oct 12 08:43:13 AM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184621158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1184621158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3945309129 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3286327670 ps |
| CPU time | 5.58 seconds |
| Started | Oct 12 08:42:32 AM UTC 24 |
| Finished | Oct 12 08:42:39 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945309129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3945309129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2616572162 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 34097449 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 08:42:34 AM UTC 24 |
| Finished | Oct 12 08:42:38 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616572162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2616572162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2632139348 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 137817757 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 08:42:33 AM UTC 24 |
| Finished | Oct 12 08:42:36 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632139348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2632139348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2684217919 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 651358126 ps |
| CPU time | 6.64 seconds |
| Started | Oct 12 08:42:47 AM UTC 24 |
| Finished | Oct 12 08:42:55 AM UTC 24 |
| Peak memory | 245804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684217919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2684217919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1037456293 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 11232308 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 08:43:53 AM UTC 24 |
| Finished | Oct 12 08:43:55 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037456293 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1037456293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.3195787578 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 16634642011 ps |
| CPU time | 25.06 seconds |
| Started | Oct 12 08:43:34 AM UTC 24 |
| Finished | Oct 12 08:44:01 AM UTC 24 |
| Peak memory | 235824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195787578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3195787578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2265685068 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 79500190 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 08:43:09 AM UTC 24 |
| Finished | Oct 12 08:43:12 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265685068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2265685068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.2551365105 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 100569320818 ps |
| CPU time | 212.6 seconds |
| Started | Oct 12 08:43:39 AM UTC 24 |
| Finished | Oct 12 08:47:15 AM UTC 24 |
| Peak memory | 278664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551365105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2551365105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1670818593 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 20700973717 ps |
| CPU time | 170.45 seconds |
| Started | Oct 12 08:43:45 AM UTC 24 |
| Finished | Oct 12 08:46:38 AM UTC 24 |
| Peak memory | 250228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670818593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1670818593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.629631804 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 36362864020 ps |
| CPU time | 342.2 seconds |
| Started | Oct 12 08:43:46 AM UTC 24 |
| Finished | Oct 12 08:49:33 AM UTC 24 |
| Peak memory | 268656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629631804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.629631804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.2683461201 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 111997197 ps |
| CPU time | 5.13 seconds |
| Started | Oct 12 08:43:37 AM UTC 24 |
| Finished | Oct 12 08:43:44 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683461201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2683461201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2007598858 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2352034617 ps |
| CPU time | 13.76 seconds |
| Started | Oct 12 08:43:38 AM UTC 24 |
| Finished | Oct 12 08:43:52 AM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007598858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.2007598858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.4086346802 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 659921814 ps |
| CPU time | 6.12 seconds |
| Started | Oct 12 08:43:29 AM UTC 24 |
| Finished | Oct 12 08:43:36 AM UTC 24 |
| Peak memory | 235524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086346802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4086346802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.1814456770 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1128255269 ps |
| CPU time | 20.08 seconds |
| Started | Oct 12 08:43:29 AM UTC 24 |
| Finished | Oct 12 08:43:51 AM UTC 24 |
| Peak memory | 246004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814456770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1814456770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1563210309 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4663273307 ps |
| CPU time | 30.09 seconds |
| Started | Oct 12 08:43:26 AM UTC 24 |
| Finished | Oct 12 08:43:58 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563210309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1563210309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2332262488 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 548192903 ps |
| CPU time | 5.37 seconds |
| Started | Oct 12 08:43:22 AM UTC 24 |
| Finished | Oct 12 08:43:28 AM UTC 24 |
| Peak memory | 245804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332262488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2332262488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2071592163 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 10982321629 ps |
| CPU time | 21.02 seconds |
| Started | Oct 12 08:43:38 AM UTC 24 |
| Finished | Oct 12 08:44:00 AM UTC 24 |
| Peak memory | 234248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071592163 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2071592163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.1358636390 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 48707815312 ps |
| CPU time | 70.76 seconds |
| Started | Oct 12 08:43:16 AM UTC 24 |
| Finished | Oct 12 08:44:28 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358636390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1358636390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2720709914 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 12489209110 ps |
| CPU time | 21.18 seconds |
| Started | Oct 12 08:43:15 AM UTC 24 |
| Finished | Oct 12 08:43:38 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720709914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2720709914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2682741092 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 17265671 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 08:43:22 AM UTC 24 |
| Finished | Oct 12 08:43:24 AM UTC 24 |
| Peak memory | 217108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682741092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2682741092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2059254279 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 20266364 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 08:43:18 AM UTC 24 |
| Finished | Oct 12 08:43:20 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059254279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2059254279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.4068652442 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 135317856 ps |
| CPU time | 3.39 seconds |
| Started | Oct 12 08:43:32 AM UTC 24 |
| Finished | Oct 12 08:43:37 AM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068652442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4068652442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.1768050052 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 146907147 ps |
| CPU time | 1.11 seconds |
| Started | Oct 12 08:44:25 AM UTC 24 |
| Finished | Oct 12 08:44:27 AM UTC 24 |
| Peak memory | 214660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768050052 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1768050052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2641657238 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 103120263 ps |
| CPU time | 4.29 seconds |
| Started | Oct 12 08:44:10 AM UTC 24 |
| Finished | Oct 12 08:44:16 AM UTC 24 |
| Peak memory | 245968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641657238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2641657238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.827542487 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 49344690 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:43:54 AM UTC 24 |
| Finished | Oct 12 08:43:56 AM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827542487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.827542487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.339940772 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 16619328505 ps |
| CPU time | 45.55 seconds |
| Started | Oct 12 08:44:15 AM UTC 24 |
| Finished | Oct 12 08:45:02 AM UTC 24 |
| Peak memory | 250224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339940772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.339940772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1623212775 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1762457053 ps |
| CPU time | 15.19 seconds |
| Started | Oct 12 08:44:17 AM UTC 24 |
| Finished | Oct 12 08:44:33 AM UTC 24 |
| Peak memory | 232404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623212775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1623212775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.751155144 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 16480980119 ps |
| CPU time | 144.18 seconds |
| Started | Oct 12 08:44:19 AM UTC 24 |
| Finished | Oct 12 08:46:46 AM UTC 24 |
| Peak memory | 280748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751155144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.751155144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.571726056 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3583624188 ps |
| CPU time | 13.18 seconds |
| Started | Oct 12 08:44:11 AM UTC 24 |
| Finished | Oct 12 08:44:26 AM UTC 24 |
| Peak memory | 235652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571726056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.571726056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.4152993410 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 16239013430 ps |
| CPU time | 149.01 seconds |
| Started | Oct 12 08:44:11 AM UTC 24 |
| Finished | Oct 12 08:46:43 AM UTC 24 |
| Peak memory | 278836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152993410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.4152993410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.3371905665 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 101379377 ps |
| CPU time | 5.52 seconds |
| Started | Oct 12 08:44:03 AM UTC 24 |
| Finished | Oct 12 08:44:09 AM UTC 24 |
| Peak memory | 245852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371905665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3371905665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3901098892 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 18096425207 ps |
| CPU time | 56.23 seconds |
| Started | Oct 12 08:44:03 AM UTC 24 |
| Finished | Oct 12 08:45:01 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901098892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3901098892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1602876564 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 6883434411 ps |
| CPU time | 20.19 seconds |
| Started | Oct 12 08:44:02 AM UTC 24 |
| Finished | Oct 12 08:44:23 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602876564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.1602876564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3762195740 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1129807787 ps |
| CPU time | 9.53 seconds |
| Started | Oct 12 08:44:02 AM UTC 24 |
| Finished | Oct 12 08:44:12 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762195740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3762195740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2153631862 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1006404147 ps |
| CPU time | 13.56 seconds |
| Started | Oct 12 08:44:13 AM UTC 24 |
| Finished | Oct 12 08:44:28 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153631862 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.2153631862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.3596808917 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 49792823822 ps |
| CPU time | 120.51 seconds |
| Started | Oct 12 08:44:24 AM UTC 24 |
| Finished | Oct 12 08:46:27 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596808917 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.3596808917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.4044045100 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4027453540 ps |
| CPU time | 11.2 seconds |
| Started | Oct 12 08:43:58 AM UTC 24 |
| Finished | Oct 12 08:44:11 AM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044045100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4044045100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1376550405 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1189775363 ps |
| CPU time | 3.19 seconds |
| Started | Oct 12 08:43:57 AM UTC 24 |
| Finished | Oct 12 08:44:02 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376550405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1376550405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.945771609 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 169644336 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 08:44:01 AM UTC 24 |
| Finished | Oct 12 08:44:04 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945771609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.945771609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.539420112 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 90823138 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 08:43:59 AM UTC 24 |
| Finished | Oct 12 08:44:01 AM UTC 24 |
| Peak memory | 216660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539420112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.539420112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.586440411 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1410036790 ps |
| CPU time | 7.08 seconds |
| Started | Oct 12 08:44:05 AM UTC 24 |
| Finished | Oct 12 08:44:13 AM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586440411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.586440411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3217166262 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 14248791 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 08:44:57 AM UTC 24 |
| Finished | Oct 12 08:44:59 AM UTC 24 |
| Peak memory | 214660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217166262 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3217166262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2020038357 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 361575996 ps |
| CPU time | 10.93 seconds |
| Started | Oct 12 08:44:36 AM UTC 24 |
| Finished | Oct 12 08:44:49 AM UTC 24 |
| Peak memory | 235504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020038357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2020038357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1200053160 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 18234721 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:44:26 AM UTC 24 |
| Finished | Oct 12 08:44:28 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200053160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1200053160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.170498968 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 69219697493 ps |
| CPU time | 129.81 seconds |
| Started | Oct 12 08:44:53 AM UTC 24 |
| Finished | Oct 12 08:47:05 AM UTC 24 |
| Peak memory | 250160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170498968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.170498968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1923377815 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 6354739333 ps |
| CPU time | 57.86 seconds |
| Started | Oct 12 08:44:53 AM UTC 24 |
| Finished | Oct 12 08:45:52 AM UTC 24 |
| Peak memory | 252296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923377815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1923377815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2266016727 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 63926923939 ps |
| CPU time | 279.32 seconds |
| Started | Oct 12 08:44:53 AM UTC 24 |
| Finished | Oct 12 08:49:36 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266016727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.2266016727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.61703290 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1876818480 ps |
| CPU time | 38.8 seconds |
| Started | Oct 12 08:44:38 AM UTC 24 |
| Finished | Oct 12 08:45:19 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61703290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.61703290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2932119012 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 7110788861 ps |
| CPU time | 119.63 seconds |
| Started | Oct 12 08:44:40 AM UTC 24 |
| Finished | Oct 12 08:46:42 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932119012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.2932119012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.3195377521 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2939372280 ps |
| CPU time | 16.42 seconds |
| Started | Oct 12 08:44:34 AM UTC 24 |
| Finished | Oct 12 08:44:51 AM UTC 24 |
| Peak memory | 246168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195377521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3195377521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2394020346 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1331062338 ps |
| CPU time | 15.82 seconds |
| Started | Oct 12 08:44:35 AM UTC 24 |
| Finished | Oct 12 08:44:52 AM UTC 24 |
| Peak memory | 250124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394020346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2394020346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3919886148 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 354057213 ps |
| CPU time | 5.61 seconds |
| Started | Oct 12 08:44:33 AM UTC 24 |
| Finished | Oct 12 08:44:39 AM UTC 24 |
| Peak memory | 245944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919886148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.3919886148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2500698445 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 31103547555 ps |
| CPU time | 18.98 seconds |
| Started | Oct 12 08:44:32 AM UTC 24 |
| Finished | Oct 12 08:44:52 AM UTC 24 |
| Peak memory | 235656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500698445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2500698445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.565051537 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 85635266 ps |
| CPU time | 4.96 seconds |
| Started | Oct 12 08:44:49 AM UTC 24 |
| Finished | Oct 12 08:44:56 AM UTC 24 |
| Peak memory | 234188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565051537 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.565051537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2537187544 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 7445720058 ps |
| CPU time | 42.32 seconds |
| Started | Oct 12 08:44:29 AM UTC 24 |
| Finished | Oct 12 08:45:13 AM UTC 24 |
| Peak memory | 228588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537187544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2537187544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.79245360 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 289258748 ps |
| CPU time | 3.98 seconds |
| Started | Oct 12 08:44:29 AM UTC 24 |
| Finished | Oct 12 08:44:34 AM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79245360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.79245360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2325983212 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 232749466 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 08:44:32 AM UTC 24 |
| Finished | Oct 12 08:44:34 AM UTC 24 |
| Peak memory | 216836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325983212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2325983212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.275330890 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 350545513 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 08:44:29 AM UTC 24 |
| Finished | Oct 12 08:44:32 AM UTC 24 |
| Peak memory | 216600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275330890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.275330890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.14769273 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 15897833182 ps |
| CPU time | 27.08 seconds |
| Started | Oct 12 08:44:35 AM UTC 24 |
| Finished | Oct 12 08:45:04 AM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14769273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.14769273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.1096131513 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 22513933 ps |
| CPU time | 1.12 seconds |
| Started | Oct 12 08:45:29 AM UTC 24 |
| Finished | Oct 12 08:45:31 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096131513 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1096131513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2182513498 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 134240611 ps |
| CPU time | 4.85 seconds |
| Started | Oct 12 08:45:14 AM UTC 24 |
| Finished | Oct 12 08:45:20 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182513498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2182513498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.246971523 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 36963389 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 08:45:00 AM UTC 24 |
| Finished | Oct 12 08:45:02 AM UTC 24 |
| Peak memory | 216476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246971523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.246971523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.1205239363 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 81437197397 ps |
| CPU time | 347.39 seconds |
| Started | Oct 12 08:45:20 AM UTC 24 |
| Finished | Oct 12 08:51:13 AM UTC 24 |
| Peak memory | 266520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205239363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1205239363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1114674411 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 14035827943 ps |
| CPU time | 315.93 seconds |
| Started | Oct 12 08:45:21 AM UTC 24 |
| Finished | Oct 12 08:50:42 AM UTC 24 |
| Peak memory | 284844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114674411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1114674411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3168157201 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 10463858158 ps |
| CPU time | 41.23 seconds |
| Started | Oct 12 08:45:27 AM UTC 24 |
| Finished | Oct 12 08:46:09 AM UTC 24 |
| Peak memory | 235632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168157201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.3168157201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.84262877 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 179045624 ps |
| CPU time | 11.28 seconds |
| Started | Oct 12 08:45:15 AM UTC 24 |
| Finished | Oct 12 08:45:27 AM UTC 24 |
| Peak memory | 246028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84262877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.84262877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1832664755 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 11263357778 ps |
| CPU time | 79.61 seconds |
| Started | Oct 12 08:45:17 AM UTC 24 |
| Finished | Oct 12 08:46:39 AM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832664755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.1832664755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.596352583 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2216890879 ps |
| CPU time | 8.66 seconds |
| Started | Oct 12 08:45:07 AM UTC 24 |
| Finished | Oct 12 08:45:16 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596352583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.596352583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3094325739 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 16768873010 ps |
| CPU time | 20.44 seconds |
| Started | Oct 12 08:45:08 AM UTC 24 |
| Finished | Oct 12 08:45:29 AM UTC 24 |
| Peak memory | 245968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094325739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3094325739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3644934110 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4493111867 ps |
| CPU time | 7.21 seconds |
| Started | Oct 12 08:45:06 AM UTC 24 |
| Finished | Oct 12 08:45:14 AM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644934110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.3644934110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3413973522 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 11504503187 ps |
| CPU time | 7.85 seconds |
| Started | Oct 12 08:45:04 AM UTC 24 |
| Finished | Oct 12 08:45:13 AM UTC 24 |
| Peak memory | 245872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413973522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3413973522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.458864448 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 121966081 ps |
| CPU time | 4.96 seconds |
| Started | Oct 12 08:45:19 AM UTC 24 |
| Finished | Oct 12 08:45:25 AM UTC 24 |
| Peak memory | 234196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458864448 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.458864448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.559200018 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 15006391094 ps |
| CPU time | 246.82 seconds |
| Started | Oct 12 08:45:28 AM UTC 24 |
| Finished | Oct 12 08:49:38 AM UTC 24 |
| Peak memory | 295096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559200018 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.559200018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3673600257 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3534156222 ps |
| CPU time | 27.1 seconds |
| Started | Oct 12 08:45:02 AM UTC 24 |
| Finished | Oct 12 08:45:31 AM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673600257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3673600257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.722463895 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 5278855734 ps |
| CPU time | 22.76 seconds |
| Started | Oct 12 08:45:02 AM UTC 24 |
| Finished | Oct 12 08:45:26 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722463895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.722463895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1482964702 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 980070973 ps |
| CPU time | 2.23 seconds |
| Started | Oct 12 08:45:03 AM UTC 24 |
| Finished | Oct 12 08:45:07 AM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482964702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1482964702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4082357658 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 77861077 ps |
| CPU time | 1.52 seconds |
| Started | Oct 12 08:45:03 AM UTC 24 |
| Finished | Oct 12 08:45:06 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082357658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4082357658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3386236710 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 183505442 ps |
| CPU time | 5.32 seconds |
| Started | Oct 12 08:45:14 AM UTC 24 |
| Finished | Oct 12 08:45:20 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386236710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3386236710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest |
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