SPI_DEVICE/2P Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.504m	82.817ms	48	50	96.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.480s	160.457us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.840s	240.576us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.170s	5.036ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.170s	1.865ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.820s	108.747us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.840s	240.576us	20	20	100.00
		spi_device_csr_aliasing	22.170s	1.865ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	25.642us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.130s	62.510us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	csb_read	spi_device_csb_read	0.870s	42.700us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	25.661us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	36.317us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	6.800s	218.025us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.800s	218.025us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.200s	41.328ms	50	50	100.00
		spi_device_tpm_sts_read	1.160s	550.491us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.238m	58.962ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.110s	10.960ms	50	50	100.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	48.820s	21.229ms	50	50	100.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	48.820s	21.229ms	50	50	100.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	18.240s	5.245ms	49	50	98.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	18.240s	5.245ms	49	50	98.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	18.240s	5.245ms	49	50	98.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	18.240s	5.245ms	49	50	98.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	18.240s	5.245ms	49	50	98.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.290s	55.072ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.157m	51.280ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.157m	51.280ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.157m	51.280ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.123m	12.011ms	50	50	100.00
		spi_device_read_buffer_direct	6.910s	27.509ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.157m	51.280ms	50	50	100.00
		spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.690m	132.753ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.870s	5.492ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.870s	5.492ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.504m	82.817ms	48	50	96.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.759m	348.861ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.609m	145.739ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.790s	11.552us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	20.193us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.510s	809.594us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.510s	809.594us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.480s	160.457us	5	5	100.00
		spi_device_csr_rw	2.840s	240.576us	20	20	100.00
		spi_device_csr_aliasing	22.170s	1.865ms	5	5	100.00
		spi_device_same_csr_outstanding	4.460s	68.580us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.480s	160.457us	5	5	100.00
		spi_device_csr_rw	2.840s	240.576us	20	20	100.00
		spi_device_csr_aliasing	22.170s	1.865ms	5	5	100.00
		spi_device_same_csr_outstanding	4.460s	68.580us	20	20	100.00
V2		TOTAL			978	980	99.80
V2S	tl_intg_err	spi_device_sec_cm	1.210s	57.563us	5	5	100.00
		spi_device_tl_intg_err	21.700s	820.522us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.700s	820.522us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.95	98.36	94.16	98.61	89.36	97.09	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_stress_all has 1 failures.

4.spi_device_stress_all.62239038785474202735865342340517876367215029797476093108236692742175108478383
Line 306, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 137653974945 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf047a0) != exp '{'{other_status:'h3c11e8, wel:'h0, busy:'h1}}
  UVM_INFO @ 137654984945 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/11
  UVM_INFO @ 138976051945 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/11
  UVM_INFO @ 139669879945 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/11
  UVM_INFO @ 140646749945 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/11

Test spi_device_flash_and_tpm has 1 failures.

20.spi_device_flash_and_tpm.711533159598198796718341683636576671016956297730228557350605377923785745740
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 28031818683 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe1adb4) != exp '{'{other_status:'h2a70ee, wel:'h0, busy:'h0}}
  UVM_INFO @ 28059128319 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/8
  UVM_INFO @ 41168583324 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/3
  UVM_INFO @ 57487947098 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/8
  UVM_INFO @ 84673083804 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/8

UVM_ERROR (spi_device_scoreboard.sv:478) [scoreboard] Check failed flash_status_q.size <= * (* [*] vs * [*]) has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

13.spi_device_flash_and_tpm.105098424676350848802412959727160862541414579849269759708406495133783201861524
Line 275, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 87919276096 ps: (spi_device_scoreboard.sv:478) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 89776917899 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 19/20
  UVM_INFO @ 92956331087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_intercept has 1 failures.

43.spi_device_intercept.32829528340416775589903301633282244401581299599262849617968127437099950018445
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_intercept/latest/run.log

  UVM_ERROR @ 565966654 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x67b640) != exp '{'{other_status:'h2f452f, wel:'h0, busy:'h0}, '{other_status:'h3ffad0, wel:'h0, busy:'h0}}
  UVM_INFO @ 623646654 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intercept_vseq] running iteration 4, test op = 0x3
  UVM_INFO @ 716086654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---